/*
** ###################################################################
** Processors: MIMX8ML3CVNKZ
** MIMX8ML3DVNLZ
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
**
** Reference manual: IMX8MPRM, Rev.D, 12/2020
** Version: rev. 5.0, 2021-03-01
** Build: b220621
**
** Abstract:
** CMSIS Peripheral Access Layer for MIMX8ML3_cm7
**
** Copyright 1997-2016 Freescale Semiconductor, Inc.
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2019-10-11)
** Initial version.
** - rev. 2.0 (2020-02-21)
** Rev.B Header.
** - rev. 3.0 (2020-06-22)
** Rev.C Header.
** - rev. 4.0 (2020-11-16)
** Rev.D Header.
** - rev. 5.0 (2021-03-01)
** Rev.D Header Final.
**
** ###################################################################
*/
/*!
* @file MIMX8ML3_cm7.h
* @version 5.0
* @date 2021-03-01
* @brief CMSIS Peripheral Access Layer for MIMX8ML3_cm7
*
* CMSIS Peripheral Access Layer for MIMX8ML3_cm7
*/
#ifndef _MIMX8ML3_CM7_H_
#define _MIMX8ML3_CM7_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0500U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 170 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
/* Device specific interrupts */
DAP_IRQn = 1, /**< DAP Interrupt */
SDMA1_IRQn = 2, /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
GPU3D_IRQn = 3, /**< GPU3D Interrupt */
SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
LCDIF1_IRQn = 5, /**< LCDIF1 Interrupt */
LCDIF2_IRQn = 6, /**< LCDIF2 Interrupt */
VPU_G1_IRQn = 7, /**< VPU G1 Decoder Interrupt */
VPU_G2_IRQn = 8, /**< VPU G2 Decoder Interrupt */
QOS_IRQn = 9, /**< QOS interrupt */
WDOG3_IRQn = 10, /**< Watchdog Timer reset */
HS_CP1_IRQn = 11, /**< HS Interrupt Request */
APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
ML_IRQn = 13, /**< Machine Learning Processor Interrupt */
BCH_IRQn = 14, /**< BCH operation complete interrupt */
GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
ISI_IRQn = 16, /**< ISI Interrupt */
MIPI_CSI1_IRQn = 17, /**< MIPI CSI Interrupt */
MIPI_DSI_IRQn = 18, /**< MIPI DSI Interrupt */
SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */
GPU2D_IRQn = 25, /**< GPU2D Interrupt */
UART1_IRQn = 26, /**< UART-1 ORed interrupt */
UART2_IRQn = 27, /**< UART-2 ORed interrupt */
UART3_IRQn = 28, /**< UART-3 ORed interrupt */
UART4_IRQn = 29, /**< UART-4 ORed interrupt */
VPU_IRQn = 30, /**< VPU Encoder Interrupt */
ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
SDMA3_IRQn = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
I2C1_IRQn = 35, /**< I2C-1 Interrupt */
I2C2_IRQn = 36, /**< I2C-2 Interrupt */
I2C3_IRQn = 37, /**< I2C-3 Interrupt */
I2C4_IRQn = 38, /**< I2C-4 Interrupt */
RDC_IRQn = 39, /**< RDC interrupt */
USB1_IRQn = 40, /**< USB1 Interrupt */
USB2_IRQn = 41, /**< USB2 Interrupt */
ISI_CH1_IRQn = 42, /**< ISI Camera Channel 1 Interrupt */
HDMI_TX_IRQn = 43, /**< HDMI TX Subsystem Interrupt */
PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */
PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */
GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
SCTR_IRQ0_IRQn = 47, /**< System Counter Interrupt 0 */
SCTR_IRQ1_IRQn = 48, /**< System Counter Interrupt 1 */
ANAMIX_IRQn = 49, /**< TempSensor (Temperature alarm and criticl alarm). */
I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
ISP1_IRQn = 74, /**< ISP 1 ISP Interrupts */
ISP2_IRQn = 75, /**< ISP 2 ISP Interrupts */
I2C5_IRQn = 76, /**< I2C-5 Interrupt */
I2C6_IRQn = 77, /**< I2C-6 Interrupt */
WDOG1_IRQn = 78, /**< Watchdog Timer reset */
WDOG2_IRQn = 79, /**< Watchdog Timer reset */
MIPI_CSI2_IRQn = 80, /**< MIPI CSI 2 Interrupt */
PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
CCM_IRQ1_IRQn = 85, /**< CCM Interrupt Request 1 */
CCM_IRQ2_IRQn = 86, /**< CCM Interrupt Request 2 */
GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
MU1_A53_IRQn = 88, /**< Interrupt to A53 (A53,M7 MU) */
SRC_IRQn = 89, /**< SRC interrupt request */
I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
RTIC_IRQn = 91, /**< RTIC Interrupt */
CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */
I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
MU1_M7_IRQn = 97, /**< Interrupt to M7 (A53, M7 MU) */
DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
DDR_IRQn = 99, /**< ddr Interrupt */
DEWARP_IRQn = 100, /**< Dewarp Interrupt */
CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
SDMA2_IRQn = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
SJC_IRQn = 104, /**< Interrupt triggered by SJC register */
CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
FlexSPI_IRQn = 107, /**< FlexSPI Interrupt */
TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
PDM_EVENT_IRQn = 109, /**< Digital Microphone interface interrupt */
PDM_ERROR_IRQn = 110, /**< Digital Microphone interface error interrupt */
I2S7_IRQn = 111, /**< SAI7 Receive / Transmit Interrupt */
PERFMON1_IRQn = 112, /**< General Interrupt */
PERFMON2_IRQn = 113, /**< General Interrupt */
CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
HS_CP0_IRQn = 116, /**< HS Interrupt Request */
CM7_CTI_IRQn = 117, /**< CTI trigger outputs from CM7 platform */
ENET1_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
ENET1_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
ENET1_IRQn = 120, /**< MAC 0 IRQ */
ENET1_1588_Timer_IRQn = 121, /**< MAC 0 1588 Timer Interrupt-synchronous */
ASRC_IRQn = 122, /**< ASRC Interrupt */
PCIE_CTRL1_0_IRQn = 123, /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 0 */
PCIE_CTRL1_1_IRQn = 124, /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 1 */
PCIE_CTRL1_2_IRQn = 125, /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 2 */
PCIE_CTRL1_3_IRQn = 126, /**< Coming from GLUE logic, of set/reset FF, driven by PCIE signals, interrupt 3 */
PCIE_EDMA_IRQn = 127, /**< Channels [63:32] interrupts requests */
AUDIO_XCVR0_IRQn = 128, /**< eARC Interrupt 0 */
AUDIO_XCVR1_IRQn = 129, /**< eARC Interrupt 1 */
AUD2HTX_IRQn = 130, /**< Audio to HDMI TX Audio Link Master Interrupt */
EDMA1_ERR_IRQn = 131, /**< Audio Subsystem eDMA Error Interrupt */
EDMA1_0_15_IRQn = 132, /**< Audio Subsystem eDMA Channel Interrupts, Logical OR of channels [15:0] */
EDMA1_16_31_IRQn = 133, /**< Audio Subsystem eDMA Channel Interrupts, Logical OR of channels [31:16] */
ENET_QOS_PMT_IRQn = 134, /**< ENET QOS TSN Interrupt from PMT */
ENET_QOS_IRQn = 135, /**< ENET QOS TSN LPI RX exit/Host System/RX/TX Channels[4:0] Interrupt */
MU2_A53_IRQn = 136, /**< Interrupt to A53 (A53, Audio Processor MU) */
MU2_AUDIO_IRQn = 137, /**< Interrupt to Audio Processor (A53, Audio Processor MU) */
MU3_M7_IRQn = 138, /**< Interrupt to M7 (M7, Audio Processor MU) */
MU3_AUDIO_IRQn = 139, /**< Interrupt to Audio Processor (M7, Audio Processor MU) */
PCIE_CTRL1_IRQn = 140, /**< RC/EP message transaction Interrupt */
PCIE_CTRL1_ERR_IRQn = 141, /**< RC/EP PME Message and Error Interrupt */
CAN_FD1_IRQn = 142, /**< CAN-FD1 Interrupt from bus off/line error/RX warning/TX warning/wakeup/match in PN/timeout in PN/busoff done/FD error */
CAN_FD1_ERROR_IRQn = 143, /**< CAN-FD1 Interrupt from correctable error/non correctable error int host/ non correctable error int internal */
CAN_FD2_IRQn = 144, /**< CAN-FD2 Interrupt from bus off/line error/RX warning/TX warning/wakeup/match in PN/timeout in PN/busoff done/FD error */
CAN_FD2_ERROR_IRQn = 145, /**< CAN-FD2 Interrupt from correctable error/non correctable error int host/ non correctable error int internal */
AUDIO_XCVR_IRQn = 146, /**< eARC PHY - SPDIF wakeup interrupt */
DDR_ERR_IRQn = 147, /**< DRAM Controller Error Interrupt */
USB1_WAKEUP_IRQn = 148, /**< USB-1 Wake-up Interrupt */
USB2_WAKEUP_IRQn = 149, /**< USB-2 Wake-up Interrupt */
MECC_IRQn = 150, /**< OCRAM Memory ECC Interrupt */
MECC_ERR_IRQn = 151, /**< OCRAM Memory ECC Error Interrupt */
MECC_S_IRQn = 152, /**< OCRAM_S Memory ECC Interrupt */
MECC_S_ERR_IRQn = 153 /**< OCRAM_S Memory ECC Error Interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M7 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
* @{
*/
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
#include "core_cm7.h" /* Core Peripheral Access Layer */
#include "system_MIMX8ML3_cm7.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_mux_ctl_pad
{
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SCL = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_HDMI_CEC = 141U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_HDMI_HPD = 142U, /**< IOMUXC SW_MUX_CTL_PAD index */
} iomuxc_sw_mux_ctl_pad_t;
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_pad_ctl_pad
{
kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SCL = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SDA = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_HDMI_CEC = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_HDMI_HPD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_CLKIN1 = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_CLKIN2 = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_CLKOUT1 = 154U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_CLKOUT2 = 155U, /**< IOMUXC SW_PAD_CTL_PAD index */
} iomuxc_sw_pad_ctl_pad_t;
/* @} */
/*!
* @brief Enumeration for the IOMUXC select input
*
* Defines the enumeration for the IOMUXC select input collections.
*/
typedef enum _iomuxc_select_input
{
kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 0U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 1U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 2U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 3U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT = 6U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1 = 7U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI3_MCLK_SELECT_INPUT = 8U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0 = 9U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT = 10U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_MCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0 = 14U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1 = 15U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2 = 16U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3 = 17U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT = 18U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT = 20U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_MCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0 = 23U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT = 24U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT = 25U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT = 26U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_MCLK_SELECT_INPUT = 27U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0 = 29U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT = 30U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT = 32U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_INPUT = 33U, /**< IOMUXC select input index */
kIOMUXC_AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT = 34U, /**< IOMUXC select input index */
kIOMUXC_CAN1_CANRX_SELECT_INPUT = 35U, /**< IOMUXC select input index */
kIOMUXC_CAN2_CANRX_SELECT_INPUT = 36U, /**< IOMUXC select input index */
kIOMUXC_CCM_GPC_PMIC_VFUNCTIONAL_READY_SELECT_INPUT = 37U, /**< IOMUXC select input index */
kIOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT = 38U, /**< IOMUXC select input index */
kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 39U, /**< IOMUXC select input index */
kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 40U, /**< IOMUXC select input index */
kIOMUXC_ECSPI1_SS_B_SELECT_INPUT_0 = 41U, /**< IOMUXC select input index */
kIOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT = 42U, /**< IOMUXC select input index */
kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 43U, /**< IOMUXC select input index */
kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 44U, /**< IOMUXC select input index */
kIOMUXC_ECSPI2_SS_B_SELECT_INPUT_0 = 45U, /**< IOMUXC select input index */
kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 46U, /**< IOMUXC select input index */
kIOMUXC_ENET1_MDIO_SELECT_INPUT = 47U, /**< IOMUXC select input index */
kIOMUXC_ENET1_RXDATA_0_SELECT_INPUT = 48U, /**< IOMUXC select input index */
kIOMUXC_ENET1_RXDATA_1_SELECT_INPUT = 49U, /**< IOMUXC select input index */
kIOMUXC_ENET1_RXEN_SELECT_INPUT = 50U, /**< IOMUXC select input index */
kIOMUXC_ENET1_RXERR_SELECT_INPUT = 51U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 52U, /**< IOMUXC select input index */
kIOMUXC_GPT1_CAPIN1_SELECT_INPUT = 53U, /**< IOMUXC select input index */
kIOMUXC_GPT1_CAPIN2_SELECT_INPUT = 54U, /**< IOMUXC select input index */
kIOMUXC_GPT1_CLKIN_SELECT_INPUT = 55U, /**< IOMUXC select input index */
kIOMUXC_PCIE_CLKREQ_B_SELECT_INPUT = 56U, /**< IOMUXC select input index */
kIOMUXC_I2C1_SCL_IN_SELECT_INPUT = 57U, /**< IOMUXC select input index */
kIOMUXC_I2C1_SDA_IN_SELECT_INPUT = 58U, /**< IOMUXC select input index */
kIOMUXC_I2C2_SCL_IN_SELECT_INPUT = 59U, /**< IOMUXC select input index */
kIOMUXC_I2C2_SDA_IN_SELECT_INPUT = 60U, /**< IOMUXC select input index */
kIOMUXC_I2C3_SCL_IN_SELECT_INPUT = 61U, /**< IOMUXC select input index */
kIOMUXC_I2C3_SDA_IN_SELECT_INPUT = 62U, /**< IOMUXC select input index */
kIOMUXC_I2C4_SCL_IN_SELECT_INPUT = 63U, /**< IOMUXC select input index */
kIOMUXC_I2C4_SDA_IN_SELECT_INPUT = 64U, /**< IOMUXC select input index */
kIOMUXC_I2C5_SCL_IN_SELECT_INPUT = 65U, /**< IOMUXC select input index */
kIOMUXC_I2C5_SDA_IN_SELECT_INPUT = 66U, /**< IOMUXC select input index */
kIOMUXC_I2C6_SCL_IN_SELECT_INPUT = 67U, /**< IOMUXC select input index */
kIOMUXC_I2C6_SDA_IN_SELECT_INPUT = 68U, /**< IOMUXC select input index */
kIOMUXC_ISP_FL_TRIG_0_SELECT_INPUT = 69U, /**< IOMUXC select input index */
kIOMUXC_ISP_FL_TRIG_1_SELECT_INPUT = 70U, /**< IOMUXC select input index */
kIOMUXC_ISP_SHUTTER_TRIG_0_SELECT_INPUT = 71U, /**< IOMUXC select input index */
kIOMUXC_ISP_SHUTTER_TRIG_1_SELECT_INPUT = 72U, /**< IOMUXC select input index */
kIOMUXC_UART1_UART_RTS_B_SELECT_INPUT = 73U, /**< IOMUXC select input index */
kIOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT = 74U, /**< IOMUXC select input index */
kIOMUXC_UART2_UART_RTS_B_SELECT_INPUT = 75U, /**< IOMUXC select input index */
kIOMUXC_UART2_UART_RXD_MUX_SELECT_INPUT = 76U, /**< IOMUXC select input index */
kIOMUXC_UART3_UART_RTS_B_SELECT_INPUT = 77U, /**< IOMUXC select input index */
kIOMUXC_UART3_UART_RXD_MUX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
kIOMUXC_UART4_UART_RTS_B_SELECT_INPUT = 79U, /**< IOMUXC select input index */
kIOMUXC_UART4_UART_RXD_MUX_SELECT_INPUT = 80U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT = 81U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_CARD_DET_SELECT_INPUT = 82U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_CMD_IN_SELECT_INPUT = 83U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT0_IN_SELECT_INPUT = 84U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT1_IN_SELECT_INPUT = 85U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT2_IN_SELECT_INPUT = 86U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT3_IN_SELECT_INPUT = 87U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT4_IN_SELECT_INPUT = 88U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT5_IN_SELECT_INPUT = 89U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT6_IN_SELECT_INPUT = 90U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_DAT7_IN_SELECT_INPUT = 91U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_STROBE_SELECT_INPUT = 92U, /**< IOMUXC select input index */
kIOMUXC_USDHC3_WP_ON_SELECT_INPUT = 93U, /**< IOMUXC select input index */
} iomuxc_select_input_t;
/*!
* @addtogroup rdc_mapping
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the RDC mapping
*
* Defines the structure for the RDC resource collections.
*/
typedef enum _rdc_master
{
kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
kRDC_Master_M7 = 1U, /**< ARM Cortex-M7 RDC Master */
kRDC_PCIE_CTRL1 = 2U, /**< Reserved */
kRDC_Master_SDMA3_PERIPH = 3U, /**< SDMA3 PERIPHERAL RDC Master */
kRDC_Master_SDMA3_BURST = 4U, /**< SDMA3 BURST RDC Master */
kRDC_Master_LCDIF1 = 5U, /**< LCDIF1 RDC Master */
kRDC_Master_ISI = 6U, /**< ISI PORT RDC Master */
kRDC_Master_NPU = 7U, /**< NPU RDC Master */
kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
kRDC_Master_DAP = 9U, /**< DAP RDC Master */
kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
kRDC_Master_USDHC3 = 17U, /**< USDHC3 RDC Master */
kRDC_Master_AUDIO_PROCESSOR = 18U, /**< AUDIO PROCESSOR RDC Master */
kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */
kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
kRDC_Master_SDMA2_SPBA2 = 24U, /**< SDMA2 to SPBA2 RDC Master */
kRDC_Master_SDMA3_SPBA2 = 25U, /**< SDMA3 to SPBA2 RDC Master */
kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
kRDC_Master_LCDIF2 = 27U, /**< LCDIF2 RDC Master */
kRDC_Master_HDMI_TX = 28U, /**< HDMI_TX RDC Master */
kRDC_Master_ENET2 = 29U, /**< ENET2 RDC Master */
kRDC_Master_GPU3D = 30U, /**< GPU3D RDC Master */
kRDC_Master_GPU2D = 31U, /**< GPU2D RDC Master */
kRDC_Master_VPU_G1 = 32U, /**< VPU_G1 RDC Master */
kRDC_Master_VPU_G2 = 33U, /**< VPU_G2 RDC Master */
kRDC_Master_VPU_VC8000E = 34U, /**< VPU_VC8000E RDC Master */
kRDC_Master_AUDIO_EDMA = 35U, /**< AUDIO_EDMA RDC Master */
kRDC_Master_ISP1 = 36U, /**< ISP1 RDC Master */
kRDC_Master_ISP2 = 37U, /**< ISP2 RDC Master */
kRDC_Master_DEWARP = 38U, /**< DEWARP RDC Master */
kRDC_Master_GIC500 = 39U, /**< GIC500 RDC Master */
} rdc_master_t;
typedef enum _rdc_mem
{
kRDC_Mem_MRC0_0 = 0U, /**< DEBUG(DAP). Region resolution 4KB. */
kRDC_Mem_MRC0_1 = 1U,
kRDC_Mem_MRC0_2 = 2U,
kRDC_Mem_MRC0_3 = 3U,
kRDC_Mem_MRC1_0 = 4U, /**< QSPI. Region resolution 4KB. */
kRDC_Mem_MRC1_1 = 5U,
kRDC_Mem_MRC1_2 = 6U,
kRDC_Mem_MRC1_3 = 7U,
kRDC_Mem_MRC1_4 = 8U,
kRDC_Mem_MRC1_5 = 9U,
kRDC_Mem_MRC1_6 = 10U,
kRDC_Mem_MRC1_7 = 11U,
kRDC_Mem_MRC2_0 = 12U, /**< OCRAM. Region resolution 128B. */
kRDC_Mem_MRC2_1 = 13U,
kRDC_Mem_MRC2_2 = 14U,
kRDC_Mem_MRC2_3 = 15U,
kRDC_Mem_MRC2_4 = 16U,
kRDC_Mem_MRC3_0 = 17U, /**< OCRAM_S. Region resolution 128B. */
kRDC_Mem_MRC3_1 = 18U,
kRDC_Mem_MRC3_2 = 19U,
kRDC_Mem_MRC3_3 = 20U,
kRDC_Mem_MRC3_4 = 21U,
kRDC_Mem_MRC4_0 = 22U, /**< TCM. Region resolution 128B. */
kRDC_Mem_MRC4_1 = 23U,
kRDC_Mem_MRC4_2 = 24U,
kRDC_Mem_MRC4_3 = 25U,
kRDC_Mem_MRC4_4 = 26U,
kRDC_Mem_MRC5_0 = 27U, /**< GIC. Region resolution 4KB. */
kRDC_Mem_MRC5_1 = 28U,
kRDC_Mem_MRC5_2 = 29U,
kRDC_Mem_MRC5_3 = 30U,
kRDC_Mem_MRC6_0 = 31U, /**< GPU. Region resolution 4KB. */
kRDC_Mem_MRC6_1 = 32U,
kRDC_Mem_MRC6_2 = 33U,
kRDC_Mem_MRC6_3 = 34U,
kRDC_Mem_MRC6_4 = 35U,
kRDC_Mem_MRC6_5 = 36U,
kRDC_Mem_MRC6_6 = 37U,
kRDC_Mem_MRC6_7 = 38U,
kRDC_Mem_MRC7_0 = 39U, /**< DRAM. Region resolution 4KB. */
kRDC_Mem_MRC7_1 = 40U,
kRDC_Mem_MRC7_2 = 41U,
kRDC_Mem_MRC7_3 = 42U,
kRDC_Mem_MRC7_4 = 43U,
kRDC_Mem_MRC7_5 = 44U,
kRDC_Mem_MRC7_6 = 45U,
kRDC_Mem_MRC7_7 = 46U,
kRDC_Mem_MRC8_0 = 47U, /**< DDRC(REG). Region resolution 4KB. */
kRDC_Mem_MRC8_1 = 48U,
kRDC_Mem_MRC8_2 = 49U,
kRDC_Mem_MRC8_3 = 50U,
kRDC_Mem_MRC8_4 = 51U,
kRDC_Mem_MRC9_0 = 52U, /**< PCIe1, USB1/2. Region resolution 4KB. */
kRDC_Mem_MRC9_1 = 53U,
kRDC_Mem_MRC9_2 = 54U,
kRDC_Mem_MRC9_3 = 55U,
kRDC_Mem_MRC9_4 = 56U,
kRDC_Mem_MRC9_5 = 57U,
kRDC_Mem_MRC9_6 = 58U,
kRDC_Mem_MRC9_7 = 59U,
kRDC_Mem_MRC10_0 = 60U, /**< VPU. Region resolution 4KB. */
kRDC_Mem_MRC10_1 = 61U,
kRDC_Mem_MRC10_2 = 62U,
kRDC_Mem_MRC10_3 = 63U,
kRDC_Mem_MRC11_0 = 64U, /**< NPU. Region resolution 4KB. */
kRDC_Mem_MRC11_1 = 65U,
kRDC_Mem_MRC11_2 = 66U,
kRDC_Mem_MRC11_3 = 67U,
kRDC_Mem_MRC12_0 = 68U, /**< AUDIO PROCESSOR. Region resolution 4KB. */
kRDC_Mem_MRC12_1 = 69U,
kRDC_Mem_MRC12_2 = 70U,
kRDC_Mem_MRC12_3 = 71U,
kRDC_Mem_MRC13_0 = 72U, /**< OCRAM_A. Region resolution 128B. */
kRDC_Mem_MRC13_1 = 73U,
kRDC_Mem_MRC13_2 = 74U,
kRDC_Mem_MRC13_3 = 75U,
kRDC_Mem_MRC13_4 = 76U,
} rdc_mem_t;
typedef enum _rdc_periph
{
kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
kRDC_Periph_MU2_A = 5U, /**< MU_2_A (A53, Audio Processor) RDC Peripheral */
kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
kRDC_Periph_OCRAM_MECC = 11U, /**< OCRAM MECC RDC Peripheral */
kRDC_Periph_OCRAM_S_MECC = 12U, /**< OCRAM_S MECC RDC Peripheral */
kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
kRDC_Periph_MU2_B = 16U, /**< MU_2_B (A53, Audio Processor) RDC Peripheral */
kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
kRDC_Periph_MU3_A = 18U, /**< MU_3_A (M7, Audio Processor) RDC Peripheral */
kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
kRDC_Periph_MU3_B = 31U, /**< MU_3_B (M7, Audio Processor) RDC Peripheral */
kRDC_Periph_ISI = 32U, /**< ISI RDC Peripheral */
kRDC_Periph_ISP0 = 33U, /**< ISP0 RDC Peripheral */
kRDC_Periph_ISP1 = 34U, /**< ISP1 RDC Peripheral */
kRDC_Periph_IPS_DEWARP = 35U, /**< IPS DEWARP RDC Peripheral */
kRDC_Periph_MIPI_CSI0 = 36U, /**< MIPI CSI0 RDC Peripheral */
kRDC_Periph_HSIOMIX_BLK_CTL = 37U, /**< HSIOMIX BLK CTL RDC Peripheral */
kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
kRDC_Periph_I2C5 = 45U, /**< I2C1 RDC Peripheral */
kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
kRDC_Periph_MIPI_CSI1 = 49U, /**< MIPI CSI1 RDC Peripheral */
kRDC_Periph_MIPI_DSI0 = 50U, /**< MIPI DSI0 RDC Peripheral */
kRDC_Periph_MEDIAMIX_BLK_CTL = 51U, /**< MEDIAMIX BLK CTL RDC Peripheral */
kRDC_Periph_LCDIF1 = 52U, /**< LCDIF1 RDC Peripheral */
kRDC_Periph_EDMA = 53U, /**< EDMA RDC Peripheral */
kRDC_Periph_EDMA_0_15 = 54U, /**< EDMA Channels [0:15] RDC Peripheral */
kRDC_Periph_EDMA_16_31 = 55U, /**< EDMA Channels [1:31] RDC Peripheral */
kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
kRDC_Periph_I2C6 = 57U, /**< I2C6 RDC Peripheral */
kRDC_Periph_CAAM = 58U, /**< CAAM RDC Peripheral */
kRDC_Periph_LCDIF2 = 59U, /**< LCDIF2 RDC Peripheral */
kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
kRDC_Periph_LVDS0 = 64U, /**< LVDS0 RDC Peripheral */
kRDC_Periph_LVDS1 = 65U, /**< LVDS1 RDC Peripheral */
kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
kRDC_Periph_HDMI_TX = 71U, /**< HDMI TX RDC Peripheral */
kRDC_Periph_IRQ_STEER = 72U, /**< IRQ STEER (Audio Processor) RDC Peripheral */
kRDC_Periph_SDMA2 = 73U, /**< SDMA2 RDC Peripheral */
kRDC_Periph_MU1_A = 74U, /**< MU1_A RDC Peripheral */
kRDC_Periph_MU1_B = 75U, /**< MU1_B RDC Peripheral */
kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */
kRDC_Periph_SAI2 = 79U, /**< SAI2 RDC Peripheral */
kRDC_Periph_SAI3 = 80U, /**< SAI3 RDC Peripheral */
kRDC_Periph_CAN_FD1 = 81U, /**< CAN_FD1 RDC Peripheral */
kRDC_Periph_SAI5 = 82U, /**< SAI5 RDC Peripheral */
kRDC_Periph_SAI6 = 83U, /**< SAI6 RDC Peripheral */
kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
kRDC_Periph_USDHC3 = 86U, /**< USDHC3 RDC Peripheral */
kRDC_Periph_PCIE_PHY1 = 87U, /**< PCIE PHY1 RDC Peripheral */
kRDC_Periph_HDMI_TX_AUDLNK_MSTR = 88U, /**< HDMI TX AUDLNK MSTR RDC Peripheral */
kRDC_Periph_CAN_FD2 = 89U, /**< CAN_FD2 RDC Peripheral */
kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
kRDC_Periph_AUDIO_BLK_CTRL = 92U, /**< AUDIO BLK CTRL RDC Peripheral */
kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
kRDC_Periph_ENET2_TSN = 95U, /**< ENET2 TSN RDC Peripheral */
kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
kRDC_Periph_SAI7 = 101U, /**< SAI7 RDC Peripheral */
kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
kRDC_Periph_PDM = 106U, /**< PDM (MICFIL) RDC Peripheral */
kRDC_Periph_AUDIO_XCVR_RX = 107U, /**< AUDIO XCVR RX RDC (eARC)Peripheral */
kRDC_Periph_SDMA3 = 109U, /**< SDMA3 RDC Peripheral */
kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
} rdc_periph_t;
/* @} */
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#else
#pragma push
#pragma anon_unions
#endif
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- AIPSTZ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
* @{
*/
/** AIPSTZ - Register Layout Typedef */
typedef struct {
__IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
uint8_t RESERVED_0[60];
__IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
__IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
__IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
__IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
__IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
} AIPSTZ_Type;
/* ----------------------------------------------------------------------------
-- AIPSTZ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
* @{
*/
/*! @name MPR - Master Priviledge Registers */
/*! @{ */
#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
/*! MPROT5
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
* 0bxx0x..This master is not trusted for write accesses.
* 0bxx1x..This master is trusted for write accesses.
* 0bx0xx..This master is not trusted for read accesses.
* 0bx1xx..This master is trusted for read accesses.
* 0b1xxx..Write accesses from this master are allowed to be buffered
*/
#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
/*! MPROT3
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
* 0bxx0x..This master is not trusted for write accesses.
* 0bxx1x..This master is trusted for write accesses.
* 0bx0xx..This master is not trusted for read accesses.
* 0bx1xx..This master is trusted for read accesses.
* 0b1xxx..Write accesses from this master are allowed to be buffered
*/
#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
/*! MPROT2
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
* 0bxx0x..This master is not trusted for write accesses.
* 0bxx1x..This master is trusted for write accesses.
* 0bx0xx..This master is not trusted for read accesses.
* 0bx1xx..This master is trusted for read accesses.
* 0b1xxx..Write accesses from this master are allowed to be buffered
*/
#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
/*! MPROT1
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
* 0bxx0x..This master is not trusted for write accesses.
* 0bxx1x..This master is trusted for write accesses.
* 0bx0xx..This master is not trusted for read accesses.
* 0bx1xx..This master is trusted for read accesses.
* 0b1xxx..Write accesses from this master are allowed to be buffered
*/
#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
/*! MPROT0
* 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
* 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
* 0bxx0x..This master is not trusted for write accesses.
* 0bxx1x..This master is trusted for write accesses.
* 0bx0xx..This master is not trusted for read accesses.
* 0bx1xx..This master is trusted for read accesses.
* 0b1xxx..Write accesses from this master are allowed to be buffered
*/
#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
/*! @} */
/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
/*! OPAC7
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
/*! OPAC6
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
/*! OPAC5
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
/*! OPAC4
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
/*! OPAC3
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
/*! OPAC2
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
/*! OPAC1
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
/*! OPAC0
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
/*! @} */
/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
/*! OPAC15
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
/*! OPAC14
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
/*! OPAC13
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
/*! OPAC12
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
/*! OPAC11
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
/*! OPAC10
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
/*! OPAC9
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
/*! OPAC8
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
/*! @} */
/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
/*! OPAC23
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
/*! OPAC22
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
/*! OPAC21
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
/*! OPAC20
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
/*! OPAC19
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
/*! OPAC18
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
/*! OPAC17
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
/*! OPAC16
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
/*! @} */
/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
/*! OPAC31
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
/*! OPAC30
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
/*! OPAC29
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
/*! OPAC28
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
/*! OPAC27
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
/*! OPAC26
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
/*! OPAC25
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
/*! OPAC24
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
/*! @} */
/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
/*! @{ */
#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
/*! OPAC33
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
/*! OPAC32
* 0bxxx0..Accesses from an untrusted master are allowed.
* 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
* the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
* 0bxx0x..This peripheral allows write accesses.
* 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
* error response and no peripheral access is initiated on the IPS bus.
* 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
* 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
* indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
* be set. If not, the access is terminated with an error response and no peripheral access is initiated
* on the IPS bus.
* 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
*/
#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AIPSTZ_Register_Masks */
/* AIPSTZ - Peripheral instance base addresses */
/** Peripheral AIPSTZ1 base address */
#define AIPSTZ1_BASE (0x301F0000u)
/** Peripheral AIPSTZ1 base pointer */
#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
/** Peripheral AIPSTZ2 base address */
#define AIPSTZ2_BASE (0x305F0000u)
/** Peripheral AIPSTZ2 base pointer */
#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
/** Peripheral AIPSTZ3 base address */
#define AIPSTZ3_BASE (0x309F0000u)
/** Peripheral AIPSTZ3 base pointer */
#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
/** Peripheral AIPSTZ4 base address */
#define AIPSTZ4_BASE (0x32DF0000u)
/** Peripheral AIPSTZ4 base pointer */
#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
/** Peripheral AIPSTZ5 base address */
#define AIPSTZ5_BASE (0x30DF0000u)
/** Peripheral AIPSTZ5 base pointer */
#define AIPSTZ5 ((AIPSTZ_Type *)AIPSTZ5_BASE)
/** Array initializer of AIPSTZ peripheral base addresses */
#define AIPSTZ_BASE_ADDRS { AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE, AIPSTZ5_BASE }
/** Array initializer of AIPSTZ peripheral base pointers */
#define AIPSTZ_BASE_PTRS { AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, AIPSTZ5 }
/*!
* @}
*/ /* end of group AIPSTZ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- APBH Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
* @{
*/
/** APBH - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
__IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
__IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
__IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
__IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
__IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
__IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
__IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
__IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
__IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
__IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
__IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
__IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
__I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
uint8_t RESERVED_1[12];
__IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
uint8_t RESERVED_2[156];
struct { /* offset: 0x100, array step: 0x70 */
__I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
uint8_t RESERVED_0[12];
__IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
uint8_t RESERVED_1[12];
__I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
uint8_t RESERVED_2[12];
__I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
uint8_t RESERVED_3[12];
__IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
uint8_t RESERVED_4[12];
__I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
uint8_t RESERVED_5[12];
__I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
uint8_t RESERVED_6[12];
} CH_CFGn[16];
__I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
} APBH_Type;
/* ----------------------------------------------------------------------------
-- APBH Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup APBH_Register_Masks APBH Register Masks
* @{
*/
/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
/*! @{ */
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
/*! CLKGATE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
#define APBH_CTRL0_RSVD0_SHIFT (16U)
#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
#define APBH_CTRL0_CLKGATE_SHIFT (30U)
#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
#define APBH_CTRL0_SFTRST_SHIFT (31U)
#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
/*! @{ */
#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
/*! CLKGATE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
/*! @{ */
#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
/*! CLKGATE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
/*! @{ */
#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
/*! CLKGATE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
/*! @} */
/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
/*! @{ */
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
/*! @} */
/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
/*! @{ */
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
/*! @} */
/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
/*! @{ */
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
/*! @} */
/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
/*! @{ */
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
/*! @} */
/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
/*! @{ */
#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
/*! CH0_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
/*! CH1_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
/*! CH2_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
/*! CH3_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
/*! CH4_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
/*! CH5_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
/*! CH6_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
/*! CH7_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
/*! CH8_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
/*! CH9_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
/*! CH10_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
/*! CH11_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
/*! CH12_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
/*! CH13_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
/*! CH14_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
/*! CH15_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
/*! @} */
/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
/*! @{ */
#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
/*! CH0_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
/*! CH1_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
/*! CH2_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
/*! CH3_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
/*! CH4_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
/*! CH5_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
/*! CH6_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
/*! CH7_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
/*! CH8_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
/*! CH9_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
/*! CH10_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
/*! CH11_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
/*! CH12_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
/*! CH13_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
/*! CH14_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
/*! CH15_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
/*! @} */
/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
/*! @{ */
#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
/*! CH0_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
/*! CH1_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
/*! CH2_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
/*! CH3_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
/*! CH4_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
/*! CH5_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
/*! CH6_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
/*! CH7_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
/*! CH8_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
/*! CH9_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
/*! CH10_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
/*! CH11_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
/*! CH12_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
/*! CH13_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
/*! CH14_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
/*! CH15_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
/*! @} */
/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
/*! @{ */
#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
/*! CH0_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
/*! CH1_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
/*! CH2_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
/*! CH3_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
/*! CH4_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
/*! CH5_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
/*! CH6_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
/*! CH7_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
/*! CH8_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
/*! CH9_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
/*! CH10_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
/*! CH11_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
/*! CH12_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
/*! CH13_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
/*! CH14_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
/*! CH15_ERROR_STATUS
* 0b0..An early termination from the device causes error IRQ.
* 0b1..An AHB bus error causes error IRQ.
*/
#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
/*! @} */
/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
/*! @{ */
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
/*! FREEZE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
/*! RESET_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
/*! @} */
/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
/*! @{ */
#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
/*! FREEZE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
/*! RESET_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
/*! @} */
/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
/*! @{ */
#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
/*! FREEZE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
/*! RESET_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
/*! @} */
/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
/*! @{ */
#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
/*! FREEZE_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
/*! RESET_CHANNEL
* 0b0000000000000001..NAND0
* 0b0000000000000010..NAND1
* 0b0000000000000100..NAND2
* 0b0000000000001000..NAND3
* 0b0000000000010000..NAND4
* 0b0000000000100000..NAND5
* 0b0000000001000000..NAND6
* 0b0000000010000000..NAND7
* 0b0000000100000000..SSP
*/
#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
/*! @} */
/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
/*! @{ */
#define APBH_DEVSEL_CH0_MASK (0x3U)
#define APBH_DEVSEL_CH0_SHIFT (0U)
#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
#define APBH_DEVSEL_CH1_MASK (0xCU)
#define APBH_DEVSEL_CH1_SHIFT (2U)
#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
#define APBH_DEVSEL_CH2_MASK (0x30U)
#define APBH_DEVSEL_CH2_SHIFT (4U)
#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
#define APBH_DEVSEL_CH3_MASK (0xC0U)
#define APBH_DEVSEL_CH3_SHIFT (6U)
#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
#define APBH_DEVSEL_CH4_MASK (0x300U)
#define APBH_DEVSEL_CH4_SHIFT (8U)
#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
#define APBH_DEVSEL_CH5_MASK (0xC00U)
#define APBH_DEVSEL_CH5_SHIFT (10U)
#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
#define APBH_DEVSEL_CH6_MASK (0x3000U)
#define APBH_DEVSEL_CH6_SHIFT (12U)
#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
#define APBH_DEVSEL_CH7_MASK (0xC000U)
#define APBH_DEVSEL_CH7_SHIFT (14U)
#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
#define APBH_DEVSEL_CH8_MASK (0x30000U)
#define APBH_DEVSEL_CH8_SHIFT (16U)
#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
#define APBH_DEVSEL_CH9_MASK (0xC0000U)
#define APBH_DEVSEL_CH9_SHIFT (18U)
#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
#define APBH_DEVSEL_CH10_MASK (0x300000U)
#define APBH_DEVSEL_CH10_SHIFT (20U)
#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
#define APBH_DEVSEL_CH11_MASK (0xC00000U)
#define APBH_DEVSEL_CH11_SHIFT (22U)
#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
#define APBH_DEVSEL_CH12_MASK (0x3000000U)
#define APBH_DEVSEL_CH12_SHIFT (24U)
#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
#define APBH_DEVSEL_CH13_MASK (0xC000000U)
#define APBH_DEVSEL_CH13_SHIFT (26U)
#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
#define APBH_DEVSEL_CH14_MASK (0x30000000U)
#define APBH_DEVSEL_CH14_SHIFT (28U)
#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
#define APBH_DEVSEL_CH15_SHIFT (30U)
#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
/*! @} */
/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
/*! @{ */
#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
/*! CH8
* 0b00..BURST0
* 0b01..BURST4
* 0b10..BURST8
*/
#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
/*! @} */
/*! @name DEBUG - AHB to APBH DMA Debug Register */
/*! @{ */
#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
/*! @} */
/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
/*! @{ */
#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
/*! @} */
/* The count of APBH_CH_CURCMDAR */
#define APBH_CH_CURCMDAR_COUNT (16U)
/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
/*! @{ */
#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
/*! @} */
/* The count of APBH_CH_NXTCMDAR */
#define APBH_CH_NXTCMDAR_COUNT (16U)
/*! @name CH_CMD - APBH DMA Channel n Command Register */
/*! @{ */
#define APBH_CH_CMD_COMMAND_MASK (0x3U)
#define APBH_CH_CMD_COMMAND_SHIFT (0U)
/*! COMMAND
* 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
* 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
* 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
* 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
* device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
* pointer if the peripheral sense line is false.
*/
#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
#define APBH_CH_CMD_CHAIN_MASK (0x4U)
#define APBH_CH_CMD_CHAIN_SHIFT (2U)
#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
/*! @} */
/* The count of APBH_CH_CMD */
#define APBH_CH_CMD_COUNT (16U)
/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
/*! @{ */
#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
/*! @} */
/* The count of APBH_CH_BAR */
#define APBH_CH_BAR_COUNT (16U)
/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
/*! @{ */
#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
#define APBH_CH_SEMA_PHORE_SHIFT (16U)
#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
/*! @} */
/* The count of APBH_CH_SEMA */
#define APBH_CH_SEMA_COUNT (16U)
/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
/*! STATEMACHINE
* 0b00000..This is the idle state of the DMA state machine.
* 0b00001..State in which the DMA is waiting to receive the first word of a command.
* 0b00010..State in which the DMA is waiting to receive the third word of a command.
* 0b00011..State in which the DMA is waiting to receive the second word of a command.
* 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
* 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
* 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
* PIO words when PIO count is greater than 1.
* 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
* 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
* 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
* 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
* 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
* 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
* 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
* 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
* 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
* 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
* 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
* effectively halts. A channel reset is required to exit this state
* 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
* 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
* indicates that the external device is ready.
*/
#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
#define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U)
#define APBH_CH_DEBUG1_RSVD1_SHIFT (5U)
#define APBH_CH_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
#define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U)
#define APBH_CH_DEBUG1_LOCK_SHIFT (25U)
#define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
#define APBH_CH_DEBUG1_READY_SHIFT (26U)
#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
#define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U)
#define APBH_CH_DEBUG1_SENSE_SHIFT (27U)
#define APBH_CH_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
#define APBH_CH_DEBUG1_END_SHIFT (28U)
#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
/*! @} */
/* The count of APBH_CH_DEBUG1 */
#define APBH_CH_DEBUG1_COUNT (16U)
/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
/*! @{ */
#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
/*! @} */
/* The count of APBH_CH_DEBUG2 */
#define APBH_CH_DEBUG2_COUNT (16U)
/*! @name VERSION - APBH Bridge Version Register */
/*! @{ */
#define APBH_VERSION_STEP_MASK (0xFFFFU)
#define APBH_VERSION_STEP_SHIFT (0U)
#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
#define APBH_VERSION_MINOR_MASK (0xFF0000U)
#define APBH_VERSION_MINOR_SHIFT (16U)
#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
#define APBH_VERSION_MAJOR_SHIFT (24U)
#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group APBH_Register_Masks */
/* APBH - Peripheral instance base addresses */
/** Peripheral APBH base address */
#define APBH_BASE (0x33000000u)
/** Peripheral APBH base pointer */
#define APBH ((APBH_Type *)APBH_BASE)
/** Array initializer of APBH peripheral base addresses */
#define APBH_BASE_ADDRS { APBH_BASE }
/** Array initializer of APBH peripheral base pointers */
#define APBH_BASE_PTRS { APBH }
/** Interrupt vectors for the APBH peripheral type */
#define APBH_IRQS { APBHDMA_IRQn }
/*!
* @}
*/ /* end of group APBH_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ASRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
* @{
*/
/** ASRC - Register Layout Typedef */
typedef struct {
__O uint32_t WRFIFO[4]; /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */
__I uint32_t RDFIFO[4]; /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */
__IO uint32_t CTX_CTRL[4]; /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */
__IO uint32_t CTX_CTRL_EXT1[4]; /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */
__IO uint32_t CTX_CTRL_EXT2[4]; /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */
__IO uint32_t CTRL_IN_ACCESS[4]; /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT0_R0[4]; /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT0_R1[4]; /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT0_R2[4]; /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT0_R3[4]; /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT1_R0[4]; /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT1_R1[4]; /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT1_R2[4]; /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array step: 0x4 */
__IO uint32_t PROC_CTRL_SLOT1_R3[4]; /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array step: 0x4 */
__IO uint32_t CTX_OUT_CTRL[4]; /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */
__IO uint32_t CTRL_OUT_ACCESS[4]; /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */
__I uint32_t SAMPLE_FIFO_STATUS[4]; /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */
struct { /* offset: 0x110, array step: 0x8 */
__IO uint32_t RS_RATIO_LOW; /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */
__IO uint32_t RS_RATIO_HIGH; /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */
} RS_RATIO_LOW[4];
__IO uint32_t RS_UPDATE_CTRL[4]; /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */
__IO uint32_t RS_UPDATE_RATE[4]; /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */
__IO uint32_t RS_CT_LOW; /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */
__IO uint32_t RS_CT_HIGH; /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */
uint8_t RESERVED_0[8];
__IO uint32_t PRE_COEFF_FIFO[4]; /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */
__O uint32_t CTX_RS_COEFF_MEM; /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */
__IO uint32_t CTX_RS_COEFF_CTRL; /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */
__IO uint32_t IRQ_CTRL; /**< ASRC Interrupt Control, offset: 0x178 */
__IO uint32_t IRQ_FLAGS; /**< ASRC Interrupt Status Flags, offset: 0x17C */
__IO uint32_t CHANNEL_STATUS_0[4]; /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */
__IO uint32_t CHANNEL_STATUS_1[4]; /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */
__IO uint32_t CHANNEL_STATUS_2[4]; /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */
__IO uint32_t CHANNEL_STATUS_3[4]; /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */
__IO uint32_t CHANNEL_STATUS_4[4]; /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */
__IO uint32_t CHANNEL_STATUS_5[4]; /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */
} ASRC_Type;
/* ----------------------------------------------------------------------------
-- ASRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASRC_Register_Masks ASRC Register Masks
* @{
*/
/*! @name WRFIFO - ASRC Input Write FIFO */
/*! @{ */
#define ASRC_WRFIFO_CTX_WR_DATA_MASK (0xFFFFFFFFU)
#define ASRC_WRFIFO_CTX_WR_DATA_SHIFT (0U)
/*! CTX_WR_DATA - Write Data For CTX Input FIFO
*/
#define ASRC_WRFIFO_CTX_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK)
/*! @} */
/* The count of ASRC_WRFIFO */
#define ASRC_WRFIFO_COUNT (4U)
/*! @name RDFIFO - ASRC Output Read FIFO */
/*! @{ */
#define ASRC_RDFIFO_CTX_RD_DATA_MASK (0xFFFFFFFFU)
#define ASRC_RDFIFO_CTX_RD_DATA_SHIFT (0U)
/*! CTX_RD_DATA - Read Data For CTX Output FIFO
*/
#define ASRC_RDFIFO_CTX_RD_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK)
/*! @} */
/* The count of ASRC_RDFIFO */
#define ASRC_RDFIFO_COUNT (4U)
/*! @name CTX_CTRL - ASRC Context Control */
/*! @{ */
#define ASRC_CTX_CTRL_NUM_CH_EN_MASK (0x1FU)
#define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT (0U)
/*! NUM_CH_EN - Number of Channels In Context
*/
#define ASRC_CTX_CTRL_NUM_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK)
#define ASRC_CTX_CTRL_SIGN_IN_MASK (0x40U)
#define ASRC_CTX_CTRL_SIGN_IN_SHIFT (6U)
/*! SIGN_IN - Input Data Sign
* 0b0..Signed Format
* 0b1..Unsigned Format
*/
#define ASRC_CTX_CTRL_SIGN_IN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK)
#define ASRC_CTX_CTRL_FLOAT_FMT_MASK (0x80U)
#define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT (7U)
/*! FLOAT_FMT - Context Input Floating Point Format
* 0b0..Integer Format
* 0b1..Single Precision Floating Point Format
*/
#define ASRC_CTX_CTRL_FLOAT_FMT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK)
#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
* 0b00..16-bits Per Sample
* 0b01..20-bits Per Sample
* 0b10..24-bits Per Sample
* 0b11..32-bits Per Sample
*/
#define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK)
#define ASRC_CTX_CTRL_BIT_REV_MASK (0x400U)
#define ASRC_CTX_CTRL_BIT_REV_SHIFT (10U)
/*! BIT_REV - Sample Bit Reversal
* 0b0..Keep Input Ordering
* 0b1..Reverse Bit Ordering
*/
#define ASRC_CTX_CTRL_BIT_REV(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK)
#define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK (0xF800U)
#define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT (11U)
/*! SAMPLE_POSITION - Sample Position
*/
#define ASRC_CTX_CTRL_SAMPLE_POSITION(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK)
#define ASRC_CTX_CTRL_FIFO_WTMK_MASK (0x7F0000U)
#define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT (16U)
/*! FIFO_WTMK - Context Input FIFO Watermark
*/
#define ASRC_CTX_CTRL_FIFO_WTMK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK)
#define ASRC_CTX_CTRL_FWMDE_MASK (0x10000000U)
#define ASRC_CTX_CTRL_FWMDE_SHIFT (28U)
/*! FWMDE - FIFO Watermark DMA Enable
* 0b0..Input DMA Requests Not Enabled for This Context
* 0b1..Input DMA Requests Enabled for This Context
*/
#define ASRC_CTX_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK)
#define ASRC_CTX_CTRL_RUN_STOP_MASK (0x20000000U)
#define ASRC_CTX_CTRL_RUN_STOP_SHIFT (29U)
/*! RUN_STOP - Context Run Stop
*/
#define ASRC_CTX_CTRL_RUN_STOP(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK)
#define ASRC_CTX_CTRL_RUN_EN_MASK (0x80000000U)
#define ASRC_CTX_CTRL_RUN_EN_SHIFT (31U)
/*! RUN_EN - Context Run Enable
*/
#define ASRC_CTX_CTRL_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK)
/*! @} */
/* The count of ASRC_CTX_CTRL */
#define ASRC_CTX_CTRL_COUNT (4U)
/*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */
/*! @{ */
#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK (0x3U)
#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT (0U)
/*! PF_INIT_MODE - Prefilter Initialization Mode
* 0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index prefilter filter tap.
* 0b01..Replicate the first sample to fill the right half of the prefilter.
* 0b10..Zero fill the right half of the prefilter.
* 0b11..N/A
*/
#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK (0xCU)
#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT (2U)
/*! RS_INIT_MODE - Resampler Initialization Mode
* 0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest index resampling filter tap.
* 0b01..Replicate the first prefilter output sample to fill the right half of the resampler.
* 0b10..Fill the right half of the re-sampler with zeros.
* 0b11..N/A
*/
#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK (0x10U)
#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT (4U)
/*! PF_STOP_MODE - Pre-Filter Stop Mode
* 0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP.
* 0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP.
*/
#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK (0x20U)
#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT (5U)
/*! RS_STOP_MODE - Resampler Stop Mode
* 0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP.
* 0b1..Zero-Fill the left-half of the resampler on RUN_STOP.
*/
#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK (0x40U)
#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT (6U)
/*! PF_BYPASS_MODE - Prefilter Bypass Mode
* 0b0..Run the prefilter in normal operation.
* 0b1..Run the prefilter in bypass mode.
*/
#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK (0x80U)
#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT (7U)
/*! RS_BYPASS_MODE - Resampler Bypass Mode
* 0b0..Run the resampler in normal operation.
* 0b1..Run the resampler in bypass mode.
*/
#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK (0x100U)
#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U)
/*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable
* 0b0..The pre-filter will run in single stage mode (ST1 only)
* 0b1..The pre-filter will run in two stage mode (ST1 and ST2)
*/
#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK (0x200U)
#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U)
/*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point
* 0b0..The pre-filter stage1 results are stored in 32-bit integer format.
* 0b1..The pre-filter stage1 results are stored in 32-bit floating point format.
*/
#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U)
#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U)
/*! PF_EXPANSION_FACTOR - Prefilter IFIR Expansion Factor
*/
#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U)
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U)
/*! PF_COEFF_MEM_RST - Prefilter Coefficient Memory Reset
*/
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK)
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U)
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U)
/*! PF_COEFF_STAGE_WR - Prefilter Coefficient Write Select
*/
#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK)
/*! @} */
/* The count of ASRC_CTX_CTRL_EXT1 */
#define ASRC_CTX_CTRL_EXT1_COUNT (4U)
/*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */
/*! @{ */
#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK (0x1FFU)
#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT (0U)
/*! ST1_NUM_TAPS - Prefilter Stage1 Number of Taps
*/
#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK)
#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK (0x1FF0000U)
#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT (16U)
/*! ST2_NUM_TAPS - Prefilter Stage2 Number of Taps
*/
#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK)
/*! @} */
/* The count of ASRC_CTX_CTRL_EXT2 */
#define ASRC_CTX_CTRL_EXT2_COUNT (4U)
/*! @name CTRL_IN_ACCESS - ASRC Control Input Access */
/*! @{ */
#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT (0U)
/*! ACCESS_LENGTH - Number Of Channels Per Source
*/
#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK)
#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT (8U)
/*! GROUP_LENGTH - Number of Channels in a Context
*/
#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK)
#define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK (0x3F0000U)
#define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT (16U)
/*! ITERATIONS - Number of Sequential Fetches Per Source
*/
#define ASRC_CTRL_IN_ACCESS_ITERATIONS(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK)
/*! @} */
/* The count of ASRC_CTRL_IN_ACCESS */
#define ASRC_CTRL_IN_ACCESS_COUNT (4U)
/*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK (0x1U)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT (0U)
/*! SLOT0_EN - SLOT0 Enable
* 0b0..Context SLOT0 is disabled
* 0b1..Context SLOT0 is enabled
*/
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U)
/*! SLOT0_CTX_NUM - Context SLOT0 Selection
*/
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U)
/*! SLOT0_NUM_CH - SLOT0 Number of Channels
* 0b00000..Context SLOT0 owns 1 of 8 channels
* 0b00001..Context SLOT0 owns 2 of 8 channels
* 0b00010..Context SLOT0 owns 3 of 8 channels
* 0b00011-0b00111..Context SLOT0 owns N of 8 channels
*/
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U)
/*! SLOT0_MIN_CH - SLOT0 Minimum Global Channel Number
*/
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U)
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U)
/*! SLOT0_MAX_CH - SLOT0 Maximum Global Channel Number
*/
#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT0_R0 */
#define ASRC_PROC_CTRL_SLOT0_R0_COUNT (4U)
/*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U)
/*! SLOT0_ST1_CHANxEXP - SLOT0 Stage1 Channels x Expansion Factor
*/
#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT0_R1 */
#define ASRC_PROC_CTRL_SLOT0_R1_COUNT (4U)
/*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U)
/*! SLOT0_ST1_ST_ADDR - SLOT0 Stage1 Start Address
*/
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK)
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U)
/*! SLOT0_ST1_MEM_ALLOC - SLOT0 Stage1 Memory Allocation
*/
#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT0_R2 */
#define ASRC_PROC_CTRL_SLOT0_R2_COUNT (4U)
/*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U)
/*! SLOT0_ST2_ST_ADDR - SLOT0 Stage2 Start Address
*/
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK)
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U)
/*! SLOT0_ST2_MEM_ALLOC - SLOT0 Stage2 Memory Allocation
*/
#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT0_R3 */
#define ASRC_PROC_CTRL_SLOT0_R3_COUNT (4U)
/*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK (0x1U)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT (0U)
/*! SLOT1_EN - SLOT1 Enable
* 0b0..Context SLOT1 is disabled
* 0b1..Context SLOT1 is enabled
*/
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U)
/*! SLOT1_CTX_NUM - Context SLOT1 Selection
*/
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U)
/*! SLOT1_NUM_CH - SLOT1 Number of Channels
* 0b00000..Context SLOT1 owns 1 of 8 channels
* 0b00001..Context SLOT1 owns 2 of 8 channels
* 0b00010..Context SLOT1 owns 3 of 8 channels
* 0b00011-0b00111..Context SLOT1 owns N of 8 channels
*/
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U)
/*! SLOT1_MIN_CH - Slot1 Minimum Global Channel Number
*/
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U)
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U)
/*! SLOT1_MAX_CH - Slot1 Maximum Global Channel Number
*/
#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT1_R0 */
#define ASRC_PROC_CTRL_SLOT1_R0_COUNT (4U)
/*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U)
/*! SLOT1_ST1_CHANxEXP - SLOT1 Stage1 Channels x Expansion Factor
*/
#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT1_R1 */
#define ASRC_PROC_CTRL_SLOT1_R1_COUNT (4U)
/*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U)
/*! SLOT1_ST1_ST_ADDR - SLOT1 Stage1 Start Address
*/
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK)
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U)
/*! SLOT1_ST1_MEM_ALLOC - SLOT1 Stage1 Memory Allocation
*/
#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT1_R2 */
#define ASRC_PROC_CTRL_SLOT1_R2_COUNT (4U)
/*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */
/*! @{ */
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU)
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U)
/*! SLOT1_ST2_ST_ADDR - SLOT1 Stage2 Start Address
*/
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK)
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U)
/*! SLOT1_ST2_MEM_ALLOC - SLOT1 Stage2 Memory Allocation
*/
#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK)
/*! @} */
/* The count of ASRC_PROC_CTRL_SLOT1_R3 */
#define ASRC_PROC_CTRL_SLOT1_R3_COUNT (4U)
/*! @name CTX_OUT_CTRL - ASRC Context Output Control */
/*! @{ */
#define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK (0x1U)
#define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT (0U)
/*! DITHER_EN - Output Dither Enable
*/
#define ASRC_CTX_OUT_CTRL_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK)
#define ASRC_CTX_OUT_CTRL_IEC_EN_MASK (0x2U)
#define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT (1U)
/*! IEC_EN - IEC60958 Bit-Field Insertion Enable
* 0b0..No Data Insertion Enabled.
* 0b1..IEC60958 Bit-Field Insertion Enabled.
*/
#define ASRC_CTX_OUT_CTRL_IEC_EN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK)
#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK (0x4U)
#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT (2U)
/*! IEC_V_DATA - IEC60958 Validity Flag
*/
#define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK)
#define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK (0x40U)
#define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT (6U)
/*! SIGN_OUT - Output Data Sign
* 0b0..Signed Format
* 0b1..Convert to Unsigned
*/
#define ASRC_CTX_OUT_CTRL_SIGN_OUT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK)
#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK (0x80U)
#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT (7U)
/*! FLOAT_FMT - Context Output Floating Point Format
* 0b0..Integer Format
* 0b1..Single Precision Floating Point Format
*/
#define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK)
#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
* 0b00..16-bits Per Sample
* 0b01..20-bits Per Sample
* 0b10..24-bits Per Sample
* 0b11..32-bits Per Sample
*/
#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK)
#define ASRC_CTX_OUT_CTRL_BIT_REV_MASK (0x400U)
#define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT (10U)
/*! BIT_REV - Sample Bit-Reversal
* 0b0..No change.
* 0b1..Bit-reverse sample data.
*/
#define ASRC_CTX_OUT_CTRL_BIT_REV(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK)
#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK (0xF800U)
#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT (11U)
/*! SAMPLE_POSITION - Sample Position
*/
#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK)
#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK (0x7F0000U)
#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT (16U)
/*! FIFO_WTMK - Context Output FIFO Watermark
*/
#define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK)
#define ASRC_CTX_OUT_CTRL_FWMDE_MASK (0x10000000U)
#define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT (28U)
/*! FWMDE - Output FIFO Watermark DMA Enable
* 0b0..Output DMA Requests Not Enabled for This Context
* 0b1..Output DMA Requests Enabled for This Context
*/
#define ASRC_CTX_OUT_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK)
/*! @} */
/* The count of ASRC_CTX_OUT_CTRL */
#define ASRC_CTX_OUT_CTRL_COUNT (4U)
/*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */
/*! @{ */
#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U)
/*! ACCESS_LENGTH - Number Of Channels Per Destination
*/
#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK)
#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT (8U)
/*! GROUP_LENGTH - Number of Channels in a Context
*/
#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK)
#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK (0x3F0000U)
#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT (16U)
/*! ITERATIONS - Number of Sequential Fetches Per Channel Group
*/
#define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK)
/*! @} */
/* The count of ASRC_CTRL_OUT_ACCESS */
#define ASRC_CTRL_OUT_ACCESS_COUNT (4U)
/*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */
/*! @{ */
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU)
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U)
/*! NUM_SAMPLE_GROUPS_OUT - Number Of Sample Groups Stored in the output FIFO
*/
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK)
#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U)
#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U)
/*! OUTFIFO_WTMK - Output FIFO Watermark Flag
*/
#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK)
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U)
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U)
/*! NUM_SAMPLE_GROUPS_IN - Number Of Sample Groups Stored in Input FIFO
*/
#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK)
#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U)
#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U)
/*! INFIFO_WTMK - Input FIFO Watermark Flag
*/
#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK)
/*! @} */
/* The count of ASRC_SAMPLE_FIFO_STATUS */
#define ASRC_SAMPLE_FIFO_STATUS_COUNT (4U)
/*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */
/*! @{ */
#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK (0xFFFFFFFFU)
#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT (0U)
/*! RS_RATIO_LOW - Resampling Ratio Low
*/
#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK)
/*! @} */
/* The count of ASRC_RS_RATIO_LOW */
#define ASRC_RS_RATIO_LOW_COUNT (4U)
/*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */
/*! @{ */
#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK (0xFFFU)
#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT (0U)
/*! RS_RATIO_HIGH - Resampling Ratio High
*/
#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK)
#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK (0x80000000U)
#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT (31U)
/*! RS_RATIO_VLD - Resampling Ratio Valid
*/
#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK)
/*! @} */
/* The count of ASRC_RS_RATIO_HIGH */
#define ASRC_RS_RATIO_HIGH_COUNT (4U)
/*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */
/*! @{ */
#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK (0xFFFFFFFFU)
#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT (0U)
/*! RS_RATIO_MOD - Resampling Ratio Modifier
*/
#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK)
/*! @} */
/* The count of ASRC_RS_UPDATE_CTRL */
#define ASRC_RS_UPDATE_CTRL_COUNT (4U)
/*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */
/*! @{ */
#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU)
#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U)
/*! RS_RATIO_RAMP_RATE - Resampling Ratio Ramp Rate
*/
#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK)
/*! @} */
/* The count of ASRC_RS_UPDATE_RATE */
#define ASRC_RS_UPDATE_RATE_COUNT (4U)
/*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */
/*! @{ */
#define ASRC_RS_CT_LOW_RS_CT_LOW_MASK (0xFFFFFFFFU)
#define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT (0U)
/*! RS_CT_LOW - Resampling Center Tap Coefficient LSBs
*/
#define ASRC_RS_CT_LOW_RS_CT_LOW(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK)
/*! @} */
/*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */
/*! @{ */
#define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK (0xFFFFFFFFU)
#define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT (0U)
/*! RS_CT_HIGH - Resampling Center Tap Coefficient MSBs
*/
#define ASRC_RS_CT_HIGH_RS_CT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK)
/*! @} */
/*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */
/*! @{ */
#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK (0xFFFFFFFFU)
#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT (0U)
/*! COEFF_DATA - Coefficient Value For Prefilter
*/
#define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK)
/*! @} */
/* The count of ASRC_PRE_COEFF_FIFO */
#define ASRC_PRE_COEFF_FIFO_COUNT (4U)
/*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */
/*! @{ */
#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU)
#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U)
/*! RS_COEFF_WDATA - Resampling Coefficient Write Data
*/
#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK)
/*! @} */
/*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */
/*! @{ */
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U)
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U)
/*! RS_COEFF_PTR_RST - Resampling Coefficient Write Pointer Reset
*/
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK)
#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U)
#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U)
/*! NUM_RES_TAPS - Number of Resampling Coefficient Taps
* 0b00..32-Tap Resampling Filter
* 0b01..64-Tap Resampling Filter
* 0b10..128-Tap Resampling Filter
* 0b11..N/A
*/
#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK)
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U)
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U)
/*! RS_COEFF_ADDR - Resampling Coefficient Address
*/
#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK)
/*! @} */
/*! @name IRQ_CTRL - ASRC Interrupt Control */
/*! @{ */
#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK (0xFU)
#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT (0U)
/*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask
* 0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3.
* 0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3.
* 0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
* 0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field.
* 0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3.
*/
#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK)
#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U)
#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U)
/*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask
* 0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3.
* 0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3.
* 0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
* 0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field.
* 0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3.
*/
#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK)
#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK (0xF00U)
#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT (8U)
/*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK
* 0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3.
* 0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3.
* 0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
* 0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field.
* 0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3.
*/
#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK)
/*! @} */
/*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */
/*! @{ */
#define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK (0xFU)
#define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT (0U)
/*! INFIFO_OVF - ASRC Input FIFO Overflow Flag
* 0b0000..No INFIFO_OVF errors have been recorded.
* 0b0001..The ASRC_WRFIFO0 has overflown.
* 0b0010..The ASRC_WRFIFO1 has overflown.
* 0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1.
* 0b1111..ASRC_WRFIFO0, ASRC_WRFIFO1, ASRC_WRFIFO2, and ASRC_WRFIFO3 have overflown.
*/
#define ASRC_IRQ_FLAGS_INFIFO_OVF(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT)) & ASRC_IRQ_FLAGS_INFIFO_OVF_MASK)
#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK (0xF0U)
#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT (4U)
/*! OUTFIFO_EMPTY_RD - ASRC Output FIFO Empty Read Flag
* 0b0000..No reads have been requested from an empty ASRC_RDFIFO.
* 0b0001..A read has been requested from ASRC_RDFIFO0 when it was empty.
* 0b0010..A read has been requested from ASRC_RDFIFO1 when it was empty.
* 0b0011-0b1110..A read has been requested from ASRC_RDFIFOn when it was empty. n = any bit position with a 0b1.
* 0b1111..A read has been requested from ASRC_RDFIFO0, ASRC_RDFIFO1, ASRC_RDFIFO2, and ASRC_RDFIFO3 while empty.
*/
#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT)) & ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK)
#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK (0xF00U)
#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT (8U)
/*! RUN_STOP_DONE - ASRC RUN STOP DONE FLAG
* 0b0000..No RUN_STOP operations have been completed.
* 0b0001..The RUN_STOP operation for Context 0 has completed.
* 0b0010..The RUN_STOP operation for Context 1 has completed.
* 0b0011-0b1110..The RUN_STOP operation has completed for any context with a 1'b1 bit field.
* 0b1111..The RUN_STOP operation has completed for Context 0 to 3.
*/
#define ASRC_IRQ_FLAGS_RUN_STOP_DONE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT)) & ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK)
/*! @} */
/*! @name CHANNEL_STATUS_0 - ASRC Channel Status 0 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_0_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_0 */
#define ASRC_CHANNEL_STATUS_0_COUNT (4U)
/*! @name CHANNEL_STATUS_1 - ASRC Channel Status 1 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_1_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_1 */
#define ASRC_CHANNEL_STATUS_1_COUNT (4U)
/*! @name CHANNEL_STATUS_2 - ASRC Channel Status 2 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_2_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_2 */
#define ASRC_CHANNEL_STATUS_2_COUNT (4U)
/*! @name CHANNEL_STATUS_3 - ASRC Channel Status 3 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_3_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_3 */
#define ASRC_CHANNEL_STATUS_3_COUNT (4U)
/*! @name CHANNEL_STATUS_4 - ASRC Channel Status 4 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_4_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_4 */
#define ASRC_CHANNEL_STATUS_4_COUNT (4U)
/*! @name CHANNEL_STATUS_5 - ASRC Channel Status 5 */
/*! @{ */
#define ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK (0xFFFFFFFFU)
#define ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT (0U)
/*! CHN_STAT - Channel Status Data
*/
#define ASRC_CHANNEL_STATUS_5_CHN_STAT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK)
/*! @} */
/* The count of ASRC_CHANNEL_STATUS_5 */
#define ASRC_CHANNEL_STATUS_5_COUNT (4U)
/*!
* @}
*/ /* end of group ASRC_Register_Masks */
/* ASRC - Peripheral instance base addresses */
/** Peripheral ASRC base address */
#define ASRC_BASE (0x30C90000u)
/** Peripheral ASRC base pointer */
#define ASRC ((ASRC_Type *)ASRC_BASE)
/** Array initializer of ASRC peripheral base addresses */
#define ASRC_BASE_ADDRS { ASRC_BASE }
/** Array initializer of ASRC peripheral base pointers */
#define ASRC_BASE_PTRS { ASRC }
/*!
* @}
*/ /* end of group ASRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AUDIOMIX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOMIX_Peripheral_Access_Layer AUDIOMIX Peripheral Access Layer
* @{
*/
/** AUDIOMIX - Register Layout Typedef */
typedef struct {
__IO uint32_t CLKEN0; /**< IP Clock Enable Control Register 0, offset: 0x0 */
__IO uint32_t CLKEN1; /**< IP Clock Enable Control Register 1, offset: 0x4 */
uint8_t RESERVED_0[248];
__I uint32_t AUDIODSP_REG0; /**< AudioDSP EXPSTATE Register, offset: 0x100 */
__IO uint32_t AUDIODSP_REG1; /**< AudioDSP IMPWIRE Register, offset: 0x104 */
__IO uint32_t AUDIODSP_REG2; /**< AudioDSP XOCDMODE Register, offset: 0x108 */
__IO uint32_t AUDIODSP_REG3; /**< AudioDSP PID Register, offset: 0x10C */
uint8_t RESERVED_1[240];
__IO uint32_t EARC; /**< EARC Control Register, offset: 0x200 */
uint8_t RESERVED_2[252];
__IO uint32_t SAI1_MCLK_SEL; /**< SAI1 MCLK SELECT Register, offset: 0x300 */
__IO uint32_t SAI2_MCLK_SEL; /**< SAI2 MCLK SELECT Register, offset: 0x304 */
__IO uint32_t SAI3_MCLK_SEL; /**< SAI3 MCLK SELECT Register, offset: 0x308 */
__IO uint32_t SAI5_MCLK_SEL; /**< SAI5 MCLK SELECT Register, offset: 0x30C */
__IO uint32_t SAI6_MCLK_SEL; /**< SAI6 MCLK SELECT Register, offset: 0x310 */
__IO uint32_t SAI7_MCLK_SEL; /**< SAI7 MCLK SELECT Register, offset: 0x314 */
__IO uint32_t PDM_CLK; /**< PDM Root Clock Select Register, offset: 0x318 */
uint8_t RESERVED_3[228];
__IO uint32_t SAI_PLL_GNRL_CTL; /**< SAI PLL General control Register, offset: 0x400 */
__IO uint32_t SAI_PLL_FDIV_CTL0; /**< SAI PLL Frequency Divider control Register, offset: 0x404 */
__IO uint32_t SAI_PLL_FDIV_CTL1; /**< SAI PLL DSM value Register, offset: 0x408 */
__IO uint32_t SAI_PLL_SSCG_CTL; /**< SAI PLL SSCG control Register, offset: 0x40C */
__IO uint32_t SAI_PLL_MNIT_CTL; /**< SAI PLL SSCG control Register, offset: 0x410 */
uint8_t RESERVED_4[236];
__IO uint32_t AUDIO_EXT_ADDR; /**< AUDIOMIX Extra Addr Bits Register, offset: 0x500 */
__IO uint32_t IPG_LP_CTRL; /**< IPG Low Power Control Register, offset: 0x504 */
__IO uint32_t AUDIO_AXI_LIMIT; /**< AUDIOMIX AXI LIMIT CTRL Register, offset: 0x508 */
} AUDIOMIX_Type;
/* ----------------------------------------------------------------------------
-- AUDIOMIX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOMIX_Register_Masks AUDIOMIX Register Masks
* @{
*/
/*! @name CLKEN0 - IP Clock Enable Control Register 0 */
/*! @{ */
#define AUDIOMIX_CLKEN0_SAI1_MASK (0x1U)
#define AUDIOMIX_CLKEN0_SAI1_SHIFT (0U)
/*! SAI1 - SAI1 clock enable
* 0b1..SAI1 sai clock enable
* 0b0..SAI1 sai clock disable
*/
#define AUDIOMIX_CLKEN0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MASK)
#define AUDIOMIX_CLKEN0_SAI1_MCLK1_MASK (0x2U)
#define AUDIOMIX_CLKEN0_SAI1_MCLK1_SHIFT (1U)
/*! SAI1_MCLK1 - SAI1 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI1_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI1_MCLK2_MASK (0x4U)
#define AUDIOMIX_CLKEN0_SAI1_MCLK2_SHIFT (2U)
/*! SAI1_MCLK2 - SAI1 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI1_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI1_MCLK3_MASK (0x8U)
#define AUDIOMIX_CLKEN0_SAI1_MCLK3_SHIFT (3U)
/*! SAI1_MCLK3 - SAI1 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI1_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI1_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI1_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_SAI2_MASK (0x10U)
#define AUDIOMIX_CLKEN0_SAI2_SHIFT (4U)
/*! SAI2 - SAI2 clock enable
* 0b1..SAI2 sai clock enable
* 0b0..SAI2 sai clock disable
*/
#define AUDIOMIX_CLKEN0_SAI2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MASK)
#define AUDIOMIX_CLKEN0_SAI2_MCLK1_MASK (0x20U)
#define AUDIOMIX_CLKEN0_SAI2_MCLK1_SHIFT (5U)
/*! SAI2_MCLK1 - SAI2 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI2_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI2_MCLK2_MASK (0x40U)
#define AUDIOMIX_CLKEN0_SAI2_MCLK2_SHIFT (6U)
/*! SAI2_MCLK2 - SAI2 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI2_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI2_MCLK3_MASK (0x80U)
#define AUDIOMIX_CLKEN0_SAI2_MCLK3_SHIFT (7U)
/*! SAI2_MCLK3 - SAI2 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI2_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI2_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI2_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_SAI3_MASK (0x100U)
#define AUDIOMIX_CLKEN0_SAI3_SHIFT (8U)
/*! SAI3 - SAI3 clock enable
* 0b1..SAI3 sai clock enable
* 0b0..SAI3 sai clock disable
*/
#define AUDIOMIX_CLKEN0_SAI3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MASK)
#define AUDIOMIX_CLKEN0_SAI3_MCLK1_MASK (0x200U)
#define AUDIOMIX_CLKEN0_SAI3_MCLK1_SHIFT (9U)
/*! SAI3_MCLK1 - SAI3 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI3_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI3_MCLK2_MASK (0x400U)
#define AUDIOMIX_CLKEN0_SAI3_MCLK2_SHIFT (10U)
/*! SAI3_MCLK2 - SAI3 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI3_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI3_MCLK3_MASK (0x800U)
#define AUDIOMIX_CLKEN0_SAI3_MCLK3_SHIFT (11U)
/*! SAI3_MCLK3 - SAI3 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI3_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI3_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI3_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_SAI5_MASK (0x1000U)
#define AUDIOMIX_CLKEN0_SAI5_SHIFT (12U)
/*! SAI5 - SAI5 clock enable
* 0b1..SAI5 sai clock enable
* 0b0..SAI5 sai clock disable
*/
#define AUDIOMIX_CLKEN0_SAI5(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MASK)
#define AUDIOMIX_CLKEN0_SAI5_MCLK1_MASK (0x2000U)
#define AUDIOMIX_CLKEN0_SAI5_MCLK1_SHIFT (13U)
/*! SAI5_MCLK1 - SAI5 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI5_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI5_MCLK2_MASK (0x4000U)
#define AUDIOMIX_CLKEN0_SAI5_MCLK2_SHIFT (14U)
/*! SAI5_MCLK2 - SAI5 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI5_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI5_MCLK3_MASK (0x8000U)
#define AUDIOMIX_CLKEN0_SAI5_MCLK3_SHIFT (15U)
/*! SAI5_MCLK3 - SAI5 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI5_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI5_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI5_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_SAI6_MASK (0x10000U)
#define AUDIOMIX_CLKEN0_SAI6_SHIFT (16U)
/*! SAI6 - SAI6 clock enable
* 0b1..SAI6 IPG clock enable
* 0b0..SAI6 IPG clock disable
*/
#define AUDIOMIX_CLKEN0_SAI6(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MASK)
#define AUDIOMIX_CLKEN0_SAI6_MCLK1_MASK (0x20000U)
#define AUDIOMIX_CLKEN0_SAI6_MCLK1_SHIFT (17U)
/*! SAI6_MCLK1 - SAI6 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI6_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI6_MCLK2_MASK (0x40000U)
#define AUDIOMIX_CLKEN0_SAI6_MCLK2_SHIFT (18U)
/*! SAI6_MCLK2 - SAI6 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI6_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI6_MCLK3_MASK (0x80000U)
#define AUDIOMIX_CLKEN0_SAI6_MCLK3_SHIFT (19U)
/*! SAI6_MCLK3 - SAI6 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI6_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI6_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI6_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_SAI7_MASK (0x100000U)
#define AUDIOMIX_CLKEN0_SAI7_SHIFT (20U)
/*! SAI7 - SAI7 clock enable
* 0b1..SAI7 sai clock enable
* 0b0..SAI7 sai clock disable
*/
#define AUDIOMIX_CLKEN0_SAI7(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MASK)
#define AUDIOMIX_CLKEN0_SAI7_MCLK1_MASK (0x200000U)
#define AUDIOMIX_CLKEN0_SAI7_MCLK1_SHIFT (21U)
/*! SAI7_MCLK1 - SAI7 mclk1 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI7_MCLK1(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK1_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK1_MASK)
#define AUDIOMIX_CLKEN0_SAI7_MCLK2_MASK (0x400000U)
#define AUDIOMIX_CLKEN0_SAI7_MCLK2_SHIFT (22U)
/*! SAI7_MCLK2 - SAI7 mclk2 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI7_MCLK2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK2_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK2_MASK)
#define AUDIOMIX_CLKEN0_SAI7_MCLK3_MASK (0x800000U)
#define AUDIOMIX_CLKEN0_SAI7_MCLK3_SHIFT (23U)
/*! SAI7_MCLK3 - SAI7 mclk3 clock enable
*/
#define AUDIOMIX_CLKEN0_SAI7_MCLK3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SAI7_MCLK3_SHIFT)) & AUDIOMIX_CLKEN0_SAI7_MCLK3_MASK)
#define AUDIOMIX_CLKEN0_ASRC_MASK (0x1000000U)
#define AUDIOMIX_CLKEN0_ASRC_SHIFT (24U)
/*! ASRC - ASRC clock enable
*/
#define AUDIOMIX_CLKEN0_ASRC(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_ASRC_SHIFT)) & AUDIOMIX_CLKEN0_ASRC_MASK)
#define AUDIOMIX_CLKEN0_PDM_MASK (0x2000000U)
#define AUDIOMIX_CLKEN0_PDM_SHIFT (25U)
/*! PDM - PDM clock enable
*/
#define AUDIOMIX_CLKEN0_PDM(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_PDM_SHIFT)) & AUDIOMIX_CLKEN0_PDM_MASK)
#define AUDIOMIX_CLKEN0_SDMA2_MASK (0x4000000U)
#define AUDIOMIX_CLKEN0_SDMA2_SHIFT (26U)
/*! SDMA2 - SDMA2 clock enable
*/
#define AUDIOMIX_CLKEN0_SDMA2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SDMA2_SHIFT)) & AUDIOMIX_CLKEN0_SDMA2_MASK)
#define AUDIOMIX_CLKEN0_SDMA3_MASK (0x8000000U)
#define AUDIOMIX_CLKEN0_SDMA3_SHIFT (27U)
/*! SDMA3 - SDMA3 clock enable
*/
#define AUDIOMIX_CLKEN0_SDMA3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SDMA3_SHIFT)) & AUDIOMIX_CLKEN0_SDMA3_MASK)
#define AUDIOMIX_CLKEN0_SPBA2_MASK (0x10000000U)
#define AUDIOMIX_CLKEN0_SPBA2_SHIFT (28U)
/*! SPBA2 - SPBA2 clock enable
*/
#define AUDIOMIX_CLKEN0_SPBA2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_SPBA2_SHIFT)) & AUDIOMIX_CLKEN0_SPBA2_MASK)
#define AUDIOMIX_CLKEN0_AUDIODSP_MASK (0x20000000U)
#define AUDIOMIX_CLKEN0_AUDIODSP_SHIFT (29U)
/*! AudioDSP - AudioDSP core clock enable
*/
#define AUDIOMIX_CLKEN0_AUDIODSP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_AUDIODSP_SHIFT)) & AUDIOMIX_CLKEN0_AUDIODSP_MASK)
#define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_MASK (0x40000000U)
#define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_SHIFT (30U)
/*! AudioDSP_DEBUG - AudioDSP DEBUG clock enable
*/
#define AUDIOMIX_CLKEN0_AUDIODSP_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_SHIFT)) & AUDIOMIX_CLKEN0_AUDIODSP_DEBUG_MASK)
#define AUDIOMIX_CLKEN0_EARC_MASK (0x80000000U)
#define AUDIOMIX_CLKEN0_EARC_SHIFT (31U)
/*! EARC - EARC clock enable
*/
#define AUDIOMIX_CLKEN0_EARC(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN0_EARC_SHIFT)) & AUDIOMIX_CLKEN0_EARC_MASK)
/*! @} */
/*! @name CLKEN1 - IP Clock Enable Control Register 1 */
/*! @{ */
#define AUDIOMIX_CLKEN1_OCRAM_A_MASK (0x1U)
#define AUDIOMIX_CLKEN1_OCRAM_A_SHIFT (0U)
/*! OCRAM_A - OCRAM_A clock enable
*/
#define AUDIOMIX_CLKEN1_OCRAM_A(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_OCRAM_A_SHIFT)) & AUDIOMIX_CLKEN1_OCRAM_A_MASK)
#define AUDIOMIX_CLKEN1_AUD2HTX_MASK (0x2U)
#define AUDIOMIX_CLKEN1_AUD2HTX_SHIFT (1U)
/*! AUD2HTX - AUDIO LINK MASTER clock enable
*/
#define AUDIOMIX_CLKEN1_AUD2HTX(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_AUD2HTX_SHIFT)) & AUDIOMIX_CLKEN1_AUD2HTX_MASK)
#define AUDIOMIX_CLKEN1_EDMA_MASK (0x4U)
#define AUDIOMIX_CLKEN1_EDMA_SHIFT (2U)
/*! EDMA - EDMA clock enable
*/
#define AUDIOMIX_CLKEN1_EDMA(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_EDMA_SHIFT)) & AUDIOMIX_CLKEN1_EDMA_MASK)
#define AUDIOMIX_CLKEN1_PLL_MASK (0x8U)
#define AUDIOMIX_CLKEN1_PLL_SHIFT (3U)
/*! PLL - PLL clock enable
*/
#define AUDIOMIX_CLKEN1_PLL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_PLL_SHIFT)) & AUDIOMIX_CLKEN1_PLL_MASK)
#define AUDIOMIX_CLKEN1_MU2_MASK (0x10U)
#define AUDIOMIX_CLKEN1_MU2_SHIFT (4U)
/*! MU2 - MU2 clock enable
*/
#define AUDIOMIX_CLKEN1_MU2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_MU2_SHIFT)) & AUDIOMIX_CLKEN1_MU2_MASK)
#define AUDIOMIX_CLKEN1_MU3_MASK (0x20U)
#define AUDIOMIX_CLKEN1_MU3_SHIFT (5U)
/*! MU3 - MU3 clock enable
*/
#define AUDIOMIX_CLKEN1_MU3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_MU3_SHIFT)) & AUDIOMIX_CLKEN1_MU3_MASK)
#define AUDIOMIX_CLKEN1_EARC_PHY_MASK (0x40U)
#define AUDIOMIX_CLKEN1_EARC_PHY_SHIFT (6U)
/*! EARC_PHY - EARC PHY audio ss clock enable
*/
#define AUDIOMIX_CLKEN1_EARC_PHY(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_CLKEN1_EARC_PHY_SHIFT)) & AUDIOMIX_CLKEN1_EARC_PHY_MASK)
/*! @} */
/*! @name AUDIODSP_REG0 - AudioDSP EXPSTATE Register */
/*! @{ */
#define AUDIOMIX_AUDIODSP_REG0_EXPSTATE_MASK (0xFFFFFFFFU)
#define AUDIOMIX_AUDIODSP_REG0_EXPSTATE_SHIFT (0U)
/*! EXPSTATE - TIE_EXPSTATE output port of the AudioDSP
*/
#define AUDIOMIX_AUDIODSP_REG0_EXPSTATE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG0_EXPSTATE_SHIFT)) & AUDIOMIX_AUDIODSP_REG0_EXPSTATE_MASK)
/*! @} */
/*! @name AUDIODSP_REG1 - AudioDSP IMPWIRE Register */
/*! @{ */
#define AUDIOMIX_AUDIODSP_REG1_IMPWIRE_MASK (0xFFFFFFFFU)
#define AUDIOMIX_AUDIODSP_REG1_IMPWIRE_SHIFT (0U)
/*! IMPWIRE - TIE_IMPWIRE input port of the AudioDSP
*/
#define AUDIOMIX_AUDIODSP_REG1_IMPWIRE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG1_IMPWIRE_SHIFT)) & AUDIOMIX_AUDIODSP_REG1_IMPWIRE_MASK)
/*! @} */
/*! @name AUDIODSP_REG2 - AudioDSP XOCDMODE Register */
/*! @{ */
#define AUDIOMIX_AUDIODSP_REG2_XOCDMODE_MASK (0x1U)
#define AUDIOMIX_AUDIODSP_REG2_XOCDMODE_SHIFT (0U)
/*! XOCDMODE - Indicates that the AudioDSP is in OCD halt mode
*/
#define AUDIOMIX_AUDIODSP_REG2_XOCDMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_XOCDMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_XOCDMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_PWAITMODE_MASK (0x2U)
#define AUDIOMIX_AUDIODSP_REG2_PWAITMODE_SHIFT (1U)
/*! PWAITMODE - Indicates that the AudioDSP is in sleep mode. The processor asserts this signal when
* it has executed a WAITI instruction and is waiting for an interrupt.
*/
#define AUDIOMIX_AUDIODSP_REG2_PWAITMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_PWAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_PWAITMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_MASK (0x10U)
#define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_SHIFT (4U)
/*! OCDHALTONRESET - AudioDSP enters OCDHaltMode if this signal is samped asserted on reset.
*/
#define AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_OCDHALTONRESET_MASK)
#define AUDIOMIX_AUDIODSP_REG2_RUNSTALL_MASK (0x20U)
#define AUDIOMIX_AUDIODSP_REG2_RUNSTALL_SHIFT (5U)
/*! RunStall - AudioDSP RunStall control bit.
* 0b1..stalls the processor
*/
#define AUDIOMIX_AUDIODSP_REG2_RUNSTALL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_RUNSTALL_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_RUNSTALL_MASK)
#define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_MASK (0x40U)
#define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_SHIFT (6U)
/*! StatVectorSel - Selects between one of two stationary vector bases
* 0b0..default
* 0b1..alternative
*/
#define AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_STATVECTORSEL_MASK)
#define AUDIOMIX_AUDIODSP_REG2_ADDRMODE_MASK (0x100U)
#define AUDIOMIX_AUDIODSP_REG2_ADDRMODE_SHIFT (8U)
#define AUDIOMIX_AUDIODSP_REG2_ADDRMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_ADDRMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_ADDRMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_DSMMODE_MASK (0x200U)
#define AUDIOMIX_AUDIODSP_REG2_DSMMODE_SHIFT (9U)
/*! DsmMode - AudioDSP in DSM Mode for MU
* 0b0..not in DSM mode
* 0b1..in DSM mode
*/
#define AUDIOMIX_AUDIODSP_REG2_DSMMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_DSMMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_WAITMODE_MASK (0x400U)
#define AUDIOMIX_AUDIODSP_REG2_WAITMODE_SHIFT (10U)
/*! WaitMode - AudioDSP in Wait Mode for MU
* 0b0..not in wait mode
* 0b1..in wait mode
*/
#define AUDIOMIX_AUDIODSP_REG2_WAITMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_WAITMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_MASK (0x800U)
#define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_SHIFT (11U)
/*! m7DsmMode - M7 in DSM Mode for MU3
* 0b0..not in DSM mode
* 0b1..in DSM mode
*/
#define AUDIOMIX_AUDIODSP_REG2_M7DSMMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_M7DSMMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_MASK (0x1000U)
#define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_SHIFT (12U)
/*! m7WaitMode - M7 in Wait Mode for MU3
* 0b0..not in wait mode
* 0b1..in wait mode
*/
#define AUDIOMIX_AUDIODSP_REG2_M7WAITMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_M7WAITMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_MASK (0x2000U)
#define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_SHIFT (13U)
/*! a53DsmMode - CA53 in DSM Mode for MU2
* 0b0..not in DSM mode
* 0b1..in DSM mode
*/
#define AUDIOMIX_AUDIODSP_REG2_A53DSMMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_A53DSMMODE_MASK)
#define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_MASK (0x4000U)
#define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_SHIFT (14U)
/*! a53WaitMode - CA53 in Wait Mode for MU2
* 0b0..not in wait mode
* 0b1..in wait mode
*/
#define AUDIOMIX_AUDIODSP_REG2_A53WAITMODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_SHIFT)) & AUDIOMIX_AUDIODSP_REG2_A53WAITMODE_MASK)
/*! @} */
/*! @name AUDIODSP_REG3 - AudioDSP PID Register */
/*! @{ */
#define AUDIOMIX_AUDIODSP_REG3_PID_MASK (0xFFFFU)
#define AUDIOMIX_AUDIODSP_REG3_PID_SHIFT (0U)
/*! PID - AudioDSP PID Register. Input to the AudioDSP, latched at reset into the low-order bits of
* the PRID(processor ID) special register.
*/
#define AUDIOMIX_AUDIODSP_REG3_PID(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIODSP_REG3_PID_SHIFT)) & AUDIOMIX_AUDIODSP_REG3_PID_MASK)
/*! @} */
/*! @name EARC - EARC Control Register */
/*! @{ */
#define AUDIOMIX_EARC_RESETB_MASK (0x1U)
#define AUDIOMIX_EARC_RESETB_SHIFT (0U)
/*! RESETB - Earc Software Reset.
* 0b0..provide a software reset for EARC controller
* 0b1..return from reset
*/
#define AUDIOMIX_EARC_RESETB(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_EARC_RESETB_SHIFT)) & AUDIOMIX_EARC_RESETB_MASK)
#define AUDIOMIX_EARC_PHY_RESETB_MASK (0x2U)
#define AUDIOMIX_EARC_PHY_RESETB_SHIFT (1U)
/*! PHY_RESETB - Earc PHY Software Reset.
* 0b0..provide a software reset for EARC PHY
* 0b1..return from reset
*/
#define AUDIOMIX_EARC_PHY_RESETB(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_EARC_PHY_RESETB_SHIFT)) & AUDIOMIX_EARC_PHY_RESETB_MASK)
/*! @} */
/*! @name SAI1_MCLK_SEL - SAI1 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL
* 0b0..SAI1_CLK_ROOT is selected
* 0b1..SAI1.MCLK is selected
*/
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI1_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK2 is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI1_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name SAI2_MCLK_SEL - SAI2 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL
* 0b0..SAI2_CLK_ROOT is selected
* 0b1..SAI2.MCLK is selected
*/
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI2_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI2_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name SAI3_MCLK_SEL - SAI3 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL - MCLK1 Select Register
* 0b0..SAI3_CLK_ROOT is selected
* 0b1..SAI3.MCLK is selected
*/
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI3_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL - MCLK2 Select Register
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI3_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name SAI5_MCLK_SEL - SAI5 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL - MCLK1 Select Register
* 0b0..SAI5_CLK_ROOT is selected
* 0b1..SAI5.MCLK is selected
*/
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI5_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL - MCLK2 Select Register
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI5_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name SAI6_MCLK_SEL - SAI6 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL - MCLK1 Select Register
* 0b0..SAI6_CLK_ROOT is selected
* 0b1..SAI6.MCLK is selected
*/
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI6_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL - MCLK2 Select Register
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI6_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name SAI7_MCLK_SEL - SAI7 MCLK SELECT Register */
/*! @{ */
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_MASK (0x1U)
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_SHIFT (0U)
/*! MCLK1_SEL - MCLK1 Select Register
* 0b0..SAI7_CLK_ROOT is selected
* 0b1..SAI7.MCLK is selected
*/
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_SHIFT)) & AUDIOMIX_SAI7_MCLK_SEL_MCLK1_SEL_MASK)
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_MASK (0x1EU)
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_SHIFT (1U)
/*! MCLK2_SEL - MCLK2 Select Register
* 0b0000..SAI1_CLK_ROOT is selected
* 0b0001..SAI2_CLK_ROOT is selected
* 0b0010..SAI3_CLK_ROOT is selected
* 0b0011..Reserved, MCLK2 is 0
* 0b0100..SAI5_CLK_ROOT is selected
* 0b0101..SAI6_CLK_ROOT is selected
* 0b0110..SAI7_CLK_ROOT is selected
* 0b0111..SAI1.MCLK is selected
* 0b1000..SAI2.MCLK is selected
* 0b1001..SAI3.MCLK is selected
* 0b1010..Reserved, MCLK is 0
* 0b1011..SAI5.MCLK is selected
* 0b1100..SAI6.MCLK is selected
* 0b1101..SAI7.MCLK is selected
* 0b1110..SPDIF.ETXCLK is selected
*/
#define AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_SHIFT)) & AUDIOMIX_SAI7_MCLK_SEL_MCLK2_SEL_MASK)
/*! @} */
/*! @name PDM_CLK - PDM Root Clock Select Register */
/*! @{ */
#define AUDIOMIX_PDM_CLK_SELECT_MASK (0x3U)
#define AUDIOMIX_PDM_CLK_SELECT_SHIFT (0U)
/*! select - PDM Root Clock Select Bits
* 0b00..ccm pdm clock is selected
* 0b01..sai_pll div2 is selected
* 0b10..SAI1_MCLK is selected
* 0b11..reserved.
*/
#define AUDIOMIX_PDM_CLK_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_PDM_CLK_SELECT_SHIFT)) & AUDIOMIX_PDM_CLK_SELECT_MASK)
/*! @} */
/*! @name SAI_PLL_GNRL_CTL - SAI PLL General control Register */
/*! @{ */
#define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_MASK (0x3U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_SHIFT (0U)
/*! ref_clk_sel - reference clock select
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_REF_CLK_SEL_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_MASK (0xCU)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_SHIFT (2U)
/*! pad_clk_sel - pad clock select
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_PAD_CLK_SEL_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_MASK (0x10U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_SHIFT (4U)
/*! bypass - pll bypass
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_BYPASS_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_MASK (0x100U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_SHIFT (8U)
/*! resetb_override - resetb override
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_OVERRIDE_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_MASK (0x200U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_SHIFT (9U)
/*! resetb - pll resetb
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_RESETB_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_MASK (0x1000U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_SHIFT (12U)
/*! cke_override - pll cke override.
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_OVERRIDE_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_MASK (0x2000U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_SHIFT (13U)
/*! cke - pll cke
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_CKE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_CKE_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_MASK (0x10000U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_SHIFT (16U)
/*! blk_bypass - blk bypass
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_BLK_BYPASS_MASK)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_MASK (0x80000000U)
#define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_SHIFT (31U)
/*! lock - pll lock
*/
#define AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_SHIFT)) & AUDIOMIX_SAI_PLL_GNRL_CTL_LOCK_MASK)
/*! @} */
/*! @name SAI_PLL_FDIV_CTL0 - SAI PLL Frequency Divider control Register */
/*! @{ */
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_MASK (0x7U)
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_SHIFT (0U)
/*! post_div - post divider value
*/
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_POST_DIV_MASK)
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_MASK (0x3F0U)
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_SHIFT (4U)
/*! pre_div - pre divider value
*/
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_PRE_DIV_MASK)
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_MASK (0x3FF000U)
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_SHIFT (12U)
/*! main_div - main divider value
*/
#define AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL0_MAIN_DIV_MASK)
/*! @} */
/*! @name SAI_PLL_FDIV_CTL1 - SAI PLL DSM value Register */
/*! @{ */
#define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_MASK (0xFFFFU)
#define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_SHIFT (0U)
/*! dsm - pll DSM(K) value
*/
#define AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_SHIFT)) & AUDIOMIX_SAI_PLL_FDIV_CTL1_DSM_MASK)
/*! @} */
/*! @name SAI_PLL_SSCG_CTL - SAI PLL SSCG control Register */
/*! @{ */
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_MASK (0x3U)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_SHIFT (0U)
/*! sel_pf - pll modulation method control
*/
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_SEL_PF_MASK)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_MASK (0x3F0U)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_SHIFT (4U)
/*! mrat_ctl - pll modulation rate control
*/
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_MRAT_CTL_MASK)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_MASK (0xFF000U)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_SHIFT (12U)
/*! mfreq_ctl - pll modulation frequency control
*/
#define AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_MFREQ_CTL_MASK)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_MASK (0x80000000U)
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_SHIFT (31U)
/*! sscg_en - SSCG Enable Bit
*/
#define AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_SHIFT)) & AUDIOMIX_SAI_PLL_SSCG_CTL_SSCG_EN_MASK)
/*! @} */
/*! @name SAI_PLL_MNIT_CTL - SAI PLL SSCG control Register */
/*! @{ */
#define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_MASK (0x7U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_SHIFT (0U)
/*! icp - Charge-pump current control
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_ICP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_ICP_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_MASK (0x8U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_SHIFT (3U)
/*! afc_enb - AFC Enable control
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_ENB_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_MASK (0x1F0U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_SHIFT (4U)
/*! extafc - AFC Enable control
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_EXTAFC_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_MASK (0x4000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_SHIFT (14U)
/*! feed_en - PLL FEED Enable control
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_FEED_EN_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_MASK (0x8000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_SHIFT (15U)
/*! fsel - PLL FEED SEL control
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_FSEL_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_MASK (0x20000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_SHIFT (17U)
/*! afcinit_sel - PLL AFC INIT SEL
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFCINIT_SEL_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_MASK (0x40000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_SHIFT (18U)
/*! pbias_ctrl_en - PLL PBIAS CTRL EN
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_EN_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_MASK (0x80000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_SHIFT (19U)
/*! pbias_ctrl - PLL PBIAS CTRL
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_PBIAS_CTRL_MASK)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_MASK (0x100000U)
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_SHIFT (20U)
/*! afc_sel - PLL AFC SEL
*/
#define AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_SHIFT)) & AUDIOMIX_SAI_PLL_MNIT_CTL_AFC_SEL_MASK)
/*! @} */
/*! @name AUDIO_EXT_ADDR - AUDIOMIX Extra Addr Bits Register */
/*! @{ */
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_MASK (0x3U)
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_SHIFT (0U)
/*! sdma2 - SDMA2 Extra Addr Bits
*/
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA2(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_SDMA2_MASK)
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_MASK (0xCU)
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_SHIFT (2U)
/*! sdma3 - SDMA3 Extra Addr Bits
*/
#define AUDIOMIX_AUDIO_EXT_ADDR_SDMA3(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_SDMA3_MASK)
#define AUDIOMIX_AUDIO_EXT_ADDR_EDMA_MASK (0x30U)
#define AUDIOMIX_AUDIO_EXT_ADDR_EDMA_SHIFT (4U)
/*! edma - EDMA extra Addr Bits
*/
#define AUDIOMIX_AUDIO_EXT_ADDR_EDMA(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_EXT_ADDR_EDMA_SHIFT)) & AUDIOMIX_AUDIO_EXT_ADDR_EDMA_MASK)
/*! @} */
/*! @name IPG_LP_CTRL - IPG Low Power Control Register */
/*! @{ */
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_MASK (0x1U)
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_SHIFT (0U)
/*! edma_ipg_stop - EDMA IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_MASK (0x2U)
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_SHIFT (1U)
/*! sdma2_ipg_stop - SDMA2 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_MASK (0x4U)
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_SHIFT (2U)
/*! sdma3_ipg_stop - SDMA3 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_MASK (0x8U)
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_SHIFT (3U)
/*! pdm_ipg_stop - PDM IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_MASK (0x10U)
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_SHIFT (4U)
/*! sai1_ipg_stop - SAI1 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_MASK (0x20U)
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_SHIFT (5U)
/*! sai2_ipg_stop - SAI2 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_MASK (0x40U)
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_SHIFT (6U)
/*! sai3_ipg_stop - SAI3 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_MASK (0x80U)
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_SHIFT (7U)
/*! sai5_ipg_stop - SAI5 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_MASK (0x100U)
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_SHIFT (8U)
/*! sai6_ipg_stop - SAI6 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_MASK (0x200U)
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_SHIFT (9U)
/*! sai7_ipg_stop - SAI1 IPG_STOP Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_MASK)
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_MASK (0x400U)
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_SHIFT (10U)
/*! edma_ipg_stop_ack - EDMA IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_EDMA_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_MASK (0x800U)
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_SHIFT (11U)
/*! sdma2_ipg_stop_ack - SDMA2 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA2_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_MASK (0x1000U)
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_SHIFT (12U)
/*! sdma3_ipg_stop_ack - SDMA3 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SDMA3_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_MASK (0x2000U)
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_SHIFT (13U)
/*! pdm_ipg_stop_ack - PDM IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_PDM_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_MASK (0x4000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_SHIFT (14U)
/*! sai1_ipg_stop_ack - SAI1 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI1_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_MASK (0x8000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_SHIFT (15U)
/*! sai2_ipg_stop_ack - SAI2 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI2_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_MASK (0x10000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_SHIFT (16U)
/*! sai3_ipg_stop_ack - SAI3 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI3_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_MASK (0x20000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_SHIFT (17U)
/*! sai5_ipg_stop_ack - SAI5 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI5_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_MASK (0x40000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_SHIFT (18U)
/*! sai6_ipg_stop_ack - SAI6 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI6_IPG_STOP_ACK_MASK)
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_MASK (0x80000U)
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_SHIFT (19U)
/*! sai7_ipg_stop_ack - SAI1 IPG_STOP_ACK Bit
*/
#define AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_SHIFT)) & AUDIOMIX_IPG_LP_CTRL_SAI7_IPG_STOP_ACK_MASK)
/*! @} */
/*! @name AUDIO_AXI_LIMIT - AUDIOMIX AXI LIMIT CTRL Register */
/*! @{ */
#define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_MASK (0x1U)
#define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_SHIFT (0U)
/*! enable - AXI Limit enable
*/
#define AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_SHIFT)) & AUDIOMIX_AUDIO_AXI_LIMIT_ENABLE_MASK)
#define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_MASK (0xFFFF0U)
#define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_SHIFT (4U)
/*! BEAT_LIMIT - Beat Limit. Limit the burst beat number from AudioDSP.
*/
#define AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_SHIFT)) & AUDIOMIX_AUDIO_AXI_LIMIT_BEAT_LIMIT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AUDIOMIX_Register_Masks */
/* AUDIOMIX - Peripheral instance base addresses */
/** Peripheral AUDIOMIX base address */
#define AUDIOMIX_BASE (0x30E20000u)
/** Peripheral AUDIOMIX base pointer */
#define AUDIOMIX ((AUDIOMIX_Type *)AUDIOMIX_BASE)
/** Array initializer of AUDIOMIX peripheral base addresses */
#define AUDIOMIX_BASE_ADDRS { AUDIOMIX_BASE }
/** Array initializer of AUDIOMIX peripheral base pointers */
#define AUDIOMIX_BASE_PTRS { AUDIOMIX }
/*!
* @}
*/ /* end of group AUDIOMIX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AUDIOPACKETIZER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOPACKETIZER_Peripheral_Access_Layer AUDIOPACKETIZER Peripheral Access Layer
* @{
*/
/** AUDIOPACKETIZER - Register Layout Typedef */
typedef struct {
__IO uint8_t AUD_N1; /**< Audio Clock Regenerator N Value Register 1 For N expected values, refer to the HDMI 1., offset: 0x0 */
__IO uint8_t AUD_N2; /**< Audio Clock Regenerator N Value Register 2 For N expected values, refer to the HDMI 1., offset: 0x1 */
__IO uint8_t AUD_N3; /**< Audio Clock Regenerator N Value Register 3 For N expected values, refer to the HDMI 1., offset: 0x2 */
__IO uint8_t AUD_CTS1; /**< Audio Clock Regenerator CTS Value Register 1 For CTS expected values, refer to the HDMI 1., offset: 0x3 */
__IO uint8_t AUD_CTS2; /**< Audio Clock Regenerator CTS Register 2 For CTS expected values, refer to the HDMI 1., offset: 0x4 */
__IO uint8_t AUD_CTS3; /**< Audio Clock Regenerator CTS value Register 3., offset: 0x5 */
uint8_t AUD_INPUTCLKFS; /**< Audio Input Clock FS Factor Register, offset: 0x6 */
__IO uint8_t AUD_CTS_DITHER; /**< Audio CTS Dither Register, offset: 0x7 */
} AUDIOPACKETIZER_Type;
/* ----------------------------------------------------------------------------
-- AUDIOPACKETIZER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOPACKETIZER_Register_Masks AUDIOPACKETIZER Register Masks
* @{
*/
/*! @name AUD_N1 - Audio Clock Regenerator N Value Register 1 For N expected values, refer to the HDMI 1. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_N1_AUDN_MASK (0xFFU)
#define AUDIOPACKETIZER_AUD_N1_AUDN_SHIFT (0U)
/*! AudN - HDMI Audio Clock Regenerator N value
*/
#define AUDIOPACKETIZER_AUD_N1_AUDN(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N1_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N1_AUDN_MASK)
/*! @} */
/*! @name AUD_N2 - Audio Clock Regenerator N Value Register 2 For N expected values, refer to the HDMI 1. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_N2_AUDN_MASK (0xFFU)
#define AUDIOPACKETIZER_AUD_N2_AUDN_SHIFT (0U)
/*! AudN - HDMI Audio Clock Regenerator N value
*/
#define AUDIOPACKETIZER_AUD_N2_AUDN(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N2_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N2_AUDN_MASK)
/*! @} */
/*! @name AUD_N3 - Audio Clock Regenerator N Value Register 3 For N expected values, refer to the HDMI 1. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_N3_AUDN_MASK (0xFU)
#define AUDIOPACKETIZER_AUD_N3_AUDN_SHIFT (0U)
/*! AudN - HDMI Audio Clock Regenerator N value
*/
#define AUDIOPACKETIZER_AUD_N3_AUDN(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N3_AUDN_SHIFT)) & AUDIOPACKETIZER_AUD_N3_AUDN_MASK)
#define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_MASK (0x80U)
#define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_SHIFT (7U)
/*! ncts_atomic_write - When set, the new N and CTS values are only used when aud_n1 register is written.
*/
#define AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_SHIFT)) & AUDIOPACKETIZER_AUD_N3_NCTS_ATOMIC_WRITE_MASK)
/*! @} */
/*! @name AUD_CTS1 - Audio Clock Regenerator CTS Value Register 1 For CTS expected values, refer to the HDMI 1. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_CTS1_AUDCTS_MASK (0xFFU)
#define AUDIOPACKETIZER_AUD_CTS1_AUDCTS_SHIFT (0U)
/*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value.
*/
#define AUDIOPACKETIZER_AUD_CTS1_AUDCTS(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS1_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS1_AUDCTS_MASK)
/*! @} */
/*! @name AUD_CTS2 - Audio Clock Regenerator CTS Register 2 For CTS expected values, refer to the HDMI 1. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_CTS2_AUDCTS_MASK (0xFFU)
#define AUDIOPACKETIZER_AUD_CTS2_AUDCTS_SHIFT (0U)
/*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value.
*/
#define AUDIOPACKETIZER_AUD_CTS2_AUDCTS(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS2_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS2_AUDCTS_MASK)
/*! @} */
/*! @name AUD_CTS3 - Audio Clock Regenerator CTS value Register 3. */
/*! @{ */
#define AUDIOPACKETIZER_AUD_CTS3_AUDCTS_MASK (0xFU)
#define AUDIOPACKETIZER_AUD_CTS3_AUDCTS_SHIFT (0U)
/*! AudCTS - HDMI Audio Clock Regenerator CTS calculated value.
*/
#define AUDIOPACKETIZER_AUD_CTS3_AUDCTS(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_AUDCTS_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_AUDCTS_MASK)
#define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_MASK (0x10U)
#define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_SHIFT (4U)
/*! CTS_manual - If the CTS_manual bit equals 0b, this registers contains audCTS[19:0] generated by
* the Cycle time counter according to the specified timing.
*/
#define AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_CTS_MANUAL_MASK)
#define AUDIOPACKETIZER_AUD_CTS3_SPARE_MASK (0xE0U)
#define AUDIOPACKETIZER_AUD_CTS3_SPARE_SHIFT (5U)
/*! spare - Reserved as "spare" bit with no associated functionality.
*/
#define AUDIOPACKETIZER_AUD_CTS3_SPARE(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS3_SPARE_SHIFT)) & AUDIOPACKETIZER_AUD_CTS3_SPARE_MASK)
/*! @} */
/*! @name AUD_CTS_DITHER - Audio CTS Dither Register */
/*! @{ */
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_MASK (0xFU)
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_SHIFT (0U)
/*! divisor - Dither divisor (4'd1 if no CTS Dither) This field should be configured with the value
* of divisor from the HDMI specification.
*/
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_SHIFT)) & AUDIOPACKETIZER_AUD_CTS_DITHER_DIVISOR_MASK)
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_MASK (0xF0U)
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_SHIFT (4U)
/*! dividend - Dither dividend (4'd1 if no CTS Dither) This field should be configured with the
* value of dividend from the HDMI specification.
*/
#define AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND(x) (((uint8_t)(((uint8_t)(x)) << AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_SHIFT)) & AUDIOPACKETIZER_AUD_CTS_DITHER_DIVIDEND_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AUDIOPACKETIZER_Register_Masks */
/* AUDIOPACKETIZER - Peripheral instance base addresses */
/** Peripheral AUDIOPACKETIZER base address */
#define AUDIOPACKETIZER_BASE (0x32FDB200u)
/** Peripheral AUDIOPACKETIZER base pointer */
#define AUDIOPACKETIZER ((AUDIOPACKETIZER_Type *)AUDIOPACKETIZER_BASE)
/** Array initializer of AUDIOPACKETIZER peripheral base addresses */
#define AUDIOPACKETIZER_BASE_ADDRS { AUDIOPACKETIZER_BASE }
/** Array initializer of AUDIOPACKETIZER peripheral base pointers */
#define AUDIOPACKETIZER_BASE_PTRS { AUDIOPACKETIZER }
/*!
* @}
*/ /* end of group AUDIOPACKETIZER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AUDIOSAMPLEGP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOSAMPLEGP_Peripheral_Access_Layer AUDIOSAMPLEGP Peripheral Access Layer
* @{
*/
/** AUDIOSAMPLEGP - Register Layout Typedef */
typedef struct {
__IO uint8_t GP_CONF0; /**< Audio GPA Software FIFO Reset Control Register 0, offset: 0x0 */
__IO uint8_t GP_CONF1; /**< Audio GPA Channel Enable Configuration Register 1, offset: 0x1 */
__IO uint8_t GP_CONF2; /**< Audio GPA HBR Enable Register 2, offset: 0x2 */
uint8_t RESERVED_0[3];
__IO uint8_t GP_MASK; /**< Audio GPA FIFO Full and Empty Mask Interrupt Register, offset: 0x6 */
} AUDIOSAMPLEGP_Type;
/* ----------------------------------------------------------------------------
-- AUDIOSAMPLEGP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIOSAMPLEGP_Register_Masks AUDIOSAMPLEGP Register Masks
* @{
*/
/*! @name GP_CONF0 - Audio GPA Software FIFO Reset Control Register 0 */
/*! @{ */
#define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_MASK (0x1U)
#define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_SHIFT (0U)
/*! sw_audio_fifo_rst - Audio FIFOs software reset - Writing 0b: no action taken - Writing 1b:
* Resets all audio FIFOs Reading from this register always returns 0b.
*/
#define AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_SHIFT)) & AUDIOSAMPLEGP_GP_CONF0_SW_AUDIO_FIFO_RST_MASK)
/*! @} */
/*! @name GP_CONF1 - Audio GPA Channel Enable Configuration Register 1 */
/*! @{ */
#define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_MASK (0xFFU)
#define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_SHIFT (0U)
/*! ch_in_en - Each bit controls the enabling of the respective audio channel.
*/
#define AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_SHIFT)) & AUDIOSAMPLEGP_GP_CONF1_CH_IN_EN_MASK)
/*! @} */
/*! @name GP_CONF2 - Audio GPA HBR Enable Register 2 */
/*! @{ */
#define AUDIOSAMPLEGP_GP_CONF2_HBR_MASK (0x1U)
#define AUDIOSAMPLEGP_GP_CONF2_HBR_SHIFT (0U)
/*! HBR - HBR packets enable.
*/
#define AUDIOSAMPLEGP_GP_CONF2_HBR(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF2_HBR_SHIFT)) & AUDIOSAMPLEGP_GP_CONF2_HBR_MASK)
#define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_MASK (0x2U)
#define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_SHIFT (1U)
/*! insert_pcuv - When set (1'b1), this bit enables the insertion of the PCUV (Parity, Channel
* Status, User bit and Validity) bits on the incoming audio stream (support limited to Linear PCM
* audio).
*/
#define AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_SHIFT)) & AUDIOSAMPLEGP_GP_CONF2_INSERT_PCUV_MASK)
/*! @} */
/*! @name GP_MASK - Audio GPA FIFO Full and Empty Mask Interrupt Register */
/*! @{ */
#define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_MASK (0x1U)
#define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_SHIFT (0U)
/*! fifo_full_mask - FIFO full flag mask
*/
#define AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_FULL_MASK_MASK)
#define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_MASK (0x2U)
#define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_SHIFT (1U)
/*! fifo_empty_mask - FIFO empty flag mask
*/
#define AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_EMPTY_MASK_MASK)
#define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_MASK (0x10U)
#define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_SHIFT (4U)
/*! fifo_overrun_mask - FIFO overrun mask
*/
#define AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK(x) (((uint8_t)(((uint8_t)(x)) << AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_SHIFT)) & AUDIOSAMPLEGP_GP_MASK_FIFO_OVERRUN_MASK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AUDIOSAMPLEGP_Register_Masks */
/* AUDIOSAMPLEGP - Peripheral instance base addresses */
/** Peripheral AUDIOSAMPLEGP base address */
#define AUDIOSAMPLEGP_BASE (0x32FDB500u)
/** Peripheral AUDIOSAMPLEGP base pointer */
#define AUDIOSAMPLEGP ((AUDIOSAMPLEGP_Type *)AUDIOSAMPLEGP_BASE)
/** Array initializer of AUDIOSAMPLEGP peripheral base addresses */
#define AUDIOSAMPLEGP_BASE_ADDRS { AUDIOSAMPLEGP_BASE }
/** Array initializer of AUDIOSAMPLEGP peripheral base pointers */
#define AUDIOSAMPLEGP_BASE_PTRS { AUDIOSAMPLEGP }
/*!
* @}
*/ /* end of group AUDIOSAMPLEGP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- BCH Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
* @{
*/
/** BCH - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
__I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
uint8_t RESERVED_1[12];
__IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
uint8_t RESERVED_3[12];
__IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
uint8_t RESERVED_4[28];
__IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
uint8_t RESERVED_5[12];
__IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
uint8_t RESERVED_6[12];
__IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
uint8_t RESERVED_7[12];
__IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
uint8_t RESERVED_8[12];
__IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
uint8_t RESERVED_9[12];
__IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
uint8_t RESERVED_10[12];
__IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
uint8_t RESERVED_11[12];
__IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
uint8_t RESERVED_12[12];
__IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
uint8_t RESERVED_13[12];
__IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
__IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
__IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
__IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
__I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */
uint8_t RESERVED_14[12];
__I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */
uint8_t RESERVED_15[12];
__I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
uint8_t RESERVED_16[12];
__I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
uint8_t RESERVED_17[12];
__I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */
uint8_t RESERVED_18[12];
__I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */
uint8_t RESERVED_19[12];
__IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
} BCH_Type;
/* ----------------------------------------------------------------------------
-- BCH Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup BCH_Register_Masks BCH Register Masks
* @{
*/
/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
/*! @{ */
#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
#define BCH_CTRL_RSVD0_MASK (0x2U)
#define BCH_CTRL_RSVD0_SHIFT (1U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
#define BCH_CTRL_RSVD1_MASK (0xF0U)
#define BCH_CTRL_RSVD1_SHIFT (4U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
#define BCH_CTRL_RSVD2_MASK (0x200U)
#define BCH_CTRL_RSVD2_SHIFT (9U)
/*! RSVD2 - This field is reserved.
*/
#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
#define BCH_CTRL_RSVD3_MASK (0xF800U)
#define BCH_CTRL_RSVD3_SHIFT (11U)
/*! RSVD3 - This field is reserved.
*/
#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
#define BCH_CTRL_RSVD4_MASK (0x300000U)
#define BCH_CTRL_RSVD4_SHIFT (20U)
/*! RSVD4 - This field is reserved.
*/
#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
#define BCH_CTRL_RSVD5_SHIFT (23U)
/*! RSVD5 - This field is reserved.
*/
#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
#define BCH_CTRL_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Allow BCH to operate normally.
* 0b1..Do not clock BCH gates in order to minimize power consumption.
*/
#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
#define BCH_CTRL_SFTRST_MASK (0x80000000U)
#define BCH_CTRL_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Allow BCH to operate normally.
* 0b1..Hold BCH in reset.
*/
#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
/*! @{ */
#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U)
#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U)
#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
#define BCH_CTRL_SET_RSVD0_MASK (0x2U)
#define BCH_CTRL_SET_RSVD0_SHIFT (1U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U)
#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U)
#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
#define BCH_CTRL_SET_RSVD1_MASK (0xF0U)
#define BCH_CTRL_SET_RSVD1_SHIFT (4U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U)
#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U)
#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
#define BCH_CTRL_SET_RSVD2_MASK (0x200U)
#define BCH_CTRL_SET_RSVD2_SHIFT (9U)
/*! RSVD2 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U)
#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
#define BCH_CTRL_SET_RSVD3_MASK (0xF800U)
#define BCH_CTRL_SET_RSVD3_SHIFT (11U)
/*! RSVD3 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U)
#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U)
#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U)
#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U)
#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U)
#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U)
#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
#define BCH_CTRL_SET_RSVD4_MASK (0x300000U)
#define BCH_CTRL_SET_RSVD4_SHIFT (20U)
/*! RSVD4 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U)
#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U)
#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U)
#define BCH_CTRL_SET_RSVD5_SHIFT (23U)
/*! RSVD5 - This field is reserved.
*/
#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define BCH_CTRL_SET_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Allow BCH to operate normally.
* 0b1..Do not clock BCH gates in order to minimize power consumption.
*/
#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U)
#define BCH_CTRL_SET_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Allow BCH to operate normally.
* 0b1..Hold BCH in reset.
*/
#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
/*! @{ */
#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U)
#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U)
#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
#define BCH_CTRL_CLR_RSVD0_MASK (0x2U)
#define BCH_CTRL_CLR_RSVD0_SHIFT (1U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U)
#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U)
#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U)
#define BCH_CTRL_CLR_RSVD1_SHIFT (4U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U)
#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U)
#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
#define BCH_CTRL_CLR_RSVD2_MASK (0x200U)
#define BCH_CTRL_CLR_RSVD2_SHIFT (9U)
/*! RSVD2 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U)
#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U)
#define BCH_CTRL_CLR_RSVD3_SHIFT (11U)
/*! RSVD3 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U)
#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U)
#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U)
#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U)
#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U)
#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U)
#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U)
#define BCH_CTRL_CLR_RSVD4_SHIFT (20U)
/*! RSVD4 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U)
#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U)
#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U)
#define BCH_CTRL_CLR_RSVD5_SHIFT (23U)
/*! RSVD5 - This field is reserved.
*/
#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Allow BCH to operate normally.
* 0b1..Do not clock BCH gates in order to minimize power consumption.
*/
#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define BCH_CTRL_CLR_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Allow BCH to operate normally.
* 0b1..Hold BCH in reset.
*/
#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
/*! @{ */
#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U)
#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U)
#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
#define BCH_CTRL_TOG_RSVD0_MASK (0x2U)
#define BCH_CTRL_TOG_RSVD0_SHIFT (1U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U)
#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U)
#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U)
#define BCH_CTRL_TOG_RSVD1_SHIFT (4U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U)
#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U)
#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
#define BCH_CTRL_TOG_RSVD2_MASK (0x200U)
#define BCH_CTRL_TOG_RSVD2_SHIFT (9U)
/*! RSVD2 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U)
#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U)
#define BCH_CTRL_TOG_RSVD3_SHIFT (11U)
/*! RSVD3 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U)
#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U)
#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U)
#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U)
#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U)
#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U)
#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U)
#define BCH_CTRL_TOG_RSVD4_SHIFT (20U)
/*! RSVD4 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U)
#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U)
#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U)
#define BCH_CTRL_TOG_RSVD5_SHIFT (23U)
/*! RSVD5 - This field is reserved.
*/
#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Allow BCH to operate normally.
* 0b1..Do not clock BCH gates in order to minimize power consumption.
*/
#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define BCH_CTRL_TOG_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Allow BCH to operate normally.
* 0b1..Hold BCH in reset.
*/
#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
/*! @{ */
#define BCH_STATUS0_RSVD0_MASK (0x3U)
#define BCH_STATUS0_RSVD0_SHIFT (0U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
#define BCH_STATUS0_CORRECTED_MASK (0x8U)
#define BCH_STATUS0_CORRECTED_SHIFT (3U)
#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
#define BCH_STATUS0_ALLONES_MASK (0x10U)
#define BCH_STATUS0_ALLONES_SHIFT (4U)
#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
#define BCH_STATUS0_RSVD1_MASK (0xE0U)
#define BCH_STATUS0_RSVD1_SHIFT (5U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
/*! STATUS_BLK0
* 0b00000000..No errors found on block.
* 0b00000001..One error found on block.
* 0b00000010..One errors found on block.
* 0b00000011..One errors found on block.
* 0b00000100..One errors found on block.
* 0b11111110..Block exhibited uncorrectable errors.
* 0b11111111..Page is erased.
*/
#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
#define BCH_STATUS0_HANDLE_SHIFT (20U)
#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
/*! @} */
/*! @name MODE - Hardware ECC Accelerator Mode Register */
/*! @{ */
#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
#define BCH_MODE_RSVD_SHIFT (8U)
/*! RSVD - This field is reserved.
*/
#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
/*! @} */
/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
/*! @{ */
#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
/*! @} */
/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
/*! @{ */
#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
#define BCH_DATAPTR_ADDR_SHIFT (0U)
#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
/*! @} */
/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
/*! @{ */
#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
#define BCH_METAPTR_ADDR_SHIFT (0U)
#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
/*! @} */
/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
/*! @{ */
#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
/*! @} */
/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
/*! @{ */
#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
/*! ECC0
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
/*! @} */
/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
/*! @{ */
#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
/*! ECCN
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
/*! @} */
/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
/*! @{ */
#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
/*! ECC0
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
/*! @} */
/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
/*! @{ */
#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
/*! ECCN
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
/*! @} */
/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
/*! @{ */
#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
/*! ECC0
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
/*! @} */
/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
/*! @{ */
#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
/*! ECCN
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
/*! @} */
/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
/*! @{ */
#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
/*! ECC0
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
/*! @} */
/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
/*! @{ */
#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
/*! ECCN
* 0b00000..No ECC to be performed
* 0b00001..ECC 2 to be performed
* 0b00010..ECC 4 to be performed
* 0b11110..ECC 60 to be performed
* 0b11111..ECC 62 to be performed
*/
#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
/*! @} */
/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
/*! @{ */
#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
#define BCH_DEBUG0_RSVD0_SHIFT (6U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
/*! BM_KES_TEST_BYPASS
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
/*! KES_DEBUG_STALL
* 0b0..KES FSM proceeds to next block supplied by bus master.
* 0b1..KES FSM waits after current equations are solved and the search engine is started.
*/
#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
/*! KES_STANDALONE
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
/*! KES_DEBUG_MODE4K
* 0b1..Mode is set for 4K NAND pages.
* 0b1..Mode is set for 2K NAND pages.
*/
#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
/*! KES_DEBUG_PAYLOAD_FLAG
* 0b1..Payload is set for 512 bytes data block.
* 0b1..Payload is set for 65 or 19 bytes auxiliary block.
*/
#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
/*! KES_DEBUG_SYNDROME_SYMBOL
* 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
* 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
#define BCH_DEBUG0_RSVD1_SHIFT (25U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
/*! @} */
/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
/*! @{ */
#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU)
#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U)
#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U)
#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U)
#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U)
/*! BM_KES_TEST_BYPASS
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U)
#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U)
/*! KES_DEBUG_STALL
* 0b0..KES FSM proceeds to next block supplied by bus master.
* 0b1..KES FSM waits after current equations are solved and the search engine is started.
*/
#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U)
#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U)
#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U)
#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U)
/*! KES_STANDALONE
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U)
#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U)
#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U)
#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U)
/*! KES_DEBUG_MODE4K
* 0b1..Mode is set for 4K NAND pages.
* 0b1..Mode is set for 2K NAND pages.
*/
#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
/*! KES_DEBUG_PAYLOAD_FLAG
* 0b1..Payload is set for 512 bytes data block.
* 0b1..Payload is set for 65 or 19 bytes auxiliary block.
*/
#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
/*! KES_DEBUG_SYNDROME_SYMBOL
* 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
* 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U)
#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
/*! @} */
/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
/*! @{ */
#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU)
#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U)
#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U)
#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U)
#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U)
/*! BM_KES_TEST_BYPASS
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U)
#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U)
/*! KES_DEBUG_STALL
* 0b0..KES FSM proceeds to next block supplied by bus master.
* 0b1..KES FSM waits after current equations are solved and the search engine is started.
*/
#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U)
#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U)
#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U)
#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U)
/*! KES_STANDALONE
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U)
#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U)
#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U)
#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U)
/*! KES_DEBUG_MODE4K
* 0b1..Mode is set for 4K NAND pages.
* 0b1..Mode is set for 2K NAND pages.
*/
#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
/*! KES_DEBUG_PAYLOAD_FLAG
* 0b1..Payload is set for 512 bytes data block.
* 0b1..Payload is set for 65 or 19 bytes auxiliary block.
*/
#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
/*! KES_DEBUG_SYNDROME_SYMBOL
* 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
* 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U)
#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
/*! @} */
/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
/*! @{ */
#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU)
#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U)
#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U)
#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U)
/*! RSVD0 - This field is reserved.
*/
#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U)
#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U)
/*! BM_KES_TEST_BYPASS
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U)
#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U)
/*! KES_DEBUG_STALL
* 0b0..KES FSM proceeds to next block supplied by bus master.
* 0b1..KES FSM waits after current equations are solved and the search engine is started.
*/
#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U)
#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U)
#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U)
#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U)
/*! KES_STANDALONE
* 0b0..Bus master address generator for SYND_GEN writes operates normally.
* 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U)
#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U)
#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U)
#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U)
/*! KES_DEBUG_MODE4K
* 0b1..Mode is set for 4K NAND pages.
* 0b1..Mode is set for 2K NAND pages.
*/
#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
/*! KES_DEBUG_PAYLOAD_FLAG
* 0b1..Payload is set for 512 bytes data block.
* 0b1..Payload is set for 65 or 19 bytes auxiliary block.
*/
#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
/*! KES_DEBUG_SYNDROME_SYMBOL
* 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
* 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
*/
#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U)
#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U)
/*! RSVD1 - This field is reserved.
*/
#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
/*! @} */
/*! @name DBGKESREAD - KES Debug Read Register */
/*! @{ */
#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
/*! @} */
/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
/*! @{ */
#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
/*! @} */
/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
/*! @{ */
#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
/*! @} */
/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
/*! @{ */
#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
/*! @} */
/*! @name BLOCKNAME - Block Name Register */
/*! @{ */
#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
#define BCH_BLOCKNAME_NAME_SHIFT (0U)
#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
/*! @} */
/*! @name VERSION - BCH Version Register */
/*! @{ */
#define BCH_VERSION_STEP_MASK (0xFFFFU)
#define BCH_VERSION_STEP_SHIFT (0U)
#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
#define BCH_VERSION_MINOR_MASK (0xFF0000U)
#define BCH_VERSION_MINOR_SHIFT (16U)
#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
#define BCH_VERSION_MAJOR_SHIFT (24U)
#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
/*! @} */
/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
/*! @{ */
#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
#define BCH_DEBUG1_RSVD_SHIFT (9U)
/*! RSVD - This field is reserved.
*/
#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
/*! DEBUG1_PREERASECHK
* 0b0..Turn off pre-erase check
* 0b1..Turn on pre-erase check
*/
#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group BCH_Register_Masks */
/* BCH - Peripheral instance base addresses */
/** Peripheral BCH base address */
#define BCH_BASE (0x33004000u)
/** Peripheral BCH base pointer */
#define BCH ((BCH_Type *)BCH_BASE)
/** Array initializer of BCH peripheral base addresses */
#define BCH_BASE_ADDRS { BCH_BASE }
/** Array initializer of BCH peripheral base pointers */
#define BCH_BASE_PTRS { BCH }
/** Interrupt vectors for the BCH peripheral type */
#define BCH_IRQS { BCH_IRQn }
/*!
* @}
*/ /* end of group BCH_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
__IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
__IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
__IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
uint8_t RESERVED_1[8];
__I uint32_t CRCR; /**< CRC register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
__IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
uint8_t RESERVED_2[44];
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[64];
uint8_t RESERVED_3[1024];
__IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
uint8_t RESERVED_4[352];
__IO uint32_t MECR; /**< Memory Error Control register, offset: 0xAE0 */
__IO uint32_t ERRIAR; /**< Error Injection Address register, offset: 0xAE4 */
__IO uint32_t ERRIDPR; /**< Error Injection Data Pattern register, offset: 0xAE8 */
__IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern register, offset: 0xAEC */
__I uint32_t RERRAR; /**< Error Report Address register, offset: 0xAF0 */
__I uint32_t RERRDR; /**< Error Report Data register, offset: 0xAF4 */
__I uint32_t RERRSYNR; /**< Error Report Syndrome register, offset: 0xAF8 */
__IO uint32_t ERRSR; /**< Error Status register, offset: 0xAFC */
uint8_t RESERVED_5[256];
__IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
__IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
__I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
} CAN_Type;
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/*! @name MCR - Module Configuration register */
/*! @{ */
#define CAN_MCR_MAXMB_MASK (0x7FU)
#define CAN_MCR_MAXMB_SHIFT (0U)
/*! MAXMB - Number Of The Last Message Buffer
*/
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK (0x300U)
#define CAN_MCR_IDAM_SHIFT (8U)
/*! IDAM - ID Acceptance Mode
* 0b00..Format A: One full ID (standard and extended) per ID filter table element.
* 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
* 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
* 0b11..Format D: All frames rejected.
*/
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
#define CAN_MCR_FDEN_MASK (0x800U)
#define CAN_MCR_FDEN_SHIFT (11U)
/*! FDEN - CAN FD operation enable
* 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
* 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
*/
#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
#define CAN_MCR_AEN_MASK (0x1000U)
#define CAN_MCR_AEN_SHIFT (12U)
/*! AEN - Abort Enable
* 0b0..Abort disabled.
* 0b1..Abort enabled.
*/
#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
#define CAN_MCR_LPRIOEN_MASK (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT (13U)
/*! LPRIOEN - Local Priority Enable
* 0b0..Local Priority disabled.
* 0b1..Local Priority enabled.
*/
#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
#define CAN_MCR_DMA_MASK (0x8000U)
#define CAN_MCR_DMA_SHIFT (15U)
/*! DMA - DMA Enable
* 0b0..DMA feature for RX FIFO disabled.
* 0b1..DMA feature for RX FIFO enabled.
*/
#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
#define CAN_MCR_IRMQ_MASK (0x10000U)
#define CAN_MCR_IRMQ_SHIFT (16U)
/*! IRMQ - Individual Rx Masking And Queue Enable
* 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
* applications, the reading of C/S word locks the MB even if it is EMPTY.
* 0b1..Individual Rx masking and queue feature are enabled.
*/
#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
#define CAN_MCR_SRXDIS_MASK (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT (17U)
/*! SRXDIS - Self Reception Disable
* 0b0..Self-reception enabled.
* 0b1..Self-reception disabled.
*/
#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
#define CAN_MCR_DOZE_MASK (0x40000U)
#define CAN_MCR_DOZE_SHIFT (18U)
/*! DOZE - Doze Mode Enable
* 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
* 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
*/
#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
#define CAN_MCR_WAKSRC_MASK (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT (19U)
/*! WAKSRC - Wake Up Source
* 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
* 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
*/
#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
#define CAN_MCR_LPMACK_MASK (0x100000U)
#define CAN_MCR_LPMACK_SHIFT (20U)
/*! LPMACK - Low-Power Mode Acknowledge
* 0b0..FlexCAN is not in a low-power mode.
* 0b1..FlexCAN is in a low-power mode.
*/
#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
#define CAN_MCR_WRNEN_MASK (0x200000U)
#define CAN_MCR_WRNEN_SHIFT (21U)
/*! WRNEN - Warning Interrupt Enable
* 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
* 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
*/
#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
#define CAN_MCR_SLFWAK_MASK (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT (22U)
/*! SLFWAK - Self Wake Up
* 0b0..FlexCAN Self Wake Up feature is disabled.
* 0b1..FlexCAN Self Wake Up feature is enabled.
*/
#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
#define CAN_MCR_SUPV_MASK (0x800000U)
#define CAN_MCR_SUPV_SHIFT (23U)
/*! SUPV - Supervisor Mode
* 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses (ips_supervisor_access signal is ignored).
* 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
* (ips_supervisor_access negated) behaves as though the access was done to an unimplemented register location
* (ips_xfr_error asserted in the SkyBlue Interface).
*/
#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
#define CAN_MCR_FRZACK_MASK (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT (24U)
/*! FRZACK - Freeze Mode Acknowledge
* 0b0..FlexCAN not in Freeze mode, prescaler running.
* 0b1..FlexCAN in Freeze mode, prescaler stopped.
*/
#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
#define CAN_MCR_SOFTRST_MASK (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT (25U)
/*! SOFTRST - Soft Reset
* 0b0..No reset request.
* 0b1..Resets the registers affected by soft reset.
*/
#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
#define CAN_MCR_WAKMSK_MASK (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT (26U)
/*! WAKMSK - Wake Up Interrupt Mask
* 0b0..Wake Up interrupt is disabled.
* 0b1..Wake Up interrupt is enabled.
*/
#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
#define CAN_MCR_NOTRDY_MASK (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT (27U)
/*! NOTRDY - FlexCAN Not Ready
* 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
* 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
*/
#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
#define CAN_MCR_HALT_MASK (0x10000000U)
#define CAN_MCR_HALT_SHIFT (28U)
/*! HALT - Halt FlexCAN
* 0b0..No Freeze mode request.
* 0b1..Enters Freeze mode if the FRZ bit is asserted.
*/
#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
#define CAN_MCR_RFEN_MASK (0x20000000U)
#define CAN_MCR_RFEN_SHIFT (29U)
/*! RFEN - Rx FIFO Enable
* 0b0..Rx FIFO not enabled.
* 0b1..Rx FIFO enabled.
*/
#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
#define CAN_MCR_FRZ_MASK (0x40000000U)
#define CAN_MCR_FRZ_SHIFT (30U)
/*! FRZ - Freeze Enable
* 0b0..Not enabled to enter Freeze mode.
* 0b1..Enabled to enter Freeze mode.
*/
#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
#define CAN_MCR_MDIS_MASK (0x80000000U)
#define CAN_MCR_MDIS_SHIFT (31U)
/*! MDIS - Module Disable
* 0b0..Enable the FlexCAN module.
* 0b1..Disable the FlexCAN module.
*/
#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */
/*! @name CTRL1 - Control 1 register */
/*! @{ */
#define CAN_CTRL1_PROPSEG_MASK (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT (0U)
/*! PROPSEG - Propagation Segment
*/
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK (0x8U)
#define CAN_CTRL1_LOM_SHIFT (3U)
/*! LOM - Listen-Only Mode
* 0b0..Listen-Only mode is deactivated.
* 0b1..FlexCAN module operates in Listen-Only mode.
*/
#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
#define CAN_CTRL1_LBUF_MASK (0x10U)
#define CAN_CTRL1_LBUF_SHIFT (4U)
/*! LBUF - Lowest Buffer Transmitted First
* 0b0..Buffer with highest priority is transmitted first.
* 0b1..Lowest number buffer is transmitted first.
*/
#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
#define CAN_CTRL1_TSYN_MASK (0x20U)
#define CAN_CTRL1_TSYN_SHIFT (5U)
/*! TSYN - Timer Sync
* 0b0..Timer sync feature disabled
* 0b1..Timer sync feature enabled
*/
#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
#define CAN_CTRL1_BOFFREC_MASK (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT (6U)
/*! BOFFREC - Bus Off Recovery
* 0b0..Automatic recovering from Bus Off state enabled.
* 0b1..Automatic recovering from Bus Off state disabled.
*/
#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
#define CAN_CTRL1_SMP_MASK (0x80U)
#define CAN_CTRL1_SMP_SHIFT (7U)
/*! SMP - CAN Bit Sampling
* 0b0..Just one sample is used to determine the bit value.
* 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
* preceding samples; a majority rule is used.
*/
#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
/*! RWRNMSK - Rx Warning Interrupt Mask
* 0b0..Rx Warning interrupt disabled.
* 0b1..Rx Warning interrupt enabled.
*/
#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
/*! TWRNMSK - Tx Warning Interrupt Mask
* 0b0..Tx Warning interrupt disabled.
* 0b1..Tx Warning interrupt enabled.
*/
#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
#define CAN_CTRL1_LPB_MASK (0x1000U)
#define CAN_CTRL1_LPB_SHIFT (12U)
/*! LPB - Loop Back Mode
* 0b0..Loop Back disabled.
* 0b1..Loop Back enabled.
*/
#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
#define CAN_CTRL1_CLKSRC_SHIFT (13U)
/*! CLKSRC - CAN Engine Clock Source
* 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
* 0b1..The CAN engine clock source is the peripheral clock.
*/
#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT (14U)
/*! ERRMSK - Error Interrupt Mask
* 0b0..Error interrupt disabled.
* 0b1..Error interrupt enabled.
*/
#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
/*! BOFFMSK - Bus Off Interrupt Mask
* 0b0..Bus Off interrupt disabled.
* 0b1..Bus Off interrupt enabled.
*/
#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
#define CAN_CTRL1_PSEG2_MASK (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT (16U)
/*! PSEG2 - Phase Segment 2
*/
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT (19U)
/*! PSEG1 - Phase Segment 1
*/
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT (22U)
/*! RJW - Resync Jump Width
*/
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT (24U)
/*! PRESDIV - Prescaler Division Factor
*/
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */
/*! @name TIMER - Free Running Timer */
/*! @{ */
#define CAN_TIMER_TIMER_MASK (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT (0U)
/*! TIMER - Timer Value
*/
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */
/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
/*! @{ */
#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT (0U)
/*! MG - Rx Mailboxes Global Mask Bits
*/
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */
/*! @name RX14MASK - Rx 14 Mask register */
/*! @{ */
#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT (0U)
/*! RX14M - Rx Buffer 14 Mask Bits
*/
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */
/*! @name RX15MASK - Rx 15 Mask register */
/*! @{ */
#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT (0U)
/*! RX15M - Rx Buffer 15 Mask Bits
*/
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */
/*! @name ECR - Error Counter */
/*! @{ */
#define CAN_ECR_TXERRCNT_MASK (0xFFU)
#define CAN_ECR_TXERRCNT_SHIFT (0U)
/*! TXERRCNT - Transmit Error Counter
*/
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
#define CAN_ECR_RXERRCNT_SHIFT (8U)
/*! RXERRCNT - Receive Error Counter
*/
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
*/
#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
/*! RXERRCNT_FAST - Receive Error Counter for fast bits
*/
#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
/*! @} */
/*! @name ESR1 - Error and Status 1 register */
/*! @{ */
#define CAN_ESR1_WAKINT_MASK (0x1U)
#define CAN_ESR1_WAKINT_SHIFT (0U)
/*! WAKINT - Wake-Up Interrupt
* 0b0..No such occurrence.
* 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
*/
#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
#define CAN_ESR1_ERRINT_MASK (0x2U)
#define CAN_ESR1_ERRINT_SHIFT (1U)
/*! ERRINT - Error Interrupt
* 0b0..No such occurrence.
* 0b1..Indicates setting of any error bit in the Error and Status register.
*/
#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
#define CAN_ESR1_BOFFINT_MASK (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT (2U)
/*! BOFFINT - Bus Off Interrupt
* 0b0..No such occurrence.
* 0b1..FlexCAN module entered Bus Off state.
*/
#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
#define CAN_ESR1_RX_MASK (0x8U)
#define CAN_ESR1_RX_SHIFT (3U)
/*! RX - FlexCAN In Reception
* 0b0..FlexCAN is not receiving a message.
* 0b1..FlexCAN is receiving a message.
*/
#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
#define CAN_ESR1_FLTCONF_MASK (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT (4U)
/*! FLTCONF - Fault Confinement State
* 0b00..Error Active
* 0b01..Error Passive
* 0b1x..Bus Off
*/
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK (0x40U)
#define CAN_ESR1_TX_SHIFT (6U)
/*! TX - FlexCAN In Transmission
* 0b0..FlexCAN is not transmitting a message.
* 0b1..FlexCAN is transmitting a message.
*/
#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
#define CAN_ESR1_IDLE_MASK (0x80U)
#define CAN_ESR1_IDLE_SHIFT (7U)
/*! IDLE - IDLE
* 0b0..No such occurrence.
* 0b1..CAN bus is now IDLE.
*/
#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
#define CAN_ESR1_RXWRN_MASK (0x100U)
#define CAN_ESR1_RXWRN_SHIFT (8U)
/*! RXWRN - Rx Error Warning
* 0b0..No such occurrence.
* 0b1..RXERRCNT is greater than or equal to 96.
*/
#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
#define CAN_ESR1_TXWRN_MASK (0x200U)
#define CAN_ESR1_TXWRN_SHIFT (9U)
/*! TXWRN - TX Error Warning
* 0b0..No such occurrence.
* 0b1..TXERRCNT is greater than or equal to 96.
*/
#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
#define CAN_ESR1_STFERR_MASK (0x400U)
#define CAN_ESR1_STFERR_SHIFT (10U)
/*! STFERR - Stuffing Error
* 0b0..No such occurrence.
* 0b1..A stuffing error occurred since last read of this register.
*/
#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
#define CAN_ESR1_FRMERR_MASK (0x800U)
#define CAN_ESR1_FRMERR_SHIFT (11U)
/*! FRMERR - Form Error
* 0b0..No such occurrence.
* 0b1..A Form Error occurred since last read of this register.
*/
#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
#define CAN_ESR1_CRCERR_MASK (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT (12U)
/*! CRCERR - Cyclic Redundancy Check Error
* 0b0..No such occurrence.
* 0b1..A CRC error occurred since last read of this register.
*/
#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
#define CAN_ESR1_ACKERR_MASK (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT (13U)
/*! ACKERR - Acknowledge Error
* 0b0..No such occurrence.
* 0b1..An ACK error occurred since last read of this register.
*/
#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT (14U)
/*! BIT0ERR - Bit0 Error
* 0b0..No such occurrence.
* 0b1..At least one bit sent as dominant is received as recessive.
*/
#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT (15U)
/*! BIT1ERR - Bit1 Error
* 0b0..No such occurrence.
* 0b1..At least one bit sent as recessive is received as dominant.
*/
#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
#define CAN_ESR1_RWRNINT_MASK (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT (16U)
/*! RWRNINT - Rx Warning Interrupt Flag
* 0b0..No such occurrence.
* 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
*/
#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
#define CAN_ESR1_TWRNINT_MASK (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT (17U)
/*! TWRNINT - Tx Warning Interrupt Flag
* 0b0..No such occurrence.
* 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
*/
#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
#define CAN_ESR1_SYNCH_MASK (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT (18U)
/*! SYNCH - CAN Synchronization Status
* 0b0..FlexCAN is not synchronized to the CAN bus.
* 0b1..FlexCAN is synchronized to the CAN bus.
*/
#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
/*! BOFFDONEINT - Bus Off Done Interrupt
* 0b0..No such occurrence.
* 0b1..FlexCAN module has completed Bus Off process.
*/
#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
* 0b0..No such occurrence.
* 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
*/
#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
#define CAN_ESR1_ERROVR_MASK (0x200000U)
#define CAN_ESR1_ERROVR_SHIFT (21U)
/*! ERROVR - Error Overrun
* 0b0..Overrun has not occurred.
* 0b1..Overrun has occurred.
*/
#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A stuffing error occurred since last read of this register.
*/
#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A form error occurred since last read of this register.
*/
#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A CRC error occurred since last read of this register.
*/
#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..At least one bit sent as dominant is received as recessive.
*/
#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..At least one bit sent as recessive is received as dominant.
*/
#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
/*! @} */
/*! @name IMASK2 - Interrupt Masks 2 register */
/*! @{ */
#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
/*! BUF63TO32M - Buffer MBi Mask
*/
#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
/*! @} */
/*! @name IMASK1 - Interrupt Masks 1 register */
/*! @{ */
#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
/*! BUF31TO0M - Buffer MBi Mask
*/
#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
/*! @} */
/*! @name IFLAG2 - Interrupt Flags 2 register */
/*! @{ */
#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
/*! BUF63TO32I - Buffer MBi Interrupt
*/
#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
/*! @} */
/*! @name IFLAG1 - Interrupt Flags 1 register */
/*! @{ */
#define CAN_IFLAG1_BUF0I_MASK (0x1U)
#define CAN_IFLAG1_BUF0I_SHIFT (0U)
/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
* 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
* 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
*/
#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
*/
#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
#define CAN_IFLAG1_BUF5I_MASK (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT (5U)
/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
* 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
* 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
* MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
*/
#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
#define CAN_IFLAG1_BUF6I_MASK (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT (6U)
/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
* 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
* 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
*/
#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
#define CAN_IFLAG1_BUF7I_MASK (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT (7U)
/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
* 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
* 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
*/
#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
/*! BUF31TO8I - Buffer MBi Interrupt
*/
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */
/*! @name CTRL2 - Control 2 register */
/*! @{ */
#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
/*! EDFLTDIS - Edge Filter Disable
* 0b0..Edge filter is enabled
* 0b1..Edge filter is disabled
*/
#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
/*! ISOCANFDEN - ISO CAN FD Enable
* 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
* 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
*/
#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
#define CAN_CTRL2_PREXCEN_SHIFT (14U)
/*! PREXCEN - Protocol Exception Enable
* 0b0..Protocol exception is disabled.
* 0b1..Protocol exception is enabled.
*/
#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
#define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
/*! TIMER_SRC - Timer Source
* 0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
* 0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
* to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
* details about the external time tick.
*/
#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
#define CAN_CTRL2_EACEN_MASK (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT (16U)
/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
* 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
* 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
* the incoming frame. Mask bits do apply.
*/
#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
#define CAN_CTRL2_RRS_MASK (0x20000U)
#define CAN_CTRL2_RRS_SHIFT (17U)
/*! RRS - Remote Request Storing
* 0b0..Remote response frame is generated.
* 0b1..Remote request frame is stored.
*/
#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
#define CAN_CTRL2_MRP_MASK (0x40000U)
#define CAN_CTRL2_MRP_SHIFT (18U)
/*! MRP - Mailboxes Reception Priority
* 0b0..Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes.
* 0b1..Matching starts from mailboxes and continues on Rx FIFO.
*/
#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
#define CAN_CTRL2_TASD_MASK (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT (19U)
/*! TASD - Tx Arbitration Start Delay
*/
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT (24U)
/*! RFFN - Number Of Rx FIFO Filters
*/
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
/*! WRMFRZ - Write-Access To Memory In Freeze Mode
* 0b0..Maintain the write access restrictions.
* 0b1..Enable unrestricted write access to FlexCAN memory.
*/
#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
#define CAN_CTRL2_ECRWRE_MASK (0x20000000U)
#define CAN_CTRL2_ECRWRE_SHIFT (29U)
/*! ECRWRE - Error-correction Configuration Register Write Enable
* 0b0..Disable update.
* 0b1..Enable update.
*/
#define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
* 0b0..Bus off done interrupt disabled.
* 0b1..Bus off done interrupt enabled.
*/
#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
* 0b0..ERRINT_FAST error interrupt disabled.
* 0b1..ERRINT_FAST error interrupt enabled.
*/
#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
/*! @} */
/*! @name ESR2 - Error and Status 2 register */
/*! @{ */
#define CAN_ESR2_IMB_MASK (0x2000U)
#define CAN_ESR2_IMB_SHIFT (13U)
/*! IMB - Inactive Mailbox
* 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
* 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
*/
#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
#define CAN_ESR2_VPS_MASK (0x4000U)
#define CAN_ESR2_VPS_SHIFT (14U)
/*! VPS - Valid Priority Status
* 0b0..Contents of IMB and LPTM are invalid.
* 0b1..Contents of IMB and LPTM are valid.
*/
#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
#define CAN_ESR2_LPTM_MASK (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT (16U)
/*! LPTM - Lowest Priority Tx Mailbox
*/
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */
/*! @name CRCR - CRC register */
/*! @{ */
#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT (0U)
/*! TXCRC - Transmitted CRC value
*/
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT (16U)
/*! MBCRC - CRC Mailbox
*/
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */
/*! @name RXFGMASK - Rx FIFO Global Mask register */
/*! @{ */
#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT (0U)
/*! FGM - Rx FIFO Global Mask Bits
*/
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */
/*! @name RXFIR - Rx FIFO Information register */
/*! @{ */
#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT (0U)
/*! IDHIT - Identifier Acceptance Filter Hit Indicator
*/
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */
/*! @name CBT - CAN Bit Timing register */
/*! @{ */
#define CAN_CBT_EPSEG2_MASK (0x1FU)
#define CAN_CBT_EPSEG2_SHIFT (0U)
/*! EPSEG2 - Extended Phase Segment 2
*/
#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
#define CAN_CBT_EPSEG1_MASK (0x3E0U)
#define CAN_CBT_EPSEG1_SHIFT (5U)
/*! EPSEG1 - Extended Phase Segment 1
*/
#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
#define CAN_CBT_EPROPSEG_SHIFT (10U)
/*! EPROPSEG - Extended Propagation Segment
*/
#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
#define CAN_CBT_ERJW_MASK (0x1F0000U)
#define CAN_CBT_ERJW_SHIFT (16U)
/*! ERJW - Extended Resync Jump Width
*/
#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
#define CAN_CBT_EPRESDIV_SHIFT (21U)
/*! EPRESDIV - Extended Prescaler Division Factor
*/
#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
#define CAN_CBT_BTF_MASK (0x80000000U)
#define CAN_CBT_BTF_SHIFT (31U)
/*! BTF - Bit Timing Format Enable
* 0b0..Extended bit time definitions disabled.
* 0b1..Extended bit time definitions enabled.
*/
#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
/*! @} */
/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
/*! @{ */
#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT (0U)
/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
* Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
* appears on the CAN bus.
*/
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK (0xF0000U)
#define CAN_CS_DLC_SHIFT (16U)
/*! DLC - Length of the data to be stored/transmitted.
*/
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK (0x100000U)
#define CAN_CS_RTR_SHIFT (20U)
/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
*/
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK (0x200000U)
#define CAN_CS_IDE_SHIFT (21U)
/*! IDE - ID Extended. One/zero for extended/standard format frame.
*/
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK (0x400000U)
#define CAN_CS_SRR_SHIFT (22U)
/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
*/
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK (0xF000000U)
#define CAN_CS_CODE_SHIFT (24U)
/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
* the FlexCAN module itself, as part of the message buffer matching and arbitration process.
*/
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
#define CAN_CS_ESI_MASK (0x20000000U)
#define CAN_CS_ESI_SHIFT (29U)
/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
*/
#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
#define CAN_CS_BRS_MASK (0x40000000U)
#define CAN_CS_BRS_SHIFT (30U)
/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
*/
#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
#define CAN_CS_EDL_MASK (0x80000000U)
#define CAN_CS_EDL_SHIFT (31U)
/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
* The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
*/
#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */
/* The count of CAN_CS */
#define CAN_CS_COUNT (64U)
/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
/*! @{ */
#define CAN_ID_EXT_MASK (0x3FFFFU)
#define CAN_ID_EXT_SHIFT (0U)
/*! EXT - Contains extended (LOW word) identifier of message buffer.
*/
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK (0x1FFC0000U)
#define CAN_ID_STD_SHIFT (18U)
/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
*/
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK (0xE0000000U)
#define CAN_ID_PRIO_SHIFT (29U)
/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
* makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
* ID to define the transmission priority.
*/
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */
/* The count of CAN_ID */
#define CAN_ID_COUNT (64U)
/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
/*! @{ */
#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */
/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT (64U)
/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
/*! @{ */
#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */
/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT (64U)
/*! @name RXIMR - Rx Individual Mask registers */
/*! @{ */
#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT (0U)
/*! MI - Individual Mask Bits
*/
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */
/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT (64U)
/*! @name MECR - Memory Error Control register */
/*! @{ */
#define CAN_MECR_NCEFAFRZ_MASK (0x80U)
#define CAN_MECR_NCEFAFRZ_SHIFT (7U)
/*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
* 0b0..Keep normal operation.
* 0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
*/
#define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
#define CAN_MECR_ECCDIS_MASK (0x100U)
#define CAN_MECR_ECCDIS_SHIFT (8U)
/*! ECCDIS - Error Correction Disable
* 0b0..Enable memory error correction.
* 0b1..Disable memory error correction.
*/
#define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
#define CAN_MECR_RERRDIS_MASK (0x200U)
#define CAN_MECR_RERRDIS_SHIFT (9U)
/*! RERRDIS - Error Report Disable
* 0b0..Enable updates of the error report registers.
* 0b1..Disable updates of the error report registers.
*/
#define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
#define CAN_MECR_EXTERRIE_MASK (0x2000U)
#define CAN_MECR_EXTERRIE_SHIFT (13U)
/*! EXTERRIE - Extended Error Injection Enable
* 0b0..Error injection is applied only to the 32-bit word.
* 0b1..Error injection is applied to the 64-bit word.
*/
#define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
#define CAN_MECR_FAERRIE_MASK (0x4000U)
#define CAN_MECR_FAERRIE_SHIFT (14U)
/*! FAERRIE - FlexCAN Access Error Injection Enable
* 0b0..Injection is disabled.
* 0b1..Injection is enabled.
*/
#define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
#define CAN_MECR_HAERRIE_MASK (0x8000U)
#define CAN_MECR_HAERRIE_SHIFT (15U)
/*! HAERRIE - Host Access Error Injection Enable
* 0b0..Injection is disabled.
* 0b1..Injection is enabled.
*/
#define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
#define CAN_MECR_CEI_MSK_MASK (0x10000U)
#define CAN_MECR_CEI_MSK_SHIFT (16U)
/*! CEI_MSK - Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
#define CAN_MECR_FANCEI_MSK_MASK (0x40000U)
#define CAN_MECR_FANCEI_MSK_SHIFT (18U)
/*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
#define CAN_MECR_HANCEI_MSK_MASK (0x80000U)
#define CAN_MECR_HANCEI_MSK_SHIFT (19U)
/*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
#define CAN_MECR_ECRWRDIS_MASK (0x80000000U)
#define CAN_MECR_ECRWRDIS_SHIFT (31U)
/*! ECRWRDIS - Error Configuration Register Write Disable
* 0b0..Write is enabled.
* 0b1..Write is disabled.
*/
#define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
/*! @} */
/*! @name ERRIAR - Error Injection Address register */
/*! @{ */
#define CAN_ERRIAR_INJADDR_L_MASK (0x3U)
#define CAN_ERRIAR_INJADDR_L_SHIFT (0U)
/*! INJADDR_L - Error Injection Address Low
*/
#define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
#define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU)
#define CAN_ERRIAR_INJADDR_H_SHIFT (2U)
/*! INJADDR_H - Error Injection Address High
*/
#define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
/*! @} */
/*! @name ERRIDPR - Error Injection Data Pattern register */
/*! @{ */
#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU)
#define CAN_ERRIDPR_DFLIP_SHIFT (0U)
/*! DFLIP - Data flip pattern
*/
#define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
/*! @} */
/*! @name ERRIPPR - Error Injection Parity Pattern register */
/*! @{ */
#define CAN_ERRIPPR_PFLIP0_MASK (0x1FU)
#define CAN_ERRIPPR_PFLIP0_SHIFT (0U)
/*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)
*/
#define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
#define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U)
#define CAN_ERRIPPR_PFLIP1_SHIFT (8U)
/*! PFLIP1 - Parity Flip Pattern For Byte 1
*/
#define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
#define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U)
#define CAN_ERRIPPR_PFLIP2_SHIFT (16U)
/*! PFLIP2 - Parity Flip Pattern For Byte 2
*/
#define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
#define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U)
#define CAN_ERRIPPR_PFLIP3_SHIFT (24U)
/*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)
*/
#define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
/*! @} */
/*! @name RERRAR - Error Report Address register */
/*! @{ */
#define CAN_RERRAR_ERRADDR_MASK (0x3FFFU)
#define CAN_RERRAR_ERRADDR_SHIFT (0U)
/*! ERRADDR - Address Where Error Detected
*/
#define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
#define CAN_RERRAR_SAID_MASK (0x70000U)
#define CAN_RERRAR_SAID_SHIFT (16U)
/*! SAID - SAID
*/
#define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
#define CAN_RERRAR_NCE_MASK (0x1000000U)
#define CAN_RERRAR_NCE_SHIFT (24U)
/*! NCE - Non-Correctable Error
* 0b0..Reporting a correctable error
* 0b1..Reporting a non-correctable error
*/
#define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
/*! @} */
/*! @name RERRDR - Error Report Data register */
/*! @{ */
#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU)
#define CAN_RERRDR_RDATA_SHIFT (0U)
/*! RDATA - Raw data word read from memory with error
*/
#define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
/*! @} */
/*! @name RERRSYNR - Error Report Syndrome register */
/*! @{ */
#define CAN_RERRSYNR_SYND0_MASK (0x1FU)
#define CAN_RERRSYNR_SYND0_SHIFT (0U)
/*! SYND0 - Error Syndrome For Byte 0 (least significant)
*/
#define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
#define CAN_RERRSYNR_BE0_MASK (0x80U)
#define CAN_RERRSYNR_BE0_SHIFT (7U)
/*! BE0 - Byte Enabled For Byte 0 (least significant)
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
#define CAN_RERRSYNR_SYND1_MASK (0x1F00U)
#define CAN_RERRSYNR_SYND1_SHIFT (8U)
/*! SYND1 - Error Syndrome for Byte 1
*/
#define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
#define CAN_RERRSYNR_BE1_MASK (0x8000U)
#define CAN_RERRSYNR_BE1_SHIFT (15U)
/*! BE1 - Byte Enabled For Byte 1
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
#define CAN_RERRSYNR_SYND2_MASK (0x1F0000U)
#define CAN_RERRSYNR_SYND2_SHIFT (16U)
/*! SYND2 - Error Syndrome For Byte 2
*/
#define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
#define CAN_RERRSYNR_BE2_MASK (0x800000U)
#define CAN_RERRSYNR_BE2_SHIFT (23U)
/*! BE2 - Byte Enabled For Byte 2
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
#define CAN_RERRSYNR_SYND3_MASK (0x1F000000U)
#define CAN_RERRSYNR_SYND3_SHIFT (24U)
/*! SYND3 - Error Syndrome For Byte 3 (most significant)
*/
#define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
#define CAN_RERRSYNR_BE3_MASK (0x80000000U)
#define CAN_RERRSYNR_BE3_SHIFT (31U)
/*! BE3 - Byte Enabled For Byte 3 (most significant)
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
/*! @} */
/*! @name ERRSR - Error Status register */
/*! @{ */
#define CAN_ERRSR_CEIOF_MASK (0x1U)
#define CAN_ERRSR_CEIOF_SHIFT (0U)
/*! CEIOF - Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on correctable errors
* 0b1..Overrun on correctable errors
*/
#define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
#define CAN_ERRSR_FANCEIOF_MASK (0x4U)
#define CAN_ERRSR_FANCEIOF_SHIFT (2U)
/*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on non-correctable errors in FlexCAN access
* 0b1..Overrun on non-correctable errors in FlexCAN access
*/
#define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
#define CAN_ERRSR_HANCEIOF_MASK (0x8U)
#define CAN_ERRSR_HANCEIOF_SHIFT (3U)
/*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on non-correctable errors in host access
* 0b1..Overrun on non-correctable errors in host access
*/
#define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
#define CAN_ERRSR_CEIF_MASK (0x10000U)
#define CAN_ERRSR_CEIF_SHIFT (16U)
/*! CEIF - Correctable Error Interrupt Flag
* 0b0..No correctable errors were detected so far.
* 0b1..A correctable error was detected.
*/
#define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
#define CAN_ERRSR_FANCEIF_MASK (0x40000U)
#define CAN_ERRSR_FANCEIF_SHIFT (18U)
/*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
* 0b0..No non-correctable errors were detected in FlexCAN accesses so far.
* 0b1..A non-correctable error was detected in a FlexCAN access.
*/
#define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
#define CAN_ERRSR_HANCEIF_MASK (0x80000U)
#define CAN_ERRSR_HANCEIF_SHIFT (19U)
/*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
* 0b0..No non-correctable errors were detected in host accesses so far.
* 0b1..A non-correctable error was detected in a host access.
*/
#define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
/*! @} */
/*! @name FDCTRL - CAN FD Control register */
/*! @{ */
#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
/*! TDCVAL - Transceiver Delay Compensation Value
*/
#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
/*! TDCOFF - Transceiver Delay Compensation Offset
*/
#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
/*! TDCFAIL - Transceiver Delay Compensation Fail
* 0b0..Measured loop delay is in range.
* 0b1..Measured loop delay is out of range.
*/
#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
#define CAN_FDCTRL_TDCEN_SHIFT (15U)
/*! TDCEN - Transceiver Delay Compensation Enable
* 0b0..TDC is disabled
* 0b1..TDC is enabled
*/
#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
/*! MBDSR0 - Message Buffer Data Size for Region 0
* 0b00..Selects 8 bytes per message buffer.
* 0b01..Selects 16 bytes per message buffer.
* 0b10..Selects 32 bytes per message buffer.
* 0b11..Selects 64 bytes per message buffer.
*/
#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
/*! MBDSR1 - Message Buffer Data Size for Region 1
* 0b00..Selects 8 bytes per message buffer.
* 0b01..Selects 16 bytes per message buffer.
* 0b10..Selects 32 bytes per message buffer.
* 0b11..Selects 64 bytes per message buffer.
*/
#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
#define CAN_FDCTRL_FDRATE_SHIFT (31U)
/*! FDRATE - Bit Rate Switch Enable
* 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
* 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
*/
#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
/*! @} */
/*! @name FDCBT - CAN FD Bit Timing register */
/*! @{ */
#define CAN_FDCBT_FPSEG2_MASK (0x7U)
#define CAN_FDCBT_FPSEG2_SHIFT (0U)
/*! FPSEG2 - Fast Phase Segment 2
*/
#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
#define CAN_FDCBT_FPSEG1_SHIFT (5U)
/*! FPSEG1 - Fast Phase Segment 1
*/
#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
/*! FPROPSEG - Fast Propagation Segment
*/
#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
#define CAN_FDCBT_FRJW_MASK (0x70000U)
#define CAN_FDCBT_FRJW_SHIFT (16U)
/*! FRJW - Fast Resync Jump Width
*/
#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
/*! FPRESDIV - Fast Prescaler Division Factor
*/
#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
/*! @} */
/*! @name FDCRC - CAN FD CRC register */
/*! @{ */
#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
/*! FD_TXCRC - Extended Transmitted CRC value
*/
#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
*/
#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral FLEXCAN1 base address */
#define FLEXCAN1_BASE (0x308C0000u)
/** Peripheral FLEXCAN1 base pointer */
#define FLEXCAN1 ((CAN_Type *)FLEXCAN1_BASE)
/** Peripheral FLEXCAN2 base address */
#define FLEXCAN2_BASE (0x308D0000u)
/** Peripheral FLEXCAN2 base pointer */
#define FLEXCAN2 ((CAN_Type *)FLEXCAN2_BASE)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { 0u, FLEXCAN1_BASE, FLEXCAN2_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { (CAN_Type *)0u, FLEXCAN1, FLEXCAN2 }
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
#define CAN_Error_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN_FD1_IRQn, CAN_FD2_IRQn }
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
* @{
*/
/** CCM - Register Layout Typedef */
typedef struct {
__IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */
__IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */
__IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */
__IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */
uint8_t RESERVED_0[2032];
struct { /* offset: 0x800, array step: 0x10 */
__IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
__IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
__IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
__IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
} PLL_CTRL[39];
uint8_t RESERVED_1[13712];
struct { /* offset: 0x4000, array step: 0x10 */
__IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
__IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
__IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
__IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
} CCGR[192];
uint8_t RESERVED_2[13312];
struct { /* offset: 0x8000, array step: 0x80 */
__IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */
__IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */
__IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */
__IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */
__IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
__IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
__IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
__IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
__IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
__IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
__IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
__IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
__IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
__IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
__IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
__IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
uint8_t RESERVED_0[48];
__IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
__IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
__IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
__IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
} ROOT[142];
} CCM_Type;
/* ----------------------------------------------------------------------------
-- CCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Register_Masks CCM Register Masks
* @{
*/
/*! @name GPR0 - General Purpose Register */
/*! @{ */
#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU)
#define CCM_GPR0_GP0_SHIFT (0U)
#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
/*! @} */
/*! @name GPR0_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU)
#define CCM_GPR0_SET_GP0_SHIFT (0U)
#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
/*! @} */
/*! @name GPR0_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU)
#define CCM_GPR0_CLR_GP0_SHIFT (0U)
#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
/*! @} */
/*! @name GPR0_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU)
#define CCM_GPR0_TOG_GP0_SHIFT (0U)
#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
/*! @} */
/*! @name PLL_CTRL - CCM PLL Control Register */
/*! @{ */
#define CCM_PLL_CTRL_SETTING0_MASK (0x3U)
#define CCM_PLL_CTRL_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
#define CCM_PLL_CTRL_SETTING1_MASK (0x30U)
#define CCM_PLL_CTRL_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
#define CCM_PLL_CTRL_SETTING2_MASK (0x300U)
#define CCM_PLL_CTRL_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U)
#define CCM_PLL_CTRL_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
/*! @} */
/* The count of CCM_PLL_CTRL */
#define CCM_PLL_CTRL_COUNT (39U)
/*! @name PLL_CTRL_SET - CCM PLL Control Register */
/*! @{ */
#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U)
#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U)
#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U)
#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U)
#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
/*! @} */
/* The count of CCM_PLL_CTRL_SET */
#define CCM_PLL_CTRL_SET_COUNT (39U)
/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
/*! @{ */
#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U)
#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U)
#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U)
#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U)
#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
/*! @} */
/* The count of CCM_PLL_CTRL_CLR */
#define CCM_PLL_CTRL_CLR_COUNT (39U)
/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
/*! @{ */
#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U)
#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U)
#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U)
#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U)
#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_PLL_CTRL_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
/*! @} */
/* The count of CCM_PLL_CTRL_TOG */
#define CCM_PLL_CTRL_TOG_COUNT (39U)
/*! @name CCGR - CCM Clock Gating Register */
/*! @{ */
#define CCM_CCGR_SETTING0_MASK (0x3U)
#define CCM_CCGR_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
#define CCM_CCGR_SETTING1_MASK (0x30U)
#define CCM_CCGR_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
#define CCM_CCGR_SETTING2_MASK (0x300U)
#define CCM_CCGR_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
#define CCM_CCGR_SETTING3_MASK (0x3000U)
#define CCM_CCGR_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
/*! @} */
/* The count of CCM_CCGR */
#define CCM_CCGR_COUNT (192U)
/*! @name CCGR_SET - CCM Clock Gating Register */
/*! @{ */
#define CCM_CCGR_SET_SETTING0_MASK (0x3U)
#define CCM_CCGR_SET_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SET_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
#define CCM_CCGR_SET_SETTING1_MASK (0x30U)
#define CCM_CCGR_SET_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SET_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
#define CCM_CCGR_SET_SETTING2_MASK (0x300U)
#define CCM_CCGR_SET_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SET_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
#define CCM_CCGR_SET_SETTING3_MASK (0x3000U)
#define CCM_CCGR_SET_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_SET_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
/*! @} */
/* The count of CCM_CCGR_SET */
#define CCM_CCGR_SET_COUNT (192U)
/*! @name CCGR_CLR - CCM Clock Gating Register */
/*! @{ */
#define CCM_CCGR_CLR_SETTING0_MASK (0x3U)
#define CCM_CCGR_CLR_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_CLR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
#define CCM_CCGR_CLR_SETTING1_MASK (0x30U)
#define CCM_CCGR_CLR_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_CLR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
#define CCM_CCGR_CLR_SETTING2_MASK (0x300U)
#define CCM_CCGR_CLR_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_CLR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U)
#define CCM_CCGR_CLR_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_CLR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
/*! @} */
/* The count of CCM_CCGR_CLR */
#define CCM_CCGR_CLR_COUNT (192U)
/*! @name CCGR_TOG - CCM Clock Gating Register */
/*! @{ */
#define CCM_CCGR_TOG_SETTING0_MASK (0x3U)
#define CCM_CCGR_TOG_SETTING0_SHIFT (0U)
/*! SETTING0
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_TOG_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
#define CCM_CCGR_TOG_SETTING1_MASK (0x30U)
#define CCM_CCGR_TOG_SETTING1_SHIFT (4U)
/*! SETTING1
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_TOG_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
#define CCM_CCGR_TOG_SETTING2_MASK (0x300U)
#define CCM_CCGR_TOG_SETTING2_SHIFT (8U)
/*! SETTING2
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_TOG_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U)
#define CCM_CCGR_TOG_SETTING3_SHIFT (12U)
/*! SETTING3
* 0b00..Domain clocks not needed
* 0b01..Domain clocks needed when in RUN
* 0b10..Domain clocks needed when in RUN and WAIT
* 0b11..Domain clocks needed all the time
*/
#define CCM_CCGR_TOG_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
/*! @} */
/* The count of CCM_CCGR_TOG */
#define CCM_CCGR_TOG_COUNT (192U)
/*! @name TARGET_ROOT - Target Register */
/*! @{ */
#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU)
#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_TARGET_ROOT_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U)
#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U)
/*! PRE_PODF
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_TARGET_ROOT_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U)
#define CCM_TARGET_ROOT_MUX_SHIFT (24U)
#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U)
#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U)
/*! ENABLE
* 0b0..clock root is OFF
* 0b1..clock root is ON
*/
#define CCM_TARGET_ROOT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
/*! @} */
/* The count of CCM_TARGET_ROOT */
#define CCM_TARGET_ROOT_COUNT (142U)
/*! @name TARGET_ROOT_SET - Target Register */
/*! @{ */
#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU)
#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_TARGET_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U)
#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U)
/*! PRE_PODF
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_TARGET_ROOT_SET_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U)
#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U)
#define CCM_TARGET_ROOT_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U)
#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U)
/*! ENABLE
* 0b0..clock root is OFF
* 0b1..clock root is ON
*/
#define CCM_TARGET_ROOT_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
/*! @} */
/* The count of CCM_TARGET_ROOT_SET */
#define CCM_TARGET_ROOT_SET_COUNT (142U)
/*! @name TARGET_ROOT_CLR - Target Register */
/*! @{ */
#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU)
#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_TARGET_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U)
#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U)
/*! PRE_PODF
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U)
#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U)
#define CCM_TARGET_ROOT_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U)
#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U)
/*! ENABLE
* 0b0..clock root is OFF
* 0b1..clock root is ON
*/
#define CCM_TARGET_ROOT_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
/*! @} */
/* The count of CCM_TARGET_ROOT_CLR */
#define CCM_TARGET_ROOT_CLR_COUNT (142U)
/*! @name TARGET_ROOT_TOG - Target Register */
/*! @{ */
#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU)
#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_TARGET_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U)
#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U)
/*! PRE_PODF
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U)
#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U)
#define CCM_TARGET_ROOT_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U)
#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U)
/*! ENABLE
* 0b0..clock root is OFF
* 0b1..clock root is ON
*/
#define CCM_TARGET_ROOT_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
/*! @} */
/* The count of CCM_TARGET_ROOT_TOG */
#define CCM_TARGET_ROOT_TOG_COUNT (142U)
/*! @name MISC - Miscellaneous Register */
/*! @{ */
#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U)
#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U)
#define CCM_MISC_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
#define CCM_MISC_TIMEOUT_MASK (0x10U)
#define CCM_MISC_TIMEOUT_SHIFT (4U)
#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
#define CCM_MISC_VIOLATE_MASK (0x100U)
#define CCM_MISC_VIOLATE_SHIFT (8U)
#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
/*! @} */
/* The count of CCM_MISC */
#define CCM_MISC_COUNT (142U)
/*! @name MISC_ROOT_SET - Miscellaneous Register */
/*! @{ */
#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U)
#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U)
#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U)
#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U)
#define CCM_MISC_ROOT_SET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U)
#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U)
#define CCM_MISC_ROOT_SET_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
/*! @} */
/* The count of CCM_MISC_ROOT_SET */
#define CCM_MISC_ROOT_SET_COUNT (142U)
/*! @name MISC_ROOT_CLR - Miscellaneous Register */
/*! @{ */
#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U)
#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U)
#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U)
#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U)
#define CCM_MISC_ROOT_CLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U)
#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U)
#define CCM_MISC_ROOT_CLR_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
/*! @} */
/* The count of CCM_MISC_ROOT_CLR */
#define CCM_MISC_ROOT_CLR_COUNT (142U)
/*! @name MISC_ROOT_TOG - Miscellaneous Register */
/*! @{ */
#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U)
#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U)
#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U)
#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U)
#define CCM_MISC_ROOT_TOG_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U)
#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U)
#define CCM_MISC_ROOT_TOG_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
/*! @} */
/* The count of CCM_MISC_ROOT_TOG */
#define CCM_MISC_ROOT_TOG_COUNT (142U)
/*! @name POST - Post Divider Register */
/*! @{ */
#define CCM_POST_POST_PODF_MASK (0x3FU)
#define CCM_POST_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
#define CCM_POST_BUSY1_MASK (0x80U)
#define CCM_POST_BUSY1_SHIFT (7U)
#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
#define CCM_POST_SELECT_MASK (0x10000000U)
#define CCM_POST_SELECT_SHIFT (28U)
/*! SELECT
* 0b0..select branch A
* 0b1..select branch B
*/
#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
#define CCM_POST_BUSY2_MASK (0x80000000U)
#define CCM_POST_BUSY2_SHIFT (31U)
#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
/*! @} */
/* The count of CCM_POST */
#define CCM_POST_COUNT (142U)
/*! @name POST_ROOT_SET - Post Divider Register */
/*! @{ */
#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU)
#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_POST_ROOT_SET_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U)
#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U)
#define CCM_POST_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U)
#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U)
/*! SELECT
* 0b0..select branch A
* 0b1..select branch B
*/
#define CCM_POST_ROOT_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U)
#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U)
#define CCM_POST_ROOT_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
/*! @} */
/* The count of CCM_POST_ROOT_SET */
#define CCM_POST_ROOT_SET_COUNT (142U)
/*! @name POST_ROOT_CLR - Post Divider Register */
/*! @{ */
#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU)
#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_POST_ROOT_CLR_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U)
#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U)
#define CCM_POST_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U)
#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U)
/*! SELECT
* 0b0..select branch A
* 0b1..select branch B
*/
#define CCM_POST_ROOT_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U)
#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U)
#define CCM_POST_ROOT_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
/*! @} */
/* The count of CCM_POST_ROOT_CLR */
#define CCM_POST_ROOT_CLR_COUNT (142U)
/*! @name POST_ROOT_TOG - Post Divider Register */
/*! @{ */
#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU)
#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U)
/*! POST_PODF
* 0b000000..Divide by 1
* 0b000001..Divide by 2
* 0b000010..Divide by 3
* 0b000011..Divide by 4
* 0b000100..Divide by 5
* 0b000101..Divide by 6
* 0b111111..Divide by 64
*/
#define CCM_POST_ROOT_TOG_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U)
#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U)
#define CCM_POST_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U)
#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U)
/*! SELECT
* 0b0..select branch A
* 0b1..select branch B
*/
#define CCM_POST_ROOT_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U)
#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U)
#define CCM_POST_ROOT_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
/*! @} */
/* The count of CCM_POST_ROOT_TOG */
#define CCM_POST_ROOT_TOG_COUNT (142U)
/*! @name PRE - Pre Divider Register */
/*! @{ */
#define CCM_PRE_PRE_PODF_B_MASK (0x7U)
#define CCM_PRE_PRE_PODF_B_SHIFT (0U)
/*! PRE_PODF_B
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
#define CCM_PRE_BUSY0_MASK (0x8U)
#define CCM_PRE_BUSY0_SHIFT (3U)
#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
#define CCM_PRE_MUX_B_MASK (0x700U)
#define CCM_PRE_MUX_B_SHIFT (8U)
#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
#define CCM_PRE_EN_B_MASK (0x1000U)
#define CCM_PRE_EN_B_SHIFT (12U)
/*! EN_B
* 0b0..Clock shutdown
* 0b1..Clock ON
*/
#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
#define CCM_PRE_BUSY1_MASK (0x8000U)
#define CCM_PRE_BUSY1_SHIFT (15U)
#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
#define CCM_PRE_PRE_PODF_A_MASK (0x70000U)
#define CCM_PRE_PRE_PODF_A_SHIFT (16U)
/*! PRE_PODF_A
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
#define CCM_PRE_BUSY3_MASK (0x80000U)
#define CCM_PRE_BUSY3_SHIFT (19U)
#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
#define CCM_PRE_MUX_A_MASK (0x7000000U)
#define CCM_PRE_MUX_A_SHIFT (24U)
#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
#define CCM_PRE_EN_A_MASK (0x10000000U)
#define CCM_PRE_EN_A_SHIFT (28U)
/*! EN_A
* 0b0..Clock shutdown
* 0b1..clock ON
*/
#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
#define CCM_PRE_BUSY4_MASK (0x80000000U)
#define CCM_PRE_BUSY4_SHIFT (31U)
#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
/*! @} */
/* The count of CCM_PRE */
#define CCM_PRE_COUNT (142U)
/*! @name PRE_ROOT_SET - Pre Divider Register */
/*! @{ */
#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U)
#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U)
/*! PRE_PODF_B
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U)
#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U)
#define CCM_PRE_ROOT_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U)
#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U)
#define CCM_PRE_ROOT_SET_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U)
#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U)
/*! EN_B
* 0b0..Clock shutdown
* 0b1..Clock ON
*/
#define CCM_PRE_ROOT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U)
#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U)
#define CCM_PRE_ROOT_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U)
#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U)
/*! PRE_PODF_A
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U)
#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U)
#define CCM_PRE_ROOT_SET_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U)
#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U)
#define CCM_PRE_ROOT_SET_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U)
#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U)
/*! EN_A
* 0b0..Clock shutdown
* 0b1..clock ON
*/
#define CCM_PRE_ROOT_SET_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U)
#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U)
#define CCM_PRE_ROOT_SET_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
/*! @} */
/* The count of CCM_PRE_ROOT_SET */
#define CCM_PRE_ROOT_SET_COUNT (142U)
/*! @name PRE_ROOT_CLR - Pre Divider Register */
/*! @{ */
#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U)
#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U)
/*! PRE_PODF_B
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U)
#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U)
#define CCM_PRE_ROOT_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U)
#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U)
#define CCM_PRE_ROOT_CLR_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U)
#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U)
/*! EN_B
* 0b0..Clock shutdown
* 0b1..Clock ON
*/
#define CCM_PRE_ROOT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U)
#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U)
#define CCM_PRE_ROOT_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U)
#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U)
/*! PRE_PODF_A
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U)
#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U)
#define CCM_PRE_ROOT_CLR_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U)
#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U)
#define CCM_PRE_ROOT_CLR_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U)
#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U)
/*! EN_A
* 0b0..Clock shutdown
* 0b1..clock ON
*/
#define CCM_PRE_ROOT_CLR_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U)
#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U)
#define CCM_PRE_ROOT_CLR_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
/*! @} */
/* The count of CCM_PRE_ROOT_CLR */
#define CCM_PRE_ROOT_CLR_COUNT (142U)
/*! @name PRE_ROOT_TOG - Pre Divider Register */
/*! @{ */
#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U)
#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U)
/*! PRE_PODF_B
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U)
#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U)
#define CCM_PRE_ROOT_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U)
#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U)
#define CCM_PRE_ROOT_TOG_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U)
#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U)
/*! EN_B
* 0b0..Clock shutdown
* 0b1..Clock ON
*/
#define CCM_PRE_ROOT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U)
#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U)
#define CCM_PRE_ROOT_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U)
#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U)
/*! PRE_PODF_A
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 3
* 0b011..Divide by 4
* 0b100..Divide by 5
* 0b101..Divide by 6
* 0b110..Divide by 7
* 0b111..Divide by 8
*/
#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U)
#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U)
#define CCM_PRE_ROOT_TOG_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U)
#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U)
#define CCM_PRE_ROOT_TOG_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U)
#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U)
/*! EN_A
* 0b0..Clock shutdown
* 0b1..clock ON
*/
#define CCM_PRE_ROOT_TOG_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U)
#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U)
#define CCM_PRE_ROOT_TOG_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
/*! @} */
/* The count of CCM_PRE_ROOT_TOG */
#define CCM_PRE_ROOT_TOG_COUNT (142U)
/*! @name ACCESS_CTRL - Access Control Register */
/*! @{ */
#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU)
#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U)
#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U)
#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U)
#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U)
#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U)
#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U)
#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U)
#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U)
#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U)
/*! OWNER_ID
* 0b00..domaino
* 0b01..domain1
* 0b10..domain2
* 0b11..domain3
*/
#define CCM_ACCESS_CTRL_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U)
#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U)
/*! MUTEX
* 0b0..Semaphore is free to take
* 0b1..Semaphore is taken
*/
#define CCM_ACCESS_CTRL_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U)
#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U)
/*! DOMAIN0_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U)
#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U)
/*! DOMAIN1_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U)
#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U)
/*! DOMAIN2_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U)
#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U)
/*! DOMAIN3_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U)
#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U)
/*! SEMA_EN
* 0b0..Disable
* 0b1..Enable
*/
#define CCM_ACCESS_CTRL_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U)
#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U)
/*! LOCK
* 0b0..Access control inactive
* 0b1..Access control active
*/
#define CCM_ACCESS_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
/*! @} */
/* The count of CCM_ACCESS_CTRL */
#define CCM_ACCESS_CTRL_COUNT (142U)
/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
/*! @{ */
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U)
#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U)
/*! OWNER_ID
* 0b00..domaino
* 0b01..domain1
* 0b10..domain2
* 0b11..domain3
*/
#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U)
#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U)
/*! MUTEX
* 0b0..Semaphore is free to take
* 0b1..Semaphore is taken
*/
#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
/*! DOMAIN0_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
/*! DOMAIN1_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
/*! DOMAIN2_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
/*! DOMAIN3_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U)
/*! SEMA_EN
* 0b0..Disable
* 0b1..Enable
*/
#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U)
#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U)
/*! LOCK
* 0b0..Access control inactive
* 0b1..Access control active
*/
#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
/*! @} */
/* The count of CCM_ACCESS_CTRL_ROOT_SET */
#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (142U)
/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
/*! @{ */
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U)
/*! OWNER_ID
* 0b00..domaino
* 0b01..domain1
* 0b10..domain2
* 0b11..domain3
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U)
/*! MUTEX
* 0b0..Semaphore is free to take
* 0b1..Semaphore is taken
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
/*! DOMAIN0_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
/*! DOMAIN1_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
/*! DOMAIN2_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
/*! DOMAIN3_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U)
/*! SEMA_EN
* 0b0..Disable
* 0b1..Enable
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U)
#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U)
/*! LOCK
* 0b0..Access control inactive
* 0b1..Access control active
*/
#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
/*! @} */
/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (142U)
/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
/*! @{ */
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U)
/*! OWNER_ID
* 0b00..domaino
* 0b01..domain1
* 0b10..domain2
* 0b11..domain3
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U)
/*! MUTEX
* 0b0..Semaphore is free to take
* 0b1..Semaphore is taken
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
/*! DOMAIN0_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
/*! DOMAIN1_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
/*! DOMAIN2_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
/*! DOMAIN3_WHITELIST
* 0b0..Domain cannot change the setting
* 0b1..Domain can change the setting
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U)
/*! SEMA_EN
* 0b0..Disable
* 0b1..Enable
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U)
#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U)
/*! LOCK
* 0b0..Access control inactive
* 0b1..Access control active
*/
#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
/*! @} */
/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (142U)
/*!
* @}
*/ /* end of group CCM_Register_Masks */
/* CCM - Peripheral instance base addresses */
/** Peripheral CCM base address */
#define CCM_BASE (0x30380000u)
/** Peripheral CCM base pointer */
#define CCM ((CCM_Type *)CCM_BASE)
/** Array initializer of CCM peripheral base addresses */
#define CCM_BASE_ADDRS { CCM_BASE }
/** Array initializer of CCM peripheral base pointers */
#define CCM_BASE_PTRS { CCM }
/** Interrupt vectors for the CCM peripheral type */
#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn }
/*!
* @}
*/ /* end of group CCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM_ANALOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
* @{
*/
/** CCM_ANALOG - Register Layout Typedef */
typedef struct {
__IO uint32_t AUDIO_PLL1_GEN_CTRL; /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
__IO uint32_t AUDIO_PLL1_FDIV_CTL0; /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
__IO uint32_t AUDIO_PLL1_FDIV_CTL1; /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
__IO uint32_t AUDIO_PLL1_SSCG_CTRL; /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
__IO uint32_t AUDIO_PLL1_MNIT_CTRL; /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
__IO uint32_t AUDIO_PLL2_GEN_CTRL; /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
__IO uint32_t AUDIO_PLL2_FDIV_CTL0; /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
__IO uint32_t AUDIO_PLL2_FDIV_CTL1; /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
__IO uint32_t AUDIO_PLL2_SSCG_CTRL; /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
__IO uint32_t AUDIO_PLL2_MNIT_CTRL; /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
__IO uint32_t VIDEO_PLL1_GEN_CTRL; /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
__IO uint32_t VIDEO_PLL1_FDIV_CTL0; /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
__IO uint32_t VIDEO_PLL1_FDIV_CTL1; /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
__IO uint32_t VIDEO_PLL1_SSCG_CTRL; /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
__IO uint32_t VIDEO_PLL1_MNIT_CTRL; /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
uint8_t RESERVED_0[20];
__IO uint32_t DRAM_PLL_GEN_CTRL; /**< DRAM PLL General Function Control Register, offset: 0x50 */
__IO uint32_t DRAM_PLL_FDIV_CTL0; /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
__IO uint32_t DRAM_PLL_FDIV_CTL1; /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
__IO uint32_t DRAM_PLL_SSCG_CTRL; /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
__IO uint32_t DRAM_PLL_MNIT_CTRL; /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
__IO uint32_t GPU_PLL_GEN_CTRL; /**< GPU PLL General Function Control Register, offset: 0x64 */
__IO uint32_t GPU_PLL_FDIV_CTL0; /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
__IO uint32_t GPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x6C */
__IO uint32_t GPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x70 */
__IO uint32_t VPU_PLL_GEN_CTRL; /**< VPU PLL General Function Control Register, offset: 0x74 */
__IO uint32_t VPU_PLL_FDIV_CTL0; /**< VPU PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
__IO uint32_t VPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x7C */
__IO uint32_t VPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x80 */
__IO uint32_t ARM_PLL_GEN_CTRL; /**< ARM PLL General Function Control Register, offset: 0x84 */
__IO uint32_t ARM_PLL_FDIV_CTL0; /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
__IO uint32_t ARM_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x8C */
__IO uint32_t ARM_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x90 */
__IO uint32_t SYS_PLL1_GEN_CTRL; /**< SYS PLL1 General Function Control Register, offset: 0x94 */
__IO uint32_t SYS_PLL1_FDIV_CTL0; /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
__IO uint32_t SYS_PLL1_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x9C */
uint8_t RESERVED_1[96];
__IO uint32_t SYS_PLL1_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x100 */
__IO uint32_t SYS_PLL2_GEN_CTRL; /**< SYS PLL2 General Function Control Register, offset: 0x104 */
__IO uint32_t SYS_PLL2_FDIV_CTL0; /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
__IO uint32_t SYS_PLL2_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x10C */
__IO uint32_t SYS_PLL2_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x110 */
__IO uint32_t SYS_PLL3_GEN_CTRL; /**< SYS PLL3 General Function Control Register, offset: 0x114 */
__IO uint32_t SYS_PLL3_FDIV_CTL0; /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
__IO uint32_t SYS_PLL3_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x11C */
__IO uint32_t SYS_PLL3_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x120 */
__IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x124 */
__IO uint32_t ANAMIX_PLL_MNIT_CTL; /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
uint8_t RESERVED_2[1748];
__I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x800 */
} CCM_ANALOG_Type;
/* ----------------------------------------------------------------------------
-- CCM_ANALOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
* @{
*/
/*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
/*! @} */
/*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
/*! SEL_PF
* 0b00..Down spread
* 0b01..Up spread
* 0b1x..Center spread
*/
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
/*! SSCG_EN
* 0b1..Enable Spread Spectrum Mode
* 0b0..Disable Spread Spectrum Mode
*/
#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
/*! @} */
/*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
/*! @} */
/*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
/*! @} */
/*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
/*! SEL_PF
* 0b00..Down spread
* 0b01..Up spread
* 0b1x..Center spread
*/
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
/*! SSCG_EN
* 0b1..Enable Spread Spectrum Mode
* 0b0..Disable Spread Spectrum Mode
*/
#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
/*! @} */
/*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
/*! @} */
/*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
/*! @{ */
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
/*! @} */
/*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
/*! @{ */
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
/*! SEL_PF
* 0b00..Down spread
* 0b01..Up spread
* 0b1x..Center spread
*/
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
/*! SSCG_EN
* 0b1..Enable Spread Spectrum Mode
* 0b0..Disable Spread Spectrum Mode
*/
#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
/*! @} */
/*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
/*! @} */
/*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
/*! @{ */
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
/*! @{ */
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
/*! @} */
/*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
/*! @{ */
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
/*! SEL_PF
* 0b00..Down spread
* 0b01..Up spread
* 0b1x..Center spread
*/
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
/*! SSCG_EN
* 0b1..Enable Spread Spectrum Mode
* 0b0..Disable Spread Spectrum Mode
*/
#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
/*! @} */
/*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK (0x7U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK (0x8000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
/*! @} */
/*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
/*! @{ */
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name VPU_PLL_GEN_CTRL - VPU PLL General Function Control Register */
/*! @{ */
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name VPU_PLL_FDIV_CTL0 - VPU PLL Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_VPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name VPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_VPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name VPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_VPU_PLL_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
/*! @{ */
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
/*! PLL_REF_CLK_SEL
* 0b00..24M_REF_CLK
* 0b01..PAD_CLK
* 0b10..Reserved
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
/*! PAD_CLK_SEL
* 0b00..CLKIN1 XOR CLKIN2
* 0b01..CLKIN2
* 0b10..CLKIN1
* 0b11..Reserved
*/
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
/*! PLL_LOCK_SEL
* 0b0..Using PLL maximum lock time
* 0b1..Using PLL output lock
*/
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
/*! @} */
/*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
/*! @} */
/*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
/*! @} */
/*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
/*! @{ */
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK (0x3U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT (0U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK (0x4000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
/*! FSEL
* 0b0..FEED_OUT = FREF
* 0b1..FEED_OUT = FEED
*/
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
/*! AFCINIT_SEL
* 0b0..nominal delay
* 0b1..nominal delay * 2
*/
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
/*! PBIAS_CTRL
* 0b0..0.50*VDD
* 0b1..0.67*VDD
*/
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U)
#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK)
/*! @} */
/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
/*! @{ */
#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
/*! OSC_32K_SEL
* 0b0..Divided by 24M clock
* 0b1..32K Oscillator
*/
#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
/*! @} */
/*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
/*! @{ */
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U)
#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK)
/*! @} */
/*! @name DIGPROG - DIGPROG Register */
/*! @{ */
#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU)
#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U)
#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CCM_ANALOG_Register_Masks */
/* CCM_ANALOG - Peripheral instance base addresses */
/** Peripheral CCM_ANALOG base address */
#define CCM_ANALOG_BASE (0x30360000u)
/** Peripheral CCM_ANALOG base pointer */
#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
/** Array initializer of CCM_ANALOG peripheral base addresses */
#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
/** Array initializer of CCM_ANALOG peripheral base pointers */
#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
/*!
* @}
*/ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CEC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CEC_Peripheral_Access_Layer CEC Peripheral Access Layer
* @{
*/
/** CEC - Register Layout Typedef */
typedef struct {
__IO uint8_t CEC_CTRL; /**< CEC Control Register This register handles the main control of the CEC initiator., offset: 0x0 */
uint8_t RESERVED_0[1];
__IO uint8_t CEC_MASK; /**< CEC Interrupt Mask Register This read/write register masks/unmasks the interrupt events., offset: 0x2 */
uint8_t RESERVED_1[2];
__IO uint8_t CEC_ADDR_L; /**< CEC Logical Address Register Low This register indicates the logical address(es) allocated to the CEC device., offset: 0x5 */
__IO uint8_t CEC_ADDR_H; /**< CEC Logical Address Register High This register indicates the logical address(es) allocated to the CEC device., offset: 0x6 */
__IO uint8_t CEC_TX_CNT; /**< CEC TX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the transmitter data buffer., offset: 0x7 */
__I uint8_t CEC_RX_CNT; /**< CEC RX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the receiver data buffer., offset: 0x8 */
uint8_t RESERVED_2[39];
__IO uint8_t CEC_LOCK; /**< CEC Buffer Lock Register, offset: 0x30 */
__IO uint8_t CEC_WAKEUPCTRL; /**< CEC Wake-up Control Register After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the message opcode[7:0] against one of the previously defined values to generate the wake-up status: Wakeupstatus is 1 when: received opcode is 0x04 and opcode0x04en is 1 or received opcode is 0x0D and opcode0x0Den is 1 or received opcode is 0x41 and opcode0x41en is 1 or received opcode is 0x42 and opcode0x42en is 1 or received opcode is 0x44 and opcode0x44en is 1 or received opcode is 0x70 and opcode0x70en is 1 or received opcode is 0x82 and opcode0x82en is 1 or received opcode is 0x86 and opcode0x86en is 1 Wakeupstatus is 0 when none of the previous conditions are true., offset: 0x31 */
} CEC_Type;
/* ----------------------------------------------------------------------------
-- CEC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CEC_Register_Masks CEC Register Masks
* @{
*/
/*! @name CEC_CTRL - CEC Control Register This register handles the main control of the CEC initiator. */
/*! @{ */
#define CEC_CEC_CTRL_SEND_MASK (0x1U)
#define CEC_CEC_CTRL_SEND_SHIFT (0U)
/*! send - - 1'b1: Set by software to trigger CEC sending a frame as an initiator.
*/
#define CEC_CEC_CTRL_SEND(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_SEND_SHIFT)) & CEC_CEC_CTRL_SEND_MASK)
#define CEC_CEC_CTRL_FRAME_TYP_MASK (0x6U)
#define CEC_CEC_CTRL_FRAME_TYP_SHIFT (1U)
/*! frame_typ - - 2'b00: Signal Free Time = 3-bit periods.
*/
#define CEC_CEC_CTRL_FRAME_TYP(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_FRAME_TYP_SHIFT)) & CEC_CEC_CTRL_FRAME_TYP_MASK)
#define CEC_CEC_CTRL_BC_NACK_MASK (0x8U)
#define CEC_CEC_CTRL_BC_NACK_SHIFT (3U)
/*! bc_nack - - 1'b1: Set by software to NACK the received broadcast message.
*/
#define CEC_CEC_CTRL_BC_NACK(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_BC_NACK_SHIFT)) & CEC_CEC_CTRL_BC_NACK_MASK)
#define CEC_CEC_CTRL_STANDBY_MASK (0x10U)
#define CEC_CEC_CTRL_STANDBY_SHIFT (4U)
/*! standby - - 1: CEC controller responds with a NACK to all messages and generates a wakeup status for opcode.
*/
#define CEC_CEC_CTRL_STANDBY(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_STANDBY_SHIFT)) & CEC_CEC_CTRL_STANDBY_MASK)
#define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_MASK (0x20U)
#define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_SHIFT (5U)
/*! slowdrvsupport_disable - - 1: CEC controller supports IO drivers with risetime of up to 1 CEC clock period.
*/
#define CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_SHIFT)) & CEC_CEC_CTRL_SLOWDRVSUPPORT_DISABLE_MASK)
/*! @} */
/*! @name CEC_MASK - CEC Interrupt Mask Register This read/write register masks/unmasks the interrupt events. */
/*! @{ */
#define CEC_CEC_MASK_DONE_MASK (0x1U)
#define CEC_CEC_MASK_DONE_SHIFT (0U)
/*! done - The current transmission is successful (for initiator only)
*/
#define CEC_CEC_MASK_DONE(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_DONE_SHIFT)) & CEC_CEC_MASK_DONE_MASK)
#define CEC_CEC_MASK_EOM_MASK (0x2U)
#define CEC_CEC_MASK_EOM_SHIFT (1U)
/*! eom - EOM is detected so that the received data is ready in the receiver data buffer (for follower only)
*/
#define CEC_CEC_MASK_EOM(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_EOM_SHIFT)) & CEC_CEC_MASK_EOM_MASK)
#define CEC_CEC_MASK_NACK_MASK (0x4U)
#define CEC_CEC_MASK_NACK_SHIFT (2U)
/*! nack - A frame is not acknowledged in a directly addressed message.
*/
#define CEC_CEC_MASK_NACK(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_NACK_SHIFT)) & CEC_CEC_MASK_NACK_MASK)
#define CEC_CEC_MASK_ARB_LOST_MASK (0x8U)
#define CEC_CEC_MASK_ARB_LOST_SHIFT (3U)
/*! arb_lost - The initiator losses the CEC line arbitration to a second initiator.
*/
#define CEC_CEC_MASK_ARB_LOST(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ARB_LOST_SHIFT)) & CEC_CEC_MASK_ARB_LOST_MASK)
#define CEC_CEC_MASK_ERROR_INITIATOR_MASK (0x10U)
#define CEC_CEC_MASK_ERROR_INITIATOR_SHIFT (4U)
/*! error_initiator - An error is detected on a CEC line (for initiator only).
*/
#define CEC_CEC_MASK_ERROR_INITIATOR(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ERROR_INITIATOR_SHIFT)) & CEC_CEC_MASK_ERROR_INITIATOR_MASK)
#define CEC_CEC_MASK_ERROR_FLOW_MASK (0x20U)
#define CEC_CEC_MASK_ERROR_FLOW_SHIFT (5U)
/*! error_flow - An error is notified by a follower.
*/
#define CEC_CEC_MASK_ERROR_FLOW(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_ERROR_FLOW_SHIFT)) & CEC_CEC_MASK_ERROR_FLOW_MASK)
#define CEC_CEC_MASK_WAKEUP_MASK (0x40U)
#define CEC_CEC_MASK_WAKEUP_SHIFT (6U)
/*! wakeup - Follower wake-up signal mask
*/
#define CEC_CEC_MASK_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_MASK_WAKEUP_SHIFT)) & CEC_CEC_MASK_WAKEUP_MASK)
/*! @} */
/*! @name CEC_ADDR_L - CEC Logical Address Register Low This register indicates the logical address(es) allocated to the CEC device. */
/*! @{ */
#define CEC_CEC_ADDR_L_CEC_ADDR_L_0_MASK (0x1U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_0_SHIFT (0U)
/*! cec_addr_l_0 - Logical address 0 - Device TV
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_0(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_0_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_0_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_1_MASK (0x2U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_1_SHIFT (1U)
/*! cec_addr_l_1 - Logical address 1 - Recording Device 1
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_1(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_1_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_1_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_2_MASK (0x4U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_2_SHIFT (2U)
/*! cec_addr_l_2 - Logical address 2 - Recording Device 2
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_2(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_2_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_2_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_3_MASK (0x8U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_3_SHIFT (3U)
/*! cec_addr_l_3 - Logical address 3 - Tuner 1
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_3(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_3_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_3_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_4_MASK (0x10U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_4_SHIFT (4U)
/*! cec_addr_l_4 - Logical address 4 - Playback Device 1
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_4(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_4_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_4_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_5_MASK (0x20U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_5_SHIFT (5U)
/*! cec_addr_l_5 - Logical address 5 - Audio System
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_5(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_5_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_5_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_6_MASK (0x40U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_6_SHIFT (6U)
/*! cec_addr_l_6 - Logical address 6 - Tuner 2
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_6(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_6_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_6_MASK)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_7_MASK (0x80U)
#define CEC_CEC_ADDR_L_CEC_ADDR_L_7_SHIFT (7U)
/*! cec_addr_l_7 - Logical address 7 - Tuner 3
*/
#define CEC_CEC_ADDR_L_CEC_ADDR_L_7(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_L_CEC_ADDR_L_7_SHIFT)) & CEC_CEC_ADDR_L_CEC_ADDR_L_7_MASK)
/*! @} */
/*! @name CEC_ADDR_H - CEC Logical Address Register High This register indicates the logical address(es) allocated to the CEC device. */
/*! @{ */
#define CEC_CEC_ADDR_H_CEC_ADDR_H_0_MASK (0x1U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_0_SHIFT (0U)
/*! cec_addr_h_0 - Logical address 8 - Playback Device 2
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_0(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_0_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_0_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_1_MASK (0x2U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_1_SHIFT (1U)
/*! cec_addr_h_1 - Logical address 9 - Playback Device 3
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_1(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_1_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_1_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_2_MASK (0x4U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_2_SHIFT (2U)
/*! cec_addr_h_2 - Logical address 10 - Tuner 4
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_2(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_2_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_2_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_3_MASK (0x8U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_3_SHIFT (3U)
/*! cec_addr_h_3 - Logical address 11 - Playback Device 3
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_3(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_3_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_3_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_4_MASK (0x10U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_4_SHIFT (4U)
/*! cec_addr_h_4 - Logical address 12 - Reserved
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_4(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_4_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_4_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_5_MASK (0x20U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_5_SHIFT (5U)
/*! cec_addr_h_5 - Logical address 13 - Reserved
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_5(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_5_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_5_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_6_MASK (0x40U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_6_SHIFT (6U)
/*! cec_addr_h_6 - Logical address 14 - Free use
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_6(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_6_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_6_MASK)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_7_MASK (0x80U)
#define CEC_CEC_ADDR_H_CEC_ADDR_H_7_SHIFT (7U)
/*! cec_addr_h_7 - Logical address 15 - Unregistered (as initiator address), Broadcast (as destination address)
*/
#define CEC_CEC_ADDR_H_CEC_ADDR_H_7(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_ADDR_H_CEC_ADDR_H_7_SHIFT)) & CEC_CEC_ADDR_H_CEC_ADDR_H_7_MASK)
/*! @} */
/*! @name CEC_TX_CNT - CEC TX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the transmitter data buffer. */
/*! @{ */
#define CEC_CEC_TX_CNT_CEC_TX_CNT_MASK (0x1FU)
#define CEC_CEC_TX_CNT_CEC_TX_CNT_SHIFT (0U)
/*! cec_tx_cnt - CEC Transmitter Counter register 5'd0: No data needs to be transmitted 5'd1: Frame size is 1 byte .
*/
#define CEC_CEC_TX_CNT_CEC_TX_CNT(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_TX_CNT_CEC_TX_CNT_SHIFT)) & CEC_CEC_TX_CNT_CEC_TX_CNT_MASK)
/*! @} */
/*! @name CEC_RX_CNT - CEC RX Frame Size Register This register indicates the size of the frame in bytes (including header and data blocks), which are available in the receiver data buffer. */
/*! @{ */
#define CEC_CEC_RX_CNT_CEC_RX_CNT_MASK (0x1FU)
#define CEC_CEC_RX_CNT_CEC_RX_CNT_SHIFT (0U)
/*! cec_rx_cnt - CEC Receiver Counter register: 5'd0: No data received 5'd1: 1-byte data is received .
*/
#define CEC_CEC_RX_CNT_CEC_RX_CNT(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_RX_CNT_CEC_RX_CNT_SHIFT)) & CEC_CEC_RX_CNT_CEC_RX_CNT_MASK)
/*! @} */
/*! @name CEC_LOCK - CEC Buffer Lock Register */
/*! @{ */
#define CEC_CEC_LOCK_LOCKED_BUFFER_MASK (0x1U)
#define CEC_CEC_LOCK_LOCKED_BUFFER_SHIFT (0U)
/*! locked_buffer - When a frame is received, this bit would be active.
*/
#define CEC_CEC_LOCK_LOCKED_BUFFER(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_LOCK_LOCKED_BUFFER_SHIFT)) & CEC_CEC_LOCK_LOCKED_BUFFER_MASK)
/*! @} */
/*! @name CEC_WAKEUPCTRL - CEC Wake-up Control Register After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the message opcode[7:0] against one of the previously defined values to generate the wake-up status: Wakeupstatus is 1 when: received opcode is 0x04 and opcode0x04en is 1 or received opcode is 0x0D and opcode0x0Den is 1 or received opcode is 0x41 and opcode0x41en is 1 or received opcode is 0x42 and opcode0x42en is 1 or received opcode is 0x44 and opcode0x44en is 1 or received opcode is 0x70 and opcode0x70en is 1 or received opcode is 0x82 and opcode0x82en is 1 or received opcode is 0x86 and opcode0x86en is 1 Wakeupstatus is 0 when none of the previous conditions are true. */
/*! @{ */
#define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_MASK (0x1U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_SHIFT (0U)
/*! opcode0x04en - OPCODE 0x04 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X04EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X04EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_MASK (0x2U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_SHIFT (1U)
/*! opcode0x0Den - OPCODE 0x0D wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X0DEN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_MASK (0x4U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_SHIFT (2U)
/*! opcode0x41en - OPCODE 0x41 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X41EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X41EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_MASK (0x8U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_SHIFT (3U)
/*! opcode0x42en - OPCODE 0x42 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X42EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X42EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_MASK (0x10U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_SHIFT (4U)
/*! opcode0x44en - OPCODE 0x44 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X44EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X44EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_MASK (0x20U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_SHIFT (5U)
/*! opcode0x70en - OPCODE 0x70 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X70EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X70EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_MASK (0x40U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_SHIFT (6U)
/*! opcode0x82en - OPCODE 0x82 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X82EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X82EN_MASK)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_MASK (0x80U)
#define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_SHIFT (7U)
/*! opcode0x86en - OPCODE 0x86 wake up enable
*/
#define CEC_CEC_WAKEUPCTRL_OPCODE0X86EN(x) (((uint8_t)(((uint8_t)(x)) << CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_SHIFT)) & CEC_CEC_WAKEUPCTRL_OPCODE0X86EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CEC_Register_Masks */
/* CEC - Peripheral instance base addresses */
/** Peripheral CEC base address */
#define CEC_BASE (0x32FDFD00u)
/** Peripheral CEC base pointer */
#define CEC ((CEC_Type *)CEC_BASE)
/** Array initializer of CEC peripheral base addresses */
#define CEC_BASE_ADDRS { CEC_BASE }
/** Array initializer of CEC peripheral base pointers */
#define CEC_BASE_PTRS { CEC }
/*!
* @}
*/ /* end of group CEC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- COLORSPACECONVERTER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup COLORSPACECONVERTER_Peripheral_Access_Layer COLORSPACECONVERTER Peripheral Access Layer
* @{
*/
/** COLORSPACECONVERTER - Register Layout Typedef */
typedef struct {
__IO uint8_t CSC_CFG; /**< Color Space Converter Interpolation and Decimation Configuration Register, offset: 0x0 */
__IO uint8_t CSC_SCALE; /**< Color Space Converter Scale and Deep Color Configuration Register, offset: 0x1 */
__IO uint8_t CSC_COEF_A1_MSB; /**< Color Space Converter Matrix A1 Coefficient Register MSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations., offset: 0x2 */
__IO uint8_t CSC_COEF_A1_LSB; /**< Color Space Converter Matrix A1 Coefficient Register LSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations., offset: 0x3 */
__IO uint8_t CSC_COEF_A2_MSB; /**< Color Space Converter Matrix A2 Coefficient Register MSB Color Space Conversion A2 coefficient., offset: 0x4 */
__IO uint8_t CSC_COEF_A2_LSB; /**< Color Space Converter Matrix A2 Coefficient Register LSB Color Space Conversion A2 coefficient., offset: 0x5 */
__IO uint8_t CSC_COEF_A3_MSB; /**< Color Space Converter Matrix A3 Coefficient Register MSB Color Space Conversion A3 coefficient., offset: 0x6 */
__IO uint8_t CSC_COEF_A3_LSB; /**< Color Space Converter Matrix A3 Coefficient Register LSB Color Space Conversion A3 coefficient., offset: 0x7 */
__IO uint8_t CSC_COEF_A4_MSB; /**< Color Space Converter Matrix A4 Coefficient Register MSB Color Space Conversion A4 coefficient., offset: 0x8 */
__IO uint8_t CSC_COEF_A4_LSB; /**< Color Space Converter Matrix A4 Coefficient Register LSB Color Space Conversion A4 coefficient., offset: 0x9 */
__IO uint8_t CSC_COEF_B1_MSB; /**< Color Space Converter Matrix B1 Coefficient Register MSB Color Space Conversion B1 coefficient., offset: 0xA */
__IO uint8_t CSC_COEF_B1_LSB; /**< Color Space Converter Matrix B1 Coefficient Register LSB Color Space Conversion B1 coefficient., offset: 0xB */
__IO uint8_t CSC_COEF_B2_MSB; /**< Color Space Converter Matrix B2 Coefficient Register MSB Color Space Conversion B2 coefficient., offset: 0xC */
__IO uint8_t CSC_COEF_B2_LSB; /**< Color Space Converter Matrix B2 Coefficient Register LSB Color Space Conversion B2 coefficient., offset: 0xD */
__IO uint8_t CSC_COEF_B3_MSB; /**< Color Space Converter Matrix B3 Coefficient Register MSB Color Space Conversion B3 coefficient., offset: 0xE */
__IO uint8_t CSC_COEF_B3_LSB; /**< Color Space Converter Matrix B3 Coefficient Register LSB Color Space Conversion B3 coefficient., offset: 0xF */
__IO uint8_t CSC_COEF_B4_MSB; /**< Color Space Converter Matrix B4 Coefficient Register MSB Color Space Conversion B4 coefficient., offset: 0x10 */
__IO uint8_t CSC_COEF_B4_LSB; /**< Color Space Converter Matrix B4 Coefficient Register LSB Color Space Conversion B4 coefficient., offset: 0x11 */
__IO uint8_t CSC_COEF_C1_MSB; /**< Color Space Converter Matrix C1 Coefficient Register MSB Color Space Conversion C1 coefficient., offset: 0x12 */
__IO uint8_t CSC_COEF_C1_LSB; /**< Color Space Converter Matrix C1 Coefficient Register LSB Color Space Conversion C1 coefficient., offset: 0x13 */
__IO uint8_t CSC_COEF_C2_MSB; /**< Color Space Converter Matrix C2 Coefficient Register MSB Color Space Conversion C2 coefficient., offset: 0x14 */
__IO uint8_t CSC_COEF_C2_LSB; /**< Color Space Converter Matrix C2 Coefficient Register LSB Color Space Conversion C2 coefficient., offset: 0x15 */
__IO uint8_t CSC_COEF_C3_MSB; /**< Color Space Converter Matrix C3 Coefficient Register MSB Color Space Conversion C3 coefficient., offset: 0x16 */
__IO uint8_t CSC_COEF_C3_LSB; /**< Color Space Converter Matrix C3 Coefficient Register LSB Color Space Conversion C3 coefficient., offset: 0x17 */
__IO uint8_t CSC_COEF_C4_MSB; /**< Color Space Converter Matrix C4 Coefficient Register MSB Color Space Conversion C4 coefficient., offset: 0x18 */
__IO uint8_t CSC_COEF_C4_LSB; /**< Color Space Converter Matrix C4 Coefficient Register LSB Color Space Conversion C4 coefficient., offset: 0x19 */
__IO uint8_t CSC_LIMIT_UP_MSB; /**< Color Space Converter Matrix Output Up Limit Register MSB For more details, refer to the HDMI 1., offset: 0x1A */
__IO uint8_t CSC_LIMIT_UP_LSB; /**< Color Space Converter Matrix output Up Limit Register LSB For more details, refer to the HDMI 1., offset: 0x1B */
__IO uint8_t CSC_LIMIT_DN_MSB; /**< Color Space Converter Matrix output Down Limit Register MSB For more details, refer to the HDMI 1., offset: 0x1C */
__IO uint8_t CSC_LIMIT_DN_LSB; /**< Color Space Converter Matrix output Down Limit Register LSB For more details, refer to the HDMI 1., offset: 0x1D */
} COLORSPACECONVERTER_Type;
/* ----------------------------------------------------------------------------
-- COLORSPACECONVERTER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup COLORSPACECONVERTER_Register_Masks COLORSPACECONVERTER Register Masks
* @{
*/
/*! @name CSC_CFG - Color Space Converter Interpolation and Decimation Configuration Register */
/*! @{ */
#define COLORSPACECONVERTER_CSC_CFG_DECMODE_MASK (0x3U)
#define COLORSPACECONVERTER_CSC_CFG_DECMODE_SHIFT (0U)
/*! decmode - Chroma decimation configuration: decmode[1:0] | Chroma Decimation 00 | decimation
* disabled 01 | Hd (z) =1 10 | Hd(z)=1/ 4 + 1/2z^(-1 )+1/4 z^(-2) 11 | Hd(z)x2^(11)= -5+12z^(-2) -
* 22z^(-4)+39z^(-8) +109z^(-10) -204z^(-12)+648z^(-14) + 1024z^(-15) +648z^(-16) -204z^(-18)
* +109z^(-20)- 65z^(-22) +39z^(-24) -22z^(-26) +12z^(-28)-5z^(-30)
*/
#define COLORSPACECONVERTER_CSC_CFG_DECMODE(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_DECMODE_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_DECMODE_MASK)
#define COLORSPACECONVERTER_CSC_CFG_SPARE_1_MASK (0xCU)
#define COLORSPACECONVERTER_CSC_CFG_SPARE_1_SHIFT (2U)
/*! spare_1 - Reserved as "spare" register with no associated functionality.
*/
#define COLORSPACECONVERTER_CSC_CFG_SPARE_1(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_SPARE_1_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_SPARE_1_MASK)
#define COLORSPACECONVERTER_CSC_CFG_INTMODE_MASK (0x30U)
#define COLORSPACECONVERTER_CSC_CFG_INTMODE_SHIFT (4U)
/*! intmode - Chroma interpolation configuration: intmode[1:0] | Chroma Interpolation 00 |
* interpolation disabled 01 | Hu (z) =1 + z^(-1) 10 | Hu(z)=1/ 2 + z^(-11)+1/2 z^(-2) 11 | interpolation
* disabled
*/
#define COLORSPACECONVERTER_CSC_CFG_INTMODE(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_INTMODE_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_INTMODE_MASK)
#define COLORSPACECONVERTER_CSC_CFG_SPARE_2_MASK (0x40U)
#define COLORSPACECONVERTER_CSC_CFG_SPARE_2_SHIFT (6U)
/*! spare_2 - Reserved as "spare" register with no associated functionality.
*/
#define COLORSPACECONVERTER_CSC_CFG_SPARE_2(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_SPARE_2_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_SPARE_2_MASK)
#define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_MASK (0x80U)
#define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_SHIFT (7U)
/*! csc_limit - When set (1'b1), the range limitation values defined in registers csc_mat_uplim and
* csc_mat_dnlim are applied to the output of the Color Space Conversion matrix.
*/
#define COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_SHIFT)) & COLORSPACECONVERTER_CSC_CFG_CSC_LIMIT_MASK)
/*! @} */
/*! @name CSC_SCALE - Color Space Converter Scale and Deep Color Configuration Register */
/*! @{ */
#define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_MASK (0x3U)
#define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_SHIFT (0U)
/*! cscscale - Defines the cscscale[1:0] scale factor to apply to all coefficients in Color Space Conversion.
*/
#define COLORSPACECONVERTER_CSC_SCALE_CSCSCALE(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_CSCSCALE_MASK)
#define COLORSPACECONVERTER_CSC_SCALE_SPARE_MASK (0xCU)
#define COLORSPACECONVERTER_CSC_SCALE_SPARE_SHIFT (2U)
/*! spare - The is a Reserved as "spare" register with no associated functionality.
*/
#define COLORSPACECONVERTER_CSC_SCALE_SPARE(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_SPARE_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_SPARE_MASK)
#define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_MASK (0xF0U)
#define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_SHIFT (4U)
/*! csc_color_depth - Color space converter color depth configuration: csc_colordepth[3:0] | Action
* 0000 | 24 bit per pixel video (8 bit per component).
*/
#define COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_SHIFT)) & COLORSPACECONVERTER_CSC_SCALE_CSC_COLOR_DEPTH_MASK)
/*! @} */
/*! @name CSC_COEF_A1_MSB - Color Space Converter Matrix A1 Coefficient Register MSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_SHIFT (0U)
/*! csc_coef_a1_msb - Color Space Converter Matrix A1 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A1_MSB_CSC_COEF_A1_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_A1_LSB - Color Space Converter Matrix A1 Coefficient Register LSB Notes: - The coefficients used in the CSC matrix use only 15 bits for the internal computations. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_SHIFT (0U)
/*! csc_coef_a1_lsb - Color Space Converter Matrix A1 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A1_LSB_CSC_COEF_A1_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_A2_MSB - Color Space Converter Matrix A2 Coefficient Register MSB Color Space Conversion A2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_SHIFT (0U)
/*! csc_coef_a2_msb - Color Space Converter Matrix A2 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A2_MSB_CSC_COEF_A2_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_A2_LSB - Color Space Converter Matrix A2 Coefficient Register LSB Color Space Conversion A2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_SHIFT (0U)
/*! csc_coef_a2_lsb - Color Space Converter Matrix A2 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A2_LSB_CSC_COEF_A2_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_A3_MSB - Color Space Converter Matrix A3 Coefficient Register MSB Color Space Conversion A3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_SHIFT (0U)
/*! csc_coef_a3_msb - Color Space Converter Matrix A3 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A3_MSB_CSC_COEF_A3_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_A3_LSB - Color Space Converter Matrix A3 Coefficient Register LSB Color Space Conversion A3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_SHIFT (0U)
/*! csc_coef_a3_lsb - Color Space Converter Matrix A3 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A3_LSB_CSC_COEF_A3_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_A4_MSB - Color Space Converter Matrix A4 Coefficient Register MSB Color Space Conversion A4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_SHIFT (0U)
/*! csc_coef_a4_msb - Color Space Converter Matrix A4 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A4_MSB_CSC_COEF_A4_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_A4_LSB - Color Space Converter Matrix A4 Coefficient Register LSB Color Space Conversion A4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_SHIFT (0U)
/*! csc_coef_a4_lsb - Color Space Converter Matrix A4 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_A4_LSB_CSC_COEF_A4_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_B1_MSB - Color Space Converter Matrix B1 Coefficient Register MSB Color Space Conversion B1 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_SHIFT (0U)
/*! csc_coef_b1_msb - Color Space Converter Matrix B1 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B1_MSB_CSC_COEF_B1_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_B1_LSB - Color Space Converter Matrix B1 Coefficient Register LSB Color Space Conversion B1 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_SHIFT (0U)
/*! csc_coef_b1_lsb - Color Space Converter Matrix B1 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B1_LSB_CSC_COEF_B1_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_B2_MSB - Color Space Converter Matrix B2 Coefficient Register MSB Color Space Conversion B2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_SHIFT (0U)
/*! csc_coef_b2_msb - Color Space Converter Matrix B2 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B2_MSB_CSC_COEF_B2_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_B2_LSB - Color Space Converter Matrix B2 Coefficient Register LSB Color Space Conversion B2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_SHIFT (0U)
/*! csc_coef_b2_lsb - Color Space Converter Matrix B2 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B2_LSB_CSC_COEF_B2_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_B3_MSB - Color Space Converter Matrix B3 Coefficient Register MSB Color Space Conversion B3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_SHIFT (0U)
/*! csc_coef_b3_msb - Color Space Converter Matrix B3 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B3_MSB_CSC_COEF_B3_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_B3_LSB - Color Space Converter Matrix B3 Coefficient Register LSB Color Space Conversion B3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_SHIFT (0U)
/*! csc_coef_b3_lsb - Color Space Converter Matrix B3 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B3_LSB_CSC_COEF_B3_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_B4_MSB - Color Space Converter Matrix B4 Coefficient Register MSB Color Space Conversion B4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_SHIFT (0U)
/*! csc_coef_b4_msb - Color Space Converter Matrix B4 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B4_MSB_CSC_COEF_B4_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_B4_LSB - Color Space Converter Matrix B4 Coefficient Register LSB Color Space Conversion B4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_SHIFT (0U)
/*! csc_coef_b4_lsb - Color Space Converter Matrix B4 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_B4_LSB_CSC_COEF_B4_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_C1_MSB - Color Space Converter Matrix C1 Coefficient Register MSB Color Space Conversion C1 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_SHIFT (0U)
/*! csc_coef_c1_msb - Color Space Converter Matrix C1 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C1_MSB_CSC_COEF_C1_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_C1_LSB - Color Space Converter Matrix C1 Coefficient Register LSB Color Space Conversion C1 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_SHIFT (0U)
/*! csc_coef_c1_lsb - Color Space Converter Matrix C1 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C1_LSB_CSC_COEF_C1_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_C2_MSB - Color Space Converter Matrix C2 Coefficient Register MSB Color Space Conversion C2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_SHIFT (0U)
/*! csc_coef_c2_msb - Color Space Converter Matrix C2 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C2_MSB_CSC_COEF_C2_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_C2_LSB - Color Space Converter Matrix C2 Coefficient Register LSB Color Space Conversion C2 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_SHIFT (0U)
/*! csc_coef_c2_lsb - Color Space Converter Matrix C2 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C2_LSB_CSC_COEF_C2_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_C3_MSB - Color Space Converter Matrix C3 Coefficient Register MSB Color Space Conversion C3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_SHIFT (0U)
/*! csc_coef_c3_msb - Color Space Converter Matrix C3 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C3_MSB_CSC_COEF_C3_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_C3_LSB - Color Space Converter Matrix C3 Coefficient Register LSB Color Space Conversion C3 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_SHIFT (0U)
/*! csc_coef_c3_lsb - Color Space Converter Matrix C3 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C3_LSB_CSC_COEF_C3_LSB_MASK)
/*! @} */
/*! @name CSC_COEF_C4_MSB - Color Space Converter Matrix C4 Coefficient Register MSB Color Space Conversion C4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_SHIFT (0U)
/*! csc_coef_c4_msb - Color Space Converter Matrix C4 Coefficient Register MSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C4_MSB_CSC_COEF_C4_MSB_MASK)
/*! @} */
/*! @name CSC_COEF_C4_LSB - Color Space Converter Matrix C4 Coefficient Register LSB Color Space Conversion C4 coefficient. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_SHIFT (0U)
/*! csc_coef_c4_lsb - Color Space Converter Matrix C4 Coefficient Register LSB
*/
#define COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_COEF_C4_LSB_CSC_COEF_C4_LSB_MASK)
/*! @} */
/*! @name CSC_LIMIT_UP_MSB - Color Space Converter Matrix Output Up Limit Register MSB For more details, refer to the HDMI 1. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_SHIFT (0U)
/*! csc_limit_up_msb - Color Space Converter Matrix Output Upper Limit Register MSB
*/
#define COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_UP_MSB_CSC_LIMIT_UP_MSB_MASK)
/*! @} */
/*! @name CSC_LIMIT_UP_LSB - Color Space Converter Matrix output Up Limit Register LSB For more details, refer to the HDMI 1. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_SHIFT (0U)
/*! csc_limit_up_lsb - Color Space Converter Matrix Output Upper Limit Register LSB
*/
#define COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_UP_LSB_CSC_LIMIT_UP_LSB_MASK)
/*! @} */
/*! @name CSC_LIMIT_DN_MSB - Color Space Converter Matrix output Down Limit Register MSB For more details, refer to the HDMI 1. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_SHIFT (0U)
/*! csc_limit_dn_msb - Color Space Converter Matrix output Down Limit Register MSB
*/
#define COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_DN_MSB_CSC_LIMIT_DN_MSB_MASK)
/*! @} */
/*! @name CSC_LIMIT_DN_LSB - Color Space Converter Matrix output Down Limit Register LSB For more details, refer to the HDMI 1. */
/*! @{ */
#define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_MASK (0xFFU)
#define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_SHIFT (0U)
/*! csc_limit_dn_lsb - Color Space Converter Matrix Output Down Limit Register LSB
*/
#define COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB(x) (((uint8_t)(((uint8_t)(x)) << COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_SHIFT)) & COLORSPACECONVERTER_CSC_LIMIT_DN_LSB_CSC_LIMIT_DN_LSB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group COLORSPACECONVERTER_Register_Masks */
/* COLORSPACECONVERTER - Peripheral instance base addresses */
/** Peripheral COLORSPACECONVERTER base address */
#define COLORSPACECONVERTER_BASE (0x32FDC100u)
/** Peripheral COLORSPACECONVERTER base pointer */
#define COLORSPACECONVERTER ((COLORSPACECONVERTER_Type *)COLORSPACECONVERTER_BASE)
/** Array initializer of COLORSPACECONVERTER peripheral base addresses */
#define COLORSPACECONVERTER_BASE_ADDRS { COLORSPACECONVERTER_BASE }
/** Array initializer of COLORSPACECONVERTER peripheral base pointers */
#define COLORSPACECONVERTER_BASE_PTRS { COLORSPACECONVERTER }
/*!
* @}
*/ /* end of group COLORSPACECONVERTER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DDRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
* @{
*/
/** DDRC - Register Layout Typedef */
typedef struct {
__IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
__I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
__IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */
__IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */
__IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
__IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
__I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
__IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
__IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
__IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
uint8_t RESERVED_0[8];
__IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
__IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
__IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
uint8_t RESERVED_1[20];
__IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
__IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
uint8_t RESERVED_2[8];
__IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
__IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
uint8_t RESERVED_3[8];
__IO uint32_t ECCCFG0; /**< ECC Configuration Register 0, offset: 0x70 */
__IO uint32_t ECCCFG1; /**< ECC Configuration Register 1, offset: 0x74 */
uint8_t RESERVED_4[88];
__IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
__IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
__IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
__IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
__IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
__IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
__IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
__IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
__IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
__IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
uint8_t RESERVED_5[8];
__IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
__IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
__IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
__IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
__IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
__IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
__IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
__IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
__IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
__IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
__IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
__IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
__IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
__IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
__IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
__IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
uint8_t RESERVED_6[64];
__IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
__IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
__IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
__I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
__IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
__IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
__IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
__IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
__IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
__IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
__IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
uint8_t RESERVED_7[4];
__IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
__IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
__IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
__I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
__IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
uint8_t RESERVED_8[60];
__IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
__IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
__IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
__IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
__IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
__IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
__IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
__IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
__IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
__IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
__IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
__IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
uint8_t RESERVED_9[16];
__IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
__IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
uint8_t RESERVED_10[8];
__IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
__IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
uint8_t RESERVED_11[4];
__IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
uint8_t RESERVED_12[4];
__IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
uint8_t RESERVED_13[4];
__IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
uint8_t RESERVED_14[144];
__IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
__IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
__I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
__IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
__I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
uint8_t RESERVED_15[12];
__IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
__I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
uint8_t RESERVED_16[68];
__IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
__I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
uint8_t RESERVED_17[136];
__I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
__IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
__IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
__IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
uint8_t RESERVED_18[132];
__IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
__IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
__IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
__IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
__IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
uint8_t RESERVED_19[7036];
__IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
__IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
uint8_t RESERVED_20[40];
__IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
uint8_t RESERVED_21[16];
__IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
uint8_t RESERVED_22[116];
__IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
__IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
uint8_t RESERVED_23[4];
__IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
__IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
uint8_t RESERVED_24[16];
__IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
__IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
__IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
__IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
__IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
__IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
__IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
__IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
__IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
__IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
__IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
__IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
__IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
__IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
__IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
__IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
uint8_t RESERVED_25[64];
__IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
uint8_t RESERVED_26[12];
__IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
__IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
uint8_t RESERVED_27[28];
__IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
__IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
uint8_t RESERVED_28[132];
__IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
} DDRC_Type;
/* ----------------------------------------------------------------------------
-- DDRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DDRC_Register_Masks DDRC Register Masks
* @{
*/
/*! @name MSTR - Master Register0 */
/*! @{ */
#define DDRC_MSTR_LPDDR2_MASK (0x4U)
#define DDRC_MSTR_LPDDR2_SHIFT (2U)
/*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use
* Present only in designs configured to support LPDDR2.
*/
#define DDRC_MSTR_LPDDR2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR2_SHIFT)) & DDRC_MSTR_LPDDR2_MASK)
#define DDRC_MSTR_LPDDR3_MASK (0x8U)
#define DDRC_MSTR_LPDDR3_SHIFT (3U)
/*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use
* Present only in designs configured to support LPDDR3.
*/
#define DDRC_MSTR_LPDDR3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR3_SHIFT)) & DDRC_MSTR_LPDDR3_MASK)
#define DDRC_MSTR_DDR4_MASK (0x10U)
#define DDRC_MSTR_DDR4_SHIFT (4U)
/*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present
* only in designs configured to support DDR4.
*/
#define DDRC_MSTR_DDR4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DDR4_SHIFT)) & DDRC_MSTR_DDR4_MASK)
#define DDRC_MSTR_LPDDR4_MASK (0x20U)
#define DDRC_MSTR_LPDDR4_SHIFT (5U)
/*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use
* Present only in designs configured to support LPDDR4.
*/
#define DDRC_MSTR_LPDDR4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_LPDDR4_SHIFT)) & DDRC_MSTR_LPDDR4_MASK)
#define DDRC_MSTR_BURSTCHOP_MASK (0x200U)
#define DDRC_MSTR_BURSTCHOP_SHIFT (9U)
/*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads
* is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode
* (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is
* exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled
* (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1),
* burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
*/
#define DDRC_MSTR_BURSTCHOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_BURSTCHOP_SHIFT)) & DDRC_MSTR_BURSTCHOP_MASK)
#define DDRC_MSTR_GEARDOWN_MODE_MASK (0x800U)
#define DDRC_MSTR_GEARDOWN_MODE_SHIFT (11U)
/*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in
* normal mode (1N). This register can be changed, only when the Controller is in self-refresh
* mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported
* if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported
* if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value
* is don't care
*/
#define DDRC_MSTR_GEARDOWN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_GEARDOWN_MODE_SHIFT)) & DDRC_MSTR_GEARDOWN_MODE_MASK)
#define DDRC_MSTR_DATA_BUS_WIDTH_MASK (0x3000U)
#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT (12U)
/*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus
* width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 -
* Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a
* multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple
* of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus
* width (excluding any ECC width).
*/
#define DDRC_MSTR_DATA_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT)) & DDRC_MSTR_DATA_BUS_WIDTH_MASK)
#define DDRC_MSTR_BURST_RDWR_MASK (0xF0000U)
#define DDRC_MSTR_BURST_RDWR_SHIFT (16U)
/*! burst_rdwr - SDRAM burst length used
* 0b0001..Burst length of 2 (only supported for mDDR)
* 0b0010..Burst length of 4
* 0b0100..Burst length of 8
* 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
*/
#define DDRC_MSTR_BURST_RDWR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_BURST_RDWR_SHIFT)) & DDRC_MSTR_BURST_RDWR_MASK)
#define DDRC_MSTR_ACTIVE_RANKS_MASK (0x3000000U)
#define DDRC_MSTR_ACTIVE_RANKS_SHIFT (24U)
/*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For
* two-rank configurations, only bits[25:24] are present.
*/
#define DDRC_MSTR_ACTIVE_RANKS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ACTIVE_RANKS_SHIFT)) & DDRC_MSTR_ACTIVE_RANKS_MASK)
#define DDRC_MSTR_FREQUENCY_MODE_MASK (0x20000000U)
#define DDRC_MSTR_FREQUENCY_MODE_SHIFT (29U)
/*! frequency_mode - Choose which registers are used.
* 0b0..Original Registers
* 0b1..Shadow Registers
*/
#define DDRC_MSTR_FREQUENCY_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_FREQUENCY_MODE_SHIFT)) & DDRC_MSTR_FREQUENCY_MODE_MASK)
#define DDRC_MSTR_DEVICE_CONFIG_MASK (0xC0000000U)
#define DDRC_MSTR_DEVICE_CONFIG_SHIFT (30U)
/*! device_config - Indicates the configuration of the device used in the system.
* 0b00..x4 device
* 0b01..x8 device
* 0b10..x16 device
* 0b11..x32 device
*/
#define DDRC_MSTR_DEVICE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_DEVICE_CONFIG_SHIFT)) & DDRC_MSTR_DEVICE_CONFIG_MASK)
/*! @} */
/*! @name STAT - Operating Mode Status Register */
/*! @{ */
#define DDRC_STAT_OPERATING_MODE_MASK (0x7U)
#define DDRC_STAT_OPERATING_MODE_SHIFT (0U)
/*! operating_mode - Operating mode
*/
#define DDRC_STAT_OPERATING_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_OPERATING_MODE_SHIFT)) & DDRC_STAT_OPERATING_MODE_MASK)
#define DDRC_STAT_SELFREF_TYPE_MASK (0x30U)
#define DDRC_STAT_SELFREF_TYPE_SHIFT (4U)
/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
* it was under Automatic Self Refresh control only or not.
* 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
* CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
* in-progress.
* 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
* Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
* 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
* Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
* (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
*/
#define DDRC_STAT_SELFREF_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_SELFREF_TYPE_SHIFT)) & DDRC_STAT_SELFREF_TYPE_MASK)
#define DDRC_STAT_SELFREF_STATE_MASK (0x300U)
#define DDRC_STAT_SELFREF_STATE_SHIFT (8U)
/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
* for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
* 0b00..SDRAM is not in Self Refresh.
* 0b01..Self refresh 1
* 0b10..Self refresh power down
* 0b11..Self refresh
*/
#define DDRC_STAT_SELFREF_STATE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_SELFREF_STATE_SHIFT)) & DDRC_STAT_SELFREF_STATE_MASK)
/*! @} */
/*! @name MSTR1 - Operating Mode Status Register */
/*! @{ */
#define DDRC_MSTR1_RANK_TMGREG_SEL_MASK (0x3U)
#define DDRC_MSTR1_RANK_TMGREG_SEL_SHIFT (0U)
/*! rank_tmgreg_sel - rank_tmgreg_sel
* 0b00..USE DRAMTMGx registers for the rank
* 0b01..USE MRAMTMGx registers for the rank
*/
#define DDRC_MSTR1_RANK_TMGREG_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_RANK_TMGREG_SEL_SHIFT)) & DDRC_MSTR1_RANK_TMGREG_SEL_MASK)
#define DDRC_MSTR1_ALT_ADDRMAP_EN_MASK (0x10000U)
#define DDRC_MSTR1_ALT_ADDRMAP_EN_SHIFT (16U)
/*! alt_addrmap_en - Enable Alternative Address Map
* 0b0..Disable Alternative Address Map
* 0b1..Enable Alternative Address Map
*/
#define DDRC_MSTR1_ALT_ADDRMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_ALT_ADDRMAP_EN_SHIFT)) & DDRC_MSTR1_ALT_ADDRMAP_EN_MASK)
/*! @} */
/*! @name MRCTRL3 - Operating Mode Status Register */
/*! @{ */
#define DDRC_MRCTRL3_MR_RANK_SEL_MASK (0x3U)
#define DDRC_MRCTRL3_MR_RANK_SEL_SHIFT (0U)
/*! mr_rank_sel - mr_rank_sel
*/
#define DDRC_MRCTRL3_MR_RANK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_MR_RANK_SEL_SHIFT)) & DDRC_MRCTRL3_MR_RANK_SEL_MASK)
/*! @} */
/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
/*! @{ */
#define DDRC_MRCTRL0_MR_TYPE_MASK (0x1U)
#define DDRC_MRCTRL0_MR_TYPE_SHIFT (0U)
/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
* 0b0..Write
* 0b1..Read
*/
#define DDRC_MRCTRL0_MR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_TYPE_SHIFT)) & DDRC_MRCTRL0_MR_TYPE_MASK)
#define DDRC_MRCTRL0_MPR_EN_MASK (0x2U)
#define DDRC_MRCTRL0_MPR_EN_SHIFT (1U)
/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
* 0b0..MRS
* 0b1..WR/RD for MPR
*/
#define DDRC_MRCTRL0_MPR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MPR_EN_SHIFT)) & DDRC_MRCTRL0_MPR_EN_MASK)
#define DDRC_MRCTRL0_PDA_EN_MASK (0x4U)
#define DDRC_MRCTRL0_PDA_EN_SHIFT (2U)
/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
* pba_mode=1, PBA access is initiated instead of PDA access.
* 0b0..MRS
* 0b1..MRS in Per DRAM Addressability
*/
#define DDRC_MRCTRL0_PDA_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_PDA_EN_SHIFT)) & DDRC_MRCTRL0_PDA_EN_MASK)
#define DDRC_MRCTRL0_SW_INIT_INT_MASK (0x8U)
#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT (3U)
/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
* automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
* DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
* program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
* independent channel mode, note that this must be programmed to both channels beforehand. Note that
* this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
* initialization routine will not re-start.
* 0b0..Software intervention is not allowed
* 0b1..Software intervention is allowed
*/
#define DDRC_MRCTRL0_SW_INIT_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_SW_INIT_INT_SHIFT)) & DDRC_MRCTRL0_SW_INIT_INT_MASK)
#define DDRC_MRCTRL0_MR_RANK_MASK (0x30U)
#define DDRC_MRCTRL0_MR_RANK_SHIFT (4U)
/*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access
* all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which
* implement address mirroring, it may be necessary to access ranks individually. Examples (assume
* DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 -
* select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3
*/
#define DDRC_MRCTRL0_MR_RANK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_RANK_SHIFT)) & DDRC_MRCTRL0_MR_RANK_MASK)
#define DDRC_MRCTRL0_MR_ADDR_MASK (0xF000U)
#define DDRC_MRCTRL0_MR_ADDR_SHIFT (12U)
/*! mr_addr - Address of the mode register that is to be written to.
* 0b0000..MR0
* 0b0001..MR1
* 0b0010..MR2
* 0b0011..MR3
* 0b0100..MR4
* 0b0101..MR5
* 0b0110..MR6
* 0b0111..MR7
*/
#define DDRC_MRCTRL0_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_ADDR_SHIFT)) & DDRC_MRCTRL0_MR_ADDR_MASK)
#define DDRC_MRCTRL0_PBA_MODE_MASK (0x40000000U)
#define DDRC_MRCTRL0_PBA_MODE_SHIFT (30U)
/*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with
* setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability
* mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by
* MRSTAT.pda_done in the same way as PDA.
*/
#define DDRC_MRCTRL0_PBA_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_PBA_MODE_SHIFT)) & DDRC_MRCTRL0_PBA_MODE_MASK)
#define DDRC_MRCTRL0_MR_WR_MASK (0x80000000U)
#define DDRC_MRCTRL0_MR_WR_SHIFT (31U)
/*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When
* the MR operation is complete, the DDRC automatically clears this bit. The other register fields
* of this register must be written in a separate APB transaction, before setting this mr_wr bit.
* It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
*/
#define DDRC_MRCTRL0_MR_WR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_MR_WR_SHIFT)) & DDRC_MRCTRL0_MR_WR_MASK)
/*! @} */
/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
/*! @{ */
#define DDRC_MRCTRL1_MR_DATA_MASK (0x3FFFFU)
#define DDRC_MRCTRL1_MR_DATA_SHIFT (0U)
/*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For
* LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes,
* don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all
* other configurations.
*/
#define DDRC_MRCTRL1_MR_DATA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_MR_DATA_SHIFT)) & DDRC_MRCTRL1_MR_DATA_MASK)
/*! @} */
/*! @name MRSTAT - Mode Register Read/Write Status Register */
/*! @{ */
#define DDRC_MRSTAT_MR_WR_BUSY_MASK (0x1U)
#define DDRC_MRSTAT_MR_WR_BUSY_SHIFT (0U)
/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
* signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
* MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
* 'MRSTAT.mr_wr_busy' is high.
* 0b0..Indicates that the SoC core can initiate a mode register write operation
* 0b1..Indicates that mode register write operation is in progress
*/
#define DDRC_MRSTAT_MR_WR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_MR_WR_BUSY_SHIFT)) & DDRC_MRSTAT_MR_WR_BUSY_MASK)
#define DDRC_MRSTAT_PDA_DONE_MASK (0x100U)
#define DDRC_MRSTAT_PDA_DONE_SHIFT (8U)
/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
* low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
* are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
* recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
* perform PDA operation next time
* 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
* 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
*/
#define DDRC_MRSTAT_PDA_DONE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_PDA_DONE_SHIFT)) & DDRC_MRSTAT_PDA_DONE_MASK)
/*! @} */
/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
/*! @{ */
#define DDRC_MRCTRL2_MR_DEVICE_SEL_MASK (0xFFFFFFFFU)
#define DDRC_MRCTRL2_MR_DEVICE_SEL_SHIFT (0U)
/*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode.
* Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to
* Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied
* to that device. A '0' indicates that the MRS commands should be skipped for that device.
*/
#define DDRC_MRCTRL2_MR_DEVICE_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_MR_DEVICE_SEL_SHIFT)) & DDRC_MRCTRL2_MR_DEVICE_SEL_MASK)
/*! @} */
/*! @name DERATEEN - Temperature Derate Enable Register */
/*! @{ */
#define DDRC_DERATEEN_DERATE_ENABLE_MASK (0x1U)
#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT (0U)
/*! derate_enable - Enables derating. Present only in designs configured to support
* LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
* 0b0..Timing parameter derating is disabled
* 0b1..Timing parameter derating is enabled using MR4 read value.
*/
#define DDRC_DERATEEN_DERATE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_ENABLE_SHIFT)) & DDRC_DERATEEN_DERATE_ENABLE_MASK)
#define DDRC_DERATEEN_DERATE_VALUE_MASK (0x2U)
#define DDRC_DERATEEN_DERATE_VALUE_SHIFT (1U)
/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
* Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
* core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
* register field should be set to 1; otherwise it should be set to 0.
* 0b0..Derating uses +1
* 0b1..Derating uses +2
*/
#define DDRC_DERATEEN_DERATE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_DERATE_VALUE_MASK)
#define DDRC_DERATEEN_DERATE_BYTE_MASK (0xF0U)
#define DDRC_DERATEEN_DERATE_BYTE_SHIFT (4U)
/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
* Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
* MEMC_DRAM_TOTAL_DATA_WIDTH.
*/
#define DDRC_DERATEEN_DERATE_BYTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_DERATE_BYTE_SHIFT)) & DDRC_DERATEEN_DERATE_BYTE_MASK)
#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK (0x300U)
#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT (8U)
/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
* LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
* core_ddrc_core_clk period, and rounding up the next integer.
* 0b00..Derating uses +1
* 0b01..Derating uses +2
* 0b10..Derating uses +3
* 0b11..Derating uses +4
*/
#define DDRC_DERATEEN_RC_DERATE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_RC_DERATE_VALUE_MASK)
/*! @} */
/*! @name DERATEINT - Temperature Derate Interval Register */
/*! @{ */
#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK (0xFFFFFFFFU)
#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT (0U)
/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
* Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
* zero. Unit: DFI clock cycle.
*/
#define DDRC_DERATEINT_MR4_READ_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT)) & DDRC_DERATEINT_MR4_READ_INTERVAL_MASK)
/*! @} */
/*! @name PWRCTL - Low Power Control Register */
/*! @{ */
#define DDRC_PWRCTL_SELFREF_EN_MASK (0x1U)
#define DDRC_PWRCTL_SELFREF_EN_SHIFT (0U)
/*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number
* of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit
* may be re-programmed during the course of normal operation.
*/
#define DDRC_PWRCTL_SELFREF_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_SELFREF_EN_SHIFT)) & DDRC_PWRCTL_SELFREF_EN_MASK)
#define DDRC_PWRCTL_POWERDOWN_EN_MASK (0x2U)
#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT (1U)
/*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles
* "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be
* re-programmed during the course of normal operation.
*/
#define DDRC_PWRCTL_POWERDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_POWERDOWN_EN_SHIFT)) & DDRC_PWRCTL_POWERDOWN_EN_MASK)
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK (0x4U)
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT (2U)
/*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the
* transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down
* mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only
* in designs configured to support mDDR or LPDDR2 or LPDDR3. For
* non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
*/
#define DDRC_PWRCTL_DEEPPOWERDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT)) & DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK)
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U)
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U)
/*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not
* required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of
* dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can
* be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3,
* can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal
* operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in
* Power Down during Normal operation (Clock Stop)
*/
#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT)) & DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK)
#define DDRC_PWRCTL_MPSM_EN_MASK (0x10U)
#define DDRC_PWRCTL_MPSM_EN_SHIFT (4U)
/*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the
* transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power
* saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register
* should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY
* parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to
* toggle. FOR PERFORMANCE ONLY.
*/
#define DDRC_PWRCTL_MPSM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_MPSM_EN_SHIFT)) & DDRC_PWRCTL_MPSM_EN_MASK)
#define DDRC_PWRCTL_SELFREF_SW_MASK (0x20U)
#define DDRC_PWRCTL_SELFREF_SW_SHIFT (5U)
/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
* immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
* Entry/Exit to Self Refresh.
* 0b0..Software Exit from Self Refresh
* 0b1..Software Entry to Self Refresh
*/
#define DDRC_PWRCTL_SELFREF_SW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_SELFREF_SW_SHIFT)) & DDRC_PWRCTL_SELFREF_SW_MASK)
#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK (0x40U)
#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT (6U)
/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
* down state or exit Self refresh power down state for LPDDR4. This register controls transition
* from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
* transition from Self refresh state
* 0b0..
* 0b1..
*/
#define DDRC_PWRCTL_STAY_IN_SELFREF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT)) & DDRC_PWRCTL_STAY_IN_SELFREF_MASK)
/*! @} */
/*! @name PWRTMG - Low Power Timing Register */
/*! @{ */
#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK (0x1FU)
#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT (0U)
/*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
* automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there
* are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit:
* Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
*/
#define DDRC_PWRTMG_POWERDOWN_TO_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT)) & DDRC_PWRTMG_POWERDOWN_TO_X32_MASK)
#define DDRC_PWRTMG_T_DPD_X4096_MASK (0xFF00U)
#define DDRC_PWRTMG_T_DPD_X4096_SHIFT (8U)
/*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as
* mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is
* de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI
* clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
* ONLY.
*/
#define DDRC_PWRTMG_T_DPD_X4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_T_DPD_X4096_SHIFT)) & DDRC_PWRTMG_T_DPD_X4096_MASK)
#define DDRC_PWRTMG_SELFREF_TO_X32_MASK (0xFF0000U)
#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT (16U)
/*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
* automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there
* are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit:
* Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
*/
#define DDRC_PWRTMG_SELFREF_TO_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT)) & DDRC_PWRTMG_SELFREF_TO_X32_MASK)
/*! @} */
/*! @name HWLPCTL - Hardware Low Power Control Register */
/*! @{ */
#define DDRC_HWLPCTL_HW_LP_EN_MASK (0x1U)
#define DDRC_HWLPCTL_HW_LP_EN_SHIFT (0U)
/*! hw_lp_en - Enable for Hardware Low Power Interface.
*/
#define DDRC_HWLPCTL_HW_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_EN_SHIFT)) & DDRC_HWLPCTL_HW_LP_EN_MASK)
#define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK (0x2U)
#define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT (1U)
/*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be
* used to exit from the automatic clock stop, automatic power down or automatic self-refresh
* modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power
* Interface and/or Software (PWRCTL.selfref_sw).
*/
#define DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT)) & DDRC_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK)
#define DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK (0xFFF0000U)
#define DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT (16U)
/*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command
* channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The
* DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware
* idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR
* PERFORMANCE ONLY.
*/
#define DDRC_HWLPCTL_HW_LP_IDLE_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_HW_LP_IDLE_X32_SHIFT)) & DDRC_HWLPCTL_HW_LP_IDLE_X32_MASK)
/*! @} */
/*! @name RFSHCTL0 - Refresh Control Register 0 */
/*! @{ */
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK (0x4U)
#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT (2U)
/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
* not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
* Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
* 0b1..Per bank refresh
* 0b0..All bank refresh
*/
#define DDRC_RFSHCTL0_PER_BANK_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT)) & DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK)
#define DDRC_RFSHCTL0_REFRESH_BURST_MASK (0x1F0U)
#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT (4U)
/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
* accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
* perform a refresh is a one-time penalty that must be paid for each group of refreshes.
* Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
* Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
* the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
* refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
* DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
* per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
* feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
* mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
* must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
* due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
* situation, the refresh burst will be delayed until the PHY-initiated update is complete.
*/
#define DDRC_RFSHCTL0_REFRESH_BURST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT)) & DDRC_RFSHCTL0_REFRESH_BURST_MASK)
#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK (0x1F000U)
#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT (12U)
/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
* but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
* performed. A speculative refresh is a refresh performed at a time when refresh would be
* useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
* determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
* the last refresh, then a speculative refresh is performed. Speculative refreshes continues
* successively until there are no refreshes pending or until new reads or writes are issued to the
* DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
*/
#define DDRC_RFSHCTL0_REFRESH_TO_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT)) & DDRC_RFSHCTL0_REFRESH_TO_X32_MASK)
#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK (0xF00000U)
#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT (20U)
/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
* page timer expires. A critical refresh is to be issued before this threshold is reached. It is
* recommended that this not be changed from the default value, currently shown as 0x2. It must
* always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
* internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
* (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
* RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
*/
#define DDRC_RFSHCTL0_REFRESH_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT)) & DDRC_RFSHCTL0_REFRESH_MARGIN_MASK)
/*! @} */
/*! @name RFSHCTL1 - Refresh Control Register 1 */
/*! @{ */
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU)
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U)
/*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank
* configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
* proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
* of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
*/
#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT)) & DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK)
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000U)
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U)
/*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank
* configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
* proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
* of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
*/
#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT)) & DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK)
/*! @} */
/*! @name RFSHCTL3 - Refresh Control Register 3 */
/*! @{ */
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK (0x1U)
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT (0U)
/*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is
* disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh,
* reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh
* transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4
* CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is
* not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled
* (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This
* register field is changeable on the fly.
*/
#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT)) & DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK)
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK (0x2U)
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U)
/*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
* the refresh register(s) have been updated. refresh_update_level must not be toggled when the
* DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when
* exiting reset.
*/
#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT)) & DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK)
#define DDRC_RFSHCTL3_REFRESH_MODE_MASK (0x70U)
#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT (4U)
/*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x -
* 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not
* supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if
* RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC.
* Note: This must be set up while the Controller is in reset or while the Controller is in
* self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic
* register will be supported in future version of the DDRC. Note: This register field has effect only
* if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
*/
#define DDRC_RFSHCTL3_REFRESH_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT)) & DDRC_RFSHCTL3_REFRESH_MODE_MASK)
/*! @} */
/*! @name RFSHTMG - Refresh Timing Register */
/*! @{ */
#define DDRC_RFSHTMG_T_RFC_MIN_MASK (0x3FFU)
#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT (0U)
/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
* operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
* is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
* LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
* is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
* equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
* on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
* appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
* Unit: Clocks.
*/
#define DDRC_RFSHTMG_T_RFC_MIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_T_RFC_MIN_SHIFT)) & DDRC_RFSHTMG_T_RFC_MIN_MASK)
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK (0x8000U)
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT (15U)
/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
* DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
* devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
* parameter not used - 1 - tREFBW parameter used
*/
#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT)) & DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK)
#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK (0xFFF0000U)
#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT (16U)
/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
* for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
* LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
* should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
* register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
* program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
* on the refresh mode. The user should program the appropriate value from the spec based on the
* value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
* greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
* DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
* 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
* RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
*/
#define DDRC_RFSHTMG_T_RFC_NOM_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT)) & DDRC_RFSHTMG_T_RFC_NOM_X32_MASK)
/*! @} */
/*! @name ECCCFG0 - ECC Configuration Register 0 */
/*! @{ */
#define DDRC_ECCCFG0_ECC_MODE_MASK (0x7U)
#define DDRC_ECCCFG0_ECC_MODE_SHIFT (0U)
/*! ecc_mode - ECC mode indicator.
*/
#define DDRC_ECCCFG0_ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_MODE_SHIFT)) & DDRC_ECCCFG0_ECC_MODE_MASK)
#define DDRC_ECCCFG0_DIS_SCRUB_MASK (0x10U)
#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT (4U)
/*! dis_scrub - Disables ECC scrubs.
*/
#define DDRC_ECCCFG0_DIS_SCRUB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_DIS_SCRUB_SHIFT)) & DDRC_ECCCFG0_DIS_SCRUB_MASK)
#define DDRC_ECCCFG0_ECC_AP_EN_MASK (0x40U)
#define DDRC_ECCCFG0_ECC_AP_EN_SHIFT (6U)
/*! ecc_ap_en - Enables address protection feature. Only supported when inline ECC is enabled.
*/
#define DDRC_ECCCFG0_ECC_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_AP_EN_SHIFT)) & DDRC_ECCCFG0_ECC_AP_EN_MASK)
#define DDRC_ECCCFG0_ECC_REGION_REMAP_EN_MASK (0x80U)
#define DDRC_ECCCFG0_ECC_REGION_REMAP_EN_SHIFT (7U)
/*! ecc_region_remap_en - Enables remapping ECC region feature. Only supported when inline ECC is enabled.
*/
#define DDRC_ECCCFG0_ECC_REGION_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_REMAP_EN_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_REMAP_EN_MASK)
#define DDRC_ECCCFG0_ECC_REGION_MAP_MASK (0x7F00U)
#define DDRC_ECCCFG0_ECC_REGION_MAP_SHIFT (8U)
/*! ecc_region_map - Selectable Protected Region setting.
*/
#define DDRC_ECCCFG0_ECC_REGION_MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_MASK)
#define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_MASK (0x3F0000U)
#define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_SHIFT (16U)
/*! blk_channel_idle_time_x32 - Indicates the number of cycles on HIF interface with no access to
* protected regions which causes flush of all the block channels.
*/
#define DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_SHIFT)) & DDRC_ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_MASK)
#define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_MASK (0x7000000U)
#define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_SHIFT (24U)
/*! ecc_ap_err_threshold - Sets threshold for address parity error.
*/
#define DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_SHIFT)) & DDRC_ECCCFG0_ECC_AP_ERR_THRESHOLD_MASK)
#define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_MASK (0x20000000U)
#define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_SHIFT (29U)
/*! ecc_region_map_other - When ECCCFG0[ecc_region_map_granu] > 0, there is a region which is not
* controlled by ecc_region_map. This register defines the region to be protected or non-protected
* for Inline ECC. This register is valid only when ECCCFG0[ecc_region_map_granu]>0 &&
* ECCCFG0[ecc_mode]=4.
*/
#define DDRC_ECCCFG0_ECC_REGION_MAP_OTHER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_OTHER_MASK)
#define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_MASK (0xC0000000U)
#define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT (30U)
/*! ecc_region_map_granu - Indicates granularity of selectable protected region
*/
#define DDRC_ECCCFG0_ECC_REGION_MAP_GRANU(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT)) & DDRC_ECCCFG0_ECC_REGION_MAP_GRANU_MASK)
/*! @} */
/*! @name ECCCFG1 - ECC Configuration Register 1 */
/*! @{ */
#define DDRC_ECCCFG1_DATA_POISON_EN_MASK (0x1U)
#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT (0U)
/*! data_poison_en - Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers.
*/
#define DDRC_ECCCFG1_DATA_POISON_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT)) & DDRC_ECCCFG1_DATA_POISON_EN_MASK)
#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK (0x2U)
#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT (1U)
/*! data_poison_bit - Selects whether to poison 1 or 2 bits.
*/
#define DDRC_ECCCFG1_DATA_POISON_BIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT)) & DDRC_ECCCFG1_DATA_POISON_BIT_MASK)
#define DDRC_ECCCFG1_POISON_CHIP_EN_MASK (0x4U)
#define DDRC_ECCCFG1_POISON_CHIP_EN_SHIFT (2U)
/*! poison_chip_en - Indicates the data poison based on chip (that is, persistently poisons the DRAM
* data once its cs is selected to mimic chip failure). It is valid if ECCCFG1[data_poison_en]=1.
*/
#define DDRC_ECCCFG1_POISON_CHIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_POISON_CHIP_EN_SHIFT)) & DDRC_ECCCFG1_POISON_CHIP_EN_MASK)
#define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_MASK (0x10U)
#define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_SHIFT (4U)
/*! ecc_region_parity_lock - Locks the parity section of the ECC region (hole) which is the highest
* system address part of the memory that stores ECC parity for protected region.
*/
#define DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_SHIFT)) & DDRC_ECCCFG1_ECC_REGION_PARITY_LOCK_MASK)
#define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_MASK (0x20U)
#define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_SHIFT (5U)
/*! ecc_region_waste_lock - Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock.
*/
#define DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_SHIFT)) & DDRC_ECCCFG1_ECC_REGION_WASTE_LOCK_MASK)
#define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_MASK (0x80U)
#define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_SHIFT (7U)
/*! blk_channel_active_term - If enabled, block channel is terminated when full block write or full
* block read is performed (all address within block are written or read). This is debug
* register, and this must be set to 1 for normal operation.
*/
#define DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_SHIFT)) & DDRC_ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_MASK)
#define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_MASK (0xF00U)
#define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_SHIFT (8U)
/*! active_blk_channel - Indicated the number of active block channels.
*/
#define DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_SHIFT)) & DDRC_ECCCFG1_ACTIVE_BLK_CHANNEL_MASK)
/*! @} */
/*! @name INIT0 - SDRAM Initialization Register 0 */
/*! @{ */
#define DDRC_INIT0_PRE_CKE_X1024_MASK (0xFFFU)
#define DDRC_INIT0_PRE_CKE_X1024_SHIFT (0U)
/*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM
* initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be
* programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2
* ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC
* spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this
* should include the time needed to satisfy tSTAB
*/
#define DDRC_INIT0_PRE_CKE_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_PRE_CKE_X1024_SHIFT)) & DDRC_INIT0_PRE_CKE_X1024_MASK)
#define DDRC_INIT0_POST_CKE_X1024_MASK (0x3FF0000U)
#define DDRC_INIT0_POST_CKE_X1024_SHIFT (16U)
/*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization
* sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value
* to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be
* programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us.
* When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
* value divided by 2, and round it up to the next integer value.
*/
#define DDRC_INIT0_POST_CKE_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_POST_CKE_X1024_SHIFT)) & DDRC_INIT0_POST_CKE_X1024_MASK)
#define DDRC_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000U)
#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT (30U)
/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
* bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
* Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
* power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
* power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
* after power-up.
* 0b00..SDRAM Initialization routine is run after power-up
* 0b01..SDRAM Initialization routine is skipped after power-up
* 0b10..SDRAM Initialization routine is run after power-up
* 0b11..SDRAM Initialization routine is skipped after power-up
*/
#define DDRC_INIT0_SKIP_DRAM_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT)) & DDRC_INIT0_SKIP_DRAM_INIT_MASK)
/*! @} */
/*! @name INIT1 - SDRAM Initialization Register 1 */
/*! @{ */
#define DDRC_INIT1_PRE_OCD_X32_MASK (0xFU)
#define DDRC_INIT1_PRE_OCD_X32_SHIFT (0U)
/*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a
* global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for
* this; it may be set to zero.
*/
#define DDRC_INIT1_PRE_OCD_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_PRE_OCD_X32_SHIFT)) & DDRC_INIT1_PRE_OCD_X32_MASK)
#define DDRC_INIT1_DRAM_RSTN_X1024_MASK (0x1FF0000U)
#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT (16U)
/*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is
* only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this
* should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode,
* program this to JEDEC spec value divided by 2, and round it up to the next integer value.
* Unit: 1024 DFI clock cycles.
*/
#define DDRC_INIT1_DRAM_RSTN_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT)) & DDRC_INIT1_DRAM_RSTN_X1024_MASK)
/*! @} */
/*! @name INIT2 - SDRAM Initialization Register 2 */
/*! @{ */
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK (0xFU)
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT (0U)
/*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs
* configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the
* controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by
* 2, and round it up to the next integer value. Unit: DFI clock cycles.
*/
#define DDRC_INIT2_MIN_STABLE_CLOCK_X1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT)) & DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK)
#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK (0xFF00U)
#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT (8U)
/*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs
* configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program
* this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI
* clock cycles.
*/
#define DDRC_INIT2_IDLE_AFTER_RESET_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT)) & DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK)
/*! @} */
/*! @name INIT3 - SDRAM Initialization Register 3 */
/*! @{ */
#define DDRC_INIT3_EMR_MASK (0xFFFFU)
#define DDRC_INIT3_EMR_SHIFT (0U)
/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
* register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
* register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
* the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
* Value to write to MR2 register
*/
#define DDRC_INIT3_EMR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_EMR_SHIFT)) & DDRC_INIT3_EMR_MASK)
#define DDRC_INIT3_MR_MASK (0xFFFF0000U)
#define DDRC_INIT3_MR_SHIFT (16U)
/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
* DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
* write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
*/
#define DDRC_INIT3_MR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_MR_SHIFT)) & DDRC_INIT3_MR_MASK)
/*! @} */
/*! @name INIT4 - SDRAM Initialization Register 4 */
/*! @{ */
#define DDRC_INIT4_EMR3_MASK (0xFFFFU)
#define DDRC_INIT4_EMR3_SHIFT (0U)
/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
* mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
*/
#define DDRC_INIT4_EMR3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_EMR3_SHIFT)) & DDRC_INIT4_EMR3_MASK)
#define DDRC_INIT4_EMR2_MASK (0xFFFF0000U)
#define DDRC_INIT4_EMR2_SHIFT (16U)
/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
* LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
*/
#define DDRC_INIT4_EMR2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_EMR2_SHIFT)) & DDRC_INIT4_EMR2_MASK)
/*! @} */
/*! @name INIT5 - SDRAM Initialization Register 5 */
/*! @{ */
#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK (0x3FFU)
#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT (0U)
/*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in
* designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI
* clock cycles.
*/
#define DDRC_INIT5_MAX_AUTO_INIT_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT)) & DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK)
#define DDRC_INIT5_DEV_ZQINIT_X32_MASK (0xFF0000U)
#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT (16U)
/*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support
* DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires
* 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2
* frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the
* next integer value. Unit: 32 DFI clock cycles.
*/
#define DDRC_INIT5_DEV_ZQINIT_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT)) & DDRC_INIT5_DEV_ZQINIT_X32_MASK)
/*! @} */
/*! @name INIT6 - SDRAM Initialization Register 6 */
/*! @{ */
#define DDRC_INIT6_MR5_MASK (0xFFFFU)
#define DDRC_INIT6_MR5_SHIFT (0U)
/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT6_MR5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_MR5_SHIFT)) & DDRC_INIT6_MR5_MASK)
#define DDRC_INIT6_MR4_MASK (0xFFFF0000U)
#define DDRC_INIT6_MR4_SHIFT (16U)
/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT6_MR4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_MR4_SHIFT)) & DDRC_INIT6_MR4_MASK)
/*! @} */
/*! @name INIT7 - SDRAM Initialization Register 7 */
/*! @{ */
#define DDRC_INIT7_MR6_MASK (0xFFFF0000U)
#define DDRC_INIT7_MR6_SHIFT (16U)
/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT7_MR6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_MR6_SHIFT)) & DDRC_INIT7_MR6_MASK)
/*! @} */
/*! @name DIMMCTL - DIMM Control Register */
/*! @{ */
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK (0x1U)
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT (0U)
/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
* LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
* Even if this bit is set it does not take care of software driven MR commands (via
* MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
* 0b0..Do not stagger accesses
* 0b1..(non-DDR4) Send all commands to even and odd ranks separately
*/
#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK)
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK (0x2U)
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT (1U)
/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
* multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
* mirroring for odd ranks, which means that the following address, bank address and bank group
* bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
* the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
* initialization routine, these bits are swapped within the DDRC to compensate for this
* UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
* UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
* DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
* software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
* SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
* because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
* 0b0..Do not implement address mirroring
* 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
* automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
*/
#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK)
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK (0x4U)
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT (2U)
/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
* RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
* following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
* A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
* DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
* separate A-side and B-side mode register accesses are generated. For B-side mode register
* accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
* is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
* on the address of any other memory accesses, or of software-driven mode register accesses.
* 0b0..Do not implement output inversion for B-side DRAMs.
* 0b1..Implement output inversion for B-side DRAMs.
*/
#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT)) & DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK)
#define DDRC_DIMMCTL_MRS_A17_EN_MASK (0x8U)
#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT (3U)
/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
* specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
* which do not have A17 are attached and the Output Inversion are enabled, this must be set to
* 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
* the address of any other memory accesses, or of software-driven mode register accesses.
* 0b0..Disabled
* 0b1..Enabled
*/
#define DDRC_DIMMCTL_MRS_A17_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_MRS_A17_EN_SHIFT)) & DDRC_DIMMCTL_MRS_A17_EN_MASK)
#define DDRC_DIMMCTL_MRS_BG1_EN_MASK (0x10U)
#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT (4U)
/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
* specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
* which do not have BG1 are attached and both the CA parity and the Output Inversion are
* enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
* This has no effect on the address of any other memory accesses, or of software-driven mode
* register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
* of odd ranks.
* 0b0..Disabled
* 0b1..Enabled
*/
#define DDRC_DIMMCTL_MRS_BG1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT)) & DDRC_DIMMCTL_MRS_BG1_EN_MASK)
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK (0x20U)
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT (5U)
/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
* BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
* with x16 devices.
* 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
* 0b1..BG0 and BG1 are NOT swapped.
*/
#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT)) & DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK)
#define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_MASK (0x40U)
#define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_SHIFT (6U)
/*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM
* commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set
* to 1. Otherwise, this bit must be set to 0.
*/
#define DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_SHIFT)) & DDRC_DIMMCTL_LRDIMM_BCOM_CMD_PROT_MASK)
/*! @} */
/*! @name RANKCTL - Rank Control Register */
/*! @{ */
#define DDRC_RANKCTL_MAX_RANK_RD_MASK (0xFU)
#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT (0U)
/*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can
* be performed back-to-back. Reads to different ranks require additional gap dictated by the
* register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to
* give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus
* access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles
* (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the
* same rank are eligible to be scheduled. This prevents reads from other ranks from having fair
* access to the data bus. This parameter represents the maximum number of reads that can be
* scheduled consecutively to the same rank. After this number is reached, a delay equal to
* RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be
* scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This
* feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on
* the same rank as long as commands are available for it. Minimum programmable value is 0 (feature
* disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
*/
#define DDRC_RANKCTL_MAX_RANK_RD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_MAX_RANK_RD_SHIFT)) & DDRC_RANKCTL_MAX_RANK_RD_MASK)
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK (0xF0U)
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT (4U)
/*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of
* gap in data responses when performing consecutive reads to different ranks. This is used to
* switch the delays in the PHY to match the rank requirements. This value should consider both
* PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for
* value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased
* by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT
* requirement: The value programmed in this register takes care of the ODT switch off timing requirement
* when switching ranks during reads. When the controller is operating in 1:1 mode, program this
* to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2
* mode, program this to the larger value divided by two and round it up to the next integer.
* Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer
* (DDR4DB01) Specification.
*/
#define DDRC_RANKCTL_DIFF_RANK_RD_GAP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT)) & DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK)
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK (0xF00U)
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT (8U)
/*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of
* gap in data responses when performing consecutive writes to different ranks. This is used to
* switch the delays in the PHY to match the rank requirements. This value should consider both
* PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for
* value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble
* is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to
* 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this
* register takes care of the ODT switch off timing requirement when switching ranks during writes.
* For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in
* 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the
* controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to
* the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in
* JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
*/
#define DDRC_RANKCTL_DIFF_RANK_WR_GAP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT)) & DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK)
/*! @} */
/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
/*! @{ */
#define DDRC_DRAMTMG0_T_RAS_MIN_MASK (0x3FU)
#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT (0U)
/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
* controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
* up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
* program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG0_T_RAS_MIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT)) & DDRC_DRAMTMG0_T_RAS_MIN_MASK)
#define DDRC_DRAMTMG0_T_RAS_MAX_MASK (0x7F00U)
#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT (8U)
/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
* maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
* When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
* No rounding up. Unit: Multiples of 1024 clocks.
*/
#define DDRC_DRAMTMG0_T_RAS_MAX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT)) & DDRC_DRAMTMG0_T_RAS_MAX_MASK)
#define DDRC_DRAMTMG0_T_FAW_MASK (0x3F0000U)
#define DDRC_DRAMTMG0_T_FAW_SHIFT (16U)
/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
* design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
* is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
* integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
* mode. Unit: Clocks
*/
#define DDRC_DRAMTMG0_T_FAW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_T_FAW_SHIFT)) & DDRC_DRAMTMG0_T_FAW_MASK)
#define DDRC_DRAMTMG0_WR2PRE_MASK (0x7F000000U)
#define DDRC_DRAMTMG0_WR2PRE_SHIFT (24U)
/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
* + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
* frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
* the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
* - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
* cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
* frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
* is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
* and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
* may be necessary to adjust the value of this parameter to compensate for the extra cycle of
* latency through the LRDIMM.
*/
#define DDRC_DRAMTMG0_WR2PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_WR2PRE_SHIFT)) & DDRC_DRAMTMG0_WR2PRE_MASK)
/*! @} */
/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
/*! @{ */
#define DDRC_DRAMTMG1_T_RC_MASK (0x7FU)
#define DDRC_DRAMTMG1_T_RC_SHIFT (0U)
/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
* frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
* Clocks.
*/
#define DDRC_DRAMTMG1_T_RC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_T_RC_SHIFT)) & DDRC_DRAMTMG1_T_RC_MASK)
#define DDRC_DRAMTMG1_RD2PRE_MASK (0x3F00U)
#define DDRC_DRAMTMG1_RD2PRE_SHIFT (8U)
/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
* 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
* or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
* LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
* - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
* use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
* divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
* mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
* Unit: Clocks.
*/
#define DDRC_DRAMTMG1_RD2PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_RD2PRE_SHIFT)) & DDRC_DRAMTMG1_RD2PRE_MASK)
#define DDRC_DRAMTMG1_T_XP_MASK (0x1F0000U)
#define DDRC_DRAMTMG1_T_XP_SHIFT (16U)
/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
* programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
* set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
* this to (tXP/2) and round it up to the next integer value. Units: Clocks
*/
#define DDRC_DRAMTMG1_T_XP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_T_XP_SHIFT)) & DDRC_DRAMTMG1_T_XP_MASK)
/*! @} */
/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
/*! @{ */
#define DDRC_DRAMTMG2_WR2RD_MASK (0x3FU)
#define DDRC_DRAMTMG2_WR2RD_SHIFT (0U)
/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
* write command to read command for same bank group. In others, minimum time from write command to
* read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
* global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
* = burst length. This must match the value programmed in the BL bit of the mode register to
* the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
* directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
* directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
* When the controller is operating in 1:2 mode, divide the value calculated using the above
* equation by 2, and round it up to next integer.
*/
#define DDRC_DRAMTMG2_WR2RD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_WR2RD_SHIFT)) & DDRC_DRAMTMG2_WR2RD_MASK)
#define DDRC_DRAMTMG2_RD2WR_MASK (0x3F00U)
#define DDRC_DRAMTMG2_RD2WR_SHIFT (8U)
/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
* + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
* + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
* RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
* Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
* the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
* WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
* the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
* preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
* LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
* tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
* value calculated using the above equation by 2, and round it up to next integer. Note that,
* depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
* to compensate for the extra cycle of latency through the LRDIMM.
*/
#define DDRC_DRAMTMG2_RD2WR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_RD2WR_SHIFT)) & DDRC_DRAMTMG2_RD2WR_MASK)
#define DDRC_DRAMTMG2_READ_LATENCY_MASK (0x3F0000U)
#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT (16U)
/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
* set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
* the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
* the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
* above equation by 2, and round it up to next integer. This register field is not required for
* DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
* DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
*/
#define DDRC_DRAMTMG2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_READ_LATENCY_SHIFT)) & DDRC_DRAMTMG2_READ_LATENCY_MASK)
#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK (0x3F000000U)
#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT (24U)
/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
* set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
* using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
* cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
* mode, divide the value calculated using the above equation by 2, and round it up to next
* integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
* as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
* protocols Unit: clocks
*/
#define DDRC_DRAMTMG2_WRITE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT)) & DDRC_DRAMTMG2_WRITE_LATENCY_MASK)
/*! @} */
/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
/*! @{ */
#define DDRC_DRAMTMG3_T_MOD_MASK (0x3FFU)
#define DDRC_DRAMTMG3_T_MOD_SHIFT (0U)
/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
* following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
* Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
* next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
* RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
* compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
* Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
* is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
* controller is operating in 1:2 frequency ratio mode.
*/
#define DDRC_DRAMTMG3_T_MOD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MOD_SHIFT)) & DDRC_DRAMTMG3_T_MOD_MASK)
#define DDRC_DRAMTMG3_T_MRD_MASK (0x3F000U)
#define DDRC_DRAMTMG3_T_MRD_SHIFT (12U)
/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
* SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
* command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
* value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
*/
#define DDRC_DRAMTMG3_T_MRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MRD_SHIFT)) & DDRC_DRAMTMG3_T_MRD_MASK)
#define DDRC_DRAMTMG3_T_MRW_MASK (0x3FF00000U)
#define DDRC_DRAMTMG3_T_MRW_SHIFT (20U)
/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
* configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
* typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
* this register is used for the time from a MRW/MRR to all other commands. When the controller
* is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
* round it up to the next integer value. For LDPDR3, this register is used for the time from a
* MRW/MRR to a MRW/MRR.
*/
#define DDRC_DRAMTMG3_T_MRW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_T_MRW_SHIFT)) & DDRC_DRAMTMG3_T_MRW_MASK)
/*! @} */
/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
/*! @{ */
#define DDRC_DRAMTMG4_T_RP_MASK (0x1FU)
#define DDRC_DRAMTMG4_T_RP_SHIFT (0U)
/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
* operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
* operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
* 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
* to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
*/
#define DDRC_DRAMTMG4_T_RP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RP_SHIFT)) & DDRC_DRAMTMG4_T_RP_MASK)
#define DDRC_DRAMTMG4_T_RRD_MASK (0xF00U)
#define DDRC_DRAMTMG4_T_RRD_SHIFT (8U)
/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
* group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
* is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
* up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG4_T_RRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RRD_SHIFT)) & DDRC_DRAMTMG4_T_RRD_MASK)
#define DDRC_DRAMTMG4_T_CCD_MASK (0xF0000U)
#define DDRC_DRAMTMG4_T_CCD_SHIFT (16U)
/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
* group. Others: tCCD: This is the minimum time between two reads or two writes. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
* up to the next integer value. Unit: clocks.
*/
#define DDRC_DRAMTMG4_T_CCD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_CCD_SHIFT)) & DDRC_DRAMTMG4_T_CCD_MASK)
#define DDRC_DRAMTMG4_T_RCD_MASK (0x1F000000U)
#define DDRC_DRAMTMG4_T_RCD_SHIFT (24U)
/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
* controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
* it up to the next integer value. Minimum value allowed for this register is 1, which implies
* minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
* mode. Unit: Clocks.
*/
#define DDRC_DRAMTMG4_T_RCD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_T_RCD_SHIFT)) & DDRC_DRAMTMG4_T_RCD_MASK)
/*! @} */
/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
/*! @{ */
#define DDRC_DRAMTMG5_T_CKE_MASK (0x1FU)
#define DDRC_DRAMTMG5_T_CKE_SHIFT (0U)
/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
* LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
* tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
* the controller is operating in 1:2 frequency ratio mode, program this to (value described
* above)/2 and round it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG5_T_CKE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKE_SHIFT)) & DDRC_DRAMTMG5_T_CKE_MASK)
#define DDRC_DRAMTMG5_T_CKESR_MASK (0x3F00U)
#define DDRC_DRAMTMG5_T_CKESR_SHIFT (8U)
/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
* in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
* - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
* latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
* by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_T_CKESR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKESR_SHIFT)) & DDRC_DRAMTMG5_T_CKESR_MASK)
#define DDRC_DRAMTMG5_T_CKSRE_MASK (0xF0000U)
#define DDRC_DRAMTMG5_T_CKSRE_SHIFT (16U)
/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
* LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
* PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
* be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
* this to recommended value divided by two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_T_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKSRE_SHIFT)) & DDRC_DRAMTMG5_T_CKSRE_MASK)
#define DDRC_DRAMTMG5_T_CKSRX_MASK (0xF000000U)
#define DDRC_DRAMTMG5_T_CKSRX_SHIFT (24U)
/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
* before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
* LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
* controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
* two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_T_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_T_CKSRX_SHIFT)) & DDRC_DRAMTMG5_T_CKSRX_MASK)
/*! @} */
/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
/*! @{ */
#define DDRC_DRAMTMG6_T_CKCSX_MASK (0xFU)
#define DDRC_DRAMTMG6_T_CKCSX_SHIFT (0U)
/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
* issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
* Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
* When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
* divided by two and round it up to next integer. This is only present for designs supporting
* mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG6_T_CKCSX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKCSX_SHIFT)) & DDRC_DRAMTMG6_T_CKCSX_MASK)
#define DDRC_DRAMTMG6_T_CKDPDX_MASK (0xF0000U)
#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT (16U)
/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
* before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
* 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
* program this to recommended value divided by two and round it up to next integer. This is only
* present for designs supporting mDDR or LPDDR2 devices.
*/
#define DDRC_DRAMTMG6_T_CKDPDX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKDPDX_SHIFT)) & DDRC_DRAMTMG6_T_CKDPDX_MASK)
#define DDRC_DRAMTMG6_T_CKDPDE_MASK (0xF000000U)
#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT (24U)
/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
* LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer. This is only present for designs
* supporting mDDR or LPDDR2/LPDDR3 devices.
*/
#define DDRC_DRAMTMG6_T_CKDPDE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_T_CKDPDE_SHIFT)) & DDRC_DRAMTMG6_T_CKDPDE_MASK)
/*! @} */
/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
/*! @{ */
#define DDRC_DRAMTMG7_T_CKPDX_MASK (0xFU)
#define DDRC_DRAMTMG7_T_CKPDX_SHIFT (0U)
/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
* issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
* LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
* same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
* program this to recommended value divided by two and round it up to next integer. This is only
* present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG7_T_CKPDX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_T_CKPDX_SHIFT)) & DDRC_DRAMTMG7_T_CKPDX_MASK)
#define DDRC_DRAMTMG7_T_CKPDE_MASK (0xF00U)
#define DDRC_DRAMTMG7_T_CKPDE_SHIFT (8U)
/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
* - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
* DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
* to recommended value divided by two and round it up to next integer. This is only present for
* designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG7_T_CKPDE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_T_CKPDE_SHIFT)) & DDRC_DRAMTMG7_T_CKPDE_MASK)
/*! @} */
/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
/*! @{ */
#define DDRC_DRAMTMG8_T_XS_X32_MASK (0x7FU)
#define DDRC_DRAMTMG8_T_XS_X32_SHIFT (0U)
/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
* operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
* up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
* DDR4 SDRAMs.
*/
#define DDRC_DRAMTMG8_T_XS_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_X32_MASK)
#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK (0x7F00U)
#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT (8U)
/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
* is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
* round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
* DDR4 SDRAMs.
*/
#define DDRC_DRAMTMG8_T_XS_DLL_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_DLL_X32_MASK)
#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK (0x7F0000U)
#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT (16U)
/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
* Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
* above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
* Note: Ensure this is less than or equal to t_xs_x32.
*/
#define DDRC_DRAMTMG8_T_XS_ABORT_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK)
#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK (0x7F000000U)
#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT (24U)
/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
* mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
* above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
* This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
* t_xs_x32.
*/
#define DDRC_DRAMTMG8_T_XS_FAST_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT)) & DDRC_DRAMTMG8_T_XS_FAST_X32_MASK)
/*! @} */
/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
/*! @{ */
#define DDRC_DRAMTMG9_WR2RD_S_MASK (0x3FU)
#define DDRC_DRAMTMG9_WR2RD_S_SHIFT (0U)
/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
* bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
* global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
* - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
* programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
* command delay for different bank group. This comes directly from the SDRAM specification. When
* the controller is operating in 1:2 mode, divide the value calculated using the above equation
* by 2, and round it up to next integer.
*/
#define DDRC_DRAMTMG9_WR2RD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_WR2RD_S_SHIFT)) & DDRC_DRAMTMG9_WR2RD_S_MASK)
#define DDRC_DRAMTMG9_T_RRD_S_MASK (0xF00U)
#define DDRC_DRAMTMG9_T_RRD_S_SHIFT (8U)
/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
* group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
* and round it up to the next integer value. Present only in designs configured to support DDR4.
* Unit: Clocks.
*/
#define DDRC_DRAMTMG9_T_RRD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_T_RRD_S_SHIFT)) & DDRC_DRAMTMG9_T_RRD_S_MASK)
#define DDRC_DRAMTMG9_T_CCD_S_MASK (0x70000U)
#define DDRC_DRAMTMG9_T_CCD_S_SHIFT (16U)
/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
* group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
* the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
* it up to the next integer value. Present only in designs configured to support DDR4. Unit:
* clocks.
*/
#define DDRC_DRAMTMG9_T_CCD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_T_CCD_S_SHIFT)) & DDRC_DRAMTMG9_T_CCD_S_MASK)
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK (0x40000000U)
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT (30U)
/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
*/
#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT)) & DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK)
/*! @} */
/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
/*! @{ */
#define DDRC_DRAMTMG10_T_GEAR_HOLD_MASK (0x3U)
#define DDRC_DRAMTMG10_T_GEAR_HOLD_SHIFT (0U)
/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
* DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
* 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
* value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_T_GEAR_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_GEAR_HOLD_SHIFT)) & DDRC_DRAMTMG10_T_GEAR_HOLD_MASK)
#define DDRC_DRAMTMG10_T_GEAR_SETUP_MASK (0xCU)
#define DDRC_DRAMTMG10_T_GEAR_SETUP_SHIFT (2U)
/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
* DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
* 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
* value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_T_GEAR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_GEAR_SETUP_SHIFT)) & DDRC_DRAMTMG10_T_GEAR_SETUP_MASK)
#define DDRC_DRAMTMG10_T_CMD_GEAR_MASK (0x1F00U)
#define DDRC_DRAMTMG10_T_CMD_GEAR_SHIFT (8U)
/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
* defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
* this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
* and round it up to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_T_CMD_GEAR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_CMD_GEAR_SHIFT)) & DDRC_DRAMTMG10_T_CMD_GEAR_MASK)
#define DDRC_DRAMTMG10_T_SYNC_GEAR_MASK (0x1F0000U)
#define DDRC_DRAMTMG10_T_SYNC_GEAR_SHIFT (16U)
/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
* number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
* tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
* When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
* to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_T_SYNC_GEAR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_T_SYNC_GEAR_SHIFT)) & DDRC_DRAMTMG10_T_SYNC_GEAR_MASK)
/*! @} */
/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
/*! @{ */
#define DDRC_DRAMTMG11_T_CKMPE_MASK (0x1FU)
#define DDRC_DRAMTMG11_T_CKMPE_SHIFT (0U)
/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
* configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
* mode, divide the value calculated using the above equation by 2, and round it up to next
* integer.
*/
#define DDRC_DRAMTMG11_T_CKMPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_CKMPE_SHIFT)) & DDRC_DRAMTMG11_T_CKMPE_MASK)
#define DDRC_DRAMTMG11_T_MPX_S_MASK (0x300U)
#define DDRC_DRAMTMG11_T_MPX_S_SHIFT (8U)
/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
* frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
* Present only in designs configured to support DDR4. Unit: Clocks.
*/
#define DDRC_DRAMTMG11_T_MPX_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_MPX_S_SHIFT)) & DDRC_DRAMTMG11_T_MPX_S_MASK)
#define DDRC_DRAMTMG11_T_MPX_LH_MASK (0x1F0000U)
#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT (16U)
/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
* controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
* only in designs configured to support DDR4. Unit: clocks.
*/
#define DDRC_DRAMTMG11_T_MPX_LH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_T_MPX_LH_SHIFT)) & DDRC_DRAMTMG11_T_MPX_LH_MASK)
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK (0x7F000000U)
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT (24U)
/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
* When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
* round it up to the next integer value. Present only in designs configured to support DDR4.
* Unit: Multiples of 32 clocks.
*/
#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT)) & DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK)
/*! @} */
/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
/*! @{ */
#define DDRC_DRAMTMG12_T_MRD_PDA_MASK (0x1FU)
#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT (0U)
/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
* to the next integer value.
*/
#define DDRC_DRAMTMG12_T_MRD_PDA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT)) & DDRC_DRAMTMG12_T_MRD_PDA_MASK)
#define DDRC_DRAMTMG12_T_CKEHCMD_MASK (0xF00U)
#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT (8U)
/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
* integer value.
*/
#define DDRC_DRAMTMG12_T_CKEHCMD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT)) & DDRC_DRAMTMG12_T_CKEHCMD_MASK)
#define DDRC_DRAMTMG12_T_CMDCKE_MASK (0x30000U)
#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT (16U)
/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
* or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
* (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
*/
#define DDRC_DRAMTMG12_T_CMDCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_T_CMDCKE_SHIFT)) & DDRC_DRAMTMG12_T_CMDCKE_MASK)
/*! @} */
/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
/*! @{ */
#define DDRC_DRAMTMG13_T_PPD_MASK (0x7U)
#define DDRC_DRAMTMG13_T_PPD_SHIFT (0U)
/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
* the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_T_PPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_T_PPD_SHIFT)) & DDRC_DRAMTMG13_T_PPD_MASK)
#define DDRC_DRAMTMG13_T_CCD_MW_MASK (0x3F0000U)
#define DDRC_DRAMTMG13_T_CCD_MW_SHIFT (16U)
/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
* command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
* this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_T_CCD_MW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_T_CCD_MW_SHIFT)) & DDRC_DRAMTMG13_T_CCD_MW_MASK)
#define DDRC_DRAMTMG13_ODTLOFF_MASK (0x7F000000U)
#define DDRC_DRAMTMG13_ODTLOFF_SHIFT (24U)
/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
* the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
* it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_ODTLOFF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_ODTLOFF_SHIFT)) & DDRC_DRAMTMG13_ODTLOFF_MASK)
/*! @} */
/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
/*! @{ */
#define DDRC_DRAMTMG14_T_XSR_MASK (0xFFFU)
#define DDRC_DRAMTMG14_T_XSR_SHIFT (0U)
/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
* frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
* Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
*/
#define DDRC_DRAMTMG14_T_XSR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_T_XSR_SHIFT)) & DDRC_DRAMTMG14_T_XSR_MASK)
/*! @} */
/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
/*! @{ */
#define DDRC_DRAMTMG15_T_STAB_X32_MASK (0xFFU)
#define DDRC_DRAMTMG15_T_STAB_X32_SHIFT (0U)
/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
* RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
* clock must be stable for a time specified by tSTAB - in the case of input clock frequency
* change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
* DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
* cycles.
*/
#define DDRC_DRAMTMG15_T_STAB_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_T_STAB_X32_SHIFT)) & DDRC_DRAMTMG15_T_STAB_X32_MASK)
#define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_MASK (0x80000000U)
#define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_SHIFT (31U)
/*! en_dfi_lp_t_stab - Enable DFI tSTAB
* 0b0..Disable using tSTAB when exiting DFI LP
* 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
*/
#define DDRC_DRAMTMG15_EN_DFI_LP_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_SHIFT)) & DDRC_DRAMTMG15_EN_DFI_LP_T_STAB_MASK)
/*! @} */
/*! @name ZQCTL0 - ZQ Control Register 0 */
/*! @{ */
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK (0x3FFU)
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT (0U)
/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
* of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
* When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
* round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
* LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT)) & DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK)
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK (0x7FF0000U)
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT (16U)
/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
* clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
* issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
* this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
* tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
* up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
* LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_T_ZQ_LONG_NOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT)) & DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK)
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK (0x10000000U)
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT (28U)
/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
* configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
* MPSM mode.
* 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
* This is only present for designs supporting DDR4 devices.
* 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
*/
#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT)) & DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK)
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK (0x20000000U)
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT (29U)
/*! zq_resistor_shared - ZQ resistor sharing
* 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
* 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
* sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
* commands to different ranks do not overlap.
*/
#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT)) & DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK)
#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK (0x40000000U)
#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT (30U)
/*! dis_srx_zqcl - Disable ZQCL/MPC
* 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
* when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
* DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
* 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
* when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
*/
#define DDRC_ZQCTL0_DIS_SRX_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT)) & DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK)
#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK (0x80000000U)
#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT (31U)
/*! dis_auto_zq - Disable Auto ZQCS/MPC
* 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
* 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
* instead to issue ZQ calibration request from APB module.
*/
#define DDRC_ZQCTL0_DIS_AUTO_ZQ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT)) & DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK)
/*! @} */
/*! @name ZQCTL1 - ZQ Control Register 1 */
/*! @{ */
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFU)
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U)
/*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ
* calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
* Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs
* supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT)) & DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK)
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK (0x3FF00000U)
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT (20U)
/*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ
* calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency
* ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only
* present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL1_T_ZQ_RESET_NOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT)) & DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK)
/*! @} */
/*! @name ZQCTL2 - ZQ Control Register 2 */
/*! @{ */
#define DDRC_ZQCTL2_ZQ_RESET_MASK (0x1U)
#define DDRC_ZQCTL2_ZQ_RESET_SHIFT (0U)
/*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset
* operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this
* signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down
* operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL2_ZQ_RESET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_ZQ_RESET_SHIFT)) & DDRC_ZQCTL2_ZQ_RESET_MASK)
/*! @} */
/*! @name ZQSTAT - ZQ Status Register */
/*! @{ */
#define DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK (0x1U)
#define DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT (0U)
/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
* signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
* Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
* not to perform ZQ Reset commands when this signal is high.
* 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
* 0b1..Indicates that ZQ Reset operation is in progress
*/
#define DDRC_ZQSTAT_ZQ_RESET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_ZQ_RESET_BUSY_SHIFT)) & DDRC_ZQSTAT_ZQ_RESET_BUSY_MASK)
/*! @} */
/*! @name DFITMG0 - DFI Timing Register 0 */
/*! @{ */
#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK (0x3FU)
#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT (0U)
/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
* (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
* specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
* necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
* the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
* clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
*/
#define DDRC_DFITMG0_DFI_TPHY_WRLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT)) & DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK)
#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK (0x3F00U)
#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT (8U)
/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
* when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
* DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
* supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
* DFITMG0.dfi_wrdata_use_sdr.
*/
#define DDRC_DFITMG0_DFI_TPHY_WRDATA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT)) & DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK)
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK (0x8000U)
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT (15U)
/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
* HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
* is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
* DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
* HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
* for correct value.
*/
#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK)
#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK (0x7F0000U)
#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT (16U)
/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
* assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
* to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
* may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
* compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
* DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
*/
#define DDRC_DFITMG0_DFI_T_RDDATA_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT)) & DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK)
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK (0x800000U)
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT (23U)
/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
* using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
* DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
* clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
* value.
*/
#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK)
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK (0x1F000000U)
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT (24U)
/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
* of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
* assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
* parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
* is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
* of DFI clock.
*/
#define DDRC_DFITMG0_DFI_T_CTRL_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT)) & DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK)
/*! @} */
/*! @name DFITMG1 - DFI Timing Register 1 */
/*! @{ */
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK (0x1FU)
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)
/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
* dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
* DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
* phase aligned, this timing parameter should be rounded up to the next integer value.
*/
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT)) & DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK)
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0x1F00U)
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)
/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
* dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
* boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
* this timing parameter should be rounded up to the next integer value.
*/
#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT)) & DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK)
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK (0x1F0000U)
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT (16U)
/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
* signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
* This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
* correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
* 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
* programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
* and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
* Clocks
*/
#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT)) & DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK)
#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK (0x3000000U)
#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT (24U)
/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
* asserted and when the associated dfi_parity_in signal is driven.
*/
#define DDRC_DFITMG1_DFI_T_PARIN_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT)) & DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK)
#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK (0xF0000000U)
#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT (28U)
/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
* asserted and when the associated command is driven. This field is used for CAL mode, should be
* set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
* can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
*/
#define DDRC_DFITMG1_DFI_T_CMD_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT)) & DDRC_DFITMG1_DFI_T_CMD_LAT_MASK)
/*! @} */
/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
/*! @{ */
#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK (0x1U)
#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT (0U)
/*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
*/
#define DDRC_DFILPCFG0_DFI_LP_EN_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK (0xF0U)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT (4U)
/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
* mode is entered. Determines the DFI's tlp_wakeup time:
* 0b0000..16 cycles
* 0b0001..32 cycles
* 0b0010..64 cycles
* 0b0011..128 cycles
* 0b0100..256 cycles
* 0b0101..512 cycles
* 0b0110..1024 cycles
* 0b0111..2048 cycles
* 0b1000..4096 cycles
* 0b1001..8192 cycles
* 0b1010..16384 cycles
* 0b1011..32768 cycles
* 0b1100..65536 cycles
* 0b1101..131072 cycles
* 0b1110..262144 cycles
* 0b1111..Unlimited cycles
*/
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK)
#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK (0x100U)
#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT (8U)
/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
* 0b0..Disabled
* 0b1..Enabled
*/
#define DDRC_DFILPCFG0_DFI_LP_EN_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK (0xF000U)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT (12U)
/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
* mode is entered. Determines the DFI's tlp_wakeup time:
* 0b0000..16 cycles
* 0b0001..32 cycles
* 0b0010..64 cycles
* 0b0011..128 cycles
* 0b0100..256 cycles
* 0b0101..512 cycles
* 0b0110..1024 cycles
* 0b0111..2048 cycles
* 0b1000..4096 cycles
* 0b1001..8192 cycles
* 0b1010..16384 cycles
* 0b1011..32768 cycles
* 0b1100..65536 cycles
* 0b1101..131072 cycles
* 0b1110..262144 cycles
* 0b1111..Unlimited cycles
*/
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK)
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK (0x10000U)
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT (16U)
/*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. -
* 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3
* devices.
*/
#define DDRC_DFILPCFG0_DFI_LP_EN_DPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK (0xF00000U)
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT (20U)
/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
* Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
* supporting mDDR or LPDDR2/LPDDR3 devices.
* 0b0000..16 cycles
* 0b0001..32 cycles
* 0b0010..64 cycles
* 0b0011..128 cycles
* 0b0100..256 cycles
* 0b0101..512 cycles
* 0b0110..1024 cycles
* 0b0111..2048 cycles
* 0b1000..4096 cycles
* 0b1001..8192 cycles
* 0b1010..16384 cycles
* 0b1011..32768 cycles
* 0b1100..65536 cycles
* 0b1101..131072 cycles
* 0b1110..262144 cycles
* 0b1111..Unlimited cycles
*/
#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT)) & DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK)
#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK (0x1F000000U)
#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT (24U)
/*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both
* Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1
* specification onwards, recommends using a fixed value of 7 always.
*/
#define DDRC_DFILPCFG0_DFI_TLP_RESP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT)) & DDRC_DFILPCFG0_DFI_TLP_RESP_MASK)
/*! @} */
/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
/*! @{ */
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK (0x1U)
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT (0U)
/*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode
* Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4
* devices.
*/
#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT)) & DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK)
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK (0xF0U)
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT (4U)
/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
* Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
* 0b0000..16 cycles
* 0b0001..32 cycles
* 0b0010..64 cycles
* 0b0011..128 cycles
* 0b0100..256 cycles
* 0b0101..512 cycles
* 0b0110..1024 cycles
* 0b0111..2048 cycles
* 0b1000..4096 cycles
* 0b1001..8192 cycles
* 0b1010..16384 cycles
* 0b1011..32768 cycles
* 0b1100..65536 cycles
* 0b1101..131072 cycles
* 0b1110..262144 cycles
* 0b1111..Unlimited cycles
*/
#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT)) & DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK)
/*! @} */
/*! @name DFIUPD0 - DFI Update Register 0 */
/*! @{ */
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK (0x3FFU)
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT (0U)
/*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req
* signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does
* not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest
* value to assign to this variable is 0x3.
*/
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT)) & DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK)
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK (0x3FF0000U)
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT (16U)
/*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req
* signal can assert. Lowest value to assign to this variable is 0x40.
*/
#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT)) & DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK)
#define DDRC_DFIUPD0_CTRLUPD_PRE_SRX_MASK (0x20000000U)
#define DDRC_DFIUPD0_CTRLUPD_PRE_SRX_SHIFT (29U)
/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
* : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
* because no dfi_ctrlupd_req will be issued when SRX.
* 0b0..send ctrlupd after SRX
* 0b1..send ctrlupd before SRX
*/
#define DDRC_DFIUPD0_CTRLUPD_PRE_SRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_CTRLUPD_PRE_SRX_SHIFT)) & DDRC_DFIUPD0_CTRLUPD_PRE_SRX_MASK)
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK (0x40000000U)
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT (30U)
/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
* 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
* 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
*/
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT)) & DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK)
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK (0x80000000U)
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT (31U)
/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
* 0b0..DDRC issues dfi_ctrlupd_req periodically.
* 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
* signal using register reg_ddrc_ctrlupd.
*/
#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT)) & DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK)
/*! @} */
/*! @name DFIUPD1 - DFI Update Register 1 */
/*! @{ */
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU)
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U)
/*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI
* update requests. This timer resets with each update request; when the timer expires
* dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
* idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used
* to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain
* calibration over PVT, but frequent updates may impact performance. Minimum allowed value for
* this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be
* greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles
*/
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT)) & DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK)
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000U)
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U)
/*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI
* update requests (which is executed whenever the DDRC is idle). Set this number higher to
* reduce the frequency of update requests, which can have a small impact on the latency of the first
* read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI
* clock cycles
*/
#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT)) & DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK)
/*! @} */
/*! @name DFIUPD2 - DFI Update Register 2 */
/*! @{ */
#define DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK (0x80000000U)
#define DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT (31U)
/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
* 0b0..Disabled
* 0b1..Enabled
*/
#define DDRC_DFIUPD2_DFI_PHYUPD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_DFI_PHYUPD_EN_SHIFT)) & DDRC_DFIUPD2_DFI_PHYUPD_EN_MASK)
/*! @} */
/*! @name DFIMISC - DFI Miscellaneous Control Register */
/*! @{ */
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK (0x1U)
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT (0U)
/*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the
* dfi_init_complete signal can be used to trigger SDRAM initialisation
*/
#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT)) & DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK)
#define DDRC_DFIMISC_PHY_DBI_MODE_MASK (0x2U)
#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT (1U)
/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
* 0b0..DDRC implements DBI functionality.
* 0b1..PHY implements DBI functionality.
*/
#define DDRC_DFIMISC_PHY_DBI_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT)) & DDRC_DFIMISC_PHY_DBI_MODE_MASK)
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK (0x4U)
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT (2U)
/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
* 0b0..Signals are active low
* 0b1..Signals are active high
*/
#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT)) & DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK)
#define DDRC_DFIMISC_CTL_IDLE_EN_MASK (0x10U)
#define DDRC_DFIMISC_CTL_IDLE_EN_SHIFT (4U)
/*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to
* certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle
* functionality.
*/
#define DDRC_DFIMISC_CTL_IDLE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_CTL_IDLE_EN_SHIFT)) & DDRC_DFIMISC_CTL_IDLE_EN_MASK)
#define DDRC_DFIMISC_DFI_INIT_START_MASK (0x20U)
#define DDRC_DFIMISC_DFI_INIT_START_SHIFT (5U)
/*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request
*/
#define DDRC_DFIMISC_DFI_INIT_START(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_INIT_START_SHIFT)) & DDRC_DFIMISC_DFI_INIT_START_MASK)
#define DDRC_DFIMISC_DFI_FREQUENCY_MASK (0x1F00U)
#define DDRC_DFIMISC_DFI_FREQUENCY_SHIFT (8U)
/*! dfi_frequency - Indicates the operating frequency of the system. The number of supported
* frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
*/
#define DDRC_DFIMISC_DFI_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_DFI_FREQUENCY_SHIFT)) & DDRC_DFIMISC_DFI_FREQUENCY_MASK)
/*! @} */
/*! @name DFITMG2 - DFI Timing Register 2 */
/*! @{ */
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK (0x3FU)
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT (0U)
/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
* DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
* to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
*/
#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT)) & DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK)
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK (0x7F00U)
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT (8U)
/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
* control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
* to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
*/
#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT)) & DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK)
/*! @} */
/*! @name DFITMG3 - DFI Timing Register 3 */
/*! @{ */
#define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_MASK (0x1FU)
#define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_SHIFT (0U)
/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
* ready to receive commands. Refer to PHY specification for correct value. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
* the next integer value. Unit: Clocks
*/
#define DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_SHIFT)) & DDRC_DFITMG3_DFI_T_GEARDOWN_DELAY_MASK)
/*! @} */
/*! @name DFISTAT - DFI Status Register */
/*! @{ */
#define DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK (0x1U)
#define DDRC_DFISTAT_DFI_INIT_COMPLETE_SHIFT (0U)
/*! dfi_init_complete - The status flag register which announces when the DFI initialization has
* been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete
* flag is polled to know when the initialization is done.
*/
#define DDRC_DFISTAT_DFI_INIT_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_DFI_INIT_COMPLETE_SHIFT)) & DDRC_DFISTAT_DFI_INIT_COMPLETE_MASK)
#define DDRC_DFISTAT_DFI_LP_ACK_MASK (0x2U)
#define DDRC_DFISTAT_DFI_LP_ACK_SHIFT (1U)
/*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller.
*/
#define DDRC_DFISTAT_DFI_LP_ACK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_DFI_LP_ACK_SHIFT)) & DDRC_DFISTAT_DFI_LP_ACK_MASK)
/*! @} */
/*! @name DBICTL - DM/DBI Control Register */
/*! @{ */
#define DDRC_DBICTL_DM_EN_MASK (0x1U)
#define DDRC_DBICTL_DM_EN_SHIFT (0U)
/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
* register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
* must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
* from this signal
* 0b0..DM is disabled
* 0b1..DM is enabled
*/
#define DDRC_DBICTL_DM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_DM_EN_SHIFT)) & DDRC_DBICTL_DM_EN_MASK)
#define DDRC_DBICTL_WR_DBI_EN_MASK (0x2U)
#define DDRC_DBICTL_WR_DBI_EN_SHIFT (1U)
/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
* When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
* 0b0..Write DBI is disabled
* 0b1..Write DBI is enabled.
*/
#define DDRC_DBICTL_WR_DBI_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_WR_DBI_EN_SHIFT)) & DDRC_DBICTL_WR_DBI_EN_MASK)
#define DDRC_DBICTL_RD_DBI_EN_MASK (0x4U)
#define DDRC_DBICTL_RD_DBI_EN_SHIFT (2U)
/*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is
* enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When
* x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
*/
#define DDRC_DBICTL_RD_DBI_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_RD_DBI_EN_SHIFT)) & DDRC_DBICTL_RD_DBI_EN_MASK)
/*! @} */
/*! @name ADDRMAP0 - Address Map Register 0 */
/*! @{ */
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK (0x1FU)
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT (0U)
/*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28,
* and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
* to the value of this field. If set to 31, rank address bit 0 is set to 0.
*/
#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT)) & DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK)
/*! @} */
/*! @name ADDRMAP1 - Address Map Register 1 */
/*! @{ */
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK (0x1FU)
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT (0U)
/*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31
* Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined
* by adding the internal base to the value of this field.
*/
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK)
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK (0x1F00U)
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT (8U)
/*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31
* Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined
* by adding the internal base to the value of this field.
*/
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK)
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK (0x1F0000U)
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT (16U)
/*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30
* and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
* to the value of this field. If set to 31, bank address bit 2 is set to 0.
*/
#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT)) & DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK)
/*! @} */
/*! @name ADDRMAP2 - Address Map Register 2 */
/*! @{ */
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK (0xFU)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT (0U)
/*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7
* Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the
* value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to
* program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and -
* PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and
* ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to
* 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1
* and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus
* Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to
* column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it
* is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If
* MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0
* so that HIF[2] maps to column address bit 3.
*/
#define DDRC_ADDRMAP2_ADDRMAP_COL_B2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK (0xF00U)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT (8U)
/*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7
* Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the
* value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width
* (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0.
*/
#define DDRC_ADDRMAP2_ADDRMAP_COL_B3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK (0xF0000U)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT (16U)
/*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7,
* and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
* to the value of this field. If set to 15, this column address bit is set to 0.
*/
#define DDRC_ADDRMAP2_ADDRMAP_COL_B4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK (0xF000000U)
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT (24U)
/*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7,
* and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, this column address bit is set to 0.
*/
#define DDRC_ADDRMAP2_ADDRMAP_COL_B5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT)) & DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK)
/*! @} */
/*! @name ADDRMAP3 - Address Map Register 3 */
/*! @{ */
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK (0xFU)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT (0U)
/*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7,
* and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
* to the value of this field. If set to 15, this column address bit is set to 0.
*/
#define DDRC_ADDRMAP3_ADDRMAP_COL_B6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK (0xF00U)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT (8U)
/*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7,
* and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base
* to the value of this field. If set to 15, this column address bit is set to 0.
*/
#define DDRC_ADDRMAP3_ADDRMAP_COL_B7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK (0xF0000U)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT (16U)
/*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter
* bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3
* mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined
* by adding the internal base to the value of this field. If set to 15, this column address bit
* is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
* indicating auto-precharge, and hence no source address bit can be mapped to column address
* bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
* column bit 10 is used.
*/
#define DDRC_ADDRMAP3_ADDRMAP_COL_B8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK (0xF000000U)
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT (24U)
/*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
* LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address
* bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
* HIF address bit is determined by adding the internal base to the value of this field. If set to
* 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
* address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
* mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
* auto-precharge in the CA bus and hence column bit 10 is used.
*/
#define DDRC_ADDRMAP3_ADDRMAP_COL_B9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT)) & DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK)
/*! @} */
/*! @name ADDRMAP4 - Address Map Register 4 */
/*! @{ */
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK (0xFU)
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT (0U)
/*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as
* column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it
* unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
* address bit is determined by adding the internal base to the value of this field. If set to
* 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
* address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
* mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge
* in the CA bus and hence column bit 10 is used.
*/
#define DDRC_ADDRMAP4_ADDRMAP_COL_B10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT)) & DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK)
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK (0xF00U)
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT (8U)
/*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit
* 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should
* be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to
* 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by
* adding the internal base to the value of this field. If set to 15, this column address bit is
* set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
* indicating auto-precharge, and hence no source address bit can be mapped to column address bit
* 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column
* bit 10 is used.
*/
#define DDRC_ADDRMAP4_ADDRMAP_COL_B11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT)) & DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK)
/*! @} */
/*! @name ADDRMAP5 - Address Map Register 5 */
/*! @{ */
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK (0xFU)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT (0U)
/*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11
* Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field.
*/
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK (0xF00U)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT (8U)
/*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11
* Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field.
*/
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK (0xF0000U)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT (16U)
/*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range:
* 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for
* row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit
* for each of the row address bits is determined by adding the internal base to the value of this
* field. When value 15 is used the values of row address bits 2 to 10 are defined by registers
* ADDRMAP9, ADDRMAP10, ADDRMAP11.
*/
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK (0xF000000U)
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT (24U)
/*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11,
* and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 11 is set to 0.
*/
#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT)) & DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK)
/*! @} */
/*! @name ADDRMAP6 - Address Map Register 6 */
/*! @{ */
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK (0xFU)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT (0U)
/*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11,
* and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 12 is set to 0.
*/
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK (0xF00U)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT (8U)
/*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11,
* and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 13 is set to 0.
*/
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK (0xF0000U)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT (16U)
/*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11,
* and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 14 is set to 0.
*/
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK (0xF000000U)
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT (24U)
/*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11,
* and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 15 is set to 0.
*/
#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT)) & DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK)
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK (0x80000000U)
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT (31U)
/*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 -
* LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as
* invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs
* configured to support LPDDR3.
*/
#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT)) & DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK)
/*! @} */
/*! @name ADDRMAP7 - Address Map Register 7 */
/*! @{ */
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK (0xFU)
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT (0U)
/*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11,
* and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 16 is set to 0.
*/
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT)) & DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK)
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK (0xF00U)
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT (8U)
/*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11,
* and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal
* base to the value of this field. If set to 15, row address bit 17 is set to 0.
*/
#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT)) & DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK)
/*! @} */
/*! @name ADDRMAP8 - Address Map Register 8 */
/*! @{ */
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK (0x1FU)
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT (0U)
/*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to
* 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is
* determined by adding the internal base to the value of this field.
*/
#define DDRC_ADDRMAP8_ADDRMAP_BG_B0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT)) & DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK)
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK (0x3F00U)
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT (8U)
/*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to
* 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address
* bits is determined by adding the internal base to the value of this field. If set to 63, bank
* group address bit 1 is set to 0.
*/
#define DDRC_ADDRMAP8_ADDRMAP_BG_B1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT)) & DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK)
/*! @} */
/*! @name ADDRMAP9 - Address Map Register 9 */
/*! @{ */
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK (0xFU)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT (0U)
/*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11
* Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK (0xF00U)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT (8U)
/*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11
* Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK (0xF0000U)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT (16U)
/*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11
* Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK (0xF000000U)
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT (24U)
/*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11
* Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT)) & DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK)
/*! @} */
/*! @name ADDRMAP10 - Address Map Register 10 */
/*! @{ */
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK (0xFU)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT (0U)
/*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11
* Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK (0xF00U)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT (8U)
/*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11
* Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK (0xF0000U)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT (16U)
/*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11
* Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK (0xF000000U)
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT (24U)
/*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11
* Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by
* adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT)) & DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK)
/*! @} */
/*! @name ADDRMAP11 - Address Map Register 11 */
/*! @{ */
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK (0xFU)
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT (0U)
/*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11
* Internal Base: 16 The selected HIF address bit for each of the row address bits is determined
* by adding the internal base to the value of this field. This register field is used only when
* ADDRMAP5.addrmap_row_b2_10 is set to value 15.
*/
#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT)) & DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK)
/*! @} */
/*! @name ODTCFG - ODT Configuration Register */
/*! @{ */
#define DDRC_ODTCFG_RD_ODT_DELAY_MASK (0x7CU)
#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT (2U)
/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
* values associated with that command. ODT setting must remain constant for the entire time that
* DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
* (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
* CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
* mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
* preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
* not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_RD_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_RD_ODT_DELAY_MASK)
#define DDRC_ODTCFG_RD_ODT_HOLD_MASK (0xF00U)
#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT (8U)
/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
* is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
* DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
* write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
* RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_RD_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_RD_ODT_HOLD_MASK)
#define DDRC_ODTCFG_WR_ODT_DELAY_MASK (0x1F0000U)
#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT (16U)
/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
* values associated with that command. ODT setting must remain constant for the entire time that
* DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
* AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
* for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
* - WL - 1 - RU(tODTon(max)/tCK))
*/
#define DDRC_ODTCFG_WR_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_WR_ODT_DELAY_MASK)
#define DDRC_ODTCFG_WR_ODT_HOLD_MASK (0xF000000U)
#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT (24U)
/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
* is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
* - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
* 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
* CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_WR_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_WR_ODT_HOLD_MASK)
/*! @} */
/*! @name ODTMAP - ODT/Rank Map Register */
/*! @{ */
#define DDRC_ODTMAP_RANK0_WR_ODT_MASK (0x3U)
#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT (0U)
/*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank
* has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
* Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
* rank, set its bit to 1 to enable its ODT.
*/
#define DDRC_ODTMAP_RANK0_WR_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT)) & DDRC_ODTMAP_RANK0_WR_ODT_MASK)
#define DDRC_ODTMAP_RANK0_RD_ODT_MASK (0x30U)
#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT (4U)
/*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each
* rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
* Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
* rank, set its bit to 1 to enable its ODT.
*/
#define DDRC_ODTMAP_RANK0_RD_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT)) & DDRC_ODTMAP_RANK0_RD_ODT_MASK)
#define DDRC_ODTMAP_RANK1_WR_ODT_MASK (0x300U)
#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT (8U)
/*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank
* has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
* Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
* rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
*/
#define DDRC_ODTMAP_RANK1_WR_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT)) & DDRC_ODTMAP_RANK1_WR_ODT_MASK)
#define DDRC_ODTMAP_RANK1_RD_ODT_MASK (0x3000U)
#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT (12U)
/*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each
* rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
* Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
* rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more
* ranks
*/
#define DDRC_ODTMAP_RANK1_RD_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT)) & DDRC_ODTMAP_RANK1_RD_ODT_MASK)
/*! @} */
/*! @name SCHED - Scheduler Control Register */
/*! @{ */
#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK (0x1U)
#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT (0U)
/*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced
* to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read
* commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all
* Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands.
* Forcing the incoming transactions to low priority implicitly turns off Bypass path for read
* commands. FOR PERFORMANCE ONLY.
*/
#define DDRC_SCHED_FORCE_LOW_PRI_N(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT)) & DDRC_SCHED_FORCE_LOW_PRI_N_MASK)
#define DDRC_SCHED_PREFER_WRITE_MASK (0x2U)
#define DDRC_SCHED_PREFER_WRITE_SHIFT (1U)
/*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
*/
#define DDRC_SCHED_PREFER_WRITE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_PREFER_WRITE_SHIFT)) & DDRC_SCHED_PREFER_WRITE_MASK)
#define DDRC_SCHED_PAGECLOSE_MASK (0x4U)
#define DDRC_SCHED_PAGECLOSE_SHIFT (2U)
/*! pageclose - If true, bank is kept open only while there are page hit transactions available in
* the CAM to that bank. The last read or write command in the CAM with a bank and page hit will
* be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and
* SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued
* in some cases where there is a mode switch between Write and Read or between LPR and HPR. The
* Read and Write commands that are executed as part of the ECC scrub requests are also executed
* without auto-precharge. If false, the bank remains open until there is a need to close it (to
* open a different page, or for page timeout or refresh timeout) - also known as open page
* policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF
* interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page
* policies. FOR PERFORMANCE ONLY.
*/
#define DDRC_SCHED_PAGECLOSE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_PAGECLOSE_SHIFT)) & DDRC_SCHED_PAGECLOSE_MASK)
#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK (0x1F00U)
#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT (8U)
/*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1.
* (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high
* priority transaction store. Setting this to maximum value allocates all entries to low
* priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and
* the rest to high priority transaction store. Note: In ECC configurations, the numbers of
* write and low priority read credits issued is one less than in the non-ECC case. One entry each is
* reserved in the write and low-priority read CAMs for storing the RMW requests arising out of
* single bit error correction RMW operation.
*/
#define DDRC_SCHED_LPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT)) & DDRC_SCHED_LPR_NUM_ENTRIES_MASK)
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK (0xFF0000U)
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT (16U)
/*! go2critical_hysteresis - UNUSED
*/
#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT)) & DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK)
#define DDRC_SCHED_RDWR_IDLE_GAP_MASK (0x7F000000U)
#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT (24U)
/*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles,
* switch to the alternate transaction store if it is non-empty. The read transaction store (both high
* and low priority) is the default preferred transaction store and the write transaction store
* is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal
* value for this register. When set to 0x0, the transaction store switching will happen
* immediately when the switching conditions become true. FOR PERFORMANCE ONLY
*/
#define DDRC_SCHED_RDWR_IDLE_GAP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT)) & DDRC_SCHED_RDWR_IDLE_GAP_MASK)
/*! @} */
/*! @name SCHED1 - Scheduler Control Register 1 */
/*! @{ */
#define DDRC_SCHED1_PAGECLOSE_TIMER_MASK (0xFFU)
#define DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT (0U)
/*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if
* SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be
* scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes
* an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for
* details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an
* auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit.
* Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per
* bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page
* hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a
* page hit. Once the timer has reached zero, an explcit precharge will be attempted to be
* scheduled.
*/
#define DDRC_SCHED1_PAGECLOSE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_PAGECLOSE_TIMER_SHIFT)) & DDRC_SCHED1_PAGECLOSE_TIMER_MASK)
/*! @} */
/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
/*! @{ */
#define DDRC_PERFHPR1_HPR_MAX_STARVE_MASK (0xFFFFU)
#define DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT (0U)
/*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical.
* The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
* disable the starvation functionality; during normal operation, this function should not be disabled
* as it will cause excessive latencies. FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFHPR1_HPR_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_HPR_MAX_STARVE_SHIFT)) & DDRC_PERFHPR1_HPR_MAX_STARVE_MASK)
#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK (0xFF000000U)
#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT (24U)
/*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical
* is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
* Transaction. FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK)
/*! @} */
/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
/*! @{ */
#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK (0xFFFFU)
#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT (0U)
/*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical.
* The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
* disable the starvation functionality; during normal operation, this function should not be disabled
* as it will cause excessive latencies. FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFLPR1_LPR_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT)) & DDRC_PERFLPR1_LPR_MAX_STARVE_MASK)
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK (0xFF000000U)
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT (24U)
/*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical
* is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
* Transaction. FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK)
/*! @} */
/*! @name PERFWR1 - Write CAM Register 1 */
/*! @{ */
#define DDRC_PERFWR1_W_MAX_STARVE_MASK (0xFFFFU)
#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT (0U)
/*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical.
* The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable
* the starvation functionality; during normal operation, this function should not be disabled as
* it will cause excessive latencies. FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFWR1_W_MAX_STARVE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_W_MAX_STARVE_SHIFT)) & DDRC_PERFWR1_W_MAX_STARVE_MASK)
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK (0xFF000000U)
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT (24U)
/*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is
* the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction.
* FOR PERFORMANCE ONLY.
*/
#define DDRC_PERFWR1_W_XACT_RUN_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT)) & DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK)
/*! @} */
/*! @name DBG0 - Debug Register 0 */
/*! @{ */
#define DDRC_DBG0_DIS_WC_MASK (0x1U)
#define DDRC_DBG0_DIS_WC_SHIFT (0U)
/*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY
*/
#define DDRC_DBG0_DIS_WC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_WC_SHIFT)) & DDRC_DBG0_DIS_WC_MASK)
#define DDRC_DBG0_DIS_RD_BYPASS_MASK (0x2U)
#define DDRC_DBG0_DIS_RD_BYPASS_SHIFT (1U)
/*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for
* high priority read page hits FOR DEBUG ONLY.
*/
#define DDRC_DBG0_DIS_RD_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_RD_BYPASS_SHIFT)) & DDRC_DBG0_DIS_RD_BYPASS_MASK)
#define DDRC_DBG0_DIS_ACT_BYPASS_MASK (0x4U)
#define DDRC_DBG0_DIS_ACT_BYPASS_SHIFT (2U)
/*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path
* for high priority read activates FOR DEBUG ONLY.
*/
#define DDRC_DBG0_DIS_ACT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_ACT_BYPASS_SHIFT)) & DDRC_DBG0_DIS_ACT_BYPASS_MASK)
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK (0x10U)
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT (4U)
/*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed
* command in a collision case. Collision cases are write followed by read to same address, read
* followed by write to same address, or write followed by write to same address with DBG0.dis_wc
* bit = 1 (where same address comparisons exclude the two address bits representing critical
* word). FOR DEBUG ONLY.
*/
#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT)) & DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK)
/*! @} */
/*! @name DBG1 - Debug Register 1 */
/*! @{ */
#define DDRC_DBG1_DIS_DQ_MASK (0x1U)
#define DDRC_DBG1_DIS_DQ_SHIFT (0U)
/*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled.
* All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this
* is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which
* makes it safe to modify certain register fields associated with reads and writes (see User
* Guide for details). After setting this bit, it is strongly recommended to poll
* DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which
* affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit
* is intended to be switched on-the-fly.
*/
#define DDRC_DBG1_DIS_DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_DIS_DQ_SHIFT)) & DDRC_DBG1_DIS_DQ_MASK)
#define DDRC_DBG1_DIS_HIF_MASK (0x2U)
#define DDRC_DBG1_DIS_HIF_SHIFT (1U)
/*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the
* hif_cmd_valid and all other associated request signals. This bit is intended to be switched
* on-the-fly.
*/
#define DDRC_DBG1_DIS_HIF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_DIS_HIF_SHIFT)) & DDRC_DBG1_DIS_HIF_MASK)
/*! @} */
/*! @name DBGCAM - CAM Debug Register */
/*! @{ */
#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK (0x3FU)
#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT (0U)
/*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_HPR_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_HPR_Q_DEPTH_MASK)
#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK (0x3F00U)
#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT (8U)
/*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC
* SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG
* ONLY
*/
#define DDRC_DBGCAM_DBG_LPR_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_LPR_Q_DEPTH_MASK)
#define DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK (0x3F0000U)
#define DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT (16U)
/*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB
* operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_W_Q_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_W_Q_DEPTH_SHIFT)) & DDRC_DBGCAM_DBG_W_Q_DEPTH_MASK)
#define DDRC_DBGCAM_DBG_STALL_MASK (0x1000000U)
#define DDRC_DBGCAM_DBG_STALL_SHIFT (24U)
/*! dbg_stall - Stall FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_STALL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_SHIFT)) & DDRC_DBGCAM_DBG_STALL_MASK)
#define DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK (0x2000000U)
#define DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT (25U)
/*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are
* empty. This register is to be used for debug purpose. An example use-case scenario: When Controller
* enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
* executed all the commands in its queues and the write and read data drained. Hence this register
* should be 1 at that time. FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_RD_Q_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_RD_Q_EMPTY_SHIFT)) & DDRC_DBGCAM_DBG_RD_Q_EMPTY_MASK)
#define DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK (0x4000000U)
#define DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT (26U)
/*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are
* empty. This register is to be used for debug purpose. An example use-case scenario: When
* Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
* executed all the commands in its queues and the write and read data drained. Hence this register
* should be 1 at that time. FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_WR_Q_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_WR_Q_EMPTY_SHIFT)) & DDRC_DBGCAM_DBG_WR_Q_EMPTY_MASK)
#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK (0x10000000U)
#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U)
/*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is
* empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
* ensure that all remaining commands/data have completed.
*/
#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT)) & DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK)
#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK (0x20000000U)
#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U)
/*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is
* empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
* ensure that all remaining commands/data have completed.
*/
#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT)) & DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK)
#define DDRC_DBGCAM_DBG_STALL_WR_MASK (0x40000000U)
#define DDRC_DBGCAM_DBG_STALL_WR_SHIFT (30U)
/*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_STALL_WR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_WR_SHIFT)) & DDRC_DBGCAM_DBG_STALL_WR_MASK)
#define DDRC_DBGCAM_DBG_STALL_RD_MASK (0x80000000U)
#define DDRC_DBGCAM_DBG_STALL_RD_SHIFT (31U)
/*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY
*/
#define DDRC_DBGCAM_DBG_STALL_RD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_DBG_STALL_RD_SHIFT)) & DDRC_DBGCAM_DBG_STALL_RD_MASK)
/*! @} */
/*! @name DBGCMD - Command Debug Register */
/*! @{ */
#define DDRC_DBGCMD_RANK0_REFRESH_MASK (0x1U)
#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT (0U)
/*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
* 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When
* DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
* to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
* recommended NOT to set this register bit if in Init or Deep power-down operating modes or
* Maximum Power Saving Mode.
*/
#define DDRC_DBGCMD_RANK0_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_RANK0_REFRESH_SHIFT)) & DDRC_DBGCMD_RANK0_REFRESH_MASK)
#define DDRC_DBGCMD_RANK1_REFRESH_MASK (0x2U)
#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT (1U)
/*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
* 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When
* DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
* to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
* recommended NOT to set this register bit if in Init or Deep power-down operating modes or
* Maximum Power Saving Mode.
*/
#define DDRC_DBGCMD_RANK1_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_RANK1_REFRESH_SHIFT)) & DDRC_DBGCMD_RANK1_REFRESH_MASK)
#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK (0x10U)
#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT (4U)
/*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ
* calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the
* DDRC, the bit is automatically cleared. This operation can be performed only when
* ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register
* bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep
* power-down operating modes and Maximum Power Saving Mode.
*/
#define DDRC_DBGCMD_ZQ_CALIB_SHORT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT)) & DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK)
#define DDRC_DBGCMD_CTRLUPD_MASK (0x20U)
#define DDRC_DBGCMD_CTRLUPD_SHIFT (5U)
/*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the
* PHY. When this request is stored in the DDRC, the bit is automatically cleared. This
* operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
*/
#define DDRC_DBGCMD_CTRLUPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_CTRLUPD_SHIFT)) & DDRC_DBGCMD_CTRLUPD_MASK)
/*! @} */
/*! @name DBGSTAT - Status Debug Register */
/*! @{ */
#define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK (0x1U)
#define DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT (0U)
/*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank
* 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh
* is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is
* recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that
* the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh
* operation has not been stored yet in the DDRC
*/
#define DDRC_DBGSTAT_RANK0_REFRESH_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT)) & DDRC_DBGSTAT_RANK0_REFRESH_BUSY_MASK)
#define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK (0x2U)
#define DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT (1U)
/*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank
* 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh
* is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is
* recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that
* the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh
* operation has not been stored yet in the DDRC
*/
#define DDRC_DBGSTAT_RANK1_REFRESH_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT)) & DDRC_DBGSTAT_RANK1_REFRESH_BUSY_MASK)
#define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK (0x10U)
#define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT (4U)
/*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this
* signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It
* goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform
* ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS
* operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
*/
#define DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT)) & DDRC_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK)
#define DDRC_DBGSTAT_CTRLUPD_BUSY_MASK (0x20U)
#define DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT (5U)
/*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal
* goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the
* ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations
* when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1
* - Indicates that ctrlupd operation has not been initiated yet in the DDRC
*/
#define DDRC_DBGSTAT_CTRLUPD_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_CTRLUPD_BUSY_SHIFT)) & DDRC_DBGSTAT_CTRLUPD_BUSY_MASK)
/*! @} */
/*! @name SWCTL - Software Register Programming Control Enable */
/*! @{ */
#define DDRC_SWCTL_SW_DONE_MASK (0x1U)
#define DDRC_SWCTL_SW_DONE_SHIFT (0U)
/*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to
* enable quasi-dynamic programming. Set back register to 1 once programming is done.
*/
#define DDRC_SWCTL_SW_DONE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_SW_DONE_SHIFT)) & DDRC_SWCTL_SW_DONE_MASK)
/*! @} */
/*! @name SWSTAT - Software Register Programming Control Status */
/*! @{ */
#define DDRC_SWSTAT_SW_DONE_ACK_MASK (0x1U)
#define DDRC_SWSTAT_SW_DONE_ACK_SHIFT (0U)
/*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for
* sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure
* that the correct registers values are propagated to the destination clock domains.
*/
#define DDRC_SWSTAT_SW_DONE_ACK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_SW_DONE_ACK_SHIFT)) & DDRC_SWSTAT_SW_DONE_ACK_MASK)
/*! @} */
/*! @name POISONCFG - AXI Poison Configuration Register. */
/*! @{ */
#define DDRC_POISONCFG_WR_POISON_SLVERR_EN_MASK (0x1U)
#define DDRC_POISONCFG_WR_POISON_SLVERR_EN_SHIFT (0U)
/*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning
*/
#define DDRC_POISONCFG_WR_POISON_SLVERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_SLVERR_EN_SHIFT)) & DDRC_POISONCFG_WR_POISON_SLVERR_EN_MASK)
#define DDRC_POISONCFG_WR_POISON_INTR_EN_MASK (0x10U)
#define DDRC_POISONCFG_WR_POISON_INTR_EN_SHIFT (4U)
/*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning
*/
#define DDRC_POISONCFG_WR_POISON_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_INTR_EN_SHIFT)) & DDRC_POISONCFG_WR_POISON_INTR_EN_MASK)
#define DDRC_POISONCFG_WR_POISON_INTR_CLR_MASK (0x100U)
#define DDRC_POISONCFG_WR_POISON_INTR_CLR_SHIFT (8U)
/*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for
* correct value to propagate to core logic and clear the interrupts.
*/
#define DDRC_POISONCFG_WR_POISON_INTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_WR_POISON_INTR_CLR_SHIFT)) & DDRC_POISONCFG_WR_POISON_INTR_CLR_MASK)
#define DDRC_POISONCFG_RD_POISON_SLVERR_EN_MASK (0x10000U)
#define DDRC_POISONCFG_RD_POISON_SLVERR_EN_SHIFT (16U)
/*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning
*/
#define DDRC_POISONCFG_RD_POISON_SLVERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_SLVERR_EN_SHIFT)) & DDRC_POISONCFG_RD_POISON_SLVERR_EN_MASK)
#define DDRC_POISONCFG_RD_POISON_INTR_EN_MASK (0x100000U)
#define DDRC_POISONCFG_RD_POISON_INTR_EN_SHIFT (20U)
/*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning
*/
#define DDRC_POISONCFG_RD_POISON_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_INTR_EN_SHIFT)) & DDRC_POISONCFG_RD_POISON_INTR_EN_MASK)
#define DDRC_POISONCFG_RD_POISON_INTR_CLR_MASK (0x1000000U)
#define DDRC_POISONCFG_RD_POISON_INTR_CLR_SHIFT (24U)
/*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for
* correct value to propagate to core logic and clear the interrupts.
*/
#define DDRC_POISONCFG_RD_POISON_INTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_RD_POISON_INTR_CLR_SHIFT)) & DDRC_POISONCFG_RD_POISON_INTR_CLR_MASK)
/*! @} */
/*! @name POISONSTAT - AXI Poison Status Register */
/*! @{ */
#define DDRC_POISONSTAT_WR_POISON_INTR_0_MASK (0x1U)
#define DDRC_POISONSTAT_WR_POISON_INTR_0_SHIFT (0U)
/*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a
* APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
* poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and
* so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
* clock.
*/
#define DDRC_POISONSTAT_WR_POISON_INTR_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_WR_POISON_INTR_0_SHIFT)) & DDRC_POISONSTAT_WR_POISON_INTR_0_MASK)
#define DDRC_POISONSTAT_RD_POISON_INTR_0_MASK (0x10000U)
#define DDRC_POISONSTAT_RD_POISON_INTR_0_SHIFT (16U)
/*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB
* clock copy (double register synchronizer) of the interrupt asserted when a transaction is
* poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and
* so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock.
*/
#define DDRC_POISONSTAT_RD_POISON_INTR_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_RD_POISON_INTR_0_SHIFT)) & DDRC_POISONSTAT_RD_POISON_INTR_0_MASK)
/*! @} */
/*! @name PSTAT - Port Status Register */
/*! @{ */
#define DDRC_PSTAT_RD_PORT_BUSY_0_MASK (0x1U)
#define DDRC_PSTAT_RD_PORT_BUSY_0_SHIFT (0U)
/*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0.
*/
#define DDRC_PSTAT_RD_PORT_BUSY_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_RD_PORT_BUSY_0_SHIFT)) & DDRC_PSTAT_RD_PORT_BUSY_0_MASK)
#define DDRC_PSTAT_WR_PORT_BUSY_0_MASK (0x10000U)
#define DDRC_PSTAT_WR_PORT_BUSY_0_SHIFT (16U)
/*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0.
*/
#define DDRC_PSTAT_WR_PORT_BUSY_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_WR_PORT_BUSY_0_SHIFT)) & DDRC_PSTAT_WR_PORT_BUSY_0_MASK)
/*! @} */
/*! @name PCCFG - Port Common Configuration Register */
/*! @{ */
#define DDRC_PCCFG_GO2CRITICAL_EN_MASK (0x1U)
#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT (0U)
/*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and
* co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from
* AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
* co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
*/
#define DDRC_PCCFG_GO2CRITICAL_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT)) & DDRC_PCCFG_GO2CRITICAL_EN_MASK)
#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK (0x10U)
#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT (4U)
/*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page
* DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is
* enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC
* transactions.
*/
#define DDRC_PCCFG_PAGEMATCH_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT)) & DDRC_PCCFG_PAGEMATCH_LIMIT_MASK)
#define DDRC_PCCFG_BL_EXP_MODE_MASK (0x100U)
#define DDRC_PCCFG_BL_EXP_MODE_SHIFT (8U)
/*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every
* AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then
* XPI will use half of the memory burst length as a unit. This applies to both reads and
* writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in
* cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l
* penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if
* DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the
* following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
* MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
* MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or
* CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel
* Interleave is enabled
*/
#define DDRC_PCCFG_BL_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_BL_EXP_MODE_SHIFT)) & DDRC_PCCFG_BL_EXP_MODE_MASK)
/*! @} */
/*! @name PCFGR_0 - Port n Configuration Read Register */
/*! @{ */
#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK (0x3FFU)
#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT (0U)
/*! rd_port_priority - Determines the initial load value of read aging counters. These counters will
* be parallel loaded after reset, or after each grant to the corresponding port. The aging
* counters down-count every clock cycle where the port is requesting but not granted. The higher
* significant 5-bits of the read aging counter sets the priority of the read channel of a given
* port. Port's priority will increase as the higher significant 5-bits of the counter starts to
* decrease. When the aging counter becomes 0, the corresponding port channel will have the highest
* priority level (timeout condition - Priority0). For multi-port configurations, the aging
* counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are
* enabled (timeout is still applicable). For single port configurations, the aging counters are
* only used when they timeout (become 0) to force read-write direction switching. In this case,
* external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read
* priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by
* command basis. Note: The two LSBs of this register field are tied internally to 2'b00.
*/
#define DDRC_PCFGR_0_RD_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT)) & DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK)
#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK (0x1000U)
#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT (12U)
/*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port.
*/
#define DDRC_PCFGR_0_RD_PORT_AGING_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK)
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK (0x2000U)
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT (13U)
/*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled
* and arurgent is asserted by the master, that port becomes the highest priority and
* co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in
* PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is
* independent of address handshaking (it is not associated with any particular command).
*/
#define DDRC_PCFGR_0_RD_PORT_URGENT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK)
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK (0x4000U)
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT (14U)
/*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
* requesting port is granted, the port is continued to be granted if the following immediate commands are
* to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
* register.
*/
#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT)) & DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK)
#define DDRC_PCFGR_0_RDWR_ORDERED_EN_MASK (0x10000U)
#define DDRC_PCFGR_0_RDWR_ORDERED_EN_SHIFT (16U)
/*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read
* transaction and write transaction issued to the same address, on a given port. In other words,
* the controller ensures that all same address read and write commands from the application port
* interface are transported to the DFI interface in the order of acceptance. This feature is
* useful in cases where software coherency is desired for masters issuing back-to-back read/write
* transactions without waiting for write/read responses. Note that this register has an effect
* only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter.
*/
#define DDRC_PCFGR_0_RDWR_ORDERED_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_RDWR_ORDERED_EN_SHIFT)) & DDRC_PCFGR_0_RDWR_ORDERED_EN_MASK)
/*! @} */
/*! @name PCFGW_0 - Port n Configuration Write Register */
/*! @{ */
#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK (0x3FFU)
#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT (0U)
/*! wr_port_priority - Determines the initial load value of write aging counters. These counters
* will be parallel loaded after reset, or after each grant to the corresponding port. The aging
* counters down-count every clock cycle where the port is requesting but not granted. The higher
* significant 5-bits of the write aging counter sets the initial priority of the write channel of
* a given port. Port's priority will increase as the higher significant 5-bits of the counter
* starts to decrease. When the aging counter becomes 0, the corresponding port channel will have
* the highest priority level. For multi-port configurations, the aging counters cannot be used to
* set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is
* still applicable). For single port configurations, the aging counters are only used when they
* timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register
* field are tied internally to 2'b00.
*/
#define DDRC_PCFGW_0_WR_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT)) & DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK)
#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK (0x1000U)
#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT (12U)
/*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port.
*/
#define DDRC_PCFGW_0_WR_PORT_AGING_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK)
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK (0x2000U)
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT (13U)
/*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled
* and awurgent is asserted by the master, that port becomes the highest priority and
* co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that
* awurgent signal can be asserted anytime and as long as required which is independent of address
* handshaking (it is not associated with any particular command).
*/
#define DDRC_PCFGW_0_WR_PORT_URGENT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK)
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK (0x4000U)
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT (14U)
/*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
* requesting port is granted, the port is continued to be granted if the following immediate commands are
* to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
* register.
*/
#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT)) & DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK)
/*! @} */
/*! @name PCTRL_0 - Port n Control Register */
/*! @{ */
#define DDRC_PCTRL_0_PORT_EN_MASK (0x1U)
#define DDRC_PCTRL_0_PORT_EN_SHIFT (0U)
/*! port_en - Enables AXI port n.
*/
#define DDRC_PCTRL_0_PORT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_PORT_EN_SHIFT)) & DDRC_PCTRL_0_PORT_EN_MASK)
/*! @} */
/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
/*! @{ */
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK (0xFU)
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT (0U)
/*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is
* 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which
* corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where
* the higher the value corresponds to higher port priority. All of the map_level* registers must
* be set to distinct values.
*/
#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK)
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK (0x30000U)
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT (16U)
/*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
* LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address
* queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled
* (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
* traffic.
*/
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK)
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK (0x300000U)
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT (20U)
/*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 :
* LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address
* queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled
* (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
* traffic.
*/
#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT)) & DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK)
/*! @} */
/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
/*! @{ */
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK (0x7FFU)
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT (0U)
/*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue.
*/
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT)) & DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK)
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK (0x7FF0000U)
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT (16U)
/*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue.
*/
#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT)) & DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK)
/*! @} */
/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
/*! @{ */
#define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK (0xFU)
#define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT (0U)
/*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0.
* Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos
* values are used directly as port priorities, where the higher the value corresponds to higher
* port priority.
*/
#define DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_LEVEL_MASK)
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK (0x30000U)
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT (16U)
/*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
* NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set
* to 1 (VPW), VPW traffic is aliased to NPW traffic.
*/
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_REGION0_MASK)
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK (0x300000U)
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT (20U)
/*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0:
* NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is
* set to 1 (VPW), VPW traffic is aliased to LPW traffic.
*/
#define DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_SHIFT)) & DDRC_PCFGWQOS0_0_WQOS_MAP_REGION1_MASK)
/*! @} */
/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
/*! @{ */
#define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK (0x7FFU)
#define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT (0U)
/*! wqos_map_timeout - Specifies the timeout value for write transactions.
*/
#define DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_SHIFT)) & DDRC_PCFGWQOS1_0_WQOS_MAP_TIMEOUT_MASK)
/*! @} */
/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
/*! @{ */
#define DDRC_DERATEEN_SHADOW_DERATE_ENABLE_MASK (0x1U)
#define DDRC_DERATEEN_SHADOW_DERATE_ENABLE_SHIFT (0U)
/*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing
* parameter derating is enabled using MR4 read value. Present only in designs configured to support
* LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
*/
#define DDRC_DERATEEN_SHADOW_DERATE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_ENABLE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_ENABLE_MASK)
#define DDRC_DERATEEN_SHADOW_DERATE_VALUE_MASK (0x2U)
#define DDRC_DERATEEN_SHADOW_DERATE_VALUE_SHIFT (1U)
/*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in
* designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as
* derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of
* core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it
* should be set to 0.
*/
#define DDRC_DERATEEN_SHADOW_DERATE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_VALUE_MASK)
#define DDRC_DERATEEN_SHADOW_DERATE_BYTE_MASK (0xF0U)
#define DDRC_DERATEEN_SHADOW_DERATE_BYTE_SHIFT (4U)
/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
* Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
* MEMC_DRAM_TOTAL_DATA_WIDTH.
*/
#define DDRC_DERATEEN_SHADOW_DERATE_BYTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_DERATE_BYTE_SHIFT)) & DDRC_DERATEEN_SHADOW_DERATE_BYTE_MASK)
#define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_MASK (0x300U)
#define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_SHIFT (8U)
/*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2.
* - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support
* LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by
* the core_ddrc_core_clk period, and rounding up the next integer.
*/
#define DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_SHIFT)) & DDRC_DERATEEN_SHADOW_RC_DERATE_VALUE_MASK)
/*! @} */
/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
/*! @{ */
#define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_MASK (0xFFFFFFFFU)
#define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_SHIFT (0U)
/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
* Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
* zero. Unit: DFI clock cycle.
*/
#define DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_SHIFT)) & DDRC_DERATEINT_SHADOW_MR4_READ_INTERVAL_MASK)
/*! @} */
/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
/*! @{ */
#define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_MASK (0x4U)
#define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_SHIFT (2U)
/*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
* traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should
* be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support
* LPDDR2/LPDDR3/LPDDR4
*/
#define DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_SHIFT)) & DDRC_RFSHCTL0_SHADOW_PER_BANK_REFRESH_MASK)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_MASK (0x1F0U)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_SHIFT (4U)
/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
* accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
* perform a refresh is a one-time penalty that must be paid for each group of refreshes.
* Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
* Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
* the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
* refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
* DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
* per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
* feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
* mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
* must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
* due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
* situation, the refresh burst will be delayed until the PHY-initiated update is complete.
*/
#define DDRC_RFSHCTL0_SHADOW_REFRESH_BURST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_BURST_MASK)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_MASK (0x1F000U)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_SHIFT (12U)
/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
* but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
* performed. A speculative refresh is a refresh performed at a time when refresh would be
* useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
* determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
* the last refresh, then a speculative refresh is performed. Speculative refreshes continues
* successively until there are no refreshes pending or until new reads or writes are issued to the
* DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
*/
#define DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_TO_X32_MASK)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_MASK (0xF00000U)
#define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_SHIFT (20U)
/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
* page timer expires. A critical refresh is to be issued before this threshold is reached. It is
* recommended that this not be changed from the default value, currently shown as 0x2. It must
* always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
* internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
* (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
* RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
*/
#define DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_SHIFT)) & DDRC_RFSHCTL0_SHADOW_REFRESH_MARGIN_MASK)
/*! @} */
/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
/*! @{ */
#define DDRC_RFSHTMG_SHADOW_T_RFC_MIN_MASK (0x3FFU)
#define DDRC_RFSHTMG_SHADOW_T_RFC_MIN_SHIFT (0U)
/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
* operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
* is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
* LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
* is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
* equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
* on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
* appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
* Unit: Clocks.
*/
#define DDRC_RFSHTMG_SHADOW_T_RFC_MIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_T_RFC_MIN_SHIFT)) & DDRC_RFSHTMG_SHADOW_T_RFC_MIN_MASK)
#define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_MASK (0x8000U)
#define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_SHIFT (15U)
/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
* DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
* devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
* parameter not used - 1 - tREFBW parameter used
*/
#define DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_SHIFT)) & DDRC_RFSHTMG_SHADOW_LPDDR3_TREFBW_EN_MASK)
#define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_MASK (0xFFF0000U)
#define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_SHIFT (16U)
/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
* for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
* LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
* should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
* register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
* program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
* on the refresh mode. The user should program the appropriate value from the spec based on the
* value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
* greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
* DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
* 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
* RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
*/
#define DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_SHIFT)) & DDRC_RFSHTMG_SHADOW_T_RFC_NOM_X32_MASK)
/*! @} */
/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
/*! @{ */
#define DDRC_INIT3_SHADOW_EMR_MASK (0xFFFFU)
#define DDRC_INIT3_SHADOW_EMR_SHIFT (0U)
/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
* register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
* register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
* the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
* Value to write to MR2 register
*/
#define DDRC_INIT3_SHADOW_EMR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_EMR_SHIFT)) & DDRC_INIT3_SHADOW_EMR_MASK)
#define DDRC_INIT3_SHADOW_MR_MASK (0xFFFF0000U)
#define DDRC_INIT3_SHADOW_MR_SHIFT (16U)
/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
* DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
* write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
*/
#define DDRC_INIT3_SHADOW_MR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_MR_SHIFT)) & DDRC_INIT3_SHADOW_MR_MASK)
/*! @} */
/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
/*! @{ */
#define DDRC_INIT4_SHADOW_EMR3_MASK (0xFFFFU)
#define DDRC_INIT4_SHADOW_EMR3_SHIFT (0U)
/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
* mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
*/
#define DDRC_INIT4_SHADOW_EMR3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_EMR3_SHIFT)) & DDRC_INIT4_SHADOW_EMR3_MASK)
#define DDRC_INIT4_SHADOW_EMR2_MASK (0xFFFF0000U)
#define DDRC_INIT4_SHADOW_EMR2_SHIFT (16U)
/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
* LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
*/
#define DDRC_INIT4_SHADOW_EMR2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_EMR2_SHIFT)) & DDRC_INIT4_SHADOW_EMR2_MASK)
/*! @} */
/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
/*! @{ */
#define DDRC_INIT6_SHADOW_MR5_MASK (0xFFFFU)
#define DDRC_INIT6_SHADOW_MR5_SHIFT (0U)
/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT6_SHADOW_MR5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_MR5_SHIFT)) & DDRC_INIT6_SHADOW_MR5_MASK)
#define DDRC_INIT6_SHADOW_MR4_MASK (0xFFFF0000U)
#define DDRC_INIT6_SHADOW_MR4_SHIFT (16U)
/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT6_SHADOW_MR4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_MR4_SHIFT)) & DDRC_INIT6_SHADOW_MR4_MASK)
/*! @} */
/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
/*! @{ */
#define DDRC_INIT7_SHADOW_MR6_MASK (0xFFFF0000U)
#define DDRC_INIT7_SHADOW_MR6_SHIFT (16U)
/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
*/
#define DDRC_INIT7_SHADOW_MR6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_MR6_SHIFT)) & DDRC_INIT7_SHADOW_MR6_MASK)
/*! @} */
/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
/*! @{ */
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_MASK (0x3FU)
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_SHIFT (0U)
/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
* controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
* up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
* program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_RAS_MIN_MASK)
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_MASK (0x7F00U)
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_SHIFT (8U)
/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
* maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
* When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
* No rounding up. Unit: Multiples of 1024 clocks.
*/
#define DDRC_DRAMTMG0_SHADOW_T_RAS_MAX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_RAS_MAX_MASK)
#define DDRC_DRAMTMG0_SHADOW_T_FAW_MASK (0x3F0000U)
#define DDRC_DRAMTMG0_SHADOW_T_FAW_SHIFT (16U)
/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
* design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
* is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
* integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
* mode. Unit: Clocks
*/
#define DDRC_DRAMTMG0_SHADOW_T_FAW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_T_FAW_SHIFT)) & DDRC_DRAMTMG0_SHADOW_T_FAW_MASK)
#define DDRC_DRAMTMG0_SHADOW_WR2PRE_MASK (0x7F000000U)
#define DDRC_DRAMTMG0_SHADOW_WR2PRE_SHIFT (24U)
/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
* + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
* frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
* the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
* - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
* cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
* frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
* is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
* and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
* may be necessary to adjust the value of this parameter to compensate for the extra cycle of
* latency through the LRDIMM.
*/
#define DDRC_DRAMTMG0_SHADOW_WR2PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_WR2PRE_SHIFT)) & DDRC_DRAMTMG0_SHADOW_WR2PRE_MASK)
/*! @} */
/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
/*! @{ */
#define DDRC_DRAMTMG1_SHADOW_T_RC_MASK (0x7FU)
#define DDRC_DRAMTMG1_SHADOW_T_RC_SHIFT (0U)
/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
* frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
* Clocks.
*/
#define DDRC_DRAMTMG1_SHADOW_T_RC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_T_RC_SHIFT)) & DDRC_DRAMTMG1_SHADOW_T_RC_MASK)
#define DDRC_DRAMTMG1_SHADOW_RD2PRE_MASK (0x3F00U)
#define DDRC_DRAMTMG1_SHADOW_RD2PRE_SHIFT (8U)
/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
* 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
* or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
* LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
* - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
* use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
* divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
* mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
* Unit: Clocks.
*/
#define DDRC_DRAMTMG1_SHADOW_RD2PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_RD2PRE_SHIFT)) & DDRC_DRAMTMG1_SHADOW_RD2PRE_MASK)
#define DDRC_DRAMTMG1_SHADOW_T_XP_MASK (0x1F0000U)
#define DDRC_DRAMTMG1_SHADOW_T_XP_SHIFT (16U)
/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
* programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
* set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
* this to (tXP/2) and round it up to the next integer value. Units: Clocks
*/
#define DDRC_DRAMTMG1_SHADOW_T_XP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_T_XP_SHIFT)) & DDRC_DRAMTMG1_SHADOW_T_XP_MASK)
/*! @} */
/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
/*! @{ */
#define DDRC_DRAMTMG2_SHADOW_WR2RD_MASK (0x3FU)
#define DDRC_DRAMTMG2_SHADOW_WR2RD_SHIFT (0U)
/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
* write command to read command for same bank group. In others, minimum time from write command to
* read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
* global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
* = burst length. This must match the value programmed in the BL bit of the mode register to
* the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
* directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
* directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
* When the controller is operating in 1:2 mode, divide the value calculated using the above
* equation by 2, and round it up to next integer.
*/
#define DDRC_DRAMTMG2_SHADOW_WR2RD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_WR2RD_SHIFT)) & DDRC_DRAMTMG2_SHADOW_WR2RD_MASK)
#define DDRC_DRAMTMG2_SHADOW_RD2WR_MASK (0x3F00U)
#define DDRC_DRAMTMG2_SHADOW_RD2WR_SHIFT (8U)
/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
* + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
* + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
* RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
* Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
* the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
* WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
* the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
* preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
* LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
* tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
* value calculated using the above equation by 2, and round it up to next integer. Note that,
* depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
* to compensate for the extra cycle of latency through the LRDIMM.
*/
#define DDRC_DRAMTMG2_SHADOW_RD2WR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_RD2WR_SHIFT)) & DDRC_DRAMTMG2_SHADOW_RD2WR_MASK)
#define DDRC_DRAMTMG2_SHADOW_READ_LATENCY_MASK (0x3F0000U)
#define DDRC_DRAMTMG2_SHADOW_READ_LATENCY_SHIFT (16U)
/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
* set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
* the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
* the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
* above equation by 2, and round it up to next integer. This register field is not required for
* DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
* DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
*/
#define DDRC_DRAMTMG2_SHADOW_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_READ_LATENCY_SHIFT)) & DDRC_DRAMTMG2_SHADOW_READ_LATENCY_MASK)
#define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_MASK (0x3F000000U)
#define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_SHIFT (24U)
/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
* set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
* using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
* cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
* mode, divide the value calculated using the above equation by 2, and round it up to next
* integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
* as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
* protocols Unit: clocks
*/
#define DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_SHIFT)) & DDRC_DRAMTMG2_SHADOW_WRITE_LATENCY_MASK)
/*! @} */
/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
/*! @{ */
#define DDRC_DRAMTMG3_SHADOW_T_MOD_MASK (0x3FFU)
#define DDRC_DRAMTMG3_SHADOW_T_MOD_SHIFT (0U)
/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
* following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
* Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
* next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
* RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
* compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
* Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
* is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
* controller is operating in 1:2 frequency ratio mode.
*/
#define DDRC_DRAMTMG3_SHADOW_T_MOD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MOD_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MOD_MASK)
#define DDRC_DRAMTMG3_SHADOW_T_MRD_MASK (0x3F000U)
#define DDRC_DRAMTMG3_SHADOW_T_MRD_SHIFT (12U)
/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
* SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
* command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
* value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
*/
#define DDRC_DRAMTMG3_SHADOW_T_MRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MRD_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MRD_MASK)
#define DDRC_DRAMTMG3_SHADOW_T_MRW_MASK (0x3FF00000U)
#define DDRC_DRAMTMG3_SHADOW_T_MRW_SHIFT (20U)
/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
* configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
* typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
* this register is used for the time from a MRW/MRR to all other commands. When the controller
* is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
* round it up to the next integer value. For LDPDR3, this register is used for the time from a
* MRW/MRR to a MRW/MRR.
*/
#define DDRC_DRAMTMG3_SHADOW_T_MRW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_T_MRW_SHIFT)) & DDRC_DRAMTMG3_SHADOW_T_MRW_MASK)
/*! @} */
/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
/*! @{ */
#define DDRC_DRAMTMG4_SHADOW_T_RP_MASK (0x1FU)
#define DDRC_DRAMTMG4_SHADOW_T_RP_SHIFT (0U)
/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
* operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
* operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
* 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
* to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
*/
#define DDRC_DRAMTMG4_SHADOW_T_RP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RP_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RP_MASK)
#define DDRC_DRAMTMG4_SHADOW_T_RRD_MASK (0xF00U)
#define DDRC_DRAMTMG4_SHADOW_T_RRD_SHIFT (8U)
/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
* group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
* is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
* up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG4_SHADOW_T_RRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RRD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RRD_MASK)
#define DDRC_DRAMTMG4_SHADOW_T_CCD_MASK (0xF0000U)
#define DDRC_DRAMTMG4_SHADOW_T_CCD_SHIFT (16U)
/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
* group. Others: tCCD: This is the minimum time between two reads or two writes. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
* up to the next integer value. Unit: clocks.
*/
#define DDRC_DRAMTMG4_SHADOW_T_CCD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_CCD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_CCD_MASK)
#define DDRC_DRAMTMG4_SHADOW_T_RCD_MASK (0x1F000000U)
#define DDRC_DRAMTMG4_SHADOW_T_RCD_SHIFT (24U)
/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
* controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
* it up to the next integer value. Minimum value allowed for this register is 1, which implies
* minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
* mode. Unit: Clocks.
*/
#define DDRC_DRAMTMG4_SHADOW_T_RCD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_T_RCD_SHIFT)) & DDRC_DRAMTMG4_SHADOW_T_RCD_MASK)
/*! @} */
/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
/*! @{ */
#define DDRC_DRAMTMG5_SHADOW_T_CKE_MASK (0x1FU)
#define DDRC_DRAMTMG5_SHADOW_T_CKE_SHIFT (0U)
/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
* LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
* tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
* the controller is operating in 1:2 frequency ratio mode, program this to (value described
* above)/2 and round it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG5_SHADOW_T_CKE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKE_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKE_MASK)
#define DDRC_DRAMTMG5_SHADOW_T_CKESR_MASK (0x3F00U)
#define DDRC_DRAMTMG5_SHADOW_T_CKESR_SHIFT (8U)
/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
* in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
* - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
* latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
* by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_SHADOW_T_CKESR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKESR_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKESR_MASK)
#define DDRC_DRAMTMG5_SHADOW_T_CKSRE_MASK (0xF0000U)
#define DDRC_DRAMTMG5_SHADOW_T_CKSRE_SHIFT (16U)
/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
* LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
* PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
* be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
* this to recommended value divided by two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_SHADOW_T_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKSRE_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKSRE_MASK)
#define DDRC_DRAMTMG5_SHADOW_T_CKSRX_MASK (0xF000000U)
#define DDRC_DRAMTMG5_SHADOW_T_CKSRX_SHIFT (24U)
/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
* before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
* LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
* controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
* two and round it up to next integer.
*/
#define DDRC_DRAMTMG5_SHADOW_T_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_T_CKSRX_SHIFT)) & DDRC_DRAMTMG5_SHADOW_T_CKSRX_MASK)
/*! @} */
/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
/*! @{ */
#define DDRC_DRAMTMG6_SHADOW_T_CKCSX_MASK (0xFU)
#define DDRC_DRAMTMG6_SHADOW_T_CKCSX_SHIFT (0U)
/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
* issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
* Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
* When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
* divided by two and round it up to next integer. This is only present for designs supporting
* mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG6_SHADOW_T_CKCSX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKCSX_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKCSX_MASK)
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDX_MASK (0xF0000U)
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDX_SHIFT (16U)
/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
* before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
* 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
* program this to recommended value divided by two and round it up to next integer. This is only
* present for designs supporting mDDR or LPDDR2 devices.
*/
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKDPDX_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKDPDX_MASK)
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDE_MASK (0xF000000U)
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDE_SHIFT (24U)
/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
* LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer. This is only present for designs
* supporting mDDR or LPDDR2/LPDDR3 devices.
*/
#define DDRC_DRAMTMG6_SHADOW_T_CKDPDE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_T_CKDPDE_SHIFT)) & DDRC_DRAMTMG6_SHADOW_T_CKDPDE_MASK)
/*! @} */
/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
/*! @{ */
#define DDRC_DRAMTMG7_SHADOW_T_CKPDX_MASK (0xFU)
#define DDRC_DRAMTMG7_SHADOW_T_CKPDX_SHIFT (0U)
/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
* issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
* LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
* same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
* program this to recommended value divided by two and round it up to next integer. This is only
* present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG7_SHADOW_T_CKPDX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_T_CKPDX_SHIFT)) & DDRC_DRAMTMG7_SHADOW_T_CKPDX_MASK)
#define DDRC_DRAMTMG7_SHADOW_T_CKPDE_MASK (0xF00U)
#define DDRC_DRAMTMG7_SHADOW_T_CKPDE_SHIFT (8U)
/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
* Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
* - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
* DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
* to recommended value divided by two and round it up to next integer. This is only present for
* designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_DRAMTMG7_SHADOW_T_CKPDE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_T_CKPDE_SHIFT)) & DDRC_DRAMTMG7_SHADOW_T_CKPDE_MASK)
/*! @} */
/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
/*! @{ */
#define DDRC_DRAMTMG8_SHADOW_T_XS_X32_MASK (0x7FU)
#define DDRC_DRAMTMG8_SHADOW_T_XS_X32_SHIFT (0U)
/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
* operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
* up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
* DDR4 SDRAMs.
*/
#define DDRC_DRAMTMG8_SHADOW_T_XS_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_X32_MASK)
#define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_MASK (0x7F00U)
#define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_SHIFT (8U)
/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
* is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
* round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
* DDR4 SDRAMs.
*/
#define DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_DLL_X32_MASK)
#define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_MASK (0x7F0000U)
#define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_SHIFT (16U)
/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
* Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
* above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
* Note: Ensure this is less than or equal to t_xs_x32.
*/
#define DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_ABORT_X32_MASK)
#define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_MASK (0x7F000000U)
#define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_SHIFT (24U)
/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
* mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
* above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
* This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
* t_xs_x32.
*/
#define DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_T_XS_FAST_X32_MASK)
/*! @} */
/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
/*! @{ */
#define DDRC_DRAMTMG9_SHADOW_WR2RD_S_MASK (0x3FU)
#define DDRC_DRAMTMG9_SHADOW_WR2RD_S_SHIFT (0U)
/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
* bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
* global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
* - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
* programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
* command delay for different bank group. This comes directly from the SDRAM specification. When
* the controller is operating in 1:2 mode, divide the value calculated using the above equation
* by 2, and round it up to next integer.
*/
#define DDRC_DRAMTMG9_SHADOW_WR2RD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_WR2RD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_WR2RD_S_MASK)
#define DDRC_DRAMTMG9_SHADOW_T_RRD_S_MASK (0xF00U)
#define DDRC_DRAMTMG9_SHADOW_T_RRD_S_SHIFT (8U)
/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
* group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
* and round it up to the next integer value. Present only in designs configured to support DDR4.
* Unit: Clocks.
*/
#define DDRC_DRAMTMG9_SHADOW_T_RRD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_T_RRD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_T_RRD_S_MASK)
#define DDRC_DRAMTMG9_SHADOW_T_CCD_S_MASK (0x70000U)
#define DDRC_DRAMTMG9_SHADOW_T_CCD_S_SHIFT (16U)
/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
* group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
* the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
* it up to the next integer value. Present only in designs configured to support DDR4. Unit:
* clocks.
*/
#define DDRC_DRAMTMG9_SHADOW_T_CCD_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_T_CCD_S_SHIFT)) & DDRC_DRAMTMG9_SHADOW_T_CCD_S_MASK)
#define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_MASK (0x40000000U)
#define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_SHIFT (30U)
/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
*/
#define DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_SHIFT)) & DDRC_DRAMTMG9_SHADOW_DDR4_WR_PREAMBLE_MASK)
/*! @} */
/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
/*! @{ */
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_MASK (0x3U)
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_SHIFT (0U)
/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
* DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
* 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
* value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_GEAR_HOLD_MASK)
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_MASK (0xCU)
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_SHIFT (2U)
/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
* DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
* 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
* value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_GEAR_SETUP_MASK)
#define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_MASK (0x1F00U)
#define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_SHIFT (8U)
/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
* defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
* this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
* and round it up to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_CMD_GEAR_MASK)
#define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_MASK (0x1F0000U)
#define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_SHIFT (16U)
/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
* number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
* tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
* When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
* to the next integer value. Unit: Clocks
*/
#define DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_SHIFT)) & DDRC_DRAMTMG10_SHADOW_T_SYNC_GEAR_MASK)
/*! @} */
/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
/*! @{ */
#define DDRC_DRAMTMG11_SHADOW_T_CKMPE_MASK (0x1FU)
#define DDRC_DRAMTMG11_SHADOW_T_CKMPE_SHIFT (0U)
/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
* configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
* mode, divide the value calculated using the above equation by 2, and round it up to next
* integer.
*/
#define DDRC_DRAMTMG11_SHADOW_T_CKMPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_CKMPE_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_CKMPE_MASK)
#define DDRC_DRAMTMG11_SHADOW_T_MPX_S_MASK (0x300U)
#define DDRC_DRAMTMG11_SHADOW_T_MPX_S_SHIFT (8U)
/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
* frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
* Present only in designs configured to support DDR4. Unit: Clocks.
*/
#define DDRC_DRAMTMG11_SHADOW_T_MPX_S(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_MPX_S_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_MPX_S_MASK)
#define DDRC_DRAMTMG11_SHADOW_T_MPX_LH_MASK (0x1F0000U)
#define DDRC_DRAMTMG11_SHADOW_T_MPX_LH_SHIFT (16U)
/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
* controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
* only in designs configured to support DDR4. Unit: clocks.
*/
#define DDRC_DRAMTMG11_SHADOW_T_MPX_LH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_T_MPX_LH_SHIFT)) & DDRC_DRAMTMG11_SHADOW_T_MPX_LH_MASK)
#define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_MASK (0x7F000000U)
#define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_SHIFT (24U)
/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
* When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
* round it up to the next integer value. Present only in designs configured to support DDR4.
* Unit: Multiples of 32 clocks.
*/
#define DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_POST_MPSM_GAP_X32_MASK)
/*! @} */
/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
/*! @{ */
#define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_MASK (0x1FU)
#define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_SHIFT (0U)
/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
* to the next integer value.
*/
#define DDRC_DRAMTMG12_SHADOW_T_MRD_PDA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_MRD_PDA_MASK)
#define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_MASK (0xF00U)
#define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_SHIFT (8U)
/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
* integer value.
*/
#define DDRC_DRAMTMG12_SHADOW_T_CKEHCMD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_CKEHCMD_MASK)
#define DDRC_DRAMTMG12_SHADOW_T_CMDCKE_MASK (0x30000U)
#define DDRC_DRAMTMG12_SHADOW_T_CMDCKE_SHIFT (16U)
/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
* or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
* (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
*/
#define DDRC_DRAMTMG12_SHADOW_T_CMDCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_T_CMDCKE_SHIFT)) & DDRC_DRAMTMG12_SHADOW_T_CMDCKE_MASK)
/*! @} */
/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
/*! @{ */
#define DDRC_DRAMTMG13_SHADOW_T_PPD_MASK (0x7U)
#define DDRC_DRAMTMG13_SHADOW_T_PPD_SHIFT (0U)
/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
* controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
* the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_SHADOW_T_PPD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_T_PPD_SHIFT)) & DDRC_DRAMTMG13_SHADOW_T_PPD_MASK)
#define DDRC_DRAMTMG13_SHADOW_T_CCD_MW_MASK (0x3F0000U)
#define DDRC_DRAMTMG13_SHADOW_T_CCD_MW_SHIFT (16U)
/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
* command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
* this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_SHADOW_T_CCD_MW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_T_CCD_MW_SHIFT)) & DDRC_DRAMTMG13_SHADOW_T_CCD_MW_MASK)
#define DDRC_DRAMTMG13_SHADOW_ODTLOFF_MASK (0x7F000000U)
#define DDRC_DRAMTMG13_SHADOW_ODTLOFF_SHIFT (24U)
/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
* the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
* it up to the next integer value. Unit: Clocks.
*/
#define DDRC_DRAMTMG13_SHADOW_ODTLOFF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_ODTLOFF_SHIFT)) & DDRC_DRAMTMG13_SHADOW_ODTLOFF_MASK)
/*! @} */
/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
/*! @{ */
#define DDRC_DRAMTMG14_SHADOW_T_XSR_MASK (0xFFFU)
#define DDRC_DRAMTMG14_SHADOW_T_XSR_SHIFT (0U)
/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
* frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
* Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
*/
#define DDRC_DRAMTMG14_SHADOW_T_XSR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_T_XSR_SHIFT)) & DDRC_DRAMTMG14_SHADOW_T_XSR_MASK)
/*! @} */
/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
/*! @{ */
#define DDRC_DRAMTMG15_SHADOW_T_STAB_X32_MASK (0xFFU)
#define DDRC_DRAMTMG15_SHADOW_T_STAB_X32_SHIFT (0U)
/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
* RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
* clock must be stable for a time specified by tSTAB - in the case of input clock frequency
* change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
* DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
* recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
* cycles.
*/
#define DDRC_DRAMTMG15_SHADOW_T_STAB_X32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_T_STAB_X32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_T_STAB_X32_MASK)
#define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_MASK (0x80000000U)
#define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_SHIFT (31U)
/*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is
* stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when
* exiting DFI LP
*/
#define DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_SHIFT)) & DDRC_DRAMTMG15_SHADOW_EN_DFI_LP_T_STAB_MASK)
/*! @} */
/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
/*! @{ */
#define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_MASK (0x3FFU)
#define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_SHIFT (0U)
/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
* of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
* When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
* round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
* LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_SHIFT)) & DDRC_ZQCTL0_SHADOW_T_ZQ_SHORT_NOP_MASK)
#define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_MASK (0x7FF0000U)
#define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_SHIFT (16U)
/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
* clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
* issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
* this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
* tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
* up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
* LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_SHIFT)) & DDRC_ZQCTL0_SHADOW_T_ZQ_LONG_NOP_MASK)
#define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_MASK (0x10000000U)
#define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_SHIFT (28U)
/*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only
* applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving
* Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting
* DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the
* DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after
* exiting MPSM mode.
*/
#define DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_MPSMX_ZQCL_MASK)
#define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_MASK (0x20000000U)
#define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_SHIFT (29U)
/*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means
* ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
* tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 -
* ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or
* LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_SHIFT)) & DDRC_ZQCTL0_SHADOW_ZQ_RESISTOR_SHARED_MASK)
#define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_MASK (0x40000000U)
#define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_SHIFT (30U)
/*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at
* Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 -
* Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only
* applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for
* designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_SRX_ZQCL_MASK)
#define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_MASK (0x80000000U)
#define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_SHIFT (31U)
/*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register
* DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 -
* Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
* This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
*/
#define DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_SHIFT)) & DDRC_ZQCTL0_SHADOW_DIS_AUTO_ZQ_MASK)
/*! @} */
/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
/*! @{ */
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK (0x3FU)
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT (0U)
/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
* (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
* specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
* necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
* the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
* clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
*/
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK)
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK (0x3F00U)
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT (8U)
/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
* when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
* DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
* supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
* DFITMG0.dfi_wrdata_use_sdr.
*/
#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK)
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK (0x8000U)
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT (15U)
/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
* HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
* is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
* DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
* HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
* for correct value.
*/
#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK)
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK (0x7F0000U)
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT (16U)
/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
* assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
* to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
* may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
* compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
* DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
*/
#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK)
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK (0x800000U)
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT (23U)
/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
* using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
* DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
* clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
* value.
*/
#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK)
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK (0x1F000000U)
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT (24U)
/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
* of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
* assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
* parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
* is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
* of DFI clock.
*/
#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT)) & DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK)
/*! @} */
/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
/*! @{ */
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_MASK (0x1FU)
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U)
/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
* dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
* DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
* phase aligned, this timing parameter should be rounded up to the next integer value.
*/
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_ENABLE_MASK)
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_MASK (0x1F00U)
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U)
/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
* dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
* boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
* this timing parameter should be rounded up to the next integer value.
*/
#define DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_DRAM_CLK_DISABLE_MASK)
#define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_MASK (0x1F0000U)
#define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_SHIFT (16U)
/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
* signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
* This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
* correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
* 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
* programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
* and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
* Clocks
*/
#define DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_WRDATA_DELAY_MASK)
#define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_MASK (0x3000000U)
#define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_SHIFT (24U)
/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
* asserted and when the associated dfi_parity_in signal is driven.
*/
#define DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_PARIN_LAT_MASK)
#define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_MASK (0xF0000000U)
#define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_SHIFT (28U)
/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
* asserted and when the associated command is driven. This field is used for CAL mode, should be
* set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
* can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
*/
#define DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_SHIFT)) & DDRC_DFITMG1_SHADOW_DFI_T_CMD_LAT_MASK)
/*! @} */
/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
/*! @{ */
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_MASK (0x3FU)
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_SHIFT (0U)
/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
* DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
* to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
*/
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_SHIFT)) & DDRC_DFITMG2_SHADOW_DFI_TPHY_WRCSLAT_MASK)
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_MASK (0x7F00U)
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_SHIFT (8U)
/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
* control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
* to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
*/
#define DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_SHIFT)) & DDRC_DFITMG2_SHADOW_DFI_TPHY_RDCSLAT_MASK)
/*! @} */
/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
/*! @{ */
#define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_MASK (0x1FU)
#define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_SHIFT (0U)
/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
* ready to receive commands. Refer to PHY specification for correct value. When the controller is
* operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
* the next integer value. Unit: Clocks
*/
#define DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_SHIFT)) & DDRC_DFITMG3_SHADOW_DFI_T_GEARDOWN_DELAY_MASK)
/*! @} */
/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
/*! @{ */
#define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_MASK (0x7CU)
#define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_SHIFT (2U)
/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
* values associated with that command. ODT setting must remain constant for the entire time that
* DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
* (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
* CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
* mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
* preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
* not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_SHADOW_RD_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_SHADOW_RD_ODT_DELAY_MASK)
#define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_MASK (0xF00U)
#define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_SHIFT (8U)
/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
* is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
* DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
* write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
* RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_SHADOW_RD_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_SHADOW_RD_ODT_HOLD_MASK)
#define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_MASK (0x1F0000U)
#define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_SHIFT (16U)
/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
* values associated with that command. ODT setting must remain constant for the entire time that
* DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
* AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
* for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
* - WL - 1 - RU(tODTon(max)/tCK))
*/
#define DDRC_ODTCFG_SHADOW_WR_ODT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_SHIFT)) & DDRC_ODTCFG_SHADOW_WR_ODT_DELAY_MASK)
#define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_MASK (0xF000000U)
#define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_SHIFT (24U)
/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
* is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
* - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
* 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
* CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
*/
#define DDRC_ODTCFG_SHADOW_WR_ODT_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_SHIFT)) & DDRC_ODTCFG_SHADOW_WR_ODT_HOLD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DDRC_Register_Masks */
/* DDRC - Peripheral instance base addresses */
/** Peripheral DDRC base address */
#define DDRC_BASE (0x3D400000u)
/** Peripheral DDRC base pointer */
#define DDRC ((DDRC_Type *)DDRC_BASE)
/** Array initializer of DDRC peripheral base addresses */
#define DDRC_BASE_ADDRS { DDRC_BASE }
/** Array initializer of DDRC peripheral base pointers */
#define DDRC_BASE_PTRS { DDRC }
/*!
* @}
*/ /* end of group DDRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DDR_BLK_CTL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DDR_BLK_CTL_Peripheral_Access_Layer DDR_BLK_CTL Peripheral Access Layer
* @{
*/
/** DDR_BLK_CTL - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[256];
__IO uint32_t DDR_SS_GPR0; /**< DDR Subsystem General Purpose Register 0, offset: 0x100 */
} DDR_BLK_CTL_Type;
/* ----------------------------------------------------------------------------
-- DDR_BLK_CTL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DDR_BLK_CTL_Register_Masks DDR_BLK_CTL Register Masks
* @{
*/
/*! @name DDR_SS_GPR0 - DDR Subsystem General Purpose Register 0 */
/*! @{ */
#define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_MASK (0xFFFFFFFFU)
#define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_SHIFT (0U)
/*! DDR_MODE - DDR Mode
* 0b00000000000000000000000000000001..LPDDR4 Mode
* 0b00000000000000000000000000000000..DDR4/DDR4L Mode
*/
#define DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_SHIFT)) & DDR_BLK_CTL_DDR_SS_GPR0_DDR_MODE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DDR_BLK_CTL_Register_Masks */
/* DDR_BLK_CTL - Peripheral instance base addresses */
/** Peripheral DDR_BLK_CTRL base address */
#define DDR_BLK_CTRL_BASE (0x3D000000u)
/** Peripheral DDR_BLK_CTRL base pointer */
#define DDR_BLK_CTRL ((DDR_BLK_CTL_Type *)DDR_BLK_CTRL_BASE)
/** Array initializer of DDR_BLK_CTL peripheral base addresses */
#define DDR_BLK_CTL_BASE_ADDRS { DDR_BLK_CTRL_BASE }
/** Array initializer of DDR_BLK_CTL peripheral base pointers */
#define DDR_BLK_CTL_BASE_PTRS { DDR_BLK_CTRL }
/*!
* @}
*/ /* end of group DDR_BLK_CTL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */
__I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */
__I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */
__I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */
uint8_t RESERVED_0[240];
__IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_1[65152];
struct { /* offset: 0x10000, array step: 0x1000 */
__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x1000 */
__IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x1000 */
__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x1000 */
__IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x1000 */
__IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x1000 */
uint8_t RESERVED_0[12];
__IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x10020, array step: 0x1000 */
__IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x10024, array step: 0x1000 */
__IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x10026, array step: 0x1000 */
union { /* offset: 0x10028, array step: 0x1000 */
__IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x10028, array step: 0x1000 */
__IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x10028, array step: 0x1000 */
};
__IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x1002C, array step: 0x1000 */
__IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x10030, array step: 0x1000 */
__IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x10034, array step: 0x1000 */
union { /* offset: 0x10036, array step: 0x1000 */
__IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x10036, array step: 0x1000 */
__IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x10036, array step: 0x1000 */
};
__IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x10038, array step: 0x1000 */
__IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x1003C, array step: 0x1000 */
union { /* offset: 0x1003E, array step: 0x1000 */
__IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1003E, array step: 0x1000 */
__IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1003E, array step: 0x1000 */
};
uint8_t RESERVED_1[4032];
} CH[32];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/*! @name MP_CSR - Management Page Control */
/*! @{ */
#define DMA_MP_CSR_EDBG_MASK (0x2U)
#define DMA_MP_CSR_EDBG_SHIFT (1U)
/*! EDBG - Enable Debug
* 0b0..Debug mode disabled
* 0b1..Debug mode is enabled.
*/
#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
#define DMA_MP_CSR_ERCA_MASK (0x4U)
#define DMA_MP_CSR_ERCA_SHIFT (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
* 0b0..Round-robin channel arbitration disabled
* 0b1..Round-robin channel arbitration enabled
*/
#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
#define DMA_MP_CSR_HAE_MASK (0x10U)
#define DMA_MP_CSR_HAE_SHIFT (4U)
/*! HAE - Halt After Error
* 0b0..Normal operation
* 0b1..Any error causes the HALT field to be set to 1
*/
#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
#define DMA_MP_CSR_HALT_MASK (0x20U)
#define DMA_MP_CSR_HALT_SHIFT (5U)
/*! HALT - Halt DMA Operations
* 0b0..Normal operation
* 0b1..Stall the start of any new channels
*/
#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
#define DMA_MP_CSR_GCLC_MASK (0x40U)
#define DMA_MP_CSR_GCLC_SHIFT (6U)
/*! GCLC - Global Channel Linking Control
* 0b0..Channel linking disabled for all channels
* 0b1..Channel linking available and controlled by each channel's link settings
*/
#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
#define DMA_MP_CSR_GMRC_MASK (0x80U)
#define DMA_MP_CSR_GMRC_SHIFT (7U)
/*! GMRC - Global Master ID Replication Control
* 0b0..Master ID replication disabled for all channels
* 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
*/
#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
#define DMA_MP_CSR_ECX_MASK (0x100U)
#define DMA_MP_CSR_ECX_SHIFT (8U)
/*! ECX - Cancel Transfer With Error
* 0b0..Normal operation
* 0b1..Cancel the remaining data transfer
*/
#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
#define DMA_MP_CSR_CX_MASK (0x200U)
#define DMA_MP_CSR_CX_SHIFT (9U)
/*! CX - Cancel Transfer
* 0b0..Normal operation
* 0b1..Cancel the remaining data transfer
*/
#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
#define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U)
#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U)
/*! ACTIVE_ID - Active Channel ID
*/
#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK)
#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U)
#define DMA_MP_CSR_ACTIVE_SHIFT (31U)
/*! ACTIVE - DMA Active Status
* 0b0..eDMA is idle
* 0b1..eDMA is executing a channel
*/
#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
/*! @} */
/*! @name MP_ES - Management Page Error Status */
/*! @{ */
#define DMA_MP_ES_DBE_MASK (0x1U)
#define DMA_MP_ES_DBE_SHIFT (0U)
/*! DBE - Destination Bus Error
* 0b0..No destination bus error
* 0b1..Last recorded error was a bus error on a destination write
*/
#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
#define DMA_MP_ES_SBE_MASK (0x2U)
#define DMA_MP_ES_SBE_SHIFT (1U)
/*! SBE - Source Bus Error
* 0b0..No source bus error
* 0b1..Last recorded error was a bus error on a source read
*/
#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
#define DMA_MP_ES_SGE_MASK (0x4U)
#define DMA_MP_ES_SGE_SHIFT (2U)
/*! SGE - Scatter/Gather Configuration Error
* 0b0..No scatter/gather configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DLASTSGA field
*/
#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
#define DMA_MP_ES_NCE_MASK (0x8U)
#define DMA_MP_ES_NCE_SHIFT (3U)
/*! NCE - NBYTES/CITER Configuration Error
* 0b0..No NBYTES/CITER configuration error
* 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
*/
#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
#define DMA_MP_ES_DOE_MASK (0x10U)
#define DMA_MP_ES_DOE_SHIFT (4U)
/*! DOE - Destination Offset Error
* 0b0..No destination offset configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
*/
#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
#define DMA_MP_ES_DAE_MASK (0x20U)
#define DMA_MP_ES_DAE_SHIFT (5U)
/*! DAE - Destination Address Error
* 0b0..No destination address configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
*/
#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
#define DMA_MP_ES_SOE_MASK (0x40U)
#define DMA_MP_ES_SOE_SHIFT (6U)
/*! SOE - Source Offset Error
* 0b0..No source offset configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
*/
#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
#define DMA_MP_ES_SAE_MASK (0x80U)
#define DMA_MP_ES_SAE_SHIFT (7U)
/*! SAE - Source Address Error
* 0b0..No source address configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
*/
#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
#define DMA_MP_ES_ECX_MASK (0x100U)
#define DMA_MP_ES_ECX_SHIFT (8U)
/*! ECX - Transfer Canceled
* 0b0..No canceled transfers
* 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input
*/
#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
#define DMA_MP_ES_ERRCHN_MASK (0x1F000000U)
#define DMA_MP_ES_ERRCHN_SHIFT (24U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number
*/
#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK)
#define DMA_MP_ES_VLD_MASK (0x80000000U)
#define DMA_MP_ES_VLD_SHIFT (31U)
/*! VLD - Valid
* 0b0..No ERR fields are set to 1
* 0b1..At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
*/
#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
/*! @} */
/*! @name MP_INT - Management Page Interrupt Request Status */
/*! @{ */
#define DMA_MP_INT_INT_MASK (0xFFFFFFFFU)
#define DMA_MP_INT_INT_SHIFT (0U)
/*! INT - Interrupt Request Status
*/
#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK)
/*! @} */
/*! @name MP_HRS - Management Page Hardware Request Status */
/*! @{ */
#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU)
#define DMA_MP_HRS_HRS_SHIFT (0U)
/*! HRS - Hardware Request Status
*/
#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
/*! @} */
/*! @name CH_GRPRI - Channel Arbitration Group */
/*! @{ */
#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU)
#define DMA_CH_GRPRI_GRPRI_SHIFT (0U)
/*! GRPRI - Arbitration Group For Channel n
*/
#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
/*! @} */
/* The count of DMA_CH_GRPRI */
#define DMA_CH_GRPRI_COUNT (32U)
/*! @name CH_CSR - Channel Control and Status */
/*! @{ */
#define DMA_CH_CSR_ERQ_MASK (0x1U)
#define DMA_CH_CSR_ERQ_SHIFT (0U)
/*! ERQ - Enable DMA Request
* 0b0..DMA hardware request signal for corresponding channel disabled
* 0b1..DMA hardware request signal for corresponding channel enabled
*/
#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
#define DMA_CH_CSR_EARQ_MASK (0x2U)
#define DMA_CH_CSR_EARQ_SHIFT (1U)
/*! EARQ - Enable Asynchronous DMA Request In Stop Mode For Channel
* 0b0..Disable asynchronous DMA request for the channel
* 0b1..Enable asynchronous DMA request for the channel
*/
#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
#define DMA_CH_CSR_EEI_MASK (0x4U)
#define DMA_CH_CSR_EEI_SHIFT (2U)
/*! EEI - Enable Error Interrupt
* 0b0..Error signal for corresponding channel does not generate error interrupt
* 0b1..Assertion of error signal for corresponding channel generates error interrupt request
*/
#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
#define DMA_CH_CSR_EBW_MASK (0x8U)
#define DMA_CH_CSR_EBW_SHIFT (3U)
/*! EBW - Enable Buffered Writes
* 0b0..Buffered writes on system bus disabled
* 0b1..Buffered writes on system bus enabled
*/
#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK)
#define DMA_CH_CSR_DONE_MASK (0x40000000U)
#define DMA_CH_CSR_DONE_SHIFT (30U)
/*! DONE - Channel Done
*/
#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U)
#define DMA_CH_CSR_ACTIVE_SHIFT (31U)
/*! ACTIVE - Channel Active
*/
#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
/*! @} */
/* The count of DMA_CH_CSR */
#define DMA_CH_CSR_COUNT (32U)
/*! @name CH_ES - Channel Error Status */
/*! @{ */
#define DMA_CH_ES_DBE_MASK (0x1U)
#define DMA_CH_ES_DBE_SHIFT (0U)
/*! DBE - Destination Bus Error
* 0b0..No destination bus error
* 0b1..Last recorded error was bus error on destination write
*/
#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
#define DMA_CH_ES_SBE_MASK (0x2U)
#define DMA_CH_ES_SBE_SHIFT (1U)
/*! SBE - Source Bus Error
* 0b0..No source bus error
* 0b1..Last recorded error was bus error on source read
*/
#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
#define DMA_CH_ES_SGE_MASK (0x4U)
#define DMA_CH_ES_SGE_SHIFT (2U)
/*! SGE - Scatter/Gather Configuration Error
* 0b0..No scatter/gather configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DLASTSGA field
*/
#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
#define DMA_CH_ES_NCE_MASK (0x8U)
#define DMA_CH_ES_NCE_SHIFT (3U)
/*! NCE - NBYTES/CITER Configuration Error
* 0b0..No NBYTES/CITER configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
*/
#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
#define DMA_CH_ES_DOE_MASK (0x10U)
#define DMA_CH_ES_DOE_SHIFT (4U)
/*! DOE - Destination Offset Error
* 0b0..No destination offset configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field
*/
#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
#define DMA_CH_ES_DAE_MASK (0x20U)
#define DMA_CH_ES_DAE_SHIFT (5U)
/*! DAE - Destination Address Error
* 0b0..No destination address configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field
*/
#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
#define DMA_CH_ES_SOE_MASK (0x40U)
#define DMA_CH_ES_SOE_SHIFT (6U)
/*! SOE - Source Offset Error
* 0b0..No source offset configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field
*/
#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
#define DMA_CH_ES_SAE_MASK (0x80U)
#define DMA_CH_ES_SAE_SHIFT (7U)
/*! SAE - Source Address Error
* 0b0..No source address configuration error
* 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field
*/
#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
#define DMA_CH_ES_ERR_MASK (0x80000000U)
#define DMA_CH_ES_ERR_SHIFT (31U)
/*! ERR - Error In Channel
* 0b0..An error in this channel has not occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
/*! @} */
/* The count of DMA_CH_ES */
#define DMA_CH_ES_COUNT (32U)
/*! @name CH_INT - Channel Interrupt Status */
/*! @{ */
#define DMA_CH_INT_INT_MASK (0x1U)
#define DMA_CH_INT_INT_SHIFT (0U)
/*! INT - Interrupt Request
* 0b0..Interrupt request for corresponding channel cleared
* 0b1..Interrupt request for corresponding channel active
*/
#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
/*! @} */
/* The count of DMA_CH_INT */
#define DMA_CH_INT_COUNT (32U)
/*! @name CH_SBR - Channel System Bus */
/*! @{ */
#define DMA_CH_SBR_MID_MASK (0x1FU)
#define DMA_CH_SBR_MID_SHIFT (0U)
/*! MID - Master ID
*/
#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
#define DMA_CH_SBR_PAL_MASK (0x8000U)
#define DMA_CH_SBR_PAL_SHIFT (15U)
/*! PAL - Privileged Access Level
* 0b0..User protection level for DMA transfers
* 0b1..Privileged protection level for DMA transfers
*/
#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
#define DMA_CH_SBR_ATTR_MASK (0x7E0000U)
#define DMA_CH_SBR_ATTR_SHIFT (17U)
/*! ATTR - Attribute Output
*/
#define DMA_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
/*! @} */
/* The count of DMA_CH_SBR */
#define DMA_CH_SBR_COUNT (32U)
/*! @name CH_PRI - Channel Priority */
/*! @{ */
#define DMA_CH_PRI_APL_MASK (0x7U)
#define DMA_CH_PRI_APL_SHIFT (0U)
/*! APL - Arbitration Priority Level
*/
#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
#define DMA_CH_PRI_DPA_MASK (0x40000000U)
#define DMA_CH_PRI_DPA_SHIFT (30U)
/*! DPA - Disable Preempt Ability
* 0b0..Channel can suspend a lower-priority channel
* 0b1..Channel cannot suspend any other channel, regardless of channel priority
*/
#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
#define DMA_CH_PRI_ECP_MASK (0x80000000U)
#define DMA_CH_PRI_ECP_SHIFT (31U)
/*! ECP - Enable Channel Preemption
* 0b0..Channel cannot be suspended by a higher-priority channel's service request
* 0b1..Channel can be temporarily suspended by a higher-priority channel's service request
*/
#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
/*! @} */
/* The count of DMA_CH_PRI */
#define DMA_CH_PRI_COUNT (32U)
/*! @name TCD_SADDR - TCD Source Address */
/*! @{ */
#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define DMA_TCD_SADDR_SADDR_SHIFT (0U)
/*! SADDR - Source Address
*/
#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
/*! @} */
/* The count of DMA_TCD_SADDR */
#define DMA_TCD_SADDR_COUNT (32U)
/*! @name TCD_SOFF - TCD Signed Source Address Offset */
/*! @{ */
#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU)
#define DMA_TCD_SOFF_SOFF_SHIFT (0U)
/*! SOFF - Source Address Signed Offset
*/
#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
/*! @} */
/* The count of DMA_TCD_SOFF */
#define DMA_TCD_SOFF_COUNT (32U)
/*! @name TCD_ATTR - TCD Transfer Attributes */
/*! @{ */
#define DMA_TCD_ATTR_DSIZE_MASK (0x7U)
#define DMA_TCD_ATTR_DSIZE_SHIFT (0U)
/*! DSIZE - Destination Data Transfer Size
*/
#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
#define DMA_TCD_ATTR_DMOD_MASK (0xF8U)
#define DMA_TCD_ATTR_DMOD_SHIFT (3U)
/*! DMOD - Destination Address Modulo
*/
#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
#define DMA_TCD_ATTR_SSIZE_MASK (0x700U)
#define DMA_TCD_ATTR_SSIZE_SHIFT (8U)
/*! SSIZE - Source Data Transfer Size
* 0b000..8-bit
* 0b001..16-bit
* 0b010..32-bit
* 0b011..64-bit
* 0b100..16-byte
* 0b101..32-byte
* 0b110..64-byte
* 0b111..Reserved
*/
#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
#define DMA_TCD_ATTR_SMOD_MASK (0xF800U)
#define DMA_TCD_ATTR_SMOD_SHIFT (11U)
/*! SMOD - Source Address Modulo
* 0b00000..Source address modulo feature disabled
* 0b00001..Source address modulo feature enabled for any non-zero value [1-31]
*/
#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
/*! @} */
/* The count of DMA_TCD_ATTR */
#define DMA_TCD_ATTR_COUNT (32U)
/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */
/*! @{ */
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request
*/
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
* 0b0..Minor loop offset not applied to DADDR
* 0b1..Minor loop offset applied to DADDR
*/
#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
/*! SMLOE - Source Minor Loop Offset Enable
* 0b0..Minor loop offset not applied to SADDR
* 0b1..Minor loop offset applied to SADDR
*/
#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */
/* The count of DMA_TCD_NBYTES_MLOFFNO */
#define DMA_TCD_NBYTES_MLOFFNO_COUNT (32U)
/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */
/*! @{ */
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
/*! NBYTES - Number of Bytes To Transfer Per Service Request
*/
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
/*! MLOFF - Minor Loop Offset
*/
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
* 0b0..Minor loop offset not applied to DADDR
* 0b1..Minor loop offset applied to DADDR
*/
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
/*! SMLOE - Source Minor Loop Offset Enable
* 0b0..Minor loop offset not applied to SADDR
* 0b1..Minor loop offset applied to SADDR
*/
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */
/* The count of DMA_TCD_NBYTES_MLOFFYES */
#define DMA_TCD_NBYTES_MLOFFYES_COUNT (32U)
/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */
/*! @{ */
#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU)
#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U)
/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address
*/
#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
/*! @} */
/* The count of DMA_TCD_SLAST_SDA */
#define DMA_TCD_SLAST_SDA_COUNT (32U)
/*! @name TCD_DADDR - TCD Destination Address */
/*! @{ */
#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define DMA_TCD_DADDR_DADDR_SHIFT (0U)
/*! DADDR - Destination Address
*/
#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
/*! @} */
/* The count of DMA_TCD_DADDR */
#define DMA_TCD_DADDR_COUNT (32U)
/*! @name TCD_DOFF - TCD Signed Destination Address Offset */
/*! @{ */
#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU)
#define DMA_TCD_DOFF_DOFF_SHIFT (0U)
/*! DOFF - Destination Address Signed Offset
*/
#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
/*! @} */
/* The count of DMA_TCD_DOFF */
#define DMA_TCD_DOFF_COUNT (32U)
/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */
#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U)
/*! CITER - Current Major Iteration Count
*/
#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U)
/*! ELINK - Enable Link
* 0b0..Channel-to-channel linking disabled
* 0b1..Channel-to-channel linking enabled
*/
#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_TCD_CITER_ELINKNO */
#define DMA_TCD_CITER_ELINKNO_COUNT (32U)
/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */
#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U)
/*! CITER - Current Major Iteration Count
*/
#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U)
/*! LINKCH - Minor Loop Link Channel Number
*/
#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U)
/*! ELINK - Enable Link
* 0b0..Channel-to-channel linking disabled
* 0b1..Channel-to-channel linking enabled
*/
#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_TCD_CITER_ELINKYES */
#define DMA_TCD_CITER_ELINKYES_COUNT (32U)
/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */
/*! @{ */
#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU)
#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U)
/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address
*/
#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
/*! @} */
/* The count of DMA_TCD_DLAST_SGA */
#define DMA_TCD_DLAST_SGA_COUNT (32U)
/*! @name TCD_CSR - TCD Control and Status */
/*! @{ */
#define DMA_TCD_CSR_START_MASK (0x1U)
#define DMA_TCD_CSR_START_SHIFT (0U)
/*! START - Channel Start
* 0b0..Channel not explicitly started
* 0b1..Channel explicitly started via a software-initiated service request
*/
#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U)
#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U)
/*! INTMAJOR - Enable Interrupt If Major count complete
* 0b0..End-of-major loop interrupt disabled
* 0b1..End-of-major loop interrupt enabled
*/
#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
#define DMA_TCD_CSR_INTHALF_MASK (0x4U)
#define DMA_TCD_CSR_INTHALF_SHIFT (2U)
/*! INTHALF - Enable Interrupt If Major Counter Half-complete
* 0b0..Halfway point interrupt disabled
* 0b1..Halfway point interrupt enabled
*/
#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
#define DMA_TCD_CSR_DREQ_MASK (0x8U)
#define DMA_TCD_CSR_DREQ_SHIFT (3U)
/*! DREQ - Disable Request
* 0b0..No operation
* 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests
*/
#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
#define DMA_TCD_CSR_ESG_MASK (0x10U)
#define DMA_TCD_CSR_ESG_SHIFT (4U)
/*! ESG - Enable Scatter/Gather Processing
* 0b0..Current channel's TCD is normal format
* 0b1..Current channel's TCD specifies scatter/gather format.
*/
#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U)
#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U)
/*! MAJORELINK - Enable Link When Major Loop Complete
* 0b0..Channel-to-channel linking disabled
* 0b1..Channel-to-channel linking enabled
*/
#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
#define DMA_TCD_CSR_EEOP_MASK (0x40U)
#define DMA_TCD_CSR_EEOP_SHIFT (6U)
/*! EEOP - Enable End-Of-Packet Processing
* 0b0..End-of-packet operation disabled
* 0b1..End-of-packet hardware input signal enabled
*/
#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
#define DMA_TCD_CSR_ESDA_MASK (0x80U)
#define DMA_TCD_CSR_ESDA_SHIFT (7U)
/*! ESDA - Enable Store Destination Address
* 0b0..Ability to store destination address to system memory disabled
* 0b1..Ability to store destination address to system memory enabled
*/
#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U)
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number
*/
#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK)
#define DMA_TCD_CSR_BWC_MASK (0xC000U)
#define DMA_TCD_CSR_BWC_SHIFT (14U)
/*! BWC - Bandwidth Control
* 0b00..No eDMA engine stalls
* 0b01..Reserved
* 0b10..eDMA engine stalls for 4 cycles after each R/W
* 0b11..eDMA engine stalls for 8 cycles after each R/W
*/
#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
/*! @} */
/* The count of DMA_TCD_CSR */
#define DMA_TCD_CSR_COUNT (32U)
/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */
/*! @{ */
#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U)
/*! BITER - Starting Major Iteration Count
*/
#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U)
/*! ELINK - Enables Link
* 0b0..Channel-to-channel linking disabled
* 0b1..Channel-to-channel linking enabled
*/
#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_TCD_BITER_ELINKNO */
#define DMA_TCD_BITER_ELINKNO_COUNT (32U)
/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */
/*! @{ */
#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U)
/*! BITER - Starting Major Iteration Count
*/
#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U)
/*! LINKCH - Link Channel Number
*/
#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U)
/*! ELINK - Enable Link
* 0b0..Channel-to-channel linking disabled
* 0b1..Channel-to-channel linking enabled
*/
#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_TCD_BITER_ELINKYES */
#define DMA_TCD_BITER_ELINKYES_COUNT (32U)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral EDMA1 base address */
#define EDMA1_BASE (0x30E30000u)
/** Peripheral EDMA1 base pointer */
#define EDMA1 ((DMA_Type *)EDMA1_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { EDMA1_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { EDMA1 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_IRQS { { EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_0_15_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn, EDMA1_16_31_IRQn } }
#define DMA_ERROR_IRQS { EDMA1_ERR_IRQn }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_ANIB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_ANIB_Peripheral_Access_Layer DWC_DDRPHYA_ANIB Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_ANIB - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[52];
__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
uint8_t RESERVED_1[24];
__IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), offset: 0x4E */
__IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0), offset: 0x50 */
uint8_t RESERVED_2[52];
__IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 */
uint8_t RESERVED_3[30];
__I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an entire ACX4 block, offset: 0xA6 */
uint8_t RESERVED_4[2];
__IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls, offset: 0xAA */
__I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offset: 0xAC */
uint8_t RESERVED_5[82];
__IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: 0x100 */
uint8_t RESERVED_6[2097150];
__IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: 0x200100 */
uint8_t RESERVED_7[2097150];
__IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: 0x400100 */
uint8_t RESERVED_8[2097150];
__IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: 0x600100 */
} DWC_DDRPHYA_ANIB_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_ANIB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_ANIB_Register_Masks DWC_DDRPHYA_ANIB Register Masks
* @{
*/
/*! @name MTESTMUXSEL - Digital Observation Pin control */
/*! @{ */
#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
/*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin.
*/
#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_ANIB_MTESTMUXSEL_MTESTMUXSEL_MASK)
/*! @} */
/*! @name AFORCEDRVCONT - Force Address/Command Driven (Lanes A3-A0) */
/*! @{ */
#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_MASK (0xFU)
#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_SHIFT (0U)
/*! AForceDrvCont - Force continuous drive, per-lane, of the ACX4 instance controlled by this
* register Setting this register will cause the PHY to drive the target lane when dfi_init_complete==1
* Bit [0] = controls lane 0 of the target ACX4 block Bit [1] = controls lane 1 of the target
* ACX4 block Bit [2] = controls lane 2 of the target ACX4 block Bit [3] = controls lane 3 of the
* target ACX4 block
*/
#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AFORCEDRVCONT_MASK)
/*! @} */
/*! @name AFORCETRICONT - Force Address/Command Tristate (Lanes A3-A0) */
/*! @{ */
#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_MASK (0xFU)
#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_SHIFT (0U)
/*! AForceTriCont - Force tristate control, per-lane, of the ACX4 instance controlled by this
* register Setting this register will cause the PHY to tristate the target lane when
* dfi_init_complete==1 Bit [0] = controls lane 0 of the target ACX4 block Bit [1] = controls lane 1 of the target
* ACX4 block Bit [2] = controls lane 2 of the target ACX4 block Bit [3] = controls lane 3 of
* the target ACX4 block
*/
#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_SHIFT)) & DWC_DDRPHYA_ANIB_AFORCETRICONT_AFORCETRICONT_MASK)
/*! @} */
/*! @name ATXIMPEDANCE - Address TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_MASK (0x1FU)
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_SHIFT (0U)
/*! ADrvStrenP - 5 bit bus used to select the target pull up output impedance.
*/
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENP_MASK)
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_MASK (0x3E0U)
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_SHIFT (5U)
/*! ADrvStrenN - 5 bit bus used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADRVSTRENN_MASK)
/*! @} */
/*! @name ATESTPRBSERR - Address Loopback PRBS Error status for an entire ACX4 block */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_MASK (0xFU)
#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_SHIFT (0U)
/*! ATestPrbsErr - Overall error indicator for each prbs bump checker.
*/
#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATESTPRBSERR_MASK)
/*! @} */
/*! @name ATXSLEWRATE - Address TX slew rate and predriver controls */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_MASK (0xFU)
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_SHIFT (0U)
/*! ATxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREP_MASK)
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_SHIFT (4U)
/*! ATxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREN_MASK)
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_SHIFT (8U)
/*! ATxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATXPREDRVMODE_MASK)
/*! @} */
/*! @name ATESTPRBSERRCNT - Address Loopback Test Result register */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_MASK (0xFFFFU)
#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_SHIFT (0U)
/*! ATestPrbsErrCnt - Overall error indicator for each prbs bump checker.
*/
#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_SHIFT)) & DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATESTPRBSERRCNT_MASK)
/*! @} */
/*! @name ATXDLY_P0 - Address/Command Delay, per pstate. */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_MASK (0x7FU)
#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_SHIFT (0U)
/*! ATxDly_p0 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4.
*/
#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P0_ATXDLY_P0_MASK)
/*! @} */
/*! @name ATXDLY_P1 - Address/Command Delay, per pstate. */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_MASK (0x7FU)
#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_SHIFT (0U)
/*! ATxDly_p1 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4.
*/
#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P1_ATXDLY_P1_MASK)
/*! @} */
/*! @name ATXDLY_P2 - Address/Command Delay, per pstate. */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_MASK (0x7FU)
#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_SHIFT (0U)
/*! ATxDly_p2 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4.
*/
#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P2_ATXDLY_P2_MASK)
/*! @} */
/*! @name ATXDLY_P3 - Address/Command Delay, per pstate. */
/*! @{ */
#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_MASK (0x7FU)
#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_SHIFT (0U)
/*! ATxDly_p3 - Trained for LPDDR3/4 to generate timed address and command signals to the DRAMs, per ACX4.
*/
#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_SHIFT)) & DWC_DDRPHYA_ANIB_ATXDLY_P3_ATXDLY_P3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_ANIB_Register_Masks */
/* DWC_DDRPHYA_ANIB - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_ANIB0 base address */
#define DWC_DDRPHYA_ANIB0_BASE (0x3C000000u)
/** Peripheral DWC_DDRPHYA_ANIB0 base pointer */
#define DWC_DDRPHYA_ANIB0 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB0_BASE)
/** Peripheral DWC_DDRPHYA_ANIB1 base address */
#define DWC_DDRPHYA_ANIB1_BASE (0x3C001000u)
/** Peripheral DWC_DDRPHYA_ANIB1 base pointer */
#define DWC_DDRPHYA_ANIB1 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB1_BASE)
/** Peripheral DWC_DDRPHYA_ANIB2 base address */
#define DWC_DDRPHYA_ANIB2_BASE (0x3C002000u)
/** Peripheral DWC_DDRPHYA_ANIB2 base pointer */
#define DWC_DDRPHYA_ANIB2 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB2_BASE)
/** Peripheral DWC_DDRPHYA_ANIB3 base address */
#define DWC_DDRPHYA_ANIB3_BASE (0x3C003000u)
/** Peripheral DWC_DDRPHYA_ANIB3 base pointer */
#define DWC_DDRPHYA_ANIB3 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB3_BASE)
/** Peripheral DWC_DDRPHYA_ANIB4 base address */
#define DWC_DDRPHYA_ANIB4_BASE (0x3C004000u)
/** Peripheral DWC_DDRPHYA_ANIB4 base pointer */
#define DWC_DDRPHYA_ANIB4 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB4_BASE)
/** Peripheral DWC_DDRPHYA_ANIB5 base address */
#define DWC_DDRPHYA_ANIB5_BASE (0x3C005000u)
/** Peripheral DWC_DDRPHYA_ANIB5 base pointer */
#define DWC_DDRPHYA_ANIB5 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB5_BASE)
/** Peripheral DWC_DDRPHYA_ANIB6 base address */
#define DWC_DDRPHYA_ANIB6_BASE (0x3C006000u)
/** Peripheral DWC_DDRPHYA_ANIB6 base pointer */
#define DWC_DDRPHYA_ANIB6 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB6_BASE)
/** Peripheral DWC_DDRPHYA_ANIB7 base address */
#define DWC_DDRPHYA_ANIB7_BASE (0x3C007000u)
/** Peripheral DWC_DDRPHYA_ANIB7 base pointer */
#define DWC_DDRPHYA_ANIB7 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB7_BASE)
/** Peripheral DWC_DDRPHYA_ANIB8 base address */
#define DWC_DDRPHYA_ANIB8_BASE (0x3C008000u)
/** Peripheral DWC_DDRPHYA_ANIB8 base pointer */
#define DWC_DDRPHYA_ANIB8 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB8_BASE)
/** Peripheral DWC_DDRPHYA_ANIB9 base address */
#define DWC_DDRPHYA_ANIB9_BASE (0x3C009000u)
/** Peripheral DWC_DDRPHYA_ANIB9 base pointer */
#define DWC_DDRPHYA_ANIB9 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB9_BASE)
/** Array initializer of DWC_DDRPHYA_ANIB peripheral base addresses */
#define DWC_DDRPHYA_ANIB_BASE_ADDRS { DWC_DDRPHYA_ANIB0_BASE, DWC_DDRPHYA_ANIB1_BASE, DWC_DDRPHYA_ANIB2_BASE, DWC_DDRPHYA_ANIB3_BASE, DWC_DDRPHYA_ANIB4_BASE, DWC_DDRPHYA_ANIB5_BASE, DWC_DDRPHYA_ANIB6_BASE, DWC_DDRPHYA_ANIB7_BASE, DWC_DDRPHYA_ANIB8_BASE, DWC_DDRPHYA_ANIB9_BASE }
/** Array initializer of DWC_DDRPHYA_ANIB peripheral base pointers */
#define DWC_DDRPHYA_ANIB_BASE_PTRS { DWC_DDRPHYA_ANIB0, DWC_DDRPHYA_ANIB1, DWC_DDRPHYA_ANIB2, DWC_DDRPHYA_ANIB3, DWC_DDRPHYA_ANIB4, DWC_DDRPHYA_ANIB5, DWC_DDRPHYA_ANIB6, DWC_DDRPHYA_ANIB7, DWC_DDRPHYA_ANIB8, DWC_DDRPHYA_ANIB9 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_ANIB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_APBONLY Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer DWC_DDRPHYA_APBONLY Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_APBONLY - Register Layout Typedef */
typedef struct {
__IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */
uint8_t RESERVED_0[6];
__I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-only Shadow, offset: 0x8 */
uint8_t RESERVED_1[86];
__IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */
__IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset: 0x62 */
__I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x64 */
uint8_t RESERVED_2[2];
__I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x68 */
uint8_t RESERVED_3[4];
__IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid csr Rd Data., offset: 0x6E */
uint8_t RESERVED_4[194];
__IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the local microcontroller, offset: 0x132 */
uint8_t RESERVED_5[192];
__I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Shadow, offset: 0x1F4 */
} DWC_DDRPHYA_APBONLY_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_APBONLY Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_APBONLY_Register_Masks DWC_DDRPHYA_APBONLY Register Masks
* @{
*/
/*! @name MICROCONTMUXSEL - PMU Config Mux Select */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_MASK (0x1U)
#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_SHIFT (0U)
/*! MicroContMuxSel - This register controls access to the PHY configuration registers.
*/
#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_SHIFT)) & DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MICROCONTMUXSEL_MASK)
/*! @} */
/*! @name UCTSHADOWREGS - PMU/Controller Protocol - Controller Read-only Shadow */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_MASK (0x1U)
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_SHIFT (0U)
/*! UctWriteProtShadow - When set to 0, the PMU has a message for the user
*/
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTWRITEPROTSHADOW_MASK)
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_MASK (0x2U)
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_SHIFT (1U)
/*! UctDatWriteProtShadow - Reserved for future use.
*/
#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UCTDATWRITEPROTSHADOW_MASK)
/*! @} */
/*! @name DCTWRITEONLY - Reserved for future use. */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_MASK (0xFFFFU)
#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_SHIFT (0U)
/*! DctWriteOnly - Reserved for future use.
*/
#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DCTWRITEONLY_MASK)
/*! @} */
/*! @name DCTWRITEPROT - DCT downstream mailbox protocol CSR. */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_MASK (0x1U)
#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_SHIFT (0U)
/*! DctWriteProt - By setting this register to 0, the user acknowledges the receipt of the message.
*/
#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_SHIFT)) & DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DCTWRITEPROT_MASK)
/*! @} */
/*! @name UCTWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_MASK (0xFFFFU)
#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_SHIFT (0U)
/*! UctWriteOnlyShadow - Used to pass the message ID for major messages.
*/
#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UCTWRITEONLYSHADOW_MASK)
/*! @} */
/*! @name UCTDATWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_MASK (0xFFFFU)
#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_SHIFT (0U)
/*! UctDatWriteOnlyShadow - Used to pass the upper 16 bits for streaming messages.
*/
#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UCTDATWRITEONLYSHADOW_MASK)
/*! @} */
/*! @name DFICFGRDDATAVALIDTICKS - Number of DfiClk ticks required for valid csr Rd Data. */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_MASK (0x3FU)
#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_SHIFT (0U)
/*! DfiCfgRdDataValidTicks - Roundtrip delay of a register read access.
*/
#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_SHIFT)) & DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DFICFGRDDATAVALIDTICKS_MASK)
/*! @} */
/*! @name MICRORESET - Controls reset and clock shutdown on the local microcontroller */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_MASK (0x1U)
#define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_SHIFT (0U)
/*! StallToMicro - Set this bit to stall the microcontroller by hardware.
*/
#define DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_STALLTOMICRO_MASK)
#define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_MASK (0x2U)
#define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_SHIFT (1U)
/*! TestWakeup - Reserved.
*/
#define DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_TESTWAKEUP_MASK)
#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_MASK (0x4U)
#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_SHIFT (2U)
/*! RSVDMicro - RSVD
*/
#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMICRO_MASK)
#define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_MASK (0x8U)
#define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_SHIFT (3U)
/*! ResetToMicro - Set this bit to apply synchronous reset to the microcontroller.
*/
#define DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_SHIFT)) & DWC_DDRPHYA_APBONLY_MICRORESET_RESETTOMICRO_MASK)
/*! @} */
/*! @name DFIINITCOMPLETESHADOW - dfi_init_complete - Controller Read-only Shadow */
/*! @{ */
#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_MASK (0x1U)
#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_SHIFT (0U)
/*! DfiInitCompleteShadow - This csr presents a read-only view (a shadow) of the Register
* DfiInitComplete which is used by the sequencer to control the state of dfi_init_complete.
*/
#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_SHIFT)) & DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DFIINITCOMPLETESHADOW_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_APBONLY_Register_Masks */
/* DWC_DDRPHYA_APBONLY - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_APBONLY0 base address */
#define DWC_DDRPHYA_APBONLY0_BASE (0x3C0D0000u)
/** Peripheral DWC_DDRPHYA_APBONLY0 base pointer */
#define DWC_DDRPHYA_APBONLY0 ((DWC_DDRPHYA_APBONLY_Type *)DWC_DDRPHYA_APBONLY0_BASE)
/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base addresses */
#define DWC_DDRPHYA_APBONLY_BASE_ADDRS { DWC_DDRPHYA_APBONLY0_BASE }
/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base pointers */
#define DWC_DDRPHYA_APBONLY_BASE_PTRS { DWC_DDRPHYA_APBONLY0 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_DBYTE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer DWC_DDRPHYA_DBYTE Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_DBYTE - Register Layout Typedef */
typedef struct {
__IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */
uint8_t RESERVED_0[50];
__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
uint8_t RESERVED_1[10];
__IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */
uint8_t RESERVED_2[30];
__IO uint16_t VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x60 */
uint8_t RESERVED_3[30];
__IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x80 */
__IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */
uint8_t RESERVED_4[2];
__IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */
uint8_t RESERVED_5[8];
__IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., offset: 0x90 */
__IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */
__IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */
__IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: 0x96 */
__IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */
__IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A */
uint8_t RESERVED_6[16];
__I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset: 0xAC */
__I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with an RxFifo consistency error, offset: 0xAE */
__I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0xB0 */
__IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */
__I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
__I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
__I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */
uint8_t RESERVED_7[4];
__IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */
uint8_t RESERVED_8[16];
__IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xD0 */
__IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xD2 */
__IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xD4 */
__IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xD6 */
uint8_t RESERVED_9[40];
__IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x100 */
__IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x102 */
__IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x104 */
__IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x106 */
uint8_t RESERVED_10[16];
__IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x118 */
__IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x11A */
__IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x11C */
__IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x11E */
__IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x120 */
__IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x122 */
__IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x124 */
uint8_t RESERVED_11[2];
__IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x128 */
uint8_t RESERVED_12[22];
__IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset: 0x140, array step: 0x2 */
uint8_t RESERVED_13[48];
__IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x180 */
__IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x182 */
__IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x184 */
__IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x186 */
uint8_t RESERVED_14[24];
__IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x1A0 */
__IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x1A2 */
__IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x1A4 */
__IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x1A6 */
uint8_t RESERVED_15[32];
__I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
uint8_t RESERVED_16[150];
__IO uint16_t VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x260 */
uint8_t RESERVED_17[30];
__IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x280 */
__IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */
uint8_t RESERVED_18[2];
__IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */
uint8_t RESERVED_19[10];
__IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */
uint8_t RESERVED_20[2];
__IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: 0x296 */
uint8_t RESERVED_21[2];
__IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29A */
uint8_t RESERVED_22[34];
__IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */
uint8_t RESERVED_23[16];
__IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x2D0 */
__IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x2D2 */
__IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x2D4 */
__IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x2D6 */
uint8_t RESERVED_24[40];
__IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x300 */
__IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x302 */
__IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x304 */
__IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x306 */
uint8_t RESERVED_25[16];
__IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x318 */
__IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x31A */
__IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x31C */
__IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x31E */
__IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x320 */
__IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x322 */
__IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x324 */
uint8_t RESERVED_26[2];
__IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x328 */
uint8_t RESERVED_27[86];
__IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x380 */
__IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x382 */
__IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x384 */
__IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x386 */
uint8_t RESERVED_28[24];
__IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x3A0 */
__IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x3A2 */
__IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x3A4 */
__IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x3A6 */
uint8_t RESERVED_29[184];
__IO uint16_t VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x460 */
uint8_t RESERVED_30[30];
__IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x480 */
uint8_t RESERVED_31[78];
__IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x4D0 */
__IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x4D2 */
__IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x4D4 */
__IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x4D6 */
uint8_t RESERVED_32[168];
__IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x580 */
__IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x582 */
__IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x584 */
__IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x586 */
uint8_t RESERVED_33[216];
__IO uint16_t VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x660 */
uint8_t RESERVED_34[30];
__IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x680 */
uint8_t RESERVED_35[78];
__IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x6D0 */
__IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x6D2 */
__IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x6D4 */
__IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x6D6 */
uint8_t RESERVED_36[168];
__IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x780 */
__IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x782 */
__IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x784 */
__IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x786 */
uint8_t RESERVED_37[216];
__IO uint16_t VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x860 */
uint8_t RESERVED_38[30];
__IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x880 */
uint8_t RESERVED_39[78];
__IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x8D0 */
__IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x8D2 */
__IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x8D4 */
__IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x8D6 */
uint8_t RESERVED_40[168];
__IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x980 */
__IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x982 */
__IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x984 */
__IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x986 */
uint8_t RESERVED_41[216];
__IO uint16_t VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xA60 */
uint8_t RESERVED_42[30];
__IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0xA80 */
uint8_t RESERVED_43[78];
__IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xAD0 */
__IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xAD2 */
__IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xAD4 */
__IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xAD6 */
uint8_t RESERVED_44[168];
__IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xB80 */
__IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xB82 */
__IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xB84 */
__IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xB86 */
uint8_t RESERVED_45[216];
__IO uint16_t VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xC60 */
uint8_t RESERVED_46[30];
__IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0xC80 */
uint8_t RESERVED_47[78];
__IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xCD0 */
__IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xCD2 */
__IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xCD4 */
__IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xCD6 */
uint8_t RESERVED_48[168];
__IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xD80 */
__IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xD82 */
__IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xD84 */
__IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xD86 */
uint8_t RESERVED_49[216];
__IO uint16_t VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xE60 */
uint8_t RESERVED_50[30];
__IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0xE80 */
uint8_t RESERVED_51[78];
__IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xED0 */
__IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xED2 */
__IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xED4 */
__IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xED6 */
uint8_t RESERVED_52[168];
__IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xF80 */
__IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xF82 */
__IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xF84 */
__IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xF86 */
uint8_t RESERVED_53[216];
__IO uint16_t VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x1060 */
uint8_t RESERVED_54[30];
__IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x1080 */
uint8_t RESERVED_55[78];
__IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x10D0 */
__IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x10D2 */
__IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x10D4 */
__IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x10D6 */
uint8_t RESERVED_56[168];
__IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x1180 */
__IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x1182 */
__IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x1184 */
__IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x1186 */
uint8_t RESERVED_57[2092728];
__IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */
uint8_t RESERVED_58[64];
__IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082 */
uint8_t RESERVED_59[2];
__IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */
uint8_t RESERVED_60[8];
__IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., offset: 0x200090 */
__IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */
uint8_t RESERVED_61[2];
__IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: 0x200096 */
__IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */
__IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20009A */
uint8_t RESERVED_62[34];
__IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */
uint8_t RESERVED_63[64];
__IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200100 */
__IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200102 */
__IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200104 */
__IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200106 */
uint8_t RESERVED_64[16];
__IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200118 */
__IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20011A */
__IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20011C */
__IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20011E */
__IO uint16_t RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200120 */
__IO uint16_t RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200122 */
__IO uint16_t RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200124 */
uint8_t RESERVED_65[2];
__IO uint16_t RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200128 */
uint8_t RESERVED_66[86];
__IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200180 */
__IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200182 */
__IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200184 */
__IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200186 */
uint8_t RESERVED_67[24];
__IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2001A0 */
__IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2001A2 */
__IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2001A4 */
__IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2001A6 */
uint8_t RESERVED_68[218];
__IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282 */
uint8_t RESERVED_69[2];
__IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */
uint8_t RESERVED_70[10];
__IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */
uint8_t RESERVED_71[2];
__IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: 0x200296 */
uint8_t RESERVED_72[2];
__IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20029A */
uint8_t RESERVED_73[34];
__IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */
uint8_t RESERVED_74[64];
__IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200300 */
__IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200302 */
__IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200304 */
__IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200306 */
uint8_t RESERVED_75[16];
__IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200318 */
__IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20031A */
__IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20031C */
__IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20031E */
__IO uint16_t RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200320 */
__IO uint16_t RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200322 */
__IO uint16_t RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200324 */
uint8_t RESERVED_76[2];
__IO uint16_t RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200328 */
uint8_t RESERVED_77[86];
__IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200380 */
__IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200382 */
__IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200384 */
__IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200386 */
uint8_t RESERVED_78[24];
__IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2003A0 */
__IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2003A2 */
__IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2003A4 */
__IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2003A6 */
uint8_t RESERVED_79[472];
__IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200580 */
__IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200582 */
__IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200584 */
__IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200586 */
uint8_t RESERVED_80[504];
__IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200780 */
__IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200782 */
__IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200784 */
__IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200786 */
uint8_t RESERVED_81[504];
__IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200980 */
__IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200982 */
__IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200984 */
__IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200986 */
uint8_t RESERVED_82[504];
__IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200B80 */
__IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200B82 */
__IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200B84 */
__IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200B86 */
uint8_t RESERVED_83[504];
__IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200D80 */
__IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200D82 */
__IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200D84 */
__IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200D86 */
uint8_t RESERVED_84[504];
__IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200F80 */
__IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200F82 */
__IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200F84 */
__IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200F86 */
uint8_t RESERVED_85[504];
__IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x201180 */
__IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x201182 */
__IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x201184 */
__IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x201186 */
uint8_t RESERVED_86[2092728];
__IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */
uint8_t RESERVED_87[64];
__IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082 */
uint8_t RESERVED_88[2];
__IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */
uint8_t RESERVED_89[8];
__IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., offset: 0x400090 */
__IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */
uint8_t RESERVED_90[2];
__IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: 0x400096 */
__IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */
__IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40009A */
uint8_t RESERVED_91[34];
__IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */
uint8_t RESERVED_92[64];
__IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400100 */
__IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400102 */
__IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400104 */
__IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400106 */
uint8_t RESERVED_93[16];
__IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400118 */
__IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40011A */
__IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40011C */
__IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40011E */
__IO uint16_t RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400120 */
__IO uint16_t RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400122 */
__IO uint16_t RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400124 */
uint8_t RESERVED_94[2];
__IO uint16_t RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400128 */
uint8_t RESERVED_95[50];
__IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015C */
__IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x40015E */
uint8_t RESERVED_96[32];
__IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400180 */
__IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400182 */
__IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400184 */
__IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400186 */
uint8_t RESERVED_97[24];
__IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4001A0 */
__IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4001A2 */
__IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4001A4 */
__IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4001A6 */
uint8_t RESERVED_98[218];
__IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282 */
uint8_t RESERVED_99[2];
__IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */
uint8_t RESERVED_100[10];
__IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */
uint8_t RESERVED_101[2];
__IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: 0x400296 */
uint8_t RESERVED_102[2];
__IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40029A */
uint8_t RESERVED_103[34];
__IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */
uint8_t RESERVED_104[64];
__IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400300 */
__IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400302 */
__IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400304 */
__IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400306 */
uint8_t RESERVED_105[16];
__IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400318 */
__IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40031A */
__IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40031C */
__IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40031E */
__IO uint16_t RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400320 */
__IO uint16_t RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400322 */
__IO uint16_t RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400324 */
uint8_t RESERVED_106[2];
__IO uint16_t RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400328 */
uint8_t RESERVED_107[86];
__IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400380 */
__IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400382 */
__IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400384 */
__IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400386 */
uint8_t RESERVED_108[24];
__IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4003A0 */
__IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4003A2 */
__IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4003A4 */
__IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4003A6 */
uint8_t RESERVED_109[472];
__IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400580 */
__IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400582 */
__IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400584 */
__IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400586 */
uint8_t RESERVED_110[504];
__IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400780 */
__IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400782 */
__IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400784 */
__IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400786 */
uint8_t RESERVED_111[504];
__IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400980 */
__IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400982 */
__IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400984 */
__IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400986 */
uint8_t RESERVED_112[504];
__IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400B80 */
__IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400B82 */
__IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400B84 */
__IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400B86 */
uint8_t RESERVED_113[504];
__IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400D80 */
__IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400D82 */
__IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400D84 */
__IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400D86 */
uint8_t RESERVED_114[504];
__IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400F80 */
__IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400F82 */
__IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400F84 */
__IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400F86 */
uint8_t RESERVED_115[504];
__IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x401180 */
__IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x401182 */
__IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x401184 */
__IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x401186 */
uint8_t RESERVED_116[2092728];
__IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */
uint8_t RESERVED_117[64];
__IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082 */
uint8_t RESERVED_118[2];
__IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */
uint8_t RESERVED_119[8];
__IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., offset: 0x600090 */
__IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */
uint8_t RESERVED_120[2];
__IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: 0x600096 */
__IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */
__IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60009A */
uint8_t RESERVED_121[34];
__IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */
uint8_t RESERVED_122[64];
__IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600100 */
__IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600102 */
__IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600104 */
__IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600106 */
uint8_t RESERVED_123[16];
__IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600118 */
__IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60011A */
__IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60011C */
__IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60011E */
__IO uint16_t RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600120 */
__IO uint16_t RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600122 */
__IO uint16_t RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600124 */
uint8_t RESERVED_124[2];
__IO uint16_t RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600128 */
uint8_t RESERVED_125[50];
__IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015C */
__IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation, offset: 0x60015E */
uint8_t RESERVED_126[32];
__IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600180 */
__IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600182 */
__IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600184 */
__IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600186 */
uint8_t RESERVED_127[24];
__IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6001A0 */
__IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6001A2 */
__IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6001A4 */
__IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6001A6 */
uint8_t RESERVED_128[218];
__IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282 */
uint8_t RESERVED_129[2];
__IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */
uint8_t RESERVED_130[10];
__IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */
uint8_t RESERVED_131[2];
__IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: 0x600296 */
uint8_t RESERVED_132[2];
__IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60029A */
uint8_t RESERVED_133[34];
__IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */
uint8_t RESERVED_134[64];
__IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600300 */
__IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600302 */
__IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600304 */
__IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600306 */
uint8_t RESERVED_135[16];
__IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600318 */
__IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60031A */
__IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60031C */
__IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60031E */
__IO uint16_t RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600320 */
__IO uint16_t RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600322 */
__IO uint16_t RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600324 */
uint8_t RESERVED_136[2];
__IO uint16_t RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600328 */
uint8_t RESERVED_137[86];
__IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600380 */
__IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600382 */
__IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600384 */
__IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600386 */
uint8_t RESERVED_138[24];
__IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6003A0 */
__IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6003A2 */
__IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6003A4 */
__IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6003A6 */
uint8_t RESERVED_139[472];
__IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600580 */
__IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600582 */
__IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600584 */
__IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600586 */
uint8_t RESERVED_140[504];
__IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600780 */
__IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600782 */
__IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600784 */
__IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600786 */
uint8_t RESERVED_141[504];
__IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600980 */
__IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600982 */
__IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600984 */
__IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600986 */
uint8_t RESERVED_142[504];
__IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600B80 */
__IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600B82 */
__IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600B84 */
__IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600B86 */
uint8_t RESERVED_143[504];
__IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600D80 */
__IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600D82 */
__IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600D84 */
__IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600D86 */
uint8_t RESERVED_144[504];
__IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600F80 */
__IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600F82 */
__IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600F84 */
__IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600F86 */
uint8_t RESERVED_145[504];
__IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x601180 */
__IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x601182 */
__IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x601184 */
__IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x601186 */
} DWC_DDRPHYA_DBYTE_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_DBYTE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_DBYTE_Register_Masks DWC_DDRPHYA_DBYTE Register Masks
* @{
*/
/*! @name DBYTEMISCMODE - DBYTE Module Disable */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_MASK (0x4U)
#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_SHIFT (2U)
/*! DByteDisable - Controls whether this DBYTE module is disabled.
*/
#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_SHIFT)) & DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DBYTEDISABLE_MASK)
/*! @} */
/*! @name MTESTMUXSEL - Digital Observation Pin control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
/*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin.
*/
#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MTESTMUXSEL_MASK)
/*! @} */
/*! @name DFIMRL_P0 - DFI MaxReadLatency */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_MASK (0x1FU)
#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_SHIFT (0U)
/*! DFIMRL_p0 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_P0_MASK)
/*! @} */
/*! @name VREFDAC1_R0 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R0 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VREFDAC0_RX_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B0_P0 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B0_P0 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXEQUALIZATIONMODE_P0 - Tx dq driver equalization mode controls. */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_MASK (0x3U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_SHIFT (0U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TXEQMODE_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B0_P0 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL1 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_SHIFT (0U)
/*! PowerDownRcvr - Active high signal which powers down the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVR_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_MASK (0x200U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_SHIFT (9U)
/*! PowerDownRcvrDqs - Active high signal which powers down the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_POWERDOWNRCVRDQS_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_MASK (0x400U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_SHIFT (10U)
/*! RxPadStandbyEn - Enables the rxdq/rxdqs StandBy power savings, per pad-group.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RXPADSTANDBYEN_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_MASK (0x800U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_SHIFT (11U)
/*! EnLPReqPDR - Reserved for future use
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_ENLPREQPDR_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B0_P0 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL2_P0 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_SHIFT (0U)
/*! EnRxAgressivePDR - reserved
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_ENRXAGRESSIVEPDR_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B0_P0 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTSTRENN_MASK)
/*! @} */
/*! @name RXFIFOCHECKSTATUS - Status of RX FIFO Consistency Checks */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_SHIFT (0U)
/*! RxFifoRdLocErr - If set, the read pointer (DFI side) on the read FIFO associated with data bits [3:0] had a non-zero value at least once.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCERR_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_SHIFT (1U)
/*! RxFifoWrLocErr - If set, the write pointer (DQS side) on the read FIFO associated with data bits
* [3:0] has a non-zero value at least once.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCERR_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_MASK (0x4U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_SHIFT (2U)
/*! RxFifoRdLocUErr - If set, the read pointer (DFI side) on the read FIFO associated with data bits [7:4] has a non-zero value at least once.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFORDLOCUERR_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_MASK (0x8U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_SHIFT (3U)
/*! RxFifoWrLocUErr - If set, the write pointer (DQS side) on the read FIFO associated with data
* bits [7:4] has a non-zero value at least once.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RXFIFOWRLOCUERR_MASK)
/*! @} */
/*! @name RXFIFOCHECKERRVALUES - Contains the captured values associated with an RxFifo consistency error */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_SHIFT (0U)
/*! RxFifoRdLocErrValue - The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [3:0];
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCERRVALUE_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_SHIFT (4U)
/*! RxFifoWrLocErrValue - The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [3:0];
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCERRVALUE_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_MASK (0xF00U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_SHIFT (8U)
/*! RxFifoRdLocUErrValue - The first error value captured for the read pointer (DFI side) on the read FIFO associated with data bits [7:4];
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFORDLOCUERRVALUE_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_MASK (0xF000U)
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_SHIFT (12U)
/*! RxFifoWrLocUErrValue - The first error value captured for the write pointer (DQS side) on the read FIFO associated with data bits [7:4];
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RXFIFOWRLOCUERRVALUE_MASK)
/*! @} */
/*! @name RXFIFOINFO - Data Receive FIFO Pointer Values */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_SHIFT (0U)
/*! RxFifoRdLoc - The Mission mode read pointer of the lower-nibble Rx fifo.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOC_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_SHIFT (4U)
/*! RxFifoWrLoc - The Mission mode write pointer of the lower-nibble Rx fifo.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOC_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_MASK (0xF00U)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_SHIFT (8U)
/*! RxFifoRdLocU - The Mission mode read pointer of the upper-nibble Rx fifo.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFORDLOCU_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_MASK (0xF000U)
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_SHIFT (12U)
/*! RxFifoWrLocU - The Mission mode write pointer of the upper-nibble Rx fifo.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOINFO_RXFIFOWRLOCU_MASK)
/*! @} */
/*! @name RXFIFOVISIBILITY - RX FIFO visibility */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_MASK (0x7U)
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_SHIFT (0U)
/*! RxFifoRdPtr - If CSR RxFifoRdPtrOVr is set, then this CSR selects the rxfifo entry is visible in
* CSR This 3b field addresses 4b units of the 8x4b (32entry) fifo; that is,
* rdfifo_nibble_address[2:0]=csrRxFifoRdPtr[2:0] For example, Register RxFifoRdPtr[2:0]=2 will enable reading
* bit-entries 11.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTR_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_MASK (0x8U)
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_SHIFT (3U)
/*! RxFifoRdPtrOvr - 0 : Normal operation - mission mode read pointer is enabled 1 : Override -
* Control of the rx fifo read pointer is ceded to CSR RxFifoRdPtr.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDPTROVR_MASK)
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_MASK (0x10U)
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_SHIFT (4U)
/*! RxFifoRdEn - Pulse set 0-->1-->0 this bit to capture the Fifo Contents.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RXFIFORDEN_MASK)
/*! @} */
/*! @name RXFIFOCONTENTSDQ3210 - RX FIFO contents, lane[3:0] */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_SHIFT (0U)
/*! RxFifoContentsDQ3210 - A window into the contents of the RxFifo, as controlled by CSR
* RxFifoVisibility This register reads 4b at a time from lane0.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RXFIFOCONTENTSDQ3210_MASK)
/*! @} */
/*! @name RXFIFOCONTENTSDQ7654 - RX FIFO contents, lane[7:4] */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_SHIFT (0U)
/*! RxFifoContentsDQ7654 - A window into the contents of the RxFifo, as controlled by CSR
* RxFifoVisibility This register reads 4b at a time from lane4.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RXFIFOCONTENTSDQ7654_MASK)
/*! @} */
/*! @name RXFIFOCONTENTSDBI - RX FIFO contents, dbi */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_SHIFT (0U)
/*! RxFifoContentsDBI - A window into the contents of the RxFifo, as controlled by CSR
* RxFifoVisibility This register reads 4b at a time from DBI from the four fifo entries addressed by
* rdfifo_nibble_address[2:0]=RxFifoRdPtr[2:0] Register [ 3: 0] = dbi_ui3,dbi_ui2,dbi_ui1,dbi_ui0 Note
* that the DBYTE DBI lane is the same as the memory DBI; it is not subject to mapping using csr
* Dq<7.
*/
#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_SHIFT)) & DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RXFIFOCONTENTSDBI_MASK)
/*! @} */
/*! @name TXSLEWRATE_B0_P0 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R0 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R0 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R0 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R0 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name RXENDLYTG0_U0_P0 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U0_P0 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U0_P0 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U0_P0 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name DQLNSEL - Maps Phy DQ lane to memory DQ0 */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_MASK (0x7U)
#define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_SHIFT (0U)
/*! DqLnSel - Supports mapping of PHY dq to dram dq within a byte (swizzle).
*/
#define DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQLNSEL_DQLNSEL_MASK)
/*! @} */
/* The count of DWC_DDRPHYA_DBYTE_DQLNSEL */
#define DWC_DDRPHYA_DBYTE_DQLNSEL_COUNT (8U)
/*! @name TXDQDLYTG0_R0_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R0_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R0_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R0_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U0_P0 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U0_P0 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U0_P0 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U0_P0 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name DXLCDLSTATUS - Debug status of the DBYTE LCDL */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_SHIFT (0U)
/*! DxLcdlFineSnapVal - Value of the LCDL 1UI estimate code, latched by pulse on csr LcdlFineSnap while csr LcdlTstEnable=1.
*/
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLFINESNAPVAL_MASK)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_MASK (0x400U)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_SHIFT (10U)
/*! DxLcdlPhdSnapVal - Value of the LCDL phase-detector output, latched by pulse on csr LcdlFineSnap.
*/
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLPHDSNAPVAL_MASK)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_MASK (0x800U)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_SHIFT (11U)
/*! DxLcdlStickyLock - latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable.
*/
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYLOCK_MASK)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_MASK (0x1000U)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_SHIFT (12U)
/*! DxLcdlStickyUnlock - latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable.
*/
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLSTICKYUNLOCK_MASK)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_MASK (0x2000U)
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_SHIFT (13U)
/*! DxLcdlLiveLock - present value of whether the LCDL is locked, valid when LcdlTstEnable=1.
*/
#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_SHIFT)) & DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DXLCDLLIVELOCK_MASK)
/*! @} */
/*! @name VREFDAC1_R1 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R1 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VREFDAC0_RX_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B1_P0 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B1_P0 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B1_P0 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B1_P0 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B1_P0 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B1_P0 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R1 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R1 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R1 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R1 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name RXENDLYTG0_U1_P0 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U1_P0 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U1_P0 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U1_P0 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R1_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R1_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R1_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R1_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U1_P0 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U1_P0 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U1_P0 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U1_P0 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R2 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R2 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R2 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R2 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R2 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R2 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R2_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R2_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R2_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R2_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R3 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R3 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R3 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R3 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R3 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R3 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R3_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R3_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R3_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R3_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R4 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R4 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R4 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R4 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R4 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R4 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R4_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R4_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R4_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R4_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R5 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R5 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R5 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R5 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R5 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R5 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R5_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R5_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R5_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R5_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R6 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R6 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R6 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R6 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R6 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R6 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R6_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R6_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R6_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R6_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R7 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R7 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R7 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R7 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R7 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R7 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R7_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R7_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R7_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R7_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name VREFDAC1_R8 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_SHIFT (0U)
/*! VrefDAC1_rx - VrefDAC1 controls the alternate VREF setting for DFE (used only when DFE is
* enabled in DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The VREF generators
* have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 011,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VREFDAC1_RX_MASK)
/*! @} */
/*! @name VREFDAC0_R8 - VrefDAC0 control for DQ Receiver */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_SHIFT (0U)
/*! VrefDAC0_rx - PHY RX VREF DAC control for rxdq cell internal VREF, (used only when 2D training
* is enabled in LPDDR4,DDR4) DAC control for rxdq cell internal VREF, trained by Firmware The
* VREF generators have different ranges, depending on the Mission Mode settings for
* DqDqsRcvCntrl::MajorMode,DqDqsRcvCntrl::ExtVrefRange 000,0 :: VREF = VDDQ*(0.
*/
#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VREFDAC0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG0_R8 - Read DQ per-bit BDL delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_SHIFT (0U)
/*! RxPBDlyTg0_rx - Read DQ per-bit BDL delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RXPBDLYTG0_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG1_R8 - Read DQ per-bit BDL delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_SHIFT (0U)
/*! RxPBDlyTg1_rx - Read DQ per-bit BDL delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RXPBDLYTG1_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG2_R8 - Read DQ per-bit BDL delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_SHIFT (0U)
/*! RxPBDlyTg2_rx - Read DQ per-bit BDL delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RXPBDLYTG2_RX_MASK)
/*! @} */
/*! @name RXPBDLYTG3_R8 - Read DQ per-bit BDL delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_MASK (0x7FU)
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_SHIFT (0U)
/*! RxPBDlyTg3_rx - Read DQ per-bit BDL delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RXPBDLYTG3_RX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R8_P0 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R8_P0 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R8_P0 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R8_P0 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name DFIMRL_P1 - DFI MaxReadLatency */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_MASK (0x1FU)
#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_SHIFT (0U)
/*! DFIMRL_p1 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_P1_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B0_P1 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B0_P1 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXEQUALIZATIONMODE_P1 - Tx dq driver equalization mode controls. */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_MASK (0x3U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_SHIFT (0U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TXEQMODE_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B0_P1 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B0_P1 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL2_P1 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_SHIFT (0U)
/*! EnRxAgressivePDR - reserved
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_ENRXAGRESSIVEPDR_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B0_P1 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B0_P1 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U0_P1 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U0_P1 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U0_P1 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U0_P1 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R0_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R0_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R0_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R0_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U0_P1 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U0_P1 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U0_P1 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U0_P1 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B1_P1 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B1_P1 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B1_P1 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B1_P1 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B1_P1 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B1_P1 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U1_P1 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U1_P1 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U1_P1 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U1_P1 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R1_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R1_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R1_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R1_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U1_P1 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U1_P1 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U1_P1 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U1_P1 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R2_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R2_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R2_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R2_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R3_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R3_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R3_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R3_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R4_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R4_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R4_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R4_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R5_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R5_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R5_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R5_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R6_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R6_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R6_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R6_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R7_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R7_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R7_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R7_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R8_P1 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R8_P1 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R8_P1 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R8_P1 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name DFIMRL_P2 - DFI MaxReadLatency */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_MASK (0x1FU)
#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_SHIFT (0U)
/*! DFIMRL_p2 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_P2_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B0_P2 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B0_P2 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXEQUALIZATIONMODE_P2 - Tx dq driver equalization mode controls. */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_MASK (0x3U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_SHIFT (0U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TXEQMODE_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B0_P2 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B0_P2 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL2_P2 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_SHIFT (0U)
/*! EnRxAgressivePDR - reserved
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_ENRXAGRESSIVEPDR_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B0_P2 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B0_P2 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U0_P2 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U0_P2 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U0_P2 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U0_P2 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name PPTDQSCNTINVTRNTG0_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_SHIFT (0U)
/*! PptDqsCntInvTrnTg0_p2 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation.
*/
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PPTDQSCNTINVTRNTG0_P2_MASK)
/*! @} */
/*! @name PPTDQSCNTINVTRNTG1_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_SHIFT (0U)
/*! PptDqsCntInvTrnTg1_p2 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation.
*/
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PPTDQSCNTINVTRNTG1_P2_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R0_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R0_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R0_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R0_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U0_P2 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U0_P2 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U0_P2 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U0_P2 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B1_P2 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B1_P2 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B1_P2 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B1_P2 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B1_P2 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B1_P2 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U1_P2 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U1_P2 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U1_P2 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U1_P2 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R1_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R1_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R1_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R1_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U1_P2 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U1_P2 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U1_P2 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U1_P2 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R2_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R2_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R2_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R2_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R3_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R3_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R3_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R3_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R4_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R4_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R4_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R4_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R5_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R5_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R5_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R5_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R6_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R6_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R6_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R6_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R7_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R7_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R7_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R7_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R8_P2 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R8_P2 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R8_P2 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R8_P2 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name DFIMRL_P3 - DFI MaxReadLatency */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_MASK (0x1FU)
#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_SHIFT (0U)
/*! DFIMRL_p3 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_P3_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B0_P3 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B0_P3 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXEQUALIZATIONMODE_P3 - Tx dq driver equalization mode controls. */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_MASK (0x3U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_SHIFT (0U)
#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TXEQMODE_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B0_P3 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B0_P3 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL2_P3 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_SHIFT (0U)
/*! EnRxAgressivePDR - reserved
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_ENRXAGRESSIVEPDR_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B0_P3 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B0_P3 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U0_P3 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U0_P3 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U0_P3 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U0_P3 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name PPTDQSCNTINVTRNTG0_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_SHIFT (0U)
/*! PptDqsCntInvTrnTg0_p3 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation.
*/
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PPTDQSCNTINVTRNTG0_P3_MASK)
/*! @} */
/*! @name PPTDQSCNTINVTRNTG1_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_SHIFT (0U)
/*! PptDqsCntInvTrnTg1_p3 - Programmed by PHY training firmware to support LPDDR3/LPDDR4 DRAM drift compensation.
*/
#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_SHIFT)) & DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PPTDQSCNTINVTRNTG1_P3_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R0_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R0_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R0_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R0_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U0_P3 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U0_P3 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U0_P3 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U0_P3 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL0_B1_P3 - Data TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_SHIFT (0U)
/*! DrvStrenDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_SHIFT (6U)
/*! DrvStrenDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull down output impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DRVSTRENDQN_MASK)
/*! @} */
/*! @name DQDQSRCVCNTRL_B1_P3 - Dq/Dqs receiver control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_MASK (0x1U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_SHIFT (0U)
/*! SelAnalogVref - Setting this signal high will force the local per-bit VREF generator to pass the global VREFA to the samplers.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SELANALOGVREF_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_MASK (0x2U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_SHIFT (1U)
/*! ExtVrefRange - Extends the range available in the local per-bit VREF generator.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_EXTVREFRANGE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_MASK (0xCU)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_SHIFT (2U)
/*! DfeCtrl - DFE may be used with MajorModeDbyte=011 only 00 - DFE off 01 - DFE on 10 - Train DFE0
* Amplifier 11 - Train DFE1 Amplifier These settings are determined by PHY Training FW and
* should not be overridden.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DFECTRL_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_MASK (0x70U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_SHIFT (4U)
/*! MajorModeDbyte - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MAJORMODEDBYTE_MASK)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_MASK (0xF80U)
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_SHIFT (7U)
/*! GainCurrAdj - Adjust gain current of RX amplifier stage.
*/
#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_SHIFT)) & DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GAINCURRADJ_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL1_B1_P3 - TX impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_SHIFT (0U)
/*! DrvStrenFSDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_SHIFT (6U)
/*! DrvStrenFSDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit bus
* used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DRVSTRENFSDQN_MASK)
/*! @} */
/*! @name TXIMPEDANCECTRL2_B1_P3 - TX equalization impedance controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_SHIFT (0U)
/*! DrvStrenEQHiDqP - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull up output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQHIDQP_MASK)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_SHIFT (6U)
/*! DrvStrenEQLoDqN - Please Refer to Technology specific PHY DATABOOK for supported options 6 bit
* bus used to select the target pull down output impedance used in equalization.
*/
#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DRVSTRENEQLODQN_MASK)
/*! @} */
/*! @name TXODTDRVSTREN_B1_P3 - TX ODT driver strength control */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_SHIFT (0U)
/*! ODTStrenP - Selects the ODT pull-up impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENP_MASK)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_MASK (0xFC0U)
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_SHIFT (6U)
/*! ODTStrenN - Selects the ODT pull-down impedance.
*/
#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTSTRENN_MASK)
/*! @} */
/*! @name TXSLEWRATE_B1_P3 - TX slew rate controls */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_MASK (0xFU)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_SHIFT (0U)
/*! TxPreP - 4 bit binary trim for the driver pull up slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREP_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_MASK (0xF0U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_SHIFT (4U)
/*! TxPreN - 4 bit binary trim for the driver pull down slew rate.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREN_MASK)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_MASK (0x700U)
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_SHIFT (8U)
/*! TxPreDrvMode - Controls predrivers to adjust timing of turn-on and turn-off of pull-up and pull-down segments.
*/
#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_SHIFT)) & DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TXPREDRVMODE_MASK)
/*! @} */
/*! @name RXENDLYTG0_U1_P3 - Trained Receive Enable Delay (For Timing Group 0) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_SHIFT (0U)
/*! RxEnDlyTg0_un_px - Trained Receive Enable Delay (For Timing Group 0) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RXENDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG1_U1_P3 - Trained Receive Enable Delay (For Timing Group 1) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_SHIFT (0U)
/*! RxEnDlyTg1_un_px - Trained Receive Enable Delay (For Timing Group 1) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RXENDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG2_U1_P3 - Trained Receive Enable Delay (For Timing Group 2) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_SHIFT (0U)
/*! RxEnDlyTg2_un_px - Trained Receive Enable Delay (For Timing Group 2) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RXENDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXENDLYTG3_U1_P3 - Trained Receive Enable Delay (For Timing Group 3) */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_MASK (0x7FFU)
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_SHIFT (0U)
/*! RxEnDlyTg3_un_px - Trained Receive Enable Delay (For Timing Group 3) Trained to set the delay
* from the memory-read command to the signal enabling the read DQS to generate read-data strobes.
*/
#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RXENDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG0_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkDlyTg0_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RXCLKDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG1_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkDlyTg1_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RXCLKDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG2_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkDlyTg2_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RXCLKDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKDLYTG3_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkDlyTg3_un_px - Trained Read DQS to RxClk Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RXCLKDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG0_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg0_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RXCLKCDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG1_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg1_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RXCLKCDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG2_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg2_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RXCLKCDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name RXCLKCDLYTG3_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_MASK (0x3FU)
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_SHIFT (0U)
/*! RxClkcDlyTg3_un_px - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RXCLKCDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R1_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R1_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R1_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R1_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG0_U1_P3 - Write DQS Delay (Timing Group DEST=0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg0_un_px - Write DQS Delay (Timing Group DEST=0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TXDQSDLYTG0_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG1_U1_P3 - Write DQS Delay (Timing Group DEST=1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg1_un_px - Write DQS Delay (Timing Group DEST=1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TXDQSDLYTG1_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG2_U1_P3 - Write DQS Delay (Timing Group DEST=2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg2_un_px - Write DQS Delay (Timing Group DEST=2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TXDQSDLYTG2_UN_PX_MASK)
/*! @} */
/*! @name TXDQSDLYTG3_U1_P3 - Write DQS Delay (Timing Group DEST=3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_MASK (0x3FFU)
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_SHIFT (0U)
/*! TxDqsDlyTg3_un_px - Write DQS Delay (Timing Group DEST=3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TXDQSDLYTG3_UN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R2_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R2_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R2_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R2_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R3_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R3_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R3_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R3_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R4_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R4_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R4_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R4_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R5_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R5_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R5_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R5_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R6_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R6_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R6_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R6_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R7_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R7_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R7_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R7_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG0_R8_P3 - Write DQ Delay (Timing Group 0). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_SHIFT (0U)
/*! TxDqDlyTg0_rn_px - Write DQ Delay (Timing Group 0).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TXDQDLYTG0_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG1_R8_P3 - Write DQ Delay (Timing Group 1). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_SHIFT (0U)
/*! TxDqDlyTg1_rn_px - Write DQ Delay (Timing Group 1).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TXDQDLYTG1_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG2_R8_P3 - Write DQ Delay (Timing Group 2). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_SHIFT (0U)
/*! TxDqDlyTg2_rn_px - Write DQ Delay (Timing Group 2).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TXDQDLYTG2_RN_PX_MASK)
/*! @} */
/*! @name TXDQDLYTG3_R8_P3 - Write DQ Delay (Timing Group 3). */
/*! @{ */
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_MASK (0x1FFU)
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_SHIFT (0U)
/*! TxDqDlyTg3_rn_px - Write DQ Delay (Timing Group 3).
*/
#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_SHIFT)) & DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TXDQDLYTG3_RN_PX_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_DBYTE_Register_Masks */
/* DWC_DDRPHYA_DBYTE - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_DBYTE0 base address */
#define DWC_DDRPHYA_DBYTE0_BASE (0x3C010000u)
/** Peripheral DWC_DDRPHYA_DBYTE0 base pointer */
#define DWC_DDRPHYA_DBYTE0 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE0_BASE)
/** Peripheral DWC_DDRPHYA_DBYTE1 base address */
#define DWC_DDRPHYA_DBYTE1_BASE (0x3C011000u)
/** Peripheral DWC_DDRPHYA_DBYTE1 base pointer */
#define DWC_DDRPHYA_DBYTE1 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE1_BASE)
/** Peripheral DWC_DDRPHYA_DBYTE2 base address */
#define DWC_DDRPHYA_DBYTE2_BASE (0x3C012000u)
/** Peripheral DWC_DDRPHYA_DBYTE2 base pointer */
#define DWC_DDRPHYA_DBYTE2 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE2_BASE)
/** Peripheral DWC_DDRPHYA_DBYTE3 base address */
#define DWC_DDRPHYA_DBYTE3_BASE (0x3C013000u)
/** Peripheral DWC_DDRPHYA_DBYTE3 base pointer */
#define DWC_DDRPHYA_DBYTE3 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE3_BASE)
/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base addresses */
#define DWC_DDRPHYA_DBYTE_BASE_ADDRS { DWC_DDRPHYA_DBYTE0_BASE, DWC_DDRPHYA_DBYTE1_BASE, DWC_DDRPHYA_DBYTE2_BASE, DWC_DDRPHYA_DBYTE3_BASE }
/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base pointers */
#define DWC_DDRPHYA_DBYTE_BASE_PTRS { DWC_DDRPHYA_DBYTE0, DWC_DDRPHYA_DBYTE1, DWC_DDRPHYA_DBYTE2, DWC_DDRPHYA_DBYTE3 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_DRTUB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer DWC_DDRPHYA_DRTUB Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_DRTUB - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[256];
__IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */
__IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */
uint8_t RESERVED_1[214];
__I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0x1DA */
__I uint16_t PUBREV; /**< The hardware version of this PUB, excluding the PHY, offset: 0x1DC */
} DWC_DDRPHYA_DRTUB_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_DRTUB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_DRTUB_Register_Masks DWC_DDRPHYA_DRTUB Register Masks
* @{
*/
/*! @name UCCLKHCLKENABLES - Ucclk and Hclk enables */
/*! @{ */
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_MASK (0x1U)
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_SHIFT (0U)
/*! UcclkEn - When training has completed (and assuming no further need for the microcontroller),
* the enable should be set to 0 to reduce power.
*/
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UCCLKEN_MASK)
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_MASK (0x2U)
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_SHIFT (1U)
/*! HclkEn - When training has completed (and assuming no further need for the training hardware),
* the enable should be set to 0 to reduce power.
*/
#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_SHIFT)) & DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HCLKEN_MASK)
/*! @} */
/*! @name CURPSTATE0B - PIE current Pstate value */
/*! @{ */
#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_MASK (0xFU)
#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_SHIFT (0U)
/*! CurPstate0b - PIE current Pstate value This register is used to select values for writing by the
* Pstate sequencer and is written in the beginning of the Pstate switch.
*/
#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_SHIFT)) & DWC_DDRPHYA_DRTUB_CURPSTATE0B_CURPSTATE0B_MASK)
/*! @} */
/*! @name CUSTPUBREV - Customer settable by the customer */
/*! @{ */
#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK (0x3FU)
#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT (0U)
/*! CUSTPUBREV - The customer settable PUB version number.
*/
#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT)) & DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK)
/*! @} */
/*! @name PUBREV - The hardware version of this PUB, excluding the PHY */
/*! @{ */
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK (0xFU)
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT (0U)
/*! PUBMNR - Indicates minor update of the PUB.
*/
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK)
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK (0xF0U)
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT (4U)
/*! PUBMDR - Indicates moderate revision of the PUB.
*/
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK)
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK (0xFF00U)
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT (8U)
/*! PUBMJR - Indicates major revision of the PUB.
*/
#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_DRTUB_Register_Masks */
/* DWC_DDRPHYA_DRTUB - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_DRTUB0 base address */
#define DWC_DDRPHYA_DRTUB0_BASE (0x3C0C0000u)
/** Peripheral DWC_DDRPHYA_DRTUB0 base pointer */
#define DWC_DDRPHYA_DRTUB0 ((DWC_DDRPHYA_DRTUB_Type *)DWC_DDRPHYA_DRTUB0_BASE)
/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base addresses */
#define DWC_DDRPHYA_DRTUB_BASE_ADDRS { DWC_DDRPHYA_DRTUB0_BASE }
/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base pointers */
#define DWC_DDRPHYA_DRTUB_BASE_PTRS { DWC_DDRPHYA_DRTUB0 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_INITENG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_INITENG_Peripheral_Access_Layer DWC_DDRPHYA_INITENG Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_INITENG - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[80];
__IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status, offset: 0x50 */
} DWC_DDRPHYA_INITENG_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_INITENG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_INITENG_Register_Masks DWC_DDRPHYA_INITENG Register Masks
* @{
*/
/*! @name PHYINLP3 - Indicator for PIE Lower Power 3 (LP3) Status */
/*! @{ */
#define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_MASK (0x1U)
#define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_SHIFT (0U)
/*! PhyInLP3 - Read Only.
*/
#define DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_SHIFT)) & DWC_DDRPHYA_INITENG_PHYINLP3_PHYINLP3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_INITENG_Register_Masks */
/* DWC_DDRPHYA_INITENG - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_INITENG0 base address */
#define DWC_DDRPHYA_INITENG0_BASE (0x3C090000u)
/** Peripheral DWC_DDRPHYA_INITENG0 base pointer */
#define DWC_DDRPHYA_INITENG0 ((DWC_DDRPHYA_INITENG_Type *)DWC_DDRPHYA_INITENG0_BASE)
/** Array initializer of DWC_DDRPHYA_INITENG peripheral base addresses */
#define DWC_DDRPHYA_INITENG_BASE_ADDRS { DWC_DDRPHYA_INITENG0_BASE }
/** Array initializer of DWC_DDRPHYA_INITENG peripheral base pointers */
#define DWC_DDRPHYA_INITENG_BASE_PTRS { DWC_DDRPHYA_INITENG0 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_INITENG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_MASTER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_MASTER_Peripheral_Access_Layer DWC_DDRPHYA_MASTER Peripheral Access Layer
* @{
*/
/** DWC_DDRPHYA_MASTER - Register Layout Typedef */
typedef struct {
__IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offset: 0x0 */
__IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */
uint8_t RESERVED_0[2];
__IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to force an internal PHY Update Event., offset: 0x6 */
__I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offset: 0x8 */
__IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., offset: 0xA */
uint8_t RESERVED_1[2];
__IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */
__IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0x10 */
uint8_t RESERVED_2[2];
__IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */
__IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x16 */
__IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x18 */
__IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x1A */
__IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x1C */
__I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */
__IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operations, offset: 0x20 */
uint8_t RESERVED_3[2];
__IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */
uint8_t RESERVED_4[2];
__I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offset: 0x28 */
__I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offset: 0x2A */
__IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset: 0x2C */
__IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset: 0x2E */
__IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces for DFI0 and DFI1, offset: 0x30 */
__IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x32 */
__IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
__IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for debug, offset: 0x36 */
__IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 */
uint8_t RESERVED_5[2];
__IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */
uint8_t RESERVED_6[2];
__IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */
__IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCLKs), offset: 0x42 */
__IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dram-Addressing of MRS, offset: 0x44 */
__IO uint16_t DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause CS and CKE timing to change., offset: 0x46 */
__IO uint16_t DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x48 */
__IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram device mode, offset: 0x4A */
__IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select., offset: 0x4C */
__IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0], offset: 0x4E */
__IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training, offset: 0x50 */
uint8_t RESERVED_7[6];
__IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58 */
__IO uint16_t DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x5A */
__IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x5C */
uint8_t RESERVED_8[22];
__IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x74 */
uint8_t RESERVED_9[20];
__IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offset: 0x8A */
uint8_t RESERVED_10[2];
__IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */
uint8_t RESERVED_11[2];
__IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control, offset: 0x92 */
__IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offset: 0x94 */
__IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control, offset: 0x96 */
uint8_t RESERVED_12[8];
__IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength control, offset: 0xA0 */
uint8_t RESERVED_13[10];
__IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0xAC */
uint8_t RESERVED_14[8];
__IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB6 */
__IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB8 */
uint8_t RESERVED_15[6];
__IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, offset: 0xC0 */
uint8_t RESERVED_16[24];
__IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
__IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */
__I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */
__IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses the final PAD node., offset: 0xE0 */
__IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE2 */
uint8_t RESERVED_17[4];
__IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE8 */
__IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */
uint8_t RESERVED_18[4];
__IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, offset: 0xF0 */
__IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */
uint8_t RESERVED_19[4];
__IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */
uint8_t RESERVED_20[22];
__IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110 */
__IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x112 */
uint8_t RESERVED_21[2];
__IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */
uint8_t RESERVED_22[2];
__IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */
uint8_t RESERVED_23[4];
__IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Done), offset: 0x120 */
uint8_t RESERVED_24[12];
__I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0x12E */
__IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls., offset: 0x130 */
uint8_t RESERVED_25[2];
__IO uint16_t CALMISC; /**< Controls for disabling the impedance calibration of certain targets., offset: 0x134 */
__I uint16_t CALVREFS; /**< , offset: 0x136 */
__I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: 0x138 */
__I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: 0x13A */
__I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: 0x13C */
uint8_t RESERVED_26[18];
__IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, offset: 0x150 */
uint8_t RESERVED_27[10];
__IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset: 0x15C */
uint8_t RESERVED_28[2];
__IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x160 */
uint8_t RESERVED_29[2];
__IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */
uint8_t RESERVED_30[2];
__IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x168 */
__I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updates (PPTs), offset: 0x16A */
__I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interface Updates, offset: 0x16C */
__I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interface Updates, offset: 0x16E */
__I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Interface Updates, offset: 0x170 */
__I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Interface Updates, offset: 0x172 */
__I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Updates, offset: 0x174 */
__I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Interface Updates, offset: 0x176 */
__I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Interface Updates, offset: 0x178 */
__IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x17A */
uint8_t RESERVED_31[10];
__IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */
__IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */
__IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, offset: 0x18A */
__IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */
__IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, offset: 0x18E */
__IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 */
__I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */
__IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x194 */
__IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */
__IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, offset: 0x198 */
__I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offset: 0x19A */
__I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output, offset: 0x19C */
__I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */
uint8_t RESERVED_32[38];
__IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing the LCDLs., offset: 0x1C6 */
__I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
uint8_t RESERVED_33[16];
__I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0x1DA */
__I uint16_t PHYREV; /**< The hardware version of this PHY, excluding the PUB, offset: 0x1DC */
__IO uint16_t LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit or Init PIE Sequence, offset: 0x1DE */
__IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset: 0x1E0 */
__IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset: 0x1E2 */
__IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset: 0x1E4 */
__IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset: 0x1E6 */
__IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset: 0x1E8 */
__IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset: 0x1EA */
__IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset: 0x1EC */
__IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset: 0x1EE */
__IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 */
__IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */
__IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */
__IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of the RX FIFOs, offset: 0x1F6 */
uint8_t RESERVED_34[6];
__IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */
__IO uint16_t MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the index of the register contents, offset: 0x200 */
__IO uint16_t MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the index of the register contents, offset: 0x202 */
__IO uint16_t MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the index of the register contents, offset: 0x204 */
__IO uint16_t MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the index of the register contents, offset: 0x206 */
__IO uint16_t MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the index of the register contents, offset: 0x208 */
__IO uint16_t MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the index of the register contents, offset: 0x20A */
__IO uint16_t MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the index of the register contents, offset: 0x20C */
__IO uint16_t MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the index of the register contents, offset: 0x20E */
__IO uint16_t MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the index of the register contents, offset: 0x210 */
__IO uint16_t MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the index of the register contents, offset: 0x212 */
uint8_t RESERVED_35[12];
__IO uint16_t MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the index of the register contents, offset: 0x220 */
__IO uint16_t MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the index of the register contents, offset: 0x222 */
__IO uint16_t MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the index of the register contents, offset: 0x224 */
__IO uint16_t MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the index of the register contents, offset: 0x226 */
__IO uint16_t MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the index of the register contents, offset: 0x228 */
__IO uint16_t MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the index of the register contents, offset: 0x22A */
__IO uint16_t MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the index of the register contents, offset: 0x22C */
__IO uint16_t MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the index of the register contents, offset: 0x22E */
__IO uint16_t MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the index of the register contents, offset: 0x230 */
__IO uint16_t MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the index of the register contents, offset: 0x232 */
uint8_t RESERVED_36[2];
__IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */
__IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x238 */
__IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */
__IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */
__I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */
__IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, offset: 0x240 */
__IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, offset: 0x242 */
__IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, offset: 0x244 */
__IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, offset: 0x246 */
__IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, offset: 0x248 */
__IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, offset: 0x24A */
__IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, offset: 0x24C */
__IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, offset: 0x24E */
__IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, offset: 0x250 */
__IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, offset: 0x252 */
__IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, offset: 0x254 */
__IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, offset: 0x256 */
__IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, offset: 0x258 */
__IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, offset: 0x25A */
__IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, offset: 0x25C */
__IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, offset: 0x25E */
__IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, offset: 0x260 */
__IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, offset: 0x262 */
__IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, offset: 0x264 */
__IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, offset: 0x266 */
__IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, offset: 0x268 */
__IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, offset: 0x26A */
__IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, offset: 0x26C */
__IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x26E */
__IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x270 */
__IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, offset: 0x272 */
__IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, offset: 0x274 */
uint8_t RESERVED_37[2];
__IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x278 */
__IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays, offset: 0x27A */
uint8_t RESERVED_38[2096532];
__IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0x200010 */
uint8_t RESERVED_39[4];
__IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x200016 */
__IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x200018 */
__IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x20001A */
__IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x20001C */
uint8_t RESERVED_40[2];
__IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operations, offset: 0x200020 */
uint8_t RESERVED_41[16];
__IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x200032 */
uint8_t RESERVED_42[12];
__IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */
uint8_t RESERVED_43[6];
__IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x200048 */
uint8_t RESERVED_44[16];
__IO uint16_t DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x20005A */
__IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x20005C */
uint8_t RESERVED_45[78];
__IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x2000AC */
uint8_t RESERVED_46[74];
__IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */
uint8_t RESERVED_47[102];
__IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200160 */
uint8_t RESERVED_48[2];
__IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */
uint8_t RESERVED_49[2];
__IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x200168 */
uint8_t RESERVED_50[32];
__IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, offset: 0x20018A */
uint8_t RESERVED_51[2];
__IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, offset: 0x20018E */
uint8_t RESERVED_52[4];
__IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x200194 */
uint8_t RESERVED_53[2];
__IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, offset: 0x200198 */
uint8_t RESERVED_54[90];
__IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */
uint8_t RESERVED_55[2096666];
__IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0x400010 */
uint8_t RESERVED_56[4];
__IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x400016 */
__IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x400018 */
__IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x40001A */
__IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x40001C */
uint8_t RESERVED_57[2];
__IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operations, offset: 0x400020 */
uint8_t RESERVED_58[16];
__IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x400032 */
uint8_t RESERVED_59[12];
__IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */
uint8_t RESERVED_60[6];
__IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x400048 */
uint8_t RESERVED_61[16];
__IO uint16_t DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x40005A */
__IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x40005C */
uint8_t RESERVED_62[78];
__IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x4000AC */
uint8_t RESERVED_63[74];
__IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */
uint8_t RESERVED_64[102];
__IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400160 */
uint8_t RESERVED_65[2];
__IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */
uint8_t RESERVED_66[2];
__IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x400168 */
uint8_t RESERVED_67[32];
__IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, offset: 0x40018A */
uint8_t RESERVED_68[2];
__IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, offset: 0x40018E */
uint8_t RESERVED_69[4];
__IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x400194 */
uint8_t RESERVED_70[2];
__IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, offset: 0x400198 */
uint8_t RESERVED_71[90];
__IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */
uint8_t RESERVED_72[2096666];
__IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0x600010 */
uint8_t RESERVED_73[4];
__IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x600016 */
__IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x600018 */
__IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x60001A */
__IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x60001C */
uint8_t RESERVED_74[2];
__IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operations, offset: 0x600020 */
uint8_t RESERVED_75[16];
__IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x600032 */
uint8_t RESERVED_76[12];
__IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */
uint8_t RESERVED_77[6];
__IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x600048 */
uint8_t RESERVED_78[16];
__IO uint16_t DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x60005A */
__IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x60005C */
uint8_t RESERVED_79[78];
__IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x6000AC */
uint8_t RESERVED_80[74];
__IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */
uint8_t RESERVED_81[102];
__IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600160 */
uint8_t RESERVED_82[2];
__IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */
uint8_t RESERVED_83[2];
__IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM, offset: 0x600168 */
uint8_t RESERVED_84[32];
__IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, offset: 0x60018A */
uint8_t RESERVED_85[2];
__IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, offset: 0x60018E */
uint8_t RESERVED_86[4];
__IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x600194 */
uint8_t RESERVED_87[2];
__IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, offset: 0x600198 */
uint8_t RESERVED_88[90];
__IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */
} DWC_DDRPHYA_MASTER_Type;
/* ----------------------------------------------------------------------------
-- DWC_DDRPHYA_MASTER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DWC_DDRPHYA_MASTER_Register_Masks DWC_DDRPHYA_MASTER Register Masks
* @{
*/
/*! @name RXFIFOINIT - Rx FIFO pointer initialization control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_SHIFT (0U)
/*! RxFifoInitPtr - Setting this bit will reset the PHY RXDATAFIFO read and write pointers.
*/
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_RXFIFOINITPTR_MASK)
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_SHIFT (1U)
/*! InhibitRxFifoRd - This field is reserved for training FW use.
*/
#define DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOINIT_INHIBITRXFIFORD_MASK)
/*! @} */
/*! @name FORCECLKDISABLE - Clock gating control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_SHIFT (0U)
/*! ForceClkDisable - This CSR forces the gating of MEMCLKs driven from the PHY ForceClkDisable[0] -
* controls CLK_H/L0 ForceClkDisable[1] - controls CLK_H/L1 (if present) ForceClkDisable[2] -
* controls CLK_H/L2 (if present) ForceClkDisable[3] - controls CLK_H/L3 (if present)
*/
#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_SHIFT)) & DWC_DDRPHYA_MASTER_FORCECLKDISABLE_FORCECLKDISABLE_MASK)
/*! @} */
/*! @name FORCEINTERNALUPDATE - This Register used by Training Firmware to force an internal PHY Update Event. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_SHIFT (0U)
/*! ForceInternalUpdate - This Register is used by Training Firmware to force an internal PHY Update Event.
*/
#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_SHIFT)) & DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_FORCEINTERNALUPDATE_MASK)
/*! @} */
/*! @name PHYCONFIG - Read Only displays PHY Configuration. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_SHIFT (0U)
/*! PhyConfigAnibs - Returns the following value .
*/
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGANIBS_MASK)
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_SHIFT (4U)
/*! PhyConfigDbytes - Returns the following value .
*/
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDBYTES_MASK)
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_MASK (0x300U)
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_SHIFT (8U)
/*! PhyConfigDfi - Returns the following value .
*/
#define DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_SHIFT)) & DWC_DDRPHYA_MASTER_PHYCONFIG_PHYCONFIGDFI_MASK)
/*! @} */
/*! @name PGCR - PHY General Configuration Register(PGCR). */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_SHIFT (0U)
/*! RxClkRiseFallMode - This register field controls independent training for RxClk_c and RxClk_t.
*/
#define DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PGCR_RXCLKRISEFALLMODE_MASK)
/*! @} */
/*! @name TESTBUMPCNTRL1 - Test Bump Control1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_SHIFT (0U)
/*! TestMajorMode - Selects the major mode of operation for the receiver.
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTMAJORMODE_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_MASK (0x8U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_SHIFT (3U)
/*! TestBiasBypassEn - Do not use, for debug only
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTBIASBYPASSEN_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_SHIFT (4U)
/*! TestAnalogOutCtrl - Select receiver internal analog signals to monitor at analog test point
* 0xxx: AnalogTestOut=HiZ 1000: AnalogTestOut=VSS 1001: AnalogTestOut=vref_dfe0 -- observe by
* sweeping MALERTVrefLevel 1010: AnalogTestOut=vref_dfe1 -- observe by sweeping MALERTVrefLevel 1011:
* AnalogTestOut=VSS 1100: AnalogTestOut=vstg2 1101: AnalogTestOut=vcasc_cs1 1110:
* AnalogTestOut=vbias_cs1 Recommended mission mode default = 4'b0000
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTANALOGOUTCTRL_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_MASK (0x1F00U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_SHIFT (8U)
/*! TestGainCurrAdj - Adjust gain and current of analog observe RX amplifier stage at analog test
* point Recommended mission mode default = 5'b01011
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTGAINCURRADJ_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_MASK (0x2000U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_SHIFT (13U)
/*! TestSelExternalVref - Do not use, for debug only
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTSELEXTERNALVREF_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_SHIFT (14U)
/*! TestExtVrefRange - Setting this bit will extend the VREF DAC range for debug.
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTEXTVREFRANGE_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_MASK (0x8000U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_SHIFT (15U)
/*! TestPowerGateEn - Do not use, for debug only
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TESTPOWERGATEEN_MASK)
/*! @} */
/*! @name CALUCLKINFO_P0 - Impedance Calibration Clock Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_MASK (0x3FFU)
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_SHIFT (0U)
/*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24.
*/
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CALUCLKTICKSPER1US_MASK)
/*! @} */
/*! @name TESTBUMPCNTRL - Test Bump Control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_SHIFT (0U)
/*! TestBumpEn - Field TestBumpEn[1:0] controls the output function of: the signal BP_ALERT_N.
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPEN_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_SHIFT (2U)
/*! TestBumpToggle - This field controls the output function of the signal Digital Observation Pin,
* if available in the configuration of the PHY.
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPTOGGLE_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_MASK (0x1F8U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_SHIFT (3U)
/*! TestBumpDataSel - RVSD.
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TESTBUMPDATASEL_MASK)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_MASK (0x200U)
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_SHIFT (9U)
/*! ForceMtestOnAlert - When set, causes the Digital Observation output pin to be driven onto BP_ALERT_N
*/
#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_SHIFT)) & DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_FORCEMTESTONALERT_MASK)
/*! @} */
/*! @name SEQ0BDLY0_P0 - PHY Initialization Engine (PIE) Delay Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_SHIFT (0U)
/*! Seq0BDLY0_p0 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_SEQ0BDLY0_P0_MASK)
/*! @} */
/*! @name SEQ0BDLY1_P0 - PHY Initialization Engine (PIE) Delay Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_SHIFT (0U)
/*! Seq0BDLY1_p0 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_SEQ0BDLY1_P0_MASK)
/*! @} */
/*! @name SEQ0BDLY2_P0 - PHY Initialization Engine (PIE) Delay Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_SHIFT (0U)
/*! Seq0BDLY2_p0 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_SEQ0BDLY2_P0_MASK)
/*! @} */
/*! @name SEQ0BDLY3_P0 - PHY Initialization Engine (PIE) Delay Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_SHIFT (0U)
/*! Seq0BDLY3_p0 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_SEQ0BDLY3_P0_MASK)
/*! @} */
/*! @name PHYALERTSTATUS - PHY Alert status bit */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_SHIFT (0U)
/*! PhyAlert - Current state of ALERT_N.
*/
#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PHYALERT_MASK)
/*! @} */
/*! @name PPTTRAINSETUP_P0 - Setup Intervals for DFI PHY Master operations */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_SHIFT (0U)
/*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRTRAININTERVAL_MASK)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_MASK (0x70U)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_SHIFT (4U)
/*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PHYMSTRMAXREQTOACK_MASK)
/*! @} */
/*! @name ATESTMODE - ATestMode control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_SHIFT (0U)
/*! ATestPrbsEn - Enables loopback PRBS7 testing of all the DDR output pins in this chiplet.
*/
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTPRBSEN_MASK)
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_SHIFT (1U)
/*! ATestClkEn - Enables the clock for loopback PRBS7 testing for all BP_A* pins.
*/
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTCLKEN_MASK)
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_MASK (0x1CU)
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_SHIFT (2U)
/*! ATestModeSel - Master Mode select for ATest (Loopback) 000 - Mission mode, all ATest disabled,
* loopback receivers powered down 001 - External Loopback mode [Single data rate pattern -
* dfi_cas sent to all lanes] 010 - Internal Loopback mode [Single data rate pattern] 011 - Internal
* Loopback mode [Double data rate pattern] 100 - External Loopback mode [Single data rate pattern
* - corresponding DFI signal sent to each lane]
*/
#define DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_SHIFT)) & DWC_DDRPHYA_MASTER_ATESTMODE_ATESTMODESEL_MASK)
/*! @} */
/*! @name TXCALBINP - TX P Impedance Calibration observation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_SHIFT (0U)
/*! TxCalBinP - This csr holds the binary result of the 31 bit thermometer pullup code.
*/
#define DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINP_TXCALBINP_MASK)
/*! @} */
/*! @name TXCALBINN - TX N Impedance Calibration observation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_SHIFT (0U)
/*! TxCalBinN - This csr holds the binary result of the 31 bit thermometer pulldown code.
*/
#define DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALBINN_TXCALBINN_MASK)
/*! @} */
/*! @name TXCALPOVR - TX P Impedance Calibration override */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_SHIFT (0U)
/*! TxCalBinPOvrVal - The binary value which can overide the Register TxCalBinP calibrator results if Register TxCalBinPOvrEn is set.
*/
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVRVAL_MASK)
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_SHIFT (5U)
/*! TxCalBinPOvrEn - 1 = use the override value present in Register TxCalBinPOvrVal 0 = don't.
*/
#define DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALPOVR_TXCALBINPOVREN_MASK)
/*! @} */
/*! @name TXCALNOVR - TX N Impedance Calibration override */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_SHIFT (0U)
/*! TxCalBinNOvrVal - The binary value which can overide the Register TxCalBinN calibrator results if Register TxCalBinPOvrEn is set.
*/
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVRVAL_MASK)
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_SHIFT (5U)
/*! TxCalBinNOvrEn - 1 = use the override value present in Register TxCalBinNOvrVal 0 = don't.
*/
#define DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_SHIFT)) & DWC_DDRPHYA_MASTER_TXCALNOVR_TXCALBINNOVREN_MASK)
/*! @} */
/*! @name DFIMODE - Enables for update and low-power interfaces for DFI0 and DFI1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_SHIFT (0U)
/*! Dfi0Enable - Enables operation for the PHY logic associated with DFI0
*/
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI0ENABLE_MASK)
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_SHIFT (1U)
/*! Dfi1Enable - Enables operation for the PHY logic associated with DFI1
*/
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI1ENABLE_MASK)
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_SHIFT (2U)
/*! Dfi1Override - DFI0 is used to control the PHY logic associated with both DFI0 and DFI1
*/
#define DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIMODE_DFI1OVERRIDE_MASK)
/*! @} */
/*! @name TRISTATEMODECA_P0 - Mode select register for MEMCLK/Address/Command Tristates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_SHIFT (0U)
/*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DISDYNADRTRI_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_SHIFT (1U)
/*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMODE_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_SHIFT (2U)
/*! CkDisVal - The PHY provides 4 memory clocks, n=0.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CKDISVAL_MASK)
/*! @} */
/*! @name MTESTMUXSEL - Digital Observation Pin control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_MASK (0x3FU)
#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_SHIFT (0U)
/*! MtestMuxSel - Controls for the 64-1 mux for asynchronous data to the Digital Observation Pin.
*/
#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTMUXSEL_MTESTMUXSEL_MASK)
/*! @} */
/*! @name MTESTPGMINFO - Digital Observation Pin program info for debug */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_SHIFT (0U)
/*! MtestPgmInfo - The value of this csr may be driven onto the Digital Observation Pin.
*/
#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTPGMINFO_MTESTPGMINFO_MASK)
/*! @} */
/*! @name DYNPWRDNUP - Dynaimc Power Up/Down control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_SHIFT (0U)
/*! DynPowerDown - 1 - analog circuitry (voltage dacs, bias gen) is turned off.
*/
#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_SHIFT)) & DWC_DDRPHYA_MASTER_DYNPWRDNUP_DYNPOWERDOWN_MASK)
/*! @} */
/*! @name PHYTID - PHY Technology ID Register */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYTID_PHYTID_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PHYTID_PHYTID_SHIFT (0U)
/*! PhyTID - This register is a placeholder to store technology-specific information
*/
#define DWC_DDRPHYA_MASTER_PHYTID_PHYTID(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYTID_PHYTID_SHIFT)) & DWC_DDRPHYA_MASTER_PHYTID_PHYTID_MASK)
/*! @} */
/*! @name HWTMRL_P0 - HWT MaxReadLatency. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_SHIFT (0U)
/*! HwtMRL_p0 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P0_HWTMRL_P0_MASK)
/*! @} */
/*! @name DFIPHYUPD - DFI PhyUpdate Request time counter (in MEMCLKs) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT (0U)
/*! DFIPHYUPDCNT - This controls the interval between the end of a phyupdate transaction and a subsequent request.
*/
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK (0x70U)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT (4U)
/*! DFIPHYUPDRESP - Enforces the t_phyupd_resp time, the maximum time that is allowed to controller
* to respond to the request for a PHY update.
*/
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT (7U)
/*! DFIPHYUPDMODE - 1'b0 [Default] deterministic timer-based Phy Update Requests; enables multi-channel/multi-phy lockstep operation.
*/
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT (8U)
/*! DFIPHYUPDTHRESHOLD - 4'h0 Disable Threshold-based Phy Update Requests when DFIPHYUPDMODE==1'b1
* Nonzero codes are the threshold value for the change in the master LCDL 1UI phase code since
* the last Phy Update Request that will trigger a new Phy Update Request; If (current_1UI_phase -
* last_1UI_phase) > DFIPHYUPDTHRESHOLD, then a Phy Update will be requested.
*/
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT (12U)
/*! DFIPHYUPDINTTHRESHOLD - This subfield is similar to DFIPHYUPDTHRESHOLD except that rather than
* affecting the Phy Update request, it affects only the threshold used to generate the VT Drift
* Alarm Interrupt.
*/
#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT)) & DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK)
/*! @} */
/*! @name PDAMRSWRITEMODE - Controls the write DQ generation for Per-Dram-Addressing of MRS */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_SHIFT (0U)
/*! PdaMrsWriteMode - Controls the write DQ generation per the timing requirements on the DQ signals
* used for Per-Dram-Addressing mode of MRS commands.
*/
#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PDAMRSWRITEMODE_MASK)
/*! @} */
/*! @name DFIGEARDOWNCTL - Controls whether dfi_geardown_en will cause CS and CKE timing to change. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT (0U)
/*! DFIGEARDOWNCTL - DFIGEARDOWNCTL[0] controls whether dfi_geardown_en will cause chip-select (CS) timing to change.
*/
#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT)) & DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK)
/*! @} */
/*! @name DQSPREAMBLECONTROL_P0 - Control the PHY logic related to the read and write DQS preamble */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_SHIFT (0U)
/*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
* take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
* configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKRXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_SHIFT (1U)
/*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
* DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_MASK (0x1CU)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_SHIFT (2U)
/*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_POSITIONDFEINIT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
/*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
* TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TGLTWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_SHIFT (6U)
/*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4POSTAMBLEEXT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_SHIFT (7U)
/*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
* to the same timing group when the bubble is 1 memclk.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4STTCPREBRIDGERXEN_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT (8U)
/*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
* respectively, before and after a write burst, except during a memory read transaction.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK)
/*! @} */
/*! @name MASTERX4CONFIG - DBYTE module controls to select X4 Dram device mode */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT (0U)
/*! X4TG - Set to 1 if this Timing Group/Rank is x4 (as opposed to x8) memory.
*/
#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT)) & DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK)
/*! @} */
/*! @name WRLEVBITS - Write level feedback DQ observability select. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_SHIFT (0U)
/*! WrLevForDQSL - Indicates which DQ bit is used for Write Levelization.
*/
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSL_MASK)
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_SHIFT (4U)
/*! WrLevForDQSU - Indicates which DQ bit is used for Write Levelization.
*/
#define DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_SHIFT)) & DWC_DDRPHYA_MASTER_WRLEVBITS_WRLEVFORDQSU_MASK)
/*! @} */
/*! @name ENABLECSMULTICAST - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0] */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_SHIFT (0U)
/*! EnableCsMulticast - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on
* CID[1:0] 0 - Do not override pins corresponding to cid[1:0] (dfi_cid[1:0] will connect to the pads)
* 1 - Overrirde pins corresponding to cid[1:0] with dfi_cs[3:2].
*/
#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_SHIFT)) & DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_ENABLECSMULTICAST_MASK)
/*! @} */
/*! @name HWTLPCSMULTICAST - Drives cs_n[0] onto cs_n[1] during training */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_SHIFT (0U)
/*! HwtLpCsMultiCast - When set, drives cs_n[0] onto cs_n[1] during training
*/
#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HWTLPCSMULTICAST_MASK)
/*! @} */
/*! @name ACX4ANIBDIS - Disable for unused ACX Nibbles */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_MASK (0xFFFU)
#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_SHIFT (0U)
/*! Acx4AnibDis - When a bit is set, the corresponding ACX nibble is disabled (specifically, the I/O
* OE is disabled, as is the Dfi-side FIFO clock
*/
#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_SHIFT)) & DWC_DDRPHYA_MASTER_ACX4ANIBDIS_ACX4ANIBDIS_MASK)
/*! @} */
/*! @name DMIPINPRESENT_P0 - This Register is used to enable the Read-DBI function in each DBYTE */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_SHIFT (0U)
/*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device.
*/
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RDDBIENABLED_MASK)
/*! @} */
/*! @name ARDPTRINITVAL_P0 - Address/Command FIFO ReadPointer Initial Value */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_SHIFT (0U)
/*! ARdPtrInitVal_p0 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips.
*/
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARDPTRINITVAL_P0_MASK)
/*! @} */
/*! @name DBYTEDLLMODECNTRL - DLL Mode control CSR for DBYTEs */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_SHIFT (1U)
/*! DllRxPreambleMode - Must be set to 1 if read DQS preamble contains a toggle, for example DDR4 or LPDDR4 read toggling preambe mode
*/
#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DLLRXPREAMBLEMODE_MASK)
/*! @} */
/*! @name CALOFFSETS - Impedance Calibration offsets control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_MASK (0x3FU)
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_SHIFT (0U)
/*! CalCmpr5Offset - This value adjusts the offset-compensated DAC code for the cmpana circuit at VRef == 0.
*/
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALCMPR5OFFSET_MASK)
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_MASK (0x3C0U)
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_SHIFT (6U)
/*! CalDrvPdThOffset - This value adjusts the driver pulldown calibration code
*/
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPDTHOFFSET_MASK)
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_MASK (0x3C00U)
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_SHIFT (10U)
/*! CalDrvPuThOffset - This value adjusts the driver pullup calibration code
*/
#define DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_SHIFT)) & DWC_DDRPHYA_MASTER_CALOFFSETS_CALDRVPUTHOFFSET_MASK)
/*! @} */
/*! @name SARINITVALS - Sar Init Vals */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_SHIFT (0U)
/*! SarInitOFFSET05 - Specify the SAR starting value for OFFSET05 calibration.
*/
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITOFFSET05_MASK)
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_MASK (0x38U)
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_SHIFT (3U)
/*! SarInitNINT - Specify the SAR starting value for NINT calibration.
*/
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITNINT_MASK)
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_MASK (0x1C0U)
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_SHIFT (6U)
/*! SarInitPEXT - Specify the SAR starting value for PEXT calibration.
*/
#define DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_SHIFT)) & DWC_DDRPHYA_MASTER_SARINITVALS_SARINITPEXT_MASK)
/*! @} */
/*! @name CALPEXTOVR - Impedance Calibration PExt Override control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_SHIFT (0U)
/*! CalPExtOvr - If the CSR CalPExtDis is set then the value provided here by software will be used
* instead of the automatically generated value which is visible via CSR CalPExt This CSR may
* only be written when the calibrator is not running.
*/
#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXTOVR_CALPEXTOVR_MASK)
/*! @} */
/*! @name CALCMPR5OVR - Impedance Calibration Cmpr 50 control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_MASK (0xFFU)
#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_SHIFT (0U)
/*! CalCmpr5Ovr - If the CSR CalCmpr5Dis is set then the value provided here by software will be
* used instead of the automatically generated value which is visible via CSR CalCmpr5 This CSR may
* only be written when the calibrator is not running.
*/
#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5OVR_CALCMPR5OVR_MASK)
/*! @} */
/*! @name CALNINTOVR - Impedance Calibration NInt Override control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_SHIFT (0U)
/*! CalNIntOvr - If the CSR CalNIntDis is set then the value provided here by software will be used
* instead of the automatically generated value which is visible via CSR CalNInt.
*/
#define DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINTOVR_CALNINTOVR_MASK)
/*! @} */
/*! @name CALDRVSTR0 - Impedance Calibration driver strength control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_SHIFT (0U)
/*! CalDrvStrPd50 - 3.
*/
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPD50_MASK)
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_SHIFT (4U)
/*! CalDrvStrPu50 - 3.
*/
#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_SHIFT)) & DWC_DDRPHYA_MASTER_CALDRVSTR0_CALDRVSTRPU50_MASK)
/*! @} */
/*! @name PROCODTTIMECTL_P0 - READ DATA On-Die Termination Timing Control (by PHY) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_SHIFT (0U)
/*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
* Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
* 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
* to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTTAILWIDTH_MASK)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_SHIFT (2U)
/*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
* start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
* from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_PODTSTARTDELAY_MASK)
/*! @} */
/*! @name MEMALERTCONTROL - This Register is used to configure the MemAlert Receiver */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_MASK (0x7FU)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_SHIFT (0U)
/*! MALERTVrefLevel - Sets the vref level of internal VREF DAC.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFLEVEL_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_SHIFT (7U)
/*! MALERTVrefExtEn - When set for test/debug, selects external Vref source, This should not be set in mission mode.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVREFEXTEN_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_SHIFT (8U)
/*! MALERTPuStren - Controls the Pull-up termination on MALERT
* ========================================== bit[8] - controls a 240 Ohm Pull-up leg bit[9] - controls a 240 Ohm Pull-up leg bit[10]
* - controls a 120 Ohm Pull-up leg bit[11] - controls a 120 Ohm Pull-up leg
* ========================================== 0000 - No PullUp Strength 0001 - 240 Ohm PullUp Strength 0010 - 240 Ohm
* PullUp Strength 0011 - 120 Ohm PullUp Strength 0100 - 120 Ohm PullUp Strength 0101 - 80 Ohm
* PullUp Strength 0110 - 80 Ohm PullUp Strength 0111 - 60 Ohm PullUp Strength 1000 - 120 Ohm
* PullUp Strength 1001 - 80 Ohm PullUp Strength 1010 - 80 Ohm PullUp Strength 1011 - 60 Ohm PullUp
* Strength 1100 - 60 Ohm PullUp Strength 1101 - 48 Ohm PullUp Strength 1110 - 48 Ohm PullUp
* Strength 1111 - 40 Ohm PullUp Strength
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUSTREN_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_MASK (0x1000U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_SHIFT (12U)
/*! MALERTPuEn - When set, enables the Pull-up termination on MALERT
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPUEN_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_MASK (0x2000U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_SHIFT (13U)
/*! MALERTRxEn - 1 - Enables receiver and received data is forwared to dfi_alert_n.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRXEN_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_SHIFT (14U)
/*! MALERTDisableVal - When MALERTRxEn is not set, this CSR state is used to drive dfi_alert_n.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDISABLEVAL_MASK)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_MASK (0x8000U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_SHIFT (15U)
/*! MALERTForceError - When MALERTForceError is set, this CSR state is used to force parity error to memory.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTFORCEERROR_MASK)
/*! @} */
/*! @name MEMALERTCONTROL2 - This Register is used to configure the MemAlert Receiver */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_SHIFT (0U)
/*! MALERTSyncBypass - MALERTSyncBypass==[0], the phy will drive dfi_alert_n with a synchronized value of the ALERT_N receiver.
*/
#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_SHIFT)) & DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSYNCBYPASS_MASK)
/*! @} */
/*! @name MEMRESETL - Protection and control of BP_MemReset_L */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_SHIFT (0U)
/*! MemResetLValue - Control the MemResetL output of the PHY.
*/
#define DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_MEMRESETLVALUE_MASK)
#define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_SHIFT (1U)
/*! ProtectMemReset - Control the MemResetL output of the PHY.
*/
#define DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_SHIFT)) & DWC_DDRPHYA_MASTER_MEMRESETL_PROTECTMEMRESET_MASK)
/*! @} */
/*! @name DRIVECSLOWONTOHIGH - Drive CS_N 3:0 onto CS_N 7:4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_SHIFT (0U)
/*! CsLowOntoHigh - When this is set to a 1, CS[3:0] from the ACSM are driven to CS[7:4] pins and CS[3:0] are deasserted.
*/
#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_SHIFT)) & DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CSLOWONTOHIGH_MASK)
/*! @} */
/*! @name PUBMODE - PUBMODE - HWT Mux Select */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_SHIFT (0U)
/*! HwtMemSrc - When this is set to a 1, the mux that switches between DCT and HWT for the source of
* memory transactions is switched to HWT.
*/
#define DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_SHIFT)) & DWC_DDRPHYA_MASTER_PUBMODE_HWTMEMSRC_MASK)
/*! @} */
/*! @name MISCPHYSTATUS - Misc PHY status bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_SHIFT (0U)
/*! DctSane - Returns the status of the custom circuit which protects the MemResetL output of the PHY on initial power-on or reset.
*/
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DCTSANE_MASK)
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_SHIFT (1U)
/*! PORMemReset - Returns the active-high value used by the custom circuit which drives the memory RESET signal.
*/
#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_SHIFT)) & DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMEMRESET_MASK)
/*! @} */
/*! @name CORELOOPBACKSEL - Controls whether the loopback path bypasses the final PAD node. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_SHIFT (0U)
/*! CoreLoopbackSel - This register is controlled by the PHY test firmware This register enables Core-Side loopback operation of the PHY.
*/
#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_SHIFT)) & DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CORELOOPBACKSEL_MASK)
/*! @} */
/*! @name DLLTRAINPARAM - DLL Various Training Parameters */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_SHIFT (0U)
/*! ExtendPhdTime - Used by the PHY firmware locking the LCDL delay cells.
*/
#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_SHIFT)) & DWC_DDRPHYA_MASTER_DLLTRAINPARAM_EXTENDPHDTIME_MASK)
/*! @} */
/*! @name HWTLPCSENBYPASS - CSn Disable Bypass for LPDDR3/4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_SHIFT (0U)
/*! HwtLpCsEnBypass - When set, these bits disable LpCsEn function for LPDDR3/4
*/
#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_SHIFT)) & DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HWTLPCSENBYPASS_MASK)
/*! @} */
/*! @name DFICAMODE - Dfi Command/Address Mode */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_SHIFT (0U)
/*! DfiLp3CAMode - Controls the output data-rate of the AC module Command/Address pins 0: LP3 DDR
* address mode disabled 1: LP3 DDR address mode enabled
*/
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFILP3CAMODE_MASK)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_SHIFT (1U)
/*! DfiD4CAMode - Enable D4 Mode 0: D4 mode disabled 1: D4 mode enabled
*/
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFID4CAMODE_MASK)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_SHIFT (2U)
/*! DfiLp4CAMode - Enable LP4 Mode 0: LP4 mode disabled 1: LP4 mode enabled
*/
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFILP4CAMODE_MASK)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_MASK (0x8U)
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_SHIFT (3U)
/*! DfiD4AltCAMode - Enable D4-Alt Mode 0: D4-Altmode disabled 1: D4-Altmode enabled
*/
#define DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_SHIFT)) & DWC_DDRPHYA_MASTER_DFICAMODE_DFID4ALTCAMODE_MASK)
/*! @} */
/*! @name DLLCONTROL - DLL Lock State machine control register */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_SHIFT (0U)
/*! DllResetRelock - Used to reset the DDL/LCDL lock state machine Deasserting starts locking sequence.
*/
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRELOCK_MASK)
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_SHIFT (1U)
/*! DllResetSlave - Reserved.
*/
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETSLAVE_MASK)
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_SHIFT (2U)
/*! DllResetRSVD - RSVD for future use
*/
#define DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_SHIFT)) & DWC_DDRPHYA_MASTER_DLLCONTROL_DLLRESETRSVD_MASK)
/*! @} */
/*! @name PULSEDLLUPDATEPHASE - DLL update phase control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_SHIFT (0U)
/*! PulseDbyteDllUpdatePhase - Causes a LongBubble to the DBYTE modules, which causes a update of the DBYTE module DLLs (tx,rxen,rxclk).
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEDBYTEDLLUPDATEPHASE_MASK)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_SHIFT (1U)
/*! PulseACkDllUpdatePhase - Causes an AC module CK (memck) DLL phase update.
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACKDLLUPDATEPHASE_MASK)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_SHIFT (2U)
/*! PulseACaDllUpdatePhase - Causes an AC module CA (command/address/cke/odt) DLL phase update.
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PULSEACADLLUPDATEPHASE_MASK)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_MASK (0x38U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_SHIFT (3U)
/*! UpdatePhaseDestReserved - reserved, not used
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UPDATEPHASEDESTRESERVED_MASK)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_SHIFT (6U)
/*! TrainUpdatePhaseOnLongBubble - Causes LongBubble to update the dbyte & anib LDCL Phase.
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TRAINUPDATEPHASEONLONGBUBBLE_MASK)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_SHIFT (7U)
/*! AlwaysUpdateLcdlPhase - Causes each new operation to reload the LcdlPhase; will increase bubbles.
*/
#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_SHIFT)) & DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_ALWAYSUPDATELCDLPHASE_MASK)
/*! @} */
/*! @name DLLGAINCTL_P0 - DLL gain control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_SHIFT (0U)
/*! DllGainIV - Initial value of DllGain.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINIV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_SHIFT (4U)
/*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
* used for maintaining lock, ie tracking pclk variation.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLGAINTV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_SHIFT (8U)
/*! DllSeedSel - Reserved, must be configured to be 0.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DLLSEEDSEL_MASK)
/*! @} */
/*! @name CALRATE - Impedance Calibration Control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_SHIFT (0U)
/*! CalInterval - This CSR specifies the interval between successive calibrations, in mS.
*/
#define DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALINTERVAL_MASK)
#define DWC_DDRPHYA_MASTER_CALRATE_CALRUN_MASK (0x10U)
#define DWC_DDRPHYA_MASTER_CALRATE_CALRUN_SHIFT (4U)
/*! CalRun - 1: A calibration sequence will be triggered by the 0->1 transition of this bit, as determined by CSR CalOnce.
*/
#define DWC_DDRPHYA_MASTER_CALRATE_CALRUN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALRUN_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALRUN_MASK)
#define DWC_DDRPHYA_MASTER_CALRATE_CALONCE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_CALRATE_CALONCE_SHIFT (5U)
/*! CalOnce - The setting of this CSR changes the behaviour of CSR CalRun.
*/
#define DWC_DDRPHYA_MASTER_CALRATE_CALONCE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CALONCE_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CALONCE_MASK)
#define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_SHIFT (6U)
/*! DisableBackgroundZQUpdates - 1: Instead of having the driver compensation codes go
* asynchronously out to all IO, hold until for any of PHYUPD ACK, CTRLUPD ACK, PHYMSTR ACK) 0: Calibrated ZQ
* Updates to IO aren't gated.
*/
#define DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_DISABLEBACKGROUNDZQUPDATES_MASK)
/*! @} */
/*! @name CALZAP - Impedance Calibration Zap/Reset */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALZAP_CALZAP_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_CALZAP_CALZAP_SHIFT (0U)
/*! CalZap - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten.
*/
#define DWC_DDRPHYA_MASTER_CALZAP_CALZAP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALZAP_CALZAP_SHIFT)) & DWC_DDRPHYA_MASTER_CALZAP_CALZAP_MASK)
/*! @} */
/*! @name PSTATE - PSTATE Selection */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PSTATE_PSTATE_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PSTATE_PSTATE_SHIFT (0U)
/*! PState - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten.
*/
#define DWC_DDRPHYA_MASTER_PSTATE_PSTATE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PSTATE_PSTATE_SHIFT)) & DWC_DDRPHYA_MASTER_PSTATE_PSTATE_MASK)
/*! @} */
/*! @name PLLOUTGATECONTROL - PLL Output Control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_SHIFT (0U)
/*! PclkGateEn - Reserved.
*/
#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PCLKGATEEN_MASK)
/*! @} */
/*! @name PORCONTROL - PMU Power-on Reset Control (PLL/DLL Lock Done) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_SHIFT (0U)
/*! PllDllLockDone - Set by the PIE to 1 after it has finished the PLL/DLL lock sequence.
*/
#define DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_SHIFT)) & DWC_DDRPHYA_MASTER_PORCONTROL_PLLDLLLOCKDONE_MASK)
/*! @} */
/*! @name CALBUSY - Impedance Calibration Busy Status */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_SHIFT (0U)
/*! CalBusy - Read 1 if the calibrator is actively calibrating.
*/
#define DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_SHIFT)) & DWC_DDRPHYA_MASTER_CALBUSY_CALBUSY_MASK)
/*! @} */
/*! @name CALMISC2 - Miscellaneous impedance calibration controls. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_SHIFT (0U)
/*! CalNumVotes - This CSR controls the number of consecutive comparator output bits over which majority voting is done.
*/
#define DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALNUMVOTES_MASK)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_MASK (0x1000U)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_SHIFT (12U)
/*! CalCmptrResTrim - Reserved for future use.
*/
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALCMPTRRESTRIM_MASK)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_MASK (0x2000U)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_SHIFT (13U)
/*! CalCancelRoundErrDis - The PEXT calibration result and NINT calibration results naturally
* include a rounding error which manifests as a change of impedance at the pad.
*/
#define DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALCANCELROUNDERRDIS_MASK)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_SHIFT (14U)
/*! CalSlowCmpana - When set, this CSR increases the time allowed for the cmpana cell to settle, by 50%.
*/
#define DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC2_CALSLOWCMPANA_MASK)
/*! @} */
/*! @name CALMISC - Controls for disabling the impedance calibration of certain targets. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_SHIFT (0U)
/*! CalCmpr5Dis - Setting this CSR prevents the calibration engine from using the result from the CalCmpr5 stage of calibration.
*/
#define DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALCMPR5DIS_MASK)
#define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_SHIFT (1U)
/*! CalNIntDis - Setting this CSR prevents the calibration engine from overwriting the CSRs
* TxCalBinN and TxCalThN with an automatically generated value, in which case a value must be supplied
* by software.
*/
#define DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALNINTDIS_MASK)
#define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_SHIFT (2U)
/*! CalPExtDis - Setting this CSR prevents the calibration engine from overwriting the CSRs
* TxCalBinP and TxCalThP with an automatically generated value, in which case a value must be supplied
* by software.
*/
#define DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_SHIFT)) & DWC_DDRPHYA_MASTER_CALMISC_CALPEXTDIS_MASK)
/*! @} */
/*! @name CALVREFS - */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_SHIFT (0U)
/*! CalVRefs - This CSR drives the Cmpdig_CalRef pin of the cmpana cell at various stages of calibration.
*/
#define DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_SHIFT)) & DWC_DDRPHYA_MASTER_CALVREFS_CALVREFS_MASK)
/*! @} */
/*! @name CALCMPR5 - Impedance Calibration Cmpr control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_MASK (0xFFU)
#define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_SHIFT (0U)
/*! CalCmpr5 - Returns the offset-compensated DAC code for the cmpana circuit at VRef == 0.
*/
#define DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPR5_CALCMPR5_MASK)
/*! @} */
/*! @name CALNINT - Impedance Calibration NInt control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_SHIFT (0U)
/*! CalNIntThB - The value here is the number of thermometer bits which are set.
*/
#define DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_SHIFT)) & DWC_DDRPHYA_MASTER_CALNINT_CALNINTTHB_MASK)
/*! @} */
/*! @name CALPEXT - Impedance Calibration PExt control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_SHIFT (0U)
/*! CalPExtThB - The value here is the number of thermometer bits which are set.
*/
#define DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_SHIFT)) & DWC_DDRPHYA_MASTER_CALPEXT_CALPEXTTHB_MASK)
/*! @} */
/*! @name CALCMPINVERT - Impedance Calibration Cmp Invert control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_SHIFT (0U)
/*! CmpInvertCalDac50 - Impedance Calibration Cmp Invert control
*/
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDAC50_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_SHIFT (1U)
/*! CmpInvertCalDrvPd50 - Impedance Calibration Cmp Invert control
*/
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPD50_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_SHIFT (2U)
/*! CmpInvertCalDrvPu50 - Impedance Calibration Cmp Invert control
*/
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALDRVPU50_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_MASK (0x8U)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_SHIFT (3U)
/*! CmpInvertCalOdtPd - Impedance Calibration Cmp Invert control
*/
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPD_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_MASK (0x10U)
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_SHIFT (4U)
/*! CmpInvertCalOdtPu - Impedance Calibration Cmp Invert control
*/
#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPINVERT_CMPINVERTCALODTPU_MASK)
/*! @} */
/*! @name CALCMPANACNTRL - Impedance Calibration Cmpana control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_MASK (0xFFU)
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_SHIFT (0U)
/*! CmprGainCurrAdj - Impedance Calibration Cmpana control
*/
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINCURRADJ_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_SHIFT (8U)
/*! CmprGainResAdj - Impedance Calibration Cmpana control
*/
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRGAINRESADJ_MASK)
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_MASK (0x200U)
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_SHIFT (9U)
/*! CmprBiasBypassEn - Impedance Calibration Cmpana control
*/
#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_SHIFT)) & DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CMPRBIASBYPASSEN_MASK)
/*! @} */
/*! @name DFIRDDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_SHIFT (0U)
/*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
* dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_SHIFT (2U)
/*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
* dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_SHIFT (4U)
/*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
* dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_SHIFT (6U)
/*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
* dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DFIRDDESTM3_MASK)
/*! @} */
/*! @name VREFINGLOBAL_P0 - PHY Global Vref Controls */
/*! @{ */
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_SHIFT (0U)
/*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
* ========================================================== 2'b00 - PHY Vref DAC Range0 --
* BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
* Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
* ========================================================== GlobalVrefInSel[2] shall be set according to Dram
* Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
* 1'b0 LPDDR3 1'b0 LPDDR4 1'b1
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINSEL_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_MASK (0x3F8U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_SHIFT (3U)
/*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
* by GlobalVrefInSel[2] ========================================================== RANGE0 :
* DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
* 0.
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINDAC_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_MASK (0x3C00U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_SHIFT (10U)
/*! GlobalVrefInTrim - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINTRIM_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_SHIFT (14U)
/*! GlobalVrefInMode - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GLOBALVREFINMODE_MASK)
/*! @} */
/*! @name DFIWRDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_SHIFT (0U)
/*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_SHIFT (2U)
/*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_SHIFT (4U)
/*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_SHIFT (6U)
/*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
* TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DFIWRDESTM3_MASK)
/*! @} */
/*! @name MASUPDGOODCTR - Counts successful PHY Master Interface Updates (PPTs) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_SHIFT (0U)
/*! MasUpdGoodCtr - This register increments whenever the Memory Controller acknowledges a PHY Master Interface request (i.
*/
#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MASUPDGOODCTR_MASK)
/*! @} */
/*! @name PHYUPD0GOODCTR - Counts successful PHY-initiated DFI0 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_SHIFT (0U)
/*! PhyUpd0GoodCtr - This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI0 interface update request.
*/
#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PHYUPD0GOODCTR_MASK)
/*! @} */
/*! @name PHYUPD1GOODCTR - Counts successful PHY-initiated DFI1 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_SHIFT (0U)
/*! PhyUpd1GoodCtr - This register increments whenever the Memory Controller acknowledges a PHY-initiated DFI1 interface update request.
*/
#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PHYUPD1GOODCTR_MASK)
/*! @} */
/*! @name CTLUPD0GOODCTR - Counts successful Memory Controller DFI0 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_SHIFT (0U)
/*! CtlUpd0GoodCtr - This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI0 interface update request.
*/
#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CTLUPD0GOODCTR_MASK)
/*! @} */
/*! @name CTLUPD1GOODCTR - Counts successful Memory Controller DFI1 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_SHIFT (0U)
/*! CtlUpd1GoodCtr - This register increments whenever the PHY acknowledges a Memory Controller-initiated DFI1 interface update request.
*/
#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_SHIFT)) & DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CTLUPD1GOODCTR_MASK)
/*! @} */
/*! @name MASUPDFAILCTR - Counts unsuccessful PHY Master Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_SHIFT (0U)
/*! MasUpdFailCtr - This register increments whenever the PHY asserts a PHY Master Interface
* request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
*/
#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MASUPDFAILCTR_MASK)
/*! @} */
/*! @name PHYUPD0FAILCTR - Counts unsuccessful PHY-initiated DFI0 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_SHIFT (0U)
/*! PhyUpd0FailCtr - This register increments whenever the PHY asserts a DFI0 Interface update
* request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
*/
#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PHYUPD0FAILCTR_MASK)
/*! @} */
/*! @name PHYUPD1FAILCTR - Counts unsuccessful PHY-initiated DFI1 Interface Updates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT (0U)
/*! PhyUpd1FailCtr - This register increments whenever the PHY asserts a DFI1 Interface update
* request, but the Memory Controller doesn't acknowledge the request within the allowed interval.
*/
#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK)
/*! @} */
/*! @name PHYPERFCTRENABLE - Enables for Performance Counters */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_SHIFT (0U)
/*! MasUpdGoodCtl - Enables MasUpdGoodCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDGOODCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_SHIFT (1U)
/*! PhyUpd0GoodCtl - Enables PhyUpd0GoodCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0GOODCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_SHIFT (2U)
/*! PhyUpd1GoodCtl - Enables PhyUpd1GoodCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1GOODCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_MASK (0x8U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_SHIFT (3U)
/*! CtlUpd0GoodCtl - Enables CtlUpd0GoodCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD0GOODCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_MASK (0x10U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_SHIFT (4U)
/*! CtlUpd1GoodCtl - Enables CtlUpd1GoodCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CTLUPD1GOODCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_SHIFT (5U)
/*! MasUpdFailCtl - Enables MasUpdFailCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MASUPDFAILCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_SHIFT (6U)
/*! PhyUpd0FailCtl - Enables PhyUpd0FailCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD0FAILCTL_MASK)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_SHIFT (7U)
/*! PhyUpd1FailCtl - Enables PhyUpd1FailCtr
*/
#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PHYUPD1FAILCTL_MASK)
/*! @} */
/*! @name PLLPWRDN - PLL Power Down */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_SHIFT (0U)
/*! PllPwrDn - NOTE : This CSR is written by PHY Initialization Engine (PIE) and the data in here will be overwritten.
*/
#define DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLPWRDN_PLLPWRDN_MASK)
/*! @} */
/*! @name PLLRESET - PLL Reset */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_SHIFT (0U)
/*! PllReset - Reserved
*/
#define DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_SHIFT)) & DWC_DDRPHYA_MASTER_PLLRESET_PLLRESET_MASK)
/*! @} */
/*! @name PLLCTRL2_P0 - PState dependent PLL Control Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_SHIFT (0U)
/*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PLLFREQSEL_MASK)
/*! @} */
/*! @name PLLCTRL0 - PLL Control Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_SHIFT (0U)
/*! PllStandby - Connects directly to standby pin of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSTANDBY_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_SHIFT (1U)
/*! PllBypSel - Reserved.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPSEL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_SHIFT (2U)
/*! PllX2Mode - conects to x2_mode pins of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLX2MODE_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_MASK (0x8U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_SHIFT (3U)
/*! PllOutBypEn - Controls the antiglitch mux on the pllout_x1x2x4 path 1: pllout_x1x2x4 =
* byp_pllin_x1 0: pllout_x1x2x4 = VCO (SCD) (selected by x2_mode)
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLOUTBYPEN_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_MASK (0x10U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_SHIFT (4U)
/*! PllPreset - Put PLL in preset mode.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLPRESET_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_SHIFT (5U)
/*! PllBypassMode - PLL Bypass clock mux control.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLBYPASSMODE_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_SHIFT (6U)
/*! PllSelDfiFreqRatio - reserved.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSELDFIFREQRATIO_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_SHIFT (7U)
/*! PllSyncBusFlush - Used to flush the syncbus logic of the PLL during PHY initialization or LP3 Exit sequence.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSFLUSH_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_SHIFT (8U)
/*! PllSyncBusByp - When asserted bypasses the Pll SyncPulse and uses a synchronizer of the same latency.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSYNCBUSBYP_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_MASK (0x600U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_SHIFT (9U)
/*! PllReserved10x9 - for future use.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLRESERVED10X9_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_MASK (0x800U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_SHIFT (11U)
/*! PllGearShift - Puts PLL in fast re-locking mode 0: default, normal mode 1: fast relock gear
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLGEARSHIFT_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_MASK (0x1000U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_SHIFT (12U)
/*! PllLockCntSel - Lock detect counter selection.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKCNTSEL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_MASK (0x6000U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_SHIFT (13U)
/*! PllLockPhSel - Lock detect phase selection.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLLOCKPHSEL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_MASK (0x8000U)
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_SHIFT (15U)
/*! PllSpareCtrl0 - Spare bits for PLL control.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL0_PLLSPARECTRL0_MASK)
/*! @} */
/*! @name PLLCTRL1_P0 - PState dependent PLL Control Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_SHIFT (0U)
/*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPINTCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_SHIFT (5U)
/*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PLLCPPROPCTRL_MASK)
/*! @} */
/*! @name PLLTST - PLL Testing Control Register */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_SHIFT (0U)
/*! PllAnaTstEn - Connects directly to pll_ana_test_en of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTEN_MASK)
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_MASK (0x1EU)
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_SHIFT (1U)
/*! PllAnaTstSel - Connects directly to pll_ana_test_sel<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLANATSTSEL_MASK)
#define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_SHIFT (5U)
/*! PllDigTstSel - Connects directly to pll_dig_test_sel<2:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTST_PLLDIGTSTSEL_MASK)
/*! @} */
/*! @name PLLLOCKSTATUS - PLL's pll_lock pin output */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_SHIFT (0U)
/*! PllLockStatus - Directly connected to the pll_Lock output.
*/
#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_SHIFT)) & DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PLLLOCKSTATUS_MASK)
/*! @} */
/*! @name PLLTESTMODE_P0 - Additional controls for PLL CP/VCO modes of operation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_SHIFT (0U)
/*! PllTestMode_p0 - It is required to use default values for this CSR unless directed otherwise by Synopsys.
*/
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PLLTESTMODE_P0_MASK)
/*! @} */
/*! @name PLLCTRL3 - PLL Control Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_SHIFT (0U)
/*! PllSpare - Spare bits for future PLL control modes
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLSPARE_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_MASK (0x1F0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_SHIFT (4U)
/*! PllMaxRange - connects directly to maxrange of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLMAXRANGE_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_MASK (0x3E00U)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_SHIFT (9U)
/*! PllDacValIn - connects directly to dacval_in<4:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLDACVALIN_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_SHIFT (14U)
/*! PllForceCal - connects directly to force_cal of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLFORCECAL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_MASK (0x8000U)
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_SHIFT (15U)
/*! PllEnCal - Calibration will run at standby rising edge if en_cal=1 if en_cal=0 calibration will not run
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL3_PLLENCAL_MASK)
/*! @} */
/*! @name PLLCTRL4_P0 - PState dependent PLL Control Register 4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_SHIFT (0U)
/*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPINTGSCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_SHIFT (5U)
/*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PLLCPPROPGSCTRL_MASK)
/*! @} */
/*! @name PLLENDOFCAL - PLL's eoc (end of calibration) output */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_SHIFT (0U)
/*! PllEndofCal - Directly connected to the pll's eoc output.
*/
#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLENDOFCAL_PLLENDOFCAL_MASK)
/*! @} */
/*! @name PLLSTANDBYEFF - PLL's standby_eff (effective standby) output */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_SHIFT (0U)
/*! PllStandbyEff - Returns state off PLL standby.
*/
#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_SHIFT)) & DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PLLSTANDBYEFF_MASK)
/*! @} */
/*! @name PLLDACVALOUT - PLL's Dacval_out output */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_SHIFT (0U)
/*! PllDacValOut - Directly connected to the pll's dacval_out output.
*/
#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_SHIFT)) & DWC_DDRPHYA_MASTER_PLLDACVALOUT_PLLDACVALOUT_MASK)
/*! @} */
/*! @name LCDLDBGCNTL - Controls for use in observing and testing the LCDLs. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_MASK (0x1FFU)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_SHIFT (0U)
/*! LcdlFineOvrVal - Value forced as the initial value while LcdlTstEnable=1 and LcdlFineOvr.
*/
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVRVAL_MASK)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_MASK (0x200U)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_SHIFT (9U)
/*! LcdlFineOvr - Forces the value of the present LCDL 1UI estimate code to be LcdlFineOvrVal for all LCDLs.
*/
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINEOVR_MASK)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_SHIFT (10U)
/*! LcdlFineSnap - Latch enable for reading the present LCDL 1UI estimate code in LcdlFineSnapVal
* and the present phase-detector value in LcdlPhdSnapVal
*/
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLFINESNAP_MASK)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_MASK (0x800U)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_SHIFT (11U)
/*! LcdlTstEnable - Enables the debug/test operations and status Ovr,Snap,StickyLock,StickyUnlock, and LiveLock.
*/
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLTSTENABLE_MASK)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_SHIFT (12U)
/*! LcdlStatusSel - Selects the LCDL status, from among the status for the 16 LCDLs in the DBYTE,
* for reading via Register DxLcdlStatus and an LCDL from among the LCDLs in the ANIB for reading
* via Register AcLcdlStatus LcdlStatusSel source for DxLcdlStatus source for AcLcdlStatus 15
* lcdl_rxclk1t reserved 14 lcdl_rxclk0t reserved 13 lcdl_rxclk1c reserved 12 lcdl_rxclk0c reserved
* 11 lcdl_rxen1 anib11-tx 10 lcdl_rxen0 anib10-tx 9 lcdl_txln9 (dqs-lower) anib9-tx 8 lcdl_txln8
* (dm/dqs-upper) anib8-tx 7 lcdl_txln7 (dq7) anib7-tx 6 lcdl_txln6 (dq6) anib6-tx 5 lcdl_txln5
* (dq5) anib5-tx 4 lcdl_txln4 (dq4) anib4-tx 3 lcdl_txln3 (dq3) anib3-tx 2 lcdl_txln2 (dq2)
* anib2-tx 1 lcdl_txln1 (dq1) anib1-tx 0 lcdl_txln0 (dq0) anib0-tx
*/
#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_SHIFT)) & DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LCDLSTATUSSEL_MASK)
/*! @} */
/*! @name ACLCDLSTATUS - Debug status of the DBYTE LCDL */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_MASK (0x3FFU)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_SHIFT (0U)
/*! AcLcdlFineSnapVal - Value of the LCDL 1UI estimate code, latched by pulse on csrLcdlFineSnap while csr LcdlTstEnable=1.
*/
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLFINESNAPVAL_MASK)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_SHIFT (10U)
/*! AcLcdlPhdSnapVal - Value of the LCDL phase-detector output, latched by pulse on LcdlFineSnap while csr LcdlTstEnable=1.
*/
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLPHDSNAPVAL_MASK)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_MASK (0x800U)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_SHIFT (11U)
/*! AcLcdlStickyLock - latched value of whether the LCDL ever achieved lock after the assertion of LcdlTstEnable.
*/
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYLOCK_MASK)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_MASK (0x1000U)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_SHIFT (12U)
/*! AcLcdlStickyUnlock - latched value of whether the LCDL ever lost lock after the assertion of LcdlTstEnable.
*/
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLSTICKYUNLOCK_MASK)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_MASK (0x2000U)
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_SHIFT (13U)
/*! AcLcdlLiveLock - present value of whether the LCDL is locked, valid when LcdlTstEnable=1.
*/
#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_SHIFT)) & DWC_DDRPHYA_MASTER_ACLCDLSTATUS_ACLCDLLIVELOCK_MASK)
/*! @} */
/*! @name CUSTPHYREV - Customer settable by the customer */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK (0x3FU)
#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT (0U)
/*! CUSTPHYREV - The customer settable PHY version number.
*/
#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT)) & DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK)
/*! @} */
/*! @name PHYREV - The hardware version of this PHY, excluding the PUB */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT (0U)
/*! PHYMNR - Indicates minor update of the PHY.
*/
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK)
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT (4U)
/*! PHYMDR - Indicates moderate revision of the PHY.
*/
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK)
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK (0xFF00U)
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT (8U)
/*! PHYMJR - Indicates major revision of the PHY.
*/
#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK)
/*! @} */
/*! @name LP3EXITSEQ0BSTARTVECTOR - Start vector value to be used for LP3-exit or Init PIE Sequence */
/*! @{ */
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_SHIFT (0U)
/*! LP3ExitSeq0BStartVecPllEnabled - PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL enabled
*/
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLENABLED_MASK)
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_SHIFT (4U)
/*! LP3ExitSeq0BStartVecPllBypassed - PIE Start Vector value to be used for LP3-exit or Init and target P-state has PLL bypassed
*/
#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_SHIFT)) & DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3EXITSEQ0BSTARTVECPLLBYPASSED_MASK)
/*! @} */
/*! @name DFIFREQXLAT0 - DFI Frequency Translation Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_SHIFT (0U)
/*! DfiFreqXlatVal0 - The sequencer start vector used when dfi_freq value is 0.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL0_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_SHIFT (4U)
/*! DfiFreqXlatVal1 - The sequencer start vector used when dfi_freq value is 1.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL1_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_SHIFT (8U)
/*! DfiFreqXlatVal2 - The sequencer start vector used when dfi_freq value is 2.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL2_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_SHIFT (12U)
/*! DfiFreqXlatVal3 - The sequencer start vector used when dfi_freq value is 3.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DFIFREQXLATVAL3_MASK)
/*! @} */
/*! @name DFIFREQXLAT1 - DFI Frequency Translation Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_SHIFT (0U)
/*! DfiFreqXlatVal4 - The sequencer start vector used when dfi_freq value is 4.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL4_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_SHIFT (4U)
/*! DfiFreqXlatVal5 - The sequencer start vector used when dfi_freq value is 5.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL5_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_SHIFT (8U)
/*! DfiFreqXlatVal6 - The sequencer start vector used when dfi_freq value is 6.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL6_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_SHIFT (12U)
/*! DfiFreqXlatVal7 - The sequencer start vector used when dfi_freq value is 7.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DFIFREQXLATVAL7_MASK)
/*! @} */
/*! @name DFIFREQXLAT2 - DFI Frequency Translation Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_SHIFT (0U)
/*! DfiFreqXlatVal8 - The sequencer start vector used when dfi_freq value is 8.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL8_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_SHIFT (4U)
/*! DfiFreqXlatVal9 - The sequencer start vector used when dfi_freq value is 9.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL9_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_SHIFT (8U)
/*! DfiFreqXlatVal10 - The sequencer start vector used when dfi_freq value is 10.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL10_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_SHIFT (12U)
/*! DfiFreqXlatVal11 - The sequencer start vector used when dfi_freq value is 11.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DFIFREQXLATVAL11_MASK)
/*! @} */
/*! @name DFIFREQXLAT3 - DFI Frequency Translation Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_SHIFT (0U)
/*! DfiFreqXlatVal12 - The sequencer start vector used when dfi_freq value is 12.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL12_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_SHIFT (4U)
/*! DfiFreqXlatVal13 - The sequencer start vector used when dfi_freq value is 13.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL13_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_SHIFT (8U)
/*! DfiFreqXlatVal14 - The sequencer start vector used when dfi_freq value is 14.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL14_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_SHIFT (12U)
/*! DfiFreqXlatVal15 - The sequencer start vector used when dfi_freq value is 15.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DFIFREQXLATVAL15_MASK)
/*! @} */
/*! @name DFIFREQXLAT4 - DFI Frequency Translation Register 4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_SHIFT (0U)
/*! DfiFreqXlatVal16 - The sequencer start vector used when dfi_freq value is 16.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL16_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_SHIFT (4U)
/*! DfiFreqXlatVal17 - The sequencer start vector used when dfi_freq value is 17.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL17_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_SHIFT (8U)
/*! DfiFreqXlatVal18 - The sequencer start vector used when dfi_freq value is 18.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL18_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_SHIFT (12U)
/*! DfiFreqXlatVal19 - The sequencer start vector used when dfi_freq value is 19.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DFIFREQXLATVAL19_MASK)
/*! @} */
/*! @name DFIFREQXLAT5 - DFI Frequency Translation Register 5 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_SHIFT (0U)
/*! DfiFreqXlatVal20 - The sequencer start vector used when dfi_freq value is 20.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL20_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_SHIFT (4U)
/*! DfiFreqXlatVal21 - The sequencer start vector used when dfi_freq value is 21.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL21_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_SHIFT (8U)
/*! DfiFreqXlatVal22 - The sequencer start vector used when dfi_freq value is 22.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL22_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_SHIFT (12U)
/*! DfiFreqXlatVal23 - The sequencer start vector used when dfi_freq value is 23.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DFIFREQXLATVAL23_MASK)
/*! @} */
/*! @name DFIFREQXLAT6 - DFI Frequency Translation Register 6 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_SHIFT (0U)
/*! DfiFreqXlatVal24 - The sequencer start vector used when dfi_freq value is 24.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL24_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_SHIFT (4U)
/*! DfiFreqXlatVal25 - The sequencer start vector used when dfi_freq value is 25.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL25_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_SHIFT (8U)
/*! DfiFreqXlatVal26 - The sequencer start vector used when dfi_freq value is 26.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL26_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_SHIFT (12U)
/*! DfiFreqXlatVal27 - The sequencer start vector used when dfi_freq value is 27.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DFIFREQXLATVAL27_MASK)
/*! @} */
/*! @name DFIFREQXLAT7 - DFI Frequency Translation Register 7 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_SHIFT (0U)
/*! DfiFreqXlatVal28 - The sequencer start vector used when dfi_freq value is 28.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL28_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_SHIFT (4U)
/*! DfiFreqXlatVal29 - The sequencer start vector used when dfi_freq value is 29.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL29_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_SHIFT (8U)
/*! DfiFreqXlatVal30 - The sequencer start vector used when dfi_freq value is 30.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL30_MASK)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_SHIFT (12U)
/*! DfiFreqXlatVal31 - The sequencer start vector used when dfi_freq value is 31.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DFIFREQXLATVAL31_MASK)
/*! @} */
/*! @name TXRDPTRINIT - TxRdPtrInit control register */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_SHIFT (0U)
/*! TxRdPtrInit - This register directly controls TxRdPtrInit, and is meant to be written by the
* PState sequencer as part of the power state switching sequence.
*/
#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_SHIFT)) & DWC_DDRPHYA_MASTER_TXRDPTRINIT_TXRDPTRINIT_MASK)
/*! @} */
/*! @name DFIINITCOMPLETE - DFI Init Complete control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_SHIFT (0U)
/*! DfiInitComplete - This register directly controls DfiInitComplete, and is meant to be written by
* the PState sequencer as part of the power state switching sequence.
*/
#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_SHIFT)) & DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DFIINITCOMPLETE_MASK)
/*! @} */
/*! @name DFIFREQRATIO_P0 - DFI Frequency Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_SHIFT (0U)
/*! DfiFreqRatio_p0 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
* 1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DFIFREQRATIO_P0_MASK)
/*! @} */
/*! @name RXFIFOCHECKS - Enable more frequent consistency checks of the RX FIFOs */
/*! @{ */
#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_SHIFT (0U)
/*! DoFrequentRxFifoChecks - When 0, read data FIFO pointer consistency checks are performed only during sideband transactions (i.
*/
#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_SHIFT)) & DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DOFREQUENTRXFIFOCHECKS_MASK)
/*! @} */
/*! @name MTESTDTOCTRL - */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_SHIFT (0U)
/*! MTestDtoCtrl - MTESTdtoEn==[0], dwc_ddrphy_dto will be squelched (0) MTESTdtoEn==[1],
* dwc_ddrphy_dto will reflect the observability signal multiplexed on MTestCombo
*/
#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTESTDTOCTRL_MASK)
/*! @} */
/*! @name MAPCAA0TODFI - Maps PHY CAA lane 0 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_SHIFT (0U)
/*! MapCAA0toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 0.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MAPCAA0TODFI_MASK)
/*! @} */
/*! @name MAPCAA1TODFI - Maps PHY CAA lane 1 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_SHIFT (0U)
/*! MapCAA1toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 1.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MAPCAA1TODFI_MASK)
/*! @} */
/*! @name MAPCAA2TODFI - Maps PHY CAA lane 2 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_SHIFT (0U)
/*! MapCAA2toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 2.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MAPCAA2TODFI_MASK)
/*! @} */
/*! @name MAPCAA3TODFI - Maps PHY CAA lane 3 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_SHIFT (0U)
/*! MapCAA3toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 3.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MAPCAA3TODFI_MASK)
/*! @} */
/*! @name MAPCAA4TODFI - Maps PHY CAA lane 4 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_SHIFT (0U)
/*! MapCAA4toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 4.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MAPCAA4TODFI_MASK)
/*! @} */
/*! @name MAPCAA5TODFI - Maps PHY CAA lane 5 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_SHIFT (0U)
/*! MapCAA5toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 5.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MAPCAA5TODFI_MASK)
/*! @} */
/*! @name MAPCAA6TODFI - Maps PHY CAA lane 6 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_SHIFT (0U)
/*! MapCAA6toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 6.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MAPCAA6TODFI_MASK)
/*! @} */
/*! @name MAPCAA7TODFI - Maps PHY CAA lane 7 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_SHIFT (0U)
/*! MapCAA7toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 7.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MAPCAA7TODFI_MASK)
/*! @} */
/*! @name MAPCAA8TODFI - Maps PHY CAA lane 8 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_SHIFT (0U)
/*! MapCAA8toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 8.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MAPCAA8TODFI_MASK)
/*! @} */
/*! @name MAPCAA9TODFI - Maps PHY CAA lane 9 from dfi0_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_SHIFT (0U)
/*! MapCAA9toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi0_address to CAA 9.
*/
#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MAPCAA9TODFI_MASK)
/*! @} */
/*! @name MAPCAB0TODFI - Maps PHY CAB lane 0 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_SHIFT (0U)
/*! MapCAB0toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 0.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MAPCAB0TODFI_MASK)
/*! @} */
/*! @name MAPCAB1TODFI - Maps PHY CAB lane 1 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_SHIFT (0U)
/*! MapCAB1toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 1.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MAPCAB1TODFI_MASK)
/*! @} */
/*! @name MAPCAB2TODFI - Maps PHY CAB lane 2 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_SHIFT (0U)
/*! MapCAB2toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 2.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MAPCAB2TODFI_MASK)
/*! @} */
/*! @name MAPCAB3TODFI - Maps PHY CAB lane 3 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_SHIFT (0U)
/*! MapCAB3toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 3.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MAPCAB3TODFI_MASK)
/*! @} */
/*! @name MAPCAB4TODFI - Maps PHY CAB lane 4 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_SHIFT (0U)
/*! MapCAB4toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 4.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MAPCAB4TODFI_MASK)
/*! @} */
/*! @name MAPCAB5TODFI - Maps PHY CAB lane 5 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_SHIFT (0U)
/*! MapCAB5toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 5.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MAPCAB5TODFI_MASK)
/*! @} */
/*! @name MAPCAB6TODFI - Maps PHY CAB lane 6 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_SHIFT (0U)
/*! MapCAB6toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 6.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MAPCAB6TODFI_MASK)
/*! @} */
/*! @name MAPCAB7TODFI - Maps PHY CAB lane 7 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_SHIFT (0U)
/*! MapCAB7toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 7.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MAPCAB7TODFI_MASK)
/*! @} */
/*! @name MAPCAB8TODFI - Maps PHY CAB lane 8 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_SHIFT (0U)
/*! MapCAB8toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 8.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MAPCAB8TODFI_MASK)
/*! @} */
/*! @name MAPCAB9TODFI - Maps PHY CAB lane 9 from dfi1_address of the index of the register contents */
/*! @{ */
#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_SHIFT (0U)
/*! MapCAB9toDfi - For LPDDR3 and LPDDR4 applications, these CSRs map a dfi1_address to CAB 9.
*/
#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_SHIFT)) & DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MAPCAB9TODFI_MASK)
/*! @} */
/*! @name PHYINTERRUPTENABLE - Interrupt Enable Bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_SHIFT (0U)
/*! PhyTrngCmpltEn - Enable for the PHY Training Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGCMPLTEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_SHIFT (1U)
/*! PhyInitCmpltEn - Enable for the PHY Initialization Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYINITCMPLTEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_SHIFT (2U)
/*! PhyTrngFailEn - Enable for the PHY Training Failure interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYTRNGFAILEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_MASK (0xF8U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_SHIFT (3U)
/*! PhyFWReservedEn - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYFWRESERVEDEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_MASK (0x300U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_SHIFT (8U)
/*! PhyVTDriftAlarmEn - Enable for the PHY VT Drift Alarm interrupts.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYVTDRIFTALARMEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_SHIFT (10U)
/*! PhyRxFifoCheckEn - Enable for the RxFifo Pointers Check Interrupt 0 : Interrupt not enabled 1 : Interrupt enabled
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYRXFIFOCHECKEN_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_MASK (0xF800U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_SHIFT (11U)
/*! PhyHWReservedEn - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PHYHWRESERVEDEN_MASK)
/*! @} */
/*! @name PHYINTERRUPTFWCONTROL - Interrupt Firmware Control Bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_SHIFT (0U)
/*! PhyTrngCmpltFW - PHY Training Complete Firmware interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGCMPLTFW_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_SHIFT (1U)
/*! PhyInitCmpltFW - PHY Initialization Complete Firmware interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYINITCMPLTFW_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_SHIFT (2U)
/*! PhyTrngFailFW - PHY Training Failure Firmware interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYTRNGFAILFW_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_MASK (0xF8U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_SHIFT (3U)
/*! PhyFWReservedFW - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PHYFWRESERVEDFW_MASK)
/*! @} */
/*! @name PHYINTERRUPTMASK - Interrupt Mask Bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_SHIFT (0U)
/*! PhyTrngCmpltMsk - Mask for the PHY Training Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGCMPLTMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_SHIFT (1U)
/*! PhyInitCmpltMsk - Mask for the PHY Initialization Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYINITCMPLTMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_SHIFT (2U)
/*! PhyTrngFailMsk - Mask for the PHY Training Failure interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYTRNGFAILMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_MASK (0xF8U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_SHIFT (3U)
/*! PhyFWReservedMsk - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYFWRESERVEDMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_MASK (0x300U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_SHIFT (8U)
/*! PhyVTDriftAlarmMsk - Mask for the PHY VT Drift Alarm interrupts.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYVTDRIFTALARMMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_SHIFT (10U)
/*! PhyRxFifoCheckMsk - Mask for the RxFifo Pointers Check Interrupt 0 : Interrupt not masked 1 : Interrupt masked
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYRXFIFOCHECKMSK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_MASK (0xF800U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_SHIFT (11U)
/*! PhyHWReservedMsk - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PHYHWRESERVEDMSK_MASK)
/*! @} */
/*! @name PHYINTERRUPTCLEAR - Interrupt Clear Bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_SHIFT (0U)
/*! PhyTrngCmpltClr - Clear for the PHY Training Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGCMPLTCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_SHIFT (1U)
/*! PhyInitCmpltClr - Clear for the PHY Initialization Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYINITCMPLTCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_SHIFT (2U)
/*! PhyTrngFailClr - Clear for the PHY Training Failure interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYTRNGFAILCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_MASK (0xF8U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_SHIFT (3U)
/*! PhyFWReservedClr - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYFWRESERVEDCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_MASK (0x300U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_SHIFT (8U)
/*! PhyVTDriftAlarmClr - Clear for the PHY VT Drift Alarm interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYVTDRIFTALARMCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_SHIFT (10U)
/*! PhyRxFifoCheckClr - Clear for the RxFifo Pointers Check Interrupt 0 : Interrupt not affected 1 : Interrupt cleared
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYRXFIFOCHECKCLR_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_MASK (0xF800U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_SHIFT (11U)
/*! PhyHWReservedClr - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PHYHWRESERVEDCLR_MASK)
/*! @} */
/*! @name PHYINTERRUPTSTATUS - Interrupt Status Bits */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_SHIFT (0U)
/*! PhyTrngCmplt - PHY Training Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGCMPLT_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_SHIFT (1U)
/*! PhyInitCmplt - PHY Initialization Complete interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYINITCMPLT_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_MASK (0x4U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_SHIFT (2U)
/*! PhyTrngFail - PHY Training Failure interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYTRNGFAIL_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_MASK (0xF8U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_SHIFT (3U)
/*! PhyFWReserved - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYFWRESERVED_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_MASK (0x300U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_SHIFT (8U)
/*! VTDriftAlarm - PHY VT Drift Alarm interrupt.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDRIFTALARM_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_MASK (0x400U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_SHIFT (10U)
/*! PhyRxFifoCheck - A mechanism in the PHY checks the Read Fifo pointers for consistency at times they are idle.
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYRXFIFOCHECK_MASK)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_MASK (0xF800U)
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_SHIFT (11U)
/*! PhyHWReserved - Reserved
*/
#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_SHIFT)) & DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PHYHWRESERVED_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS0 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_SHIFT (0U)
/*! HwtSwizzleHwtAddress0 - This set of registers is used in DDR3/DDR4 mode where a user has re-mapped the DFI inputs to the PHY.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HWTSWIZZLEHWTADDRESS0_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS1 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_SHIFT (0U)
/*! HwtSwizzleHwtAddress1 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HWTSWIZZLEHWTADDRESS1_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS2 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_SHIFT (0U)
/*! HwtSwizzleHwtAddress2 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HWTSWIZZLEHWTADDRESS2_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS3 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_SHIFT (0U)
/*! HwtSwizzleHwtAddress3 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HWTSWIZZLEHWTADDRESS3_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS4 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_SHIFT (0U)
/*! HwtSwizzleHwtAddress4 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HWTSWIZZLEHWTADDRESS4_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS5 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_SHIFT (0U)
/*! HwtSwizzleHwtAddress5 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HWTSWIZZLEHWTADDRESS5_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS6 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_SHIFT (0U)
/*! HwtSwizzleHwtAddress6 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HWTSWIZZLEHWTADDRESS6_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS7 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_SHIFT (0U)
/*! HwtSwizzleHwtAddress7 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HWTSWIZZLEHWTADDRESS7_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS8 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_SHIFT (0U)
/*! HwtSwizzleHwtAddress8 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HWTSWIZZLEHWTADDRESS8_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS9 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_SHIFT (0U)
/*! HwtSwizzleHwtAddress9 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HWTSWIZZLEHWTADDRESS9_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS10 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_SHIFT (0U)
/*! HwtSwizzleHwtAddress10 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HWTSWIZZLEHWTADDRESS10_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS11 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_SHIFT (0U)
/*! HwtSwizzleHwtAddress11 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HWTSWIZZLEHWTADDRESS11_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS12 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_SHIFT (0U)
/*! HwtSwizzleHwtAddress12 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HWTSWIZZLEHWTADDRESS12_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS13 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_SHIFT (0U)
/*! HwtSwizzleHwtAddress13 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HWTSWIZZLEHWTADDRESS13_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS14 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_SHIFT (0U)
/*! HwtSwizzleHwtAddress14 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HWTSWIZZLEHWTADDRESS14_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS15 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_SHIFT (0U)
/*! HwtSwizzleHwtAddress15 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HWTSWIZZLEHWTADDRESS15_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTADDRESS17 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_SHIFT (0U)
/*! HwtSwizzleHwtAddress17 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HWTSWIZZLEHWTADDRESS17_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTACTN - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_SHIFT (0U)
/*! HwtSwizzleHwtActN - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HWTSWIZZLEHWTACTN_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTBANK0 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_SHIFT (0U)
/*! HwtSwizzleHwtBank0 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HWTSWIZZLEHWTBANK0_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTBANK1 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_SHIFT (0U)
/*! HwtSwizzleHwtBank1 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HWTSWIZZLEHWTBANK1_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTBANK2 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_SHIFT (0U)
/*! HwtSwizzleHwtBank2 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HWTSWIZZLEHWTBANK2_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTBG0 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_SHIFT (0U)
/*! HwtSwizzleHwtBg0 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HWTSWIZZLEHWTBG0_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTBG1 - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_SHIFT (0U)
/*! HwtSwizzleHwtBg1 - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HWTSWIZZLEHWTBG1_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTCASN - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_SHIFT (0U)
/*! HwtSwizzleHwtCasN - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HWTSWIZZLEHWTCASN_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTRASN - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_SHIFT (0U)
/*! HwtSwizzleHwtRasN - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HWTSWIZZLEHWTRASN_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTWEN - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_SHIFT (0U)
/*! HwtSwizzleHwtWeN - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HWTSWIZZLEHWTWEN_MASK)
/*! @} */
/*! @name HWTSWIZZLEHWTPARITYIN - Signal swizzle selection for HWT swizzle */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_SHIFT (0U)
/*! HwtSwizzleHwtParityIn - See Description of HwtSwizzleHwtAddress0 for details.
*/
#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_SHIFT)) & DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HWTSWIZZLEHWTPARITYIN_MASK)
/*! @} */
/*! @name DFIHANDSHAKEDELAYS0 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_SHIFT (0U)
/*! PhyUpdAckDelay0 - Adds 0-15 DfiClks of delay after dfi0_phyupd_ack asserts, before the PHY takes
* any action (such as starting DDL calibration).
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDACKDELAY0_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_SHIFT (4U)
/*! PhyUpdReqDelay0 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi0_phyupd_req.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PHYUPDREQDELAY0_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_SHIFT (8U)
/*! CtrlUpdAckDelay0 - Adds 0-15 DfiClks of delay after dfi0_ctrlupd_req asserts, before the PHY takes any action.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDACKDELAY0_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_SHIFT (12U)
/*! CtrlUpdReqDelay0 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi0_ctrlupd_ack.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CTRLUPDREQDELAY0_MASK)
/*! @} */
/*! @name DFIHANDSHAKEDELAYS1 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal assertions exceed the programmed delays */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_SHIFT (0U)
/*! PhyUpdAckDelay1 - Adds 0-15 DfiClks of delay after dfi1_phyupd_ack asserts, before the PHY takes
* any action (such as starting DDL calibration).
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDACKDELAY1_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_SHIFT (4U)
/*! PhyUpdReqDelay1 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi1_phyupd_req.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PHYUPDREQDELAY1_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_SHIFT (8U)
/*! CtrlUpdAckDelay1 - Adds 0-15 DfiClks of delay after dfi1_ctrlupd_req asserts, before the PHY takes any action.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDACKDELAY1_MASK)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_MASK (0xF000U)
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_SHIFT (12U)
/*! CtrlUpdReqDelay1 - Adds 0-15 DfiClks of delay after the PHY completes all PHY update activities, before deasserting dfi1_ctrlupd_ack.
*/
#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CTRLUPDREQDELAY1_MASK)
/*! @} */
/*! @name CALUCLKINFO_P1 - Impedance Calibration Clock Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_MASK (0x3FFU)
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_SHIFT (0U)
/*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24.
*/
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CALUCLKTICKSPER1US_MASK)
/*! @} */
/*! @name SEQ0BDLY0_P1 - PHY Initialization Engine (PIE) Delay Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_SHIFT (0U)
/*! Seq0BDLY0_p1 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_SEQ0BDLY0_P1_MASK)
/*! @} */
/*! @name SEQ0BDLY1_P1 - PHY Initialization Engine (PIE) Delay Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_SHIFT (0U)
/*! Seq0BDLY1_p1 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_SEQ0BDLY1_P1_MASK)
/*! @} */
/*! @name SEQ0BDLY2_P1 - PHY Initialization Engine (PIE) Delay Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_SHIFT (0U)
/*! Seq0BDLY2_p1 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_SEQ0BDLY2_P1_MASK)
/*! @} */
/*! @name SEQ0BDLY3_P1 - PHY Initialization Engine (PIE) Delay Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_SHIFT (0U)
/*! Seq0BDLY3_p1 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_SEQ0BDLY3_P1_MASK)
/*! @} */
/*! @name PPTTRAINSETUP_P1 - Setup Intervals for DFI PHY Master operations */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_SHIFT (0U)
/*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRTRAININTERVAL_MASK)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_MASK (0x70U)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_SHIFT (4U)
/*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PHYMSTRMAXREQTOACK_MASK)
/*! @} */
/*! @name TRISTATEMODECA_P1 - Mode select register for MEMCLK/Address/Command Tristates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_SHIFT (0U)
/*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DISDYNADRTRI_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_SHIFT (1U)
/*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMODE_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_SHIFT (2U)
/*! CkDisVal - The PHY provides 4 memory clocks, n=0.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CKDISVAL_MASK)
/*! @} */
/*! @name HWTMRL_P1 - HWT MaxReadLatency. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_SHIFT (0U)
/*! HwtMRL_p1 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P1_HWTMRL_P1_MASK)
/*! @} */
/*! @name DQSPREAMBLECONTROL_P1 - Control the PHY logic related to the read and write DQS preamble */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_SHIFT (0U)
/*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
* take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
* configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKRXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_SHIFT (1U)
/*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
* DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_MASK (0x1CU)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_SHIFT (2U)
/*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_POSITIONDFEINIT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
/*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
* TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TGLTWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_SHIFT (6U)
/*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4POSTAMBLEEXT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_SHIFT (7U)
/*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
* to the same timing group when the bubble is 1 memclk.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4STTCPREBRIDGERXEN_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT (8U)
/*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
* respectively, before and after a write burst, except during a memory read transaction.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK)
/*! @} */
/*! @name DMIPINPRESENT_P1 - This Register is used to enable the Read-DBI function in each DBYTE */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_SHIFT (0U)
/*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device.
*/
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RDDBIENABLED_MASK)
/*! @} */
/*! @name ARDPTRINITVAL_P1 - Address/Command FIFO ReadPointer Initial Value */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_SHIFT (0U)
/*! ARdPtrInitVal_p1 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips.
*/
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARDPTRINITVAL_P1_MASK)
/*! @} */
/*! @name PROCODTTIMECTL_P1 - READ DATA On-Die Termination Timing Control (by PHY) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_SHIFT (0U)
/*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
* Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
* 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
* to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTTAILWIDTH_MASK)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_SHIFT (2U)
/*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
* start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
* from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_PODTSTARTDELAY_MASK)
/*! @} */
/*! @name DLLGAINCTL_P1 - DLL gain control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_SHIFT (0U)
/*! DllGainIV - Initial value of DllGain.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINIV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_SHIFT (4U)
/*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
* used for maintaining lock, ie tracking pclk variation.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLGAINTV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_SHIFT (8U)
/*! DllSeedSel - Reserved, must be configured to be 0.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DLLSEEDSEL_MASK)
/*! @} */
/*! @name DFIRDDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_SHIFT (0U)
/*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
* dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_SHIFT (2U)
/*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
* dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_SHIFT (4U)
/*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
* dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_SHIFT (6U)
/*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
* dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DFIRDDESTM3_MASK)
/*! @} */
/*! @name VREFINGLOBAL_P1 - PHY Global Vref Controls */
/*! @{ */
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_SHIFT (0U)
/*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
* ========================================================== 2'b00 - PHY Vref DAC Range0 --
* BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
* Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
* ========================================================== GlobalVrefInSel[2] shall be set according to Dram
* Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
* 1'b0 LPDDR3 1'b0 LPDDR4 1'b1
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINSEL_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_MASK (0x3F8U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_SHIFT (3U)
/*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
* by GlobalVrefInSel[2] ========================================================== RANGE0 :
* DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
* 0.
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINDAC_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_MASK (0x3C00U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_SHIFT (10U)
/*! GlobalVrefInTrim - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINTRIM_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_SHIFT (14U)
/*! GlobalVrefInMode - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GLOBALVREFINMODE_MASK)
/*! @} */
/*! @name DFIWRDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_SHIFT (0U)
/*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_SHIFT (2U)
/*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_SHIFT (4U)
/*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_SHIFT (6U)
/*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
* TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DFIWRDESTM3_MASK)
/*! @} */
/*! @name PLLCTRL2_P1 - PState dependent PLL Control Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_SHIFT (0U)
/*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PLLFREQSEL_MASK)
/*! @} */
/*! @name PLLCTRL1_P1 - PState dependent PLL Control Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_SHIFT (0U)
/*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPINTCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_SHIFT (5U)
/*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PLLCPPROPCTRL_MASK)
/*! @} */
/*! @name PLLTESTMODE_P1 - Additional controls for PLL CP/VCO modes of operation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_SHIFT (0U)
/*! PllTestMode_p1 - It is required to use default values for this CSR unless directed otherwise by Synopsys.
*/
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PLLTESTMODE_P1_MASK)
/*! @} */
/*! @name PLLCTRL4_P1 - PState dependent PLL Control Register 4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_SHIFT (0U)
/*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPINTGSCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_SHIFT (5U)
/*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PLLCPPROPGSCTRL_MASK)
/*! @} */
/*! @name DFIFREQRATIO_P1 - DFI Frequency Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_SHIFT (0U)
/*! DfiFreqRatio_p1 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
* 1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DFIFREQRATIO_P1_MASK)
/*! @} */
/*! @name CALUCLKINFO_P2 - Impedance Calibration Clock Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_MASK (0x3FFU)
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_SHIFT (0U)
/*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24.
*/
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CALUCLKTICKSPER1US_MASK)
/*! @} */
/*! @name SEQ0BDLY0_P2 - PHY Initialization Engine (PIE) Delay Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_SHIFT (0U)
/*! Seq0BDLY0_p2 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_SEQ0BDLY0_P2_MASK)
/*! @} */
/*! @name SEQ0BDLY1_P2 - PHY Initialization Engine (PIE) Delay Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_SHIFT (0U)
/*! Seq0BDLY1_p2 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_SEQ0BDLY1_P2_MASK)
/*! @} */
/*! @name SEQ0BDLY2_P2 - PHY Initialization Engine (PIE) Delay Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_SHIFT (0U)
/*! Seq0BDLY2_p2 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_SEQ0BDLY2_P2_MASK)
/*! @} */
/*! @name SEQ0BDLY3_P2 - PHY Initialization Engine (PIE) Delay Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_SHIFT (0U)
/*! Seq0BDLY3_p2 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_SEQ0BDLY3_P2_MASK)
/*! @} */
/*! @name PPTTRAINSETUP_P2 - Setup Intervals for DFI PHY Master operations */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_SHIFT (0U)
/*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRTRAININTERVAL_MASK)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_MASK (0x70U)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_SHIFT (4U)
/*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PHYMSTRMAXREQTOACK_MASK)
/*! @} */
/*! @name TRISTATEMODECA_P2 - Mode select register for MEMCLK/Address/Command Tristates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_SHIFT (0U)
/*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DISDYNADRTRI_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_SHIFT (1U)
/*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMODE_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_SHIFT (2U)
/*! CkDisVal - The PHY provides 4 memory clocks, n=0.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CKDISVAL_MASK)
/*! @} */
/*! @name HWTMRL_P2 - HWT MaxReadLatency. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_SHIFT (0U)
/*! HwtMRL_p2 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P2_HWTMRL_P2_MASK)
/*! @} */
/*! @name DQSPREAMBLECONTROL_P2 - Control the PHY logic related to the read and write DQS preamble */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_SHIFT (0U)
/*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
* take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
* configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKRXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_SHIFT (1U)
/*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
* DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_MASK (0x1CU)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_SHIFT (2U)
/*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_POSITIONDFEINIT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
/*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
* TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TGLTWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_SHIFT (6U)
/*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4POSTAMBLEEXT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_SHIFT (7U)
/*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
* to the same timing group when the bubble is 1 memclk.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4STTCPREBRIDGERXEN_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT (8U)
/*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
* respectively, before and after a write burst, except during a memory read transaction.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK)
/*! @} */
/*! @name DMIPINPRESENT_P2 - This Register is used to enable the Read-DBI function in each DBYTE */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_SHIFT (0U)
/*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device.
*/
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RDDBIENABLED_MASK)
/*! @} */
/*! @name ARDPTRINITVAL_P2 - Address/Command FIFO ReadPointer Initial Value */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_SHIFT (0U)
/*! ARdPtrInitVal_p2 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips.
*/
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARDPTRINITVAL_P2_MASK)
/*! @} */
/*! @name PROCODTTIMECTL_P2 - READ DATA On-Die Termination Timing Control (by PHY) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_SHIFT (0U)
/*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
* Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
* 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
* to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTTAILWIDTH_MASK)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_SHIFT (2U)
/*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
* start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
* from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_PODTSTARTDELAY_MASK)
/*! @} */
/*! @name DLLGAINCTL_P2 - DLL gain control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_SHIFT (0U)
/*! DllGainIV - Initial value of DllGain.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINIV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_SHIFT (4U)
/*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
* used for maintaining lock, ie tracking pclk variation.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLGAINTV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_SHIFT (8U)
/*! DllSeedSel - Reserved, must be configured to be 0.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DLLSEEDSEL_MASK)
/*! @} */
/*! @name DFIRDDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_SHIFT (0U)
/*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
* dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_SHIFT (2U)
/*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
* dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_SHIFT (4U)
/*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
* dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_SHIFT (6U)
/*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
* dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DFIRDDESTM3_MASK)
/*! @} */
/*! @name VREFINGLOBAL_P2 - PHY Global Vref Controls */
/*! @{ */
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_SHIFT (0U)
/*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
* ========================================================== 2'b00 - PHY Vref DAC Range0 --
* BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
* Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
* ========================================================== GlobalVrefInSel[2] shall be set according to Dram
* Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
* 1'b0 LPDDR3 1'b0 LPDDR4 1'b1
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINSEL_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_MASK (0x3F8U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_SHIFT (3U)
/*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
* by GlobalVrefInSel[2] ========================================================== RANGE0 :
* DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
* 0.
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINDAC_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_MASK (0x3C00U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_SHIFT (10U)
/*! GlobalVrefInTrim - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINTRIM_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_SHIFT (14U)
/*! GlobalVrefInMode - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GLOBALVREFINMODE_MASK)
/*! @} */
/*! @name DFIWRDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_SHIFT (0U)
/*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_SHIFT (2U)
/*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_SHIFT (4U)
/*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_SHIFT (6U)
/*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
* TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DFIWRDESTM3_MASK)
/*! @} */
/*! @name PLLCTRL2_P2 - PState dependent PLL Control Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_SHIFT (0U)
/*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PLLFREQSEL_MASK)
/*! @} */
/*! @name PLLCTRL1_P2 - PState dependent PLL Control Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_SHIFT (0U)
/*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPINTCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_SHIFT (5U)
/*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PLLCPPROPCTRL_MASK)
/*! @} */
/*! @name PLLTESTMODE_P2 - Additional controls for PLL CP/VCO modes of operation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_SHIFT (0U)
/*! PllTestMode_p2 - It is required to use default values for this CSR unless directed otherwise by Synopsys.
*/
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PLLTESTMODE_P2_MASK)
/*! @} */
/*! @name PLLCTRL4_P2 - PState dependent PLL Control Register 4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_SHIFT (0U)
/*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPINTGSCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_SHIFT (5U)
/*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PLLCPPROPGSCTRL_MASK)
/*! @} */
/*! @name DFIFREQRATIO_P2 - DFI Frequency Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_SHIFT (0U)
/*! DfiFreqRatio_p2 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
* 1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DFIFREQRATIO_P2_MASK)
/*! @} */
/*! @name CALUCLKINFO_P3 - Impedance Calibration Clock Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_MASK (0x3FFU)
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_SHIFT (0U)
/*! CalUClkTicksPer1uS - Must be programmed to the number of DfiClks in 1us (rounded up), with minimum value of 24.
*/
#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_SHIFT)) & DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CALUCLKTICKSPER1US_MASK)
/*! @} */
/*! @name SEQ0BDLY0_P3 - PHY Initialization Engine (PIE) Delay Register 0 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_SHIFT (0U)
/*! Seq0BDLY0_p3 - PHY Initialization Engine (PIE) Delay Register 0 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_SEQ0BDLY0_P3_MASK)
/*! @} */
/*! @name SEQ0BDLY1_P3 - PHY Initialization Engine (PIE) Delay Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_SHIFT (0U)
/*! Seq0BDLY1_p3 - PHY Initialization Engine (PIE) Delay Register 1 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_SEQ0BDLY1_P3_MASK)
/*! @} */
/*! @name SEQ0BDLY2_P3 - PHY Initialization Engine (PIE) Delay Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_SHIFT (0U)
/*! Seq0BDLY2_p3 - PHY Initialization Engine (PIE) Delay Register 2 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_SEQ0BDLY2_P3_MASK)
/*! @} */
/*! @name SEQ0BDLY3_P3 - PHY Initialization Engine (PIE) Delay Register 3 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_SHIFT (0U)
/*! Seq0BDLY3_p3 - PHY Initialization Engine (PIE) Delay Register 3 This register is available for
* selection by the NOP and WAIT instructions in the PIE for the delay value.
*/
#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_SHIFT)) & DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_SEQ0BDLY3_P3_MASK)
/*! @} */
/*! @name PPTTRAINSETUP_P3 - Setup Intervals for DFI PHY Master operations */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_SHIFT (0U)
/*! PhyMstrTrainInterval - Bits 3:0 of this register specifies the time between the end of one training and the start of the next.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRTRAININTERVAL_MASK)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_MASK (0x70U)
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_SHIFT (4U)
/*! PhyMstrMaxReqToAck - Bits 6:4 of this register specify the max time from tdfi_phymstr_req asserted to tdfi_phymstr_ack asserted.
*/
#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_SHIFT)) & DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PHYMSTRMAXREQTOACK_MASK)
/*! @} */
/*! @name TRISTATEMODECA_P3 - Mode select register for MEMCLK/Address/Command Tristates */
/*! @{ */
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_SHIFT (0U)
/*! DisDynAdrTri - When DisDynAdrTri=1, Dynamic Tristating is disabled.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DISDYNADRTRI_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_SHIFT (1U)
/*! DDR2TMode - Must be set to 1 for Dynamic Tristate to work when CA bus is 2T or Geardown mode.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMODE_MASK)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_SHIFT (2U)
/*! CkDisVal - The PHY provides 4 memory clocks, n=0.
*/
#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_SHIFT)) & DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CKDISVAL_MASK)
/*! @} */
/*! @name HWTMRL_P3 - HWT MaxReadLatency. */
/*! @{ */
#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_SHIFT (0U)
/*! HwtMRL_p3 - This Max Read Latency CSR is to be trained to ensure the rx-data fifo is not read
* until after all dbytes have their read data valid.
*/
#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_SHIFT)) & DWC_DDRPHYA_MASTER_HWTMRL_P3_HWTMRL_P3_MASK)
/*! @} */
/*! @name DQSPREAMBLECONTROL_P3 - Control the PHY logic related to the read and write DQS preamble */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_SHIFT (0U)
/*! TwoTckRxDqsPre - Widens the RxDqsEn window to allow larger drift in the incoming read DQS to
* take advantage of the larger/wider preamble generated by the DRAMSs when the D4 DRAMS are
* configured with DDR4 MR4 A11 Read Preamble=1 for causing a 2nCK read preamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKRXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_MASK (0x2U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_SHIFT (1U)
/*! TwoTckTxDqsPre - 0: Standard 1tck TxDqs Preamble 1: Enable Optional D4 2tck TxDqs Preamble The
* DDR4 MR4 A12 is Write Preamble, 1=2nCK, 0=1nCK.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_MASK (0x1CU)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_SHIFT (2U)
/*! PositionDfeInit - For DDR4 phy only when receive DFE is enabled.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_POSITIONDFEINIT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_MASK (0x20U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_SHIFT (5U)
/*! LP4TglTwoTckTxDqsPre - Used in LPDDR4 mode to modify the early preamble when Register
* TwoTckTxDqsPre=1 0: level first-memclk preamble 1: toggling first-memclk preamble
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TGLTWOTCKTXDQSPRE_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_MASK (0x40U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_SHIFT (6U)
/*! LP4PostambleExt - In LPDDR4 mode must be set to extend the write postamble.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4POSTAMBLEEXT_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_MASK (0x80U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_SHIFT (7U)
/*! LP4SttcPreBridgeRxEn - Used in LPDDR4 static-preamble mode to bridge the RxEn between two reads
* to the same timing group when the bubble is 1 memclk.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4STTCPREBRIDGERXEN_MASK)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK (0x100U)
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT (8U)
/*! WDQSEXTENSION - When set, DQS_T and DQS_C will be driven differentially to 0 and 1,
* respectively, before and after a write burst, except during a memory read transaction.
*/
#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT)) & DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK)
/*! @} */
/*! @name DMIPINPRESENT_P3 - This Register is used to enable the Read-DBI function in each DBYTE */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_MASK (0x1U)
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_SHIFT (0U)
/*! RdDbiEnabled - This bit must be set to 1'b1 if Read-DBI is enabled in a connected DDR4 or LPDDR4 device.
*/
#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_SHIFT)) & DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RDDBIENABLED_MASK)
/*! @} */
/*! @name ARDPTRINITVAL_P3 - Address/Command FIFO ReadPointer Initial Value */
/*! @{ */
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_SHIFT (0U)
/*! ARdPtrInitVal_p3 - This is the initial Pointer Offset for the free-running FIFOs in the DBYTE and ACX4 hardips.
*/
#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_SHIFT)) & DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARDPTRINITVAL_P3_MASK)
/*! @} */
/*! @name PROCODTTIMECTL_P3 - READ DATA On-Die Termination Timing Control (by PHY) */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_SHIFT (0U)
/*! POdtTailWidth - controls the length of the tail of ProcOdt, units of UI 3 tail 3UI more than for
* Register POdtTailWidth=0, maximum 2 tail 2UI more than for Register POdtTailWidth=0, default
* 1 tail 1UI more than for Register POdtTailWidth=0 0 minimum length tail The time from ProcODT
* to closing the window to receive DQS to ProcODT POdtTailWidth is (2 + POdtTailWidth) UI
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTTAILWIDTH_MASK)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_SHIFT (2U)
/*! POdtStartDelay - controls the start of ProcOdt, units of UI 3 delay start 2 UI, maximum delay of
* start of ProcOdt 2 delay start 1 UI, 1 delay start 0 UI, default 0 early by 1 UI, The time
* from ProcODT assertion to opening the window to receive DQS is (10 - POdtStartDelay) UI.
*/
#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_SHIFT)) & DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_PODTSTARTDELAY_MASK)
/*! @} */
/*! @name DLLGAINCTL_P3 - DLL gain control */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_MASK (0xFU)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_SHIFT (0U)
/*! DllGainIV - Initial value of DllGain.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINIV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_MASK (0xF0U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_SHIFT (4U)
/*! DllGainTV - Terminal value of DllGain, ie the value in effect when locking is done and the value
* used for maintaining lock, ie tracking pclk variation.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLGAINTV_MASK)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_MASK (0xF00U)
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_SHIFT (8U)
/*! DllSeedSel - Reserved, must be configured to be 0.
*/
#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_SHIFT)) & DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DLLSEEDSEL_MASK)
/*! @} */
/*! @name DFIRDDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_SHIFT (0U)
/*! DfiRdDestm0 - Maps dfi_rddata_cs_n_p0[0] to dest DfiRdDestm0 timing For example, if 0
* dfi_rddata_cs_n_p0[0] will use Register RxEn,ClkDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_SHIFT (2U)
/*! DfiRdDestm1 - Maps dfi_rddata_cs_n_p0[1] to dest DfiRdDestm1 timing For example, if 1
* dfi_rddata_cs_n[_p01] will use Register RxEn,ClkDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_SHIFT (4U)
/*! DfiRdDestm2 - Maps dfi_rddata_cs_n_p0[2] to dest DfiRdDestm2 timing For example, if 2
* dfi_rddata_cs_n_p0[2] will use Register RxEn,ClkDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_SHIFT (6U)
/*! DfiRdDestm3 - Maps dfi_rddata_cs_n_p0[3] to dest DfiRdDestm3 timing For example, if 3
* dfi_rddata_cs_n_p0[3] will use Register RxEn,ClkDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DFIRDDESTM3_MASK)
/*! @} */
/*! @name VREFINGLOBAL_P3 - PHY Global Vref Controls */
/*! @{ */
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_MASK (0x7U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_SHIFT (0U)
/*! GlobalVrefInSel - GlobalVrefInSel[1:0] controls the mode of the PHY VREF DAC and the BP_VREF pin
* ========================================================== 2'b00 - PHY Vref DAC Range0 --
* BP_VREF = Hi-Z 2'b01 - Reserved Encoding 2'b10 - PHY Vref DAC Range0 -- BP_VREF connected to PLL
* Analog Bus 2'b11 - PHY Vref DAC Range0 -- BP_VREF connected to PHY Vref DAC
* ========================================================== GlobalVrefInSel[2] shall be set according to Dram
* Protocol: Protocol GlobalVrefInSel[2] ------------------------------------------ DDR3 1'b0 DDR4
* 1'b0 LPDDR3 1'b0 LPDDR4 1'b1
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINSEL_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_MASK (0x3F8U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_SHIFT (3U)
/*! GlobalVrefInDAC - DAC code for internal Vref generation The DAC has two ranges; the range is set
* by GlobalVrefInSel[2] ========================================================== RANGE0 :
* DDR3,DDR4,LPDDR3 [GlobalVrefInSel[2] = 0] DAC Output Voltage = GlobalVrefInDAC == 6'h00 ? Hi-Z :
* 0.
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINDAC_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_MASK (0x3C00U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_SHIFT (10U)
/*! GlobalVrefInTrim - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINTRIM_MASK)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_MASK (0x4000U)
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_SHIFT (14U)
/*! GlobalVrefInMode - RSVD
*/
#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_SHIFT)) & DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GLOBALVREFINMODE_MASK)
/*! @} */
/*! @name DFIWRDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_SHIFT (0U)
/*! DfiWrDestm0 - Maps dfi_wrdata_cs_n_p0[0] to dest DfiWrDestm0 timing For example, if 0
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg0 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM0_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_MASK (0xCU)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_SHIFT (2U)
/*! DfiWrDestm1 - Maps dfi_wrdata_cs_n_p0[1] to dest DfiWrDestm1 timing For example, if 1
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg1 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM1_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_MASK (0x30U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_SHIFT (4U)
/*! DfiWrDestm2 - Maps dfi_wrdata_cs_n_p0[2] to dest DfiWrDestm2 timing For example, if 2
* dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg2 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM2_MASK)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_MASK (0xC0U)
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_SHIFT (6U)
/*! DfiWrDestm3 - Maps dfi_wrdata_cs_n_p0[3] to dest DfiWrDestm3 timing (use Register
* TxDq,DqsDlyTg3) For example, if 3 dfi_wrdata_cs_n_p0[0] will use Register TxDq,DqsDlyTg3 timing.
*/
#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DFIWRDESTM3_MASK)
/*! @} */
/*! @name PLLCTRL2_P3 - PState dependent PLL Control Register 2 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_SHIFT (0U)
/*! PllFreqSel - Adjusts the loop parameters to compensate for different VCO bias points, and input/output clock division ratios.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PLLFREQSEL_MASK)
/*! @} */
/*! @name PLLCTRL1_P3 - PState dependent PLL Control Register 1 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_SHIFT (0U)
/*! PllCpIntCtrl - connects directly to cp_int_cntrl<1:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPINTCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_SHIFT (5U)
/*! PllCpPropCtrl - connects directly to cp_prop_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PLLCPPROPCTRL_MASK)
/*! @} */
/*! @name PLLTESTMODE_P3 - Additional controls for PLL CP/VCO modes of operation */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_MASK (0xFFFFU)
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_SHIFT (0U)
/*! PllTestMode_p3 - It is required to use default values for this CSR unless directed otherwise by Synopsys.
*/
#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_SHIFT)) & DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PLLTESTMODE_P3_MASK)
/*! @} */
/*! @name PLLCTRL4_P3 - PState dependent PLL Control Register 4 */
/*! @{ */
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_MASK (0x1FU)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_SHIFT (0U)
/*! PllCpIntGsCtrl - connects directly to cp_int_gs_cntrl<4:0> in PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPINTGSCTRL_MASK)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_MASK (0x1E0U)
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_SHIFT (5U)
/*! PllCpPropGsCtrl - connects directly to cp_prop_gs_cntrl<3:0> of PLL.
*/
#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_SHIFT)) & DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PLLCPPROPGSCTRL_MASK)
/*! @} */
/*! @name DFIFREQRATIO_P3 - DFI Frequency Ratio */
/*! @{ */
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_MASK (0x3U)
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_SHIFT (0U)
/*! DfiFreqRatio_p3 - Used in dwc_ddrphy_pub_serdes to serialize or de-serialize DFI signals 00 =
* 1:1 mode 01 = 1:2 mode 1x = 1:4 mode* *Note: 1:4 is for future pub revision.
*/
#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3(x) (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_SHIFT)) & DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DFIFREQRATIO_P3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DWC_DDRPHYA_MASTER_Register_Masks */
/* DWC_DDRPHYA_MASTER - Peripheral instance base addresses */
/** Peripheral DWC_DDRPHYA_MASTER0 base address */
#define DWC_DDRPHYA_MASTER0_BASE (0x3C020000u)
/** Peripheral DWC_DDRPHYA_MASTER0 base pointer */
#define DWC_DDRPHYA_MASTER0 ((DWC_DDRPHYA_MASTER_Type *)DWC_DDRPHYA_MASTER0_BASE)
/** Array initializer of DWC_DDRPHYA_MASTER peripheral base addresses */
#define DWC_DDRPHYA_MASTER_BASE_ADDRS { DWC_DDRPHYA_MASTER0_BASE }
/** Array initializer of DWC_DDRPHYA_MASTER peripheral base pointers */
#define DWC_DDRPHYA_MASTER_BASE_PTRS { DWC_DDRPHYA_MASTER0 }
/*!
* @}
*/ /* end of group DWC_DDRPHYA_MASTER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EARC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EARC_Peripheral_Access_Layer EARC Peripheral Access Layer
* @{
*/
/** EARC - Register Layout Typedef */
typedef struct {
__IO uint32_t VERSION; /**< Version control register, offset: 0x0 */
uint8_t RESERVED_0[12];
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< External control register, offset: 0x10 */
__IO uint32_t SET; /**< External control register, offset: 0x14 */
__IO uint32_t CLR; /**< External control register, offset: 0x18 */
__IO uint32_t TOG; /**< External control register, offset: 0x1C */
} EXT_CTRL;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< External Status register, offset: 0x20 */
__IO uint32_t SET; /**< External Status register, offset: 0x24 */
__IO uint32_t CLR; /**< External Status register, offset: 0x28 */
__IO uint32_t TOG; /**< External Status register, offset: 0x2C */
} EXT_STATUS;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< Interrupt enables for interrupt 0, offset: 0x30 */
__IO uint32_t SET; /**< Interrupt enables for interrupt 0, offset: 0x34 */
__IO uint32_t CLR; /**< Interrupt enables for interrupt 0, offset: 0x38 */
__IO uint32_t TOG; /**< Interrupt enables for interrupt 0, offset: 0x3C */
} EXT_IER0;
struct { /* offset: 0x40 */
__IO uint32_t RW; /**< Interrupt enables for interrupt 1, offset: 0x40 */
__IO uint32_t SET; /**< Interrupt enables for interrupt 1, offset: 0x44 */
__IO uint32_t CLR; /**< Interrupt enables for interrupt 1, offset: 0x48 */
__IO uint32_t TOG; /**< Interrupt enables for interrupt 1, offset: 0x4C */
} EXT_IER1;
struct { /* offset: 0x50 */
__IO uint32_t RW; /**< External Interrupt Status register, offset: 0x50 */
__IO uint32_t SET; /**< External Interrupt Status register, offset: 0x54 */
__IO uint32_t CLR; /**< External Interrupt Status register, offset: 0x58 */
__IO uint32_t TOG; /**< External Interrupt Status register, offset: 0x5C */
} EXT_ISR;
uint8_t RESERVED_1[16];
struct { /* offset: 0x70 */
__IO uint32_t RW; /**< Interrupt enable register for M0+, offset: 0x70 */
__IO uint32_t SET; /**< Interrupt enable register for M0+, offset: 0x74 */
__IO uint32_t CLR; /**< Interrupt enable register for M0+, offset: 0x78 */
__IO uint32_t TOG; /**< Interrupt enable register for M0+, offset: 0x7C */
} IER;
struct { /* offset: 0x80 */
__IO uint32_t RW; /**< Interrupt status register, offset: 0x80 */
__IO uint32_t SET; /**< Interrupt status register, offset: 0x84 */
__IO uint32_t CLR; /**< Interrupt status register, offset: 0x88 */
__IO uint32_t TOG; /**< Interrupt status register, offset: 0x8C */
} ISR;
struct { /* offset: 0x90 */
__IO uint32_t RW; /**< AI interface control register, offset: 0x90 */
__IO uint32_t SET; /**< AI interface control register, offset: 0x94 */
__IO uint32_t CLR; /**< AI interface control register, offset: 0x98 */
__IO uint32_t TOG; /**< AI interface control register, offset: 0x9C */
} PHY_AI_CTRL;
__IO uint32_t PHY_AI_WDATA; /**< AI interface WDATA register, offset: 0xA0 */
__I uint32_t PHY_AI_RDATA; /**< AI interface RDATA register, offset: 0xA4 */
__I uint32_t DPATH_STATUS; /**< Audio XCVR datapath status, offset: 0xA8 */
uint8_t RESERVED_2[20];
struct { /* offset: 0xC0 */
__IO uint32_t RW; /**< CMDC receiver control register, offset: 0xC0 */
__IO uint32_t SET; /**< CMDC receiver control register, offset: 0xC4 */
__IO uint32_t CLR; /**< CMDC receiver control register, offset: 0xC8 */
__IO uint32_t TOG; /**< CMDC receiver control register, offset: 0xCC */
} RX_CMDC_CTRL;
__I uint32_t RX_CMDC_STATUS; /**< eARC receiver CMDC status, offset: 0xD0 */
uint8_t RESERVED_3[12];
__IO uint32_t RX_CMDC_TX_DATA; /**< CMDC transmit data register, offset: 0xE0 */
uint8_t RESERVED_4[12];
__I uint32_t RX_CMDC_RX_DATA; /**< CMDC receive data register, offset: 0xF0 */
uint8_t RESERVED_5[140];
struct { /* offset: 0x180 */
__IO uint32_t RW; /**< Data path control register, offset: 0x180 */
__IO uint32_t SET; /**< Data path control register, offset: 0x184 */
__IO uint32_t CLR; /**< Data path control register, offset: 0x188 */
__IO uint32_t TOG; /**< Data path control register, offset: 0x18C */
} RX_DATAPATH_CTRL;
__I uint32_t RX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x190, array step: 0x4 */
__I uint32_t RX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x1A8, array step: 0x4 */
struct { /* offset: 0x1C0 */
__IO uint32_t RW; /**< DMAC counter control register, offset: 0x1C0 */
__IO uint32_t SET; /**< DMAC counter control register, offset: 0x1C4 */
__IO uint32_t CLR; /**< DMAC counter control register, offset: 0x1C8 */
__IO uint32_t TOG; /**< DMAC counter control register, offset: 0x1CC */
} RX_DPATH_CNTR_CTRL;
__I uint32_t RX_DPATH_TSCR; /**< Receive Datapath Timestamp Counter Register, offset: 0x1D0 */
__I uint32_t RX_DPATH_BCR; /**< Receive Datapath Bit counter register, offset: 0x1D4 */
__I uint32_t RX_DPATH_BCTR; /**< Receive datapath Bit count timestamp register., offset: 0x1D8 */
__I uint32_t RX_DPATH_BCRR; /**< Receive datapath Bit read timestamp register., offset: 0x1DC */
struct { /* offset: 0x1E0 */
__IO uint32_t RW; /**< Preamble match value register, offset: 0x1E0 */
__IO uint32_t SET; /**< Preamble match value register, offset: 0x1E4 */
__IO uint32_t CLR; /**< Preamble match value register, offset: 0x1E8 */
__IO uint32_t TOG; /**< Preamble match value register, offset: 0x1EC */
} DMAC_PRE_MATCH_VAL;
struct { /* offset: 0x1F0 */
__IO uint32_t RW; /**< Preamble match value register, offset: 0x1F0 */
__IO uint32_t SET; /**< Preamble match value register, offset: 0x1F4 */
__IO uint32_t CLR; /**< Preamble match value register, offset: 0x1F8 */
__IO uint32_t TOG; /**< Preamble match value register, offset: 0x1FC */
} DMAC_DTS_PRE_MATCH_VAL;
__IO uint32_t RX_DPATH_PRE_ERR; /**< Error count for IEC60958-1 Block Synchronization., offset: 0x200 */
__IO uint32_t RX_DPATH_PARITY_ERR; /**< Parity Error count for IEC60958-1 Blocks., offset: 0x204 */
uint8_t RESERVED_6[8];
__I uint32_t RX_DPATH_PKT_CNT; /**< Receive Data packet count., offset: 0x210 */
__I uint32_t RX_DPATH_ONE_BIT_ERR_CNT; /**< Receive Data packet Corrected error count., offset: 0x214 */
__I uint32_t DMAC_PRE_MATCH_OFFSET; /**< Preamble match offset value register, offset: 0x218 */
uint8_t RESERVED_7[4];
struct { /* offset: 0x220 */
__IO uint32_t RW; /**< Transmit Data path control register, offset: 0x220 */
__IO uint32_t SET; /**< Transmit Data path control register, offset: 0x224 */
__IO uint32_t CLR; /**< Transmit Data path control register, offset: 0x228 */
__IO uint32_t TOG; /**< Transmit Data path control register, offset: 0x22C */
} TX_DATAPATH_CTRL;
__IO uint32_t TX_CS_DATA_BITS[6]; /**< Channel staus bits, array offset: 0x230, array step: 0x4 */
__IO uint32_t TX_USER_DATA_BITS[6]; /**< User data bits, array offset: 0x248, array step: 0x4 */
struct { /* offset: 0x260 */
__IO uint32_t RW; /**< DMAC counter control register, offset: 0x260 */
__IO uint32_t SET; /**< DMAC counter control register, offset: 0x264 */
__IO uint32_t CLR; /**< DMAC counter control register, offset: 0x268 */
__IO uint32_t TOG; /**< DMAC counter control register, offset: 0x26C */
} TX_DPATH_CNTR_CTRL;
__I uint32_t TX_DPATH_TSCR; /**< Transmit Datapath Timestamp Counter Register, offset: 0x270 */
__I uint32_t TX_DPATH_BCR; /**< Transmit Datapath Bit counter register, offset: 0x274 */
__I uint32_t TX_DPATH_BCTR; /**< Transmit datapath Bit count timestamp register., offset: 0x278 */
__I uint32_t TX_DPATH_BCRR; /**< Transmmit datapath Bit read timestamp register., offset: 0x27C */
uint8_t RESERVED_8[32];
struct { /* offset: 0x2A0 */
__IO uint32_t RW; /**< HPD Debounce Control Register, offset: 0x2A0 */
__IO uint32_t SET; /**< HPD Debounce Control Register, offset: 0x2A4 */
__IO uint32_t CLR; /**< HPD Debounce Control Register, offset: 0x2A8 */
__IO uint32_t TOG; /**< HPD Debounce Control Register, offset: 0x2AC */
} HPD_DBNC_CTRL;
uint8_t RESERVED_9[32];
__IO uint32_t TEMPERATURE; /**< Chip Temperature for eARC PHY, offset: 0x2D0 */
} EARC_Type;
/* ----------------------------------------------------------------------------
-- EARC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EARC_Register_Masks EARC Register Masks
* @{
*/
/*! @name VERSION - Version control register */
/*! @{ */
#define EARC_VERSION_VERID_MASK (0xFFFFFFFFU)
#define EARC_VERSION_VERID_SHIFT (0U)
/*! VERID - Version ID
*/
#define EARC_VERSION_VERID(x) (((uint32_t)(((uint32_t)(x)) << EARC_VERSION_VERID_SHIFT)) & EARC_VERSION_VERID_MASK)
/*! @} */
/*! @name EXT_CTRL - External control register */
/*! @{ */
#define EARC_EXT_CTRL_TX_FIFO_WMARK_MASK (0x7FU)
#define EARC_EXT_CTRL_TX_FIFO_WMARK_SHIFT (0U)
/*! TX_FIFO_WMARK - Audio Transmit FIFO Watermark Level
*/
#define EARC_EXT_CTRL_TX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_FIFO_WMARK_SHIFT)) & EARC_EXT_CTRL_TX_FIFO_WMARK_MASK)
#define EARC_EXT_CTRL_RX_FIFO_WMARK_MASK (0x7F00U)
#define EARC_EXT_CTRL_RX_FIFO_WMARK_SHIFT (8U)
/*! RX_FIFO_WMARK - Audio Receive FIFO Watermark Level
*/
#define EARC_EXT_CTRL_RX_FIFO_WMARK(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_FIFO_WMARK_SHIFT)) & EARC_EXT_CTRL_RX_FIFO_WMARK_MASK)
#define EARC_EXT_CTRL_FABRIC_RR_SEL_MASK (0x8000U)
#define EARC_EXT_CTRL_FABRIC_RR_SEL_SHIFT (15U)
/*! FABRIC_RR_SEL - Selects Arbitration mode of crossbar switch.
*/
#define EARC_EXT_CTRL_FABRIC_RR_SEL(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_FABRIC_RR_SEL_SHIFT)) & EARC_EXT_CTRL_FABRIC_RR_SEL_MASK)
#define EARC_EXT_CTRL_PAGE_MASK (0xF0000U)
#define EARC_EXT_CTRL_PAGE_SHIFT (16U)
/*! PAGE - Page Select.
*/
#define EARC_EXT_CTRL_PAGE(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_PAGE_SHIFT)) & EARC_EXT_CTRL_PAGE_MASK)
#define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK (0x200000U)
#define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT (21U)
/*! CORE_SLEEP_HOLD_REQ_B - Hold core from going to sleep mode when 0.
*/
#define EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_SHIFT)) & EARC_EXT_CTRL_CORE_SLEEP_HOLD_REQ_B_MASK)
#define EARC_EXT_CTRL_CORE_WAIT_MASK (0x400000U)
#define EARC_EXT_CTRL_CORE_WAIT_SHIFT (22U)
/*! CORE_WAIT - Stop executing code
*/
#define EARC_EXT_CTRL_CORE_WAIT(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_WAIT_SHIFT)) & EARC_EXT_CTRL_CORE_WAIT_MASK)
#define EARC_EXT_CTRL_SPDIF_MODE_MASK (0x800000U)
#define EARC_EXT_CTRL_SPDIF_MODE_SHIFT (23U)
/*! SPDIF_MODE - Indicates SPDIF output mode.
*/
#define EARC_EXT_CTRL_SPDIF_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SPDIF_MODE_SHIFT)) & EARC_EXT_CTRL_SPDIF_MODE_MASK)
#define EARC_EXT_CTRL_SDMA_WR_REQ_DIS_MASK (0x1000000U)
#define EARC_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT (24U)
/*! SDMA_WR_REQ_DIS - SDMA WR REQ disable
*/
#define EARC_EXT_CTRL_SDMA_WR_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SDMA_WR_REQ_DIS_SHIFT)) & EARC_EXT_CTRL_SDMA_WR_REQ_DIS_MASK)
#define EARC_EXT_CTRL_SDMA_RD_REQ_DIS_MASK (0x2000000U)
#define EARC_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT (25U)
/*! SDMA_RD_REQ_DIS - SDMA RD REQ disable
*/
#define EARC_EXT_CTRL_SDMA_RD_REQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_SDMA_RD_REQ_DIS_SHIFT)) & EARC_EXT_CTRL_SDMA_RD_REQ_DIS_MASK)
#define EARC_EXT_CTRL_TX_DPATH_RESET_MASK (0x8000000U)
#define EARC_EXT_CTRL_TX_DPATH_RESET_SHIFT (27U)
/*! TX_DPATH_RESET - Soft reset to the Datapath for Transmit
*/
#define EARC_EXT_CTRL_TX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_DPATH_RESET_SHIFT)) & EARC_EXT_CTRL_TX_DPATH_RESET_MASK)
#define EARC_EXT_CTRL_RX_DPATH_RESET_MASK (0x10000000U)
#define EARC_EXT_CTRL_RX_DPATH_RESET_SHIFT (28U)
/*! RX_DPATH_RESET - Soft reset to the eARC Differential data Receiver
*/
#define EARC_EXT_CTRL_RX_DPATH_RESET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_DPATH_RESET_SHIFT)) & EARC_EXT_CTRL_RX_DPATH_RESET_MASK)
#define EARC_EXT_CTRL_TX_CMDC_RESET_MASK (0x20000000U)
#define EARC_EXT_CTRL_TX_CMDC_RESET_SHIFT (29U)
/*! TX_CMDC_RESET - Soft reset to the eARC Common mode Transmitter
*/
#define EARC_EXT_CTRL_TX_CMDC_RESET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_TX_CMDC_RESET_SHIFT)) & EARC_EXT_CTRL_TX_CMDC_RESET_MASK)
#define EARC_EXT_CTRL_RX_CMDC_RESET_MASK (0x40000000U)
#define EARC_EXT_CTRL_RX_CMDC_RESET_SHIFT (30U)
/*! RX_CMDC_RESET - Soft reset to the eARC Common mode Receiver
*/
#define EARC_EXT_CTRL_RX_CMDC_RESET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_RX_CMDC_RESET_SHIFT)) & EARC_EXT_CTRL_RX_CMDC_RESET_MASK)
#define EARC_EXT_CTRL_CORE_RESET_MASK (0x80000000U)
#define EARC_EXT_CTRL_CORE_RESET_SHIFT (31U)
/*! CORE_RESET - M0+ Reset
*/
#define EARC_EXT_CTRL_CORE_RESET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_CTRL_CORE_RESET_SHIFT)) & EARC_EXT_CTRL_CORE_RESET_MASK)
/*! @} */
/*! @name EXT_STATUS - External Status register */
/*! @{ */
#define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK (0xFFU)
#define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT (0U)
/*! NO_TX_FIFO_ENTRIES - TX FIFO entries
*/
#define EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_SHIFT)) & EARC_EXT_STATUS_NO_TX_FIFO_ENTRIES_MASK)
#define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK (0xFF00U)
#define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT (8U)
/*! NO_RX_FIFO_ENTRIES - RX FIFO entries
*/
#define EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_SHIFT)) & EARC_EXT_STATUS_NO_RX_FIFO_ENTRIES_MASK)
#define EARC_EXT_STATUS_CM0_SLEEPING_MASK (0x10000U)
#define EARC_EXT_STATUS_CM0_SLEEPING_SHIFT (16U)
/*! CM0_SLEEPING - CM0 is in Sleep mode.
*/
#define EARC_EXT_STATUS_CM0_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_SLEEPING_SHIFT)) & EARC_EXT_STATUS_CM0_SLEEPING_MASK)
#define EARC_EXT_STATUS_CM0_DEEP_SLEEP_MASK (0x20000U)
#define EARC_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT (17U)
/*! CM0_DEEP_SLEEP - CM0 is in deep sleep mode.
*/
#define EARC_EXT_STATUS_CM0_DEEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_DEEP_SLEEP_SHIFT)) & EARC_EXT_STATUS_CM0_DEEP_SLEEP_MASK)
#define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK (0x40000U)
#define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT (18U)
/*! CM0_SLEEP_HOLD_ACK_B - Sleep extension acknowledge.
*/
#define EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_SHIFT)) & EARC_EXT_STATUS_CM0_SLEEP_HOLD_ACK_B_MASK)
#define EARC_EXT_STATUS_TX_PIPE_EMPTY_MASK (0x200000U)
#define EARC_EXT_STATUS_TX_PIPE_EMPTY_SHIFT (21U)
/*! TX_PIPE_EMPTY - Indicates TX pipe status.
*/
#define EARC_EXT_STATUS_TX_PIPE_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_TX_PIPE_EMPTY_SHIFT)) & EARC_EXT_STATUS_TX_PIPE_EMPTY_MASK)
#define EARC_EXT_STATUS_RX_CMDC_RESP_TO_MASK (0x800000U)
#define EARC_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT (23U)
/*! RX_CMDC_RESP_TO - CMDC Response not sent in programmed time
*/
#define EARC_EXT_STATUS_RX_CMDC_RESP_TO(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_RX_CMDC_RESP_TO_SHIFT)) & EARC_EXT_STATUS_RX_CMDC_RESP_TO_MASK)
#define EARC_EXT_STATUS_RX_CMDC_COMMA_TO_MASK (0x2000000U)
#define EARC_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT (25U)
/*! RX_CMDC_COMMA_TO - Receiver CMDC comma timeout Interrupt
*/
#define EARC_EXT_STATUS_RX_CMDC_COMMA_TO(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_RX_CMDC_COMMA_TO_SHIFT)) & EARC_EXT_STATUS_RX_CMDC_COMMA_TO_MASK)
#define EARC_EXT_STATUS_HEARTBEAT_STATUS_MASK (0x8000000U)
#define EARC_EXT_STATUS_HEARTBEAT_STATUS_SHIFT (27U)
/*! HEARTBEAT_STATUS - Earc Connection Status
*/
#define EARC_EXT_STATUS_HEARTBEAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_HEARTBEAT_STATUS_SHIFT)) & EARC_EXT_STATUS_HEARTBEAT_STATUS_MASK)
#define EARC_EXT_STATUS_NEW_UD4_REC_MASK (0x10000000U)
#define EARC_EXT_STATUS_NEW_UD4_REC_SHIFT (28U)
/*! NEW_UD4_REC - New user data
*/
#define EARC_EXT_STATUS_NEW_UD4_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD4_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD4_REC_MASK)
#define EARC_EXT_STATUS_NEW_UD5_REC_MASK (0x20000000U)
#define EARC_EXT_STATUS_NEW_UD5_REC_SHIFT (29U)
/*! NEW_UD5_REC - New user data
*/
#define EARC_EXT_STATUS_NEW_UD5_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD5_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD5_REC_MASK)
#define EARC_EXT_STATUS_NEW_UD6_REC_MASK (0x40000000U)
#define EARC_EXT_STATUS_NEW_UD6_REC_SHIFT (30U)
/*! NEW_UD6_REC - New user data
*/
#define EARC_EXT_STATUS_NEW_UD6_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_NEW_UD6_REC_SHIFT)) & EARC_EXT_STATUS_NEW_UD6_REC_MASK)
#define EARC_EXT_STATUS_HPD_I_MASK (0x80000000U)
#define EARC_EXT_STATUS_HPD_I_SHIFT (31U)
/*! HPD_I - HPD Input status
*/
#define EARC_EXT_STATUS_HPD_I(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_STATUS_HPD_I_SHIFT)) & EARC_EXT_STATUS_HPD_I_MASK)
/*! @} */
/*! @name EXT_IER0 - Interrupt enables for interrupt 0 */
/*! @{ */
#define EARC_EXT_IER0_NEW_CS_IE_0_MASK (0x1U)
#define EARC_EXT_IER0_NEW_CS_IE_0_SHIFT (0U)
/*! NEW_CS_IE_0 - Enable for New channel status block received interrupt
*/
#define EARC_EXT_IER0_NEW_CS_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_NEW_CS_IE_0_SHIFT)) & EARC_EXT_IER0_NEW_CS_IE_0_MASK)
#define EARC_EXT_IER0_NEW_UD_IE_0_MASK (0x2U)
#define EARC_EXT_IER0_NEW_UD_IE_0_SHIFT (1U)
/*! NEW_UD_IE_0 - Enable for new user data received interrupt
*/
#define EARC_EXT_IER0_NEW_UD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_NEW_UD_IE_0_SHIFT)) & EARC_EXT_IER0_NEW_UD_IE_0_MASK)
#define EARC_EXT_IER0_MUTE_IE_0_MASK (0x4U)
#define EARC_EXT_IER0_MUTE_IE_0_SHIFT (2U)
/*! MUTE_IE_0 - Enable for Mute detected interrupt
*/
#define EARC_EXT_IER0_MUTE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_MUTE_IE_0_SHIFT)) & EARC_EXT_IER0_MUTE_IE_0_MASK)
#define EARC_EXT_IER0_CMDC_RESP_TO_IE_0_MASK (0x8U)
#define EARC_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT (3U)
/*! CMDC_RESP_TO_IE_0 - Receiver CMDC data response timeout interrupt enable
*/
#define EARC_EXT_IER0_CMDC_RESP_TO_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CMDC_RESP_TO_IE_0_SHIFT)) & EARC_EXT_IER0_CMDC_RESP_TO_IE_0_MASK)
#define EARC_EXT_IER0_ECC_ERR_IE_0_MASK (0x10U)
#define EARC_EXT_IER0_ECC_ERR_IE_0_SHIFT (4U)
/*! ECC_ERR_IE_0 - 60958 Compressed data uncorrectable error interrupt enable
*/
#define EARC_EXT_IER0_ECC_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_ECC_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_ECC_ERR_IE_0_MASK)
#define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK (0x20U)
#define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT (5U)
/*! PREAMBLE_MISMATCH_IE_0 - Preamble mismatch interrupt enable.
*/
#define EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_PREAMBLE_MISMATCH_IE_0_MASK)
#define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK (0x40U)
#define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT (6U)
/*! FIFO_OFLOW_UFLOW_ERR_IE_0 - Receive FIFO overflow error interrupt enable.
*/
#define EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_FIFO_OFLOW_UFLOW_ERR_IE_0_MASK)
#define EARC_EXT_IER0_HOST_WAKEUP_IE_0_MASK (0x80U)
#define EARC_EXT_IER0_HOST_WAKEUP_IE_0_SHIFT (7U)
/*! HOST_WAKEUP_IE_0 - Host wakeup on CEC match interrupt enable.
*/
#define EARC_EXT_IER0_HOST_WAKEUP_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_HOST_WAKEUP_IE_0_SHIFT)) & EARC_EXT_IER0_HOST_WAKEUP_IE_0_MASK)
#define EARC_EXT_IER0_OHPD_IE_0_MASK (0x100U)
#define EARC_EXT_IER0_OHPD_IE_0_SHIFT (8U)
/*! OHPD_IE_0 - Output HPD interrupt enable.
*/
#define EARC_EXT_IER0_OHPD_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_OHPD_IE_0_SHIFT)) & EARC_EXT_IER0_OHPD_IE_0_MASK)
#define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK (0x200U)
#define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT (9U)
/*! DMAC_NO_DATA_REC_IE_0 - Indicates no DMAC data is received.
*/
#define EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_NO_DATA_REC_IE_0_MASK)
#define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK (0x400U)
#define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT (10U)
/*! DMAC_FMT_CHG_DET_IE_0 - Indicates DMAC format change was detected
*/
#define EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_FMT_CHG_DET_IE_0_MASK)
#define EARC_EXT_IER0_HB_STATE_CHG_IE_0_MASK (0x800U)
#define EARC_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT (11U)
/*! HB_STATE_CHG_IE_0 - Interrupt enable for Heartbeat status change
*/
#define EARC_EXT_IER0_HB_STATE_CHG_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_HB_STATE_CHG_IE_0_SHIFT)) & EARC_EXT_IER0_HB_STATE_CHG_IE_0_MASK)
#define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK (0x1000U)
#define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT (12U)
/*! CMDC_STATUS_UPDATE_IE_0 - Interrupt enable for CMDC status register update.
*/
#define EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_SHIFT)) & EARC_EXT_IER0_CMDC_STATUS_UPDATE_IE_0_MASK)
#define EARC_EXT_IER0_TEMP_UPDATE_IE_0_MASK (0x2000U)
#define EARC_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT (13U)
/*! TEMP_UPDATE_IE_0 - Update request for chip temperature value.
*/
#define EARC_EXT_IER0_TEMP_UPDATE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_TEMP_UPDATE_IE_0_SHIFT)) & EARC_EXT_IER0_TEMP_UPDATE_IE_0_MASK)
#define EARC_EXT_IER0_DMA_RD_REQ_IE_0_MASK (0x4000U)
#define EARC_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT (14U)
/*! DMA_RD_REQ_IE_0 - Request to read data from FIFO.
*/
#define EARC_EXT_IER0_DMA_RD_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMA_RD_REQ_IE_0_SHIFT)) & EARC_EXT_IER0_DMA_RD_REQ_IE_0_MASK)
#define EARC_EXT_IER0_DMA_WR_REQ_IE_0_MASK (0x8000U)
#define EARC_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT (15U)
/*! DMA_WR_REQ_IE_0 - Request to write data to FIFO.
*/
#define EARC_EXT_IER0_DMA_WR_REQ_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMA_WR_REQ_IE_0_SHIFT)) & EARC_EXT_IER0_DMA_WR_REQ_IE_0_MASK)
#define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK (0x10000U)
#define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT (16U)
/*! DMAC_RX_BME_ERR_IE_0 - Bi-phase mark encoding error
*/
#define EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_SHIFT)) & EARC_EXT_IER0_DMAC_RX_BME_ERR_IE_0_MASK)
#define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK (0x20000U)
#define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT (17U)
/*! PREAMBLE_MATCH_IE_0 - Interrupt enable for preamble match received.
*/
#define EARC_EXT_IER0_PREAMBLE_MATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_SHIFT)) & EARC_EXT_IER0_PREAMBLE_MATCH_IE_0_MASK)
#define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK (0x40000U)
#define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT (18U)
/*! M_W_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame M/W preamble mismatch received.
*/
#define EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_M_W_PRE_MISMATCH_IE_0_MASK)
#define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK (0x80000U)
#define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT (19U)
/*! B_PRE_MISMATCH_IE_0 - Interrupt enable for sub-frame B preamble mismatch received.
*/
#define EARC_EXT_IER0_B_PRE_MISMATCH_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_SHIFT)) & EARC_EXT_IER0_B_PRE_MISMATCH_IE_0_MASK)
#define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK (0x100000U)
#define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT (20U)
/*! UNEXP_PRE_REC_IE_0 - Interrupt enable for Unexpected preamble received.
*/
#define EARC_EXT_IER0_UNEXP_PRE_REC_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_SHIFT)) & EARC_EXT_IER0_UNEXP_PRE_REC_IE_0_MASK)
#define EARC_EXT_IER0_ARC_MODE_IE_0_MASK (0x200000U)
#define EARC_EXT_IER0_ARC_MODE_IE_0_SHIFT (21U)
/*! ARC_MODE_IE_0 - Interrupt to indicate ARC mode setup.
*/
#define EARC_EXT_IER0_ARC_MODE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_ARC_MODE_IE_0_SHIFT)) & EARC_EXT_IER0_ARC_MODE_IE_0_MASK)
#define EARC_EXT_IER0_CH_UD_OFLOW_IE_0_MASK (0x400000U)
#define EARC_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT (22U)
/*! CH_UD_OFLOW_IE_0 - Channel status or used data could not be stored.
*/
#define EARC_EXT_IER0_CH_UD_OFLOW_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_CH_UD_OFLOW_IE_0_SHIFT)) & EARC_EXT_IER0_CH_UD_OFLOW_IE_0_MASK)
#define EARC_EXT_IER0_SPARE_IE_0_MASK (0xFF800000U)
#define EARC_EXT_IER0_SPARE_IE_0_SHIFT (23U)
/*! SPARE_IE_0 - Spare interrupts
*/
#define EARC_EXT_IER0_SPARE_IE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER0_SPARE_IE_0_SHIFT)) & EARC_EXT_IER0_SPARE_IE_0_MASK)
/*! @} */
/*! @name EXT_IER1 - Interrupt enables for interrupt 1 */
/*! @{ */
#define EARC_EXT_IER1_NEW_CS_IE_1_MASK (0x1U)
#define EARC_EXT_IER1_NEW_CS_IE_1_SHIFT (0U)
/*! NEW_CS_IE_1 - Enable for New channel status block received interrupt
*/
#define EARC_EXT_IER1_NEW_CS_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_NEW_CS_IE_1_SHIFT)) & EARC_EXT_IER1_NEW_CS_IE_1_MASK)
#define EARC_EXT_IER1_NEW_UD_IE_1_MASK (0x2U)
#define EARC_EXT_IER1_NEW_UD_IE_1_SHIFT (1U)
/*! NEW_UD_IE_1 - Enable for new user data received interrupt
*/
#define EARC_EXT_IER1_NEW_UD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_NEW_UD_IE_1_SHIFT)) & EARC_EXT_IER1_NEW_UD_IE_1_MASK)
#define EARC_EXT_IER1_MUTE_IE_1_MASK (0x4U)
#define EARC_EXT_IER1_MUTE_IE_1_SHIFT (2U)
/*! MUTE_IE_1 - Enable for Mute detected interrupt
*/
#define EARC_EXT_IER1_MUTE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_MUTE_IE_1_SHIFT)) & EARC_EXT_IER1_MUTE_IE_1_MASK)
#define EARC_EXT_IER1_CMDC_RESP_TO_IE_1_MASK (0x8U)
#define EARC_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT (3U)
/*! CMDC_RESP_TO_IE_1 - Receiver CMDC data response timeout interrupt enable
*/
#define EARC_EXT_IER1_CMDC_RESP_TO_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CMDC_RESP_TO_IE_1_SHIFT)) & EARC_EXT_IER1_CMDC_RESP_TO_IE_1_MASK)
#define EARC_EXT_IER1_ECC_ERR_IE_1_MASK (0x10U)
#define EARC_EXT_IER1_ECC_ERR_IE_1_SHIFT (4U)
/*! ECC_ERR_IE_1 - 60958 Compressed data uncorrectable error interrupt enable
*/
#define EARC_EXT_IER1_ECC_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_ECC_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_ECC_ERR_IE_1_MASK)
#define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK (0x20U)
#define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT (5U)
/*! PREAMBLE_MISMATCH_IE_1 - Preamble mismatch interrupt enable.
*/
#define EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_PREAMBLE_MISMATCH_IE_1_MASK)
#define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK (0x40U)
#define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT (6U)
/*! FIFO_OFLOW_UFLOW_ERR_IE_1 - Receive FIFO overflow error interrupt enable.
*/
#define EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_FIFO_OFLOW_UFLOW_ERR_IE_1_MASK)
#define EARC_EXT_IER1_HOST_WAKEUP_IE_1_MASK (0x80U)
#define EARC_EXT_IER1_HOST_WAKEUP_IE_1_SHIFT (7U)
/*! HOST_WAKEUP_IE_1 - Host wakeup on CEC match interrupt enable.
*/
#define EARC_EXT_IER1_HOST_WAKEUP_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_HOST_WAKEUP_IE_1_SHIFT)) & EARC_EXT_IER1_HOST_WAKEUP_IE_1_MASK)
#define EARC_EXT_IER1_OHPD_IE_1_MASK (0x100U)
#define EARC_EXT_IER1_OHPD_IE_1_SHIFT (8U)
/*! OHPD_IE_1 - Output HPD interrupt enable.
*/
#define EARC_EXT_IER1_OHPD_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_OHPD_IE_1_SHIFT)) & EARC_EXT_IER1_OHPD_IE_1_MASK)
#define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK (0x200U)
#define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT (9U)
/*! DMAC_NO_DATA_REC_IE_1 - Indicates no DMAC data is received.
*/
#define EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_NO_DATA_REC_IE_1_MASK)
#define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK (0x400U)
#define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT (10U)
/*! DMAC_FMT_CHG_DET_IE_1 - Indicates DMAC format change was detected
*/
#define EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_FMT_CHG_DET_IE_1_MASK)
#define EARC_EXT_IER1_HB_STATE_CHG_IE_1_MASK (0x800U)
#define EARC_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT (11U)
/*! HB_STATE_CHG_IE_1 - Interrupt enable for Heartbeat status change
*/
#define EARC_EXT_IER1_HB_STATE_CHG_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_HB_STATE_CHG_IE_1_SHIFT)) & EARC_EXT_IER1_HB_STATE_CHG_IE_1_MASK)
#define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK (0x1000U)
#define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT (12U)
/*! CMDC_STATUS_UPDATE_IE_1 - Interrupt enable for CMDC status register update.
*/
#define EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_SHIFT)) & EARC_EXT_IER1_CMDC_STATUS_UPDATE_IE_1_MASK)
#define EARC_EXT_IER1_TEMP_UPDATE_IE_1_MASK (0x2000U)
#define EARC_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT (13U)
/*! TEMP_UPDATE_IE_1 - Update request for chip temperature value.
*/
#define EARC_EXT_IER1_TEMP_UPDATE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_TEMP_UPDATE_IE_1_SHIFT)) & EARC_EXT_IER1_TEMP_UPDATE_IE_1_MASK)
#define EARC_EXT_IER1_DMA_RD_REQ_IE_1_MASK (0x4000U)
#define EARC_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT (14U)
/*! DMA_RD_REQ_IE_1 - Request to read data from FIFO.
*/
#define EARC_EXT_IER1_DMA_RD_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMA_RD_REQ_IE_1_SHIFT)) & EARC_EXT_IER1_DMA_RD_REQ_IE_1_MASK)
#define EARC_EXT_IER1_DMA_WR_REQ_IE_1_MASK (0x8000U)
#define EARC_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT (15U)
/*! DMA_WR_REQ_IE_1 - Request to write data to FIFO.
*/
#define EARC_EXT_IER1_DMA_WR_REQ_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMA_WR_REQ_IE_1_SHIFT)) & EARC_EXT_IER1_DMA_WR_REQ_IE_1_MASK)
#define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK (0x10000U)
#define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT (16U)
/*! DMAC_RX_BME_ERR_IE_1 - Bi-phase mark encoding error
*/
#define EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_SHIFT)) & EARC_EXT_IER1_DMAC_RX_BME_ERR_IE_1_MASK)
#define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK (0x20000U)
#define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT (17U)
/*! PREAMBLE_MATCH_IE_1 - Interrupt enable for preamble match received.
*/
#define EARC_EXT_IER1_PREAMBLE_MATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_SHIFT)) & EARC_EXT_IER1_PREAMBLE_MATCH_IE_1_MASK)
#define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK (0x40000U)
#define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT (18U)
/*! M_W_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame M/W preamble mismatch received.
*/
#define EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_M_W_PRE_MISMATCH_IE_1_MASK)
#define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK (0x80000U)
#define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT (19U)
/*! B_PRE_MISMATCH_IE_1 - Interrupt enable for sub-frame B preamble mismatch received.
*/
#define EARC_EXT_IER1_B_PRE_MISMATCH_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_SHIFT)) & EARC_EXT_IER1_B_PRE_MISMATCH_IE_1_MASK)
#define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK (0x100000U)
#define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT (20U)
/*! UNEXP_PRE_REC_IE_1 - Interrupt enable for Unexpected preamble received.
*/
#define EARC_EXT_IER1_UNEXP_PRE_REC_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_SHIFT)) & EARC_EXT_IER1_UNEXP_PRE_REC_IE_1_MASK)
#define EARC_EXT_IER1_ARC_MODE_IE_1_MASK (0x200000U)
#define EARC_EXT_IER1_ARC_MODE_IE_1_SHIFT (21U)
/*! ARC_MODE_IE_1 - Interrupt to indicate ARC mode setup.
*/
#define EARC_EXT_IER1_ARC_MODE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_ARC_MODE_IE_1_SHIFT)) & EARC_EXT_IER1_ARC_MODE_IE_1_MASK)
#define EARC_EXT_IER1_CH_UD_OFLOW_IE_1_MASK (0x400000U)
#define EARC_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT (22U)
/*! CH_UD_OFLOW_IE_1 - Channel status or used data could not be stored.
*/
#define EARC_EXT_IER1_CH_UD_OFLOW_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_CH_UD_OFLOW_IE_1_SHIFT)) & EARC_EXT_IER1_CH_UD_OFLOW_IE_1_MASK)
#define EARC_EXT_IER1_SPARE_IE_1_MASK (0xFF800000U)
#define EARC_EXT_IER1_SPARE_IE_1_SHIFT (23U)
/*! SPARE_IE_1 - Spare interrupt enables.
*/
#define EARC_EXT_IER1_SPARE_IE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_IER1_SPARE_IE_1_SHIFT)) & EARC_EXT_IER1_SPARE_IE_1_MASK)
/*! @} */
/*! @name EXT_ISR - External Interrupt Status register */
/*! @{ */
#define EARC_EXT_ISR_RX_NEW_CH_STAT_MASK (0x1U)
#define EARC_EXT_ISR_RX_NEW_CH_STAT_SHIFT (0U)
/*! RX_NEW_CH_STAT - Received new channel status block
*/
#define EARC_EXT_ISR_RX_NEW_CH_STAT(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_RX_NEW_CH_STAT_SHIFT)) & EARC_EXT_ISR_RX_NEW_CH_STAT_MASK)
#define EARC_EXT_ISR_RX_NEW_USR_DATA_MASK (0x2U)
#define EARC_EXT_ISR_RX_NEW_USR_DATA_SHIFT (1U)
/*! RX_NEW_USR_DATA - Received new User data Information
*/
#define EARC_EXT_ISR_RX_NEW_USR_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_RX_NEW_USR_DATA_SHIFT)) & EARC_EXT_ISR_RX_NEW_USR_DATA_MASK)
#define EARC_EXT_ISR_MUTE_DET_MASK (0x4U)
#define EARC_EXT_ISR_MUTE_DET_SHIFT (2U)
/*! MUTE_DET - Interrupt to indicate HW mute bit was detected.
*/
#define EARC_EXT_ISR_MUTE_DET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_MUTE_DET_SHIFT)) & EARC_EXT_ISR_MUTE_DET_MASK)
#define EARC_EXT_ISR_CMDC_RESP_TO_ERR_MASK (0x8U)
#define EARC_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT (3U)
/*! CMDC_RESP_TO_ERR - CMDC response timeout interrupt
*/
#define EARC_EXT_ISR_CMDC_RESP_TO_ERR(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CMDC_RESP_TO_ERR_SHIFT)) & EARC_EXT_ISR_CMDC_RESP_TO_ERR_MASK)
#define EARC_EXT_ISR_ECC_ERR_MASK (0x10U)
#define EARC_EXT_ISR_ECC_ERR_SHIFT (4U)
/*! ECC_ERR - 60958 Compressed data uncorrectable error interrupt
*/
#define EARC_EXT_ISR_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_ECC_ERR_SHIFT)) & EARC_EXT_ISR_ECC_ERR_MASK)
#define EARC_EXT_ISR_PREAMBLE_MISMATCH_MASK (0x20U)
#define EARC_EXT_ISR_PREAMBLE_MISMATCH_SHIFT (5U)
/*! PREAMBLE_MISMATCH - Preamble mismatch interrupt
*/
#define EARC_EXT_ISR_PREAMBLE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_PREAMBLE_MISMATCH_SHIFT)) & EARC_EXT_ISR_PREAMBLE_MISMATCH_MASK)
#define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK (0x40U)
#define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT (6U)
/*! FIFO_OFLOW_UFLOW_ERR - Receive FIFO overflow error interrupt
*/
#define EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_SHIFT)) & EARC_EXT_ISR_FIFO_OFLOW_UFLOW_ERR_MASK)
#define EARC_EXT_ISR_HOST_WAKEUP_MASK (0x80U)
#define EARC_EXT_ISR_HOST_WAKEUP_SHIFT (7U)
/*! HOST_WAKEUP - Host wakeup on CEC OPCODE match interrupt.
*/
#define EARC_EXT_ISR_HOST_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_HOST_WAKEUP_SHIFT)) & EARC_EXT_ISR_HOST_WAKEUP_MASK)
#define EARC_EXT_ISR_OHPD_MASK (0x100U)
#define EARC_EXT_ISR_OHPD_SHIFT (8U)
/*! OHPD - HPD output driver
*/
#define EARC_EXT_ISR_OHPD(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_OHPD_SHIFT)) & EARC_EXT_ISR_OHPD_MASK)
#define EARC_EXT_ISR_DMAC_NO_DATA_REC_MASK (0x200U)
#define EARC_EXT_ISR_DMAC_NO_DATA_REC_SHIFT (9U)
/*! DMAC_NO_DATA_REC - No DMAC data is received for 1us.
*/
#define EARC_EXT_ISR_DMAC_NO_DATA_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMAC_NO_DATA_REC_SHIFT)) & EARC_EXT_ISR_DMAC_NO_DATA_REC_MASK)
#define EARC_EXT_ISR_FMT_CHG_DET_MASK (0x400U)
#define EARC_EXT_ISR_FMT_CHG_DET_SHIFT (10U)
/*! FMT_CHG_DET - Format change detect interrupt
*/
#define EARC_EXT_ISR_FMT_CHG_DET(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_FMT_CHG_DET_SHIFT)) & EARC_EXT_ISR_FMT_CHG_DET_MASK)
#define EARC_EXT_ISR_HB_STATE_CHG_MASK (0x800U)
#define EARC_EXT_ISR_HB_STATE_CHG_SHIFT (11U)
/*! HB_STATE_CHG - Interrupt enable for Heartbeat status change
*/
#define EARC_EXT_ISR_HB_STATE_CHG(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_HB_STATE_CHG_SHIFT)) & EARC_EXT_ISR_HB_STATE_CHG_MASK)
#define EARC_EXT_ISR_CMDC_STATUS_UPDATE_MASK (0x1000U)
#define EARC_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT (12U)
/*! CMDC_STATUS_UPDATE - Interrupt enable for CMDC status register update.
*/
#define EARC_EXT_ISR_CMDC_STATUS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CMDC_STATUS_UPDATE_SHIFT)) & EARC_EXT_ISR_CMDC_STATUS_UPDATE_MASK)
#define EARC_EXT_ISR_TEMP_UPDATE_INT_MASK (0x2000U)
#define EARC_EXT_ISR_TEMP_UPDATE_INT_SHIFT (13U)
/*! TEMP_UPDATE_INT - Interrupt to get the new temperature value.
*/
#define EARC_EXT_ISR_TEMP_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_TEMP_UPDATE_INT_SHIFT)) & EARC_EXT_ISR_TEMP_UPDATE_INT_MASK)
#define EARC_EXT_ISR_DMA_RD_REQ_MASK (0x4000U)
#define EARC_EXT_ISR_DMA_RD_REQ_SHIFT (14U)
/*! DMA_RD_REQ - Set when DMA read request is asserted.
*/
#define EARC_EXT_ISR_DMA_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMA_RD_REQ_SHIFT)) & EARC_EXT_ISR_DMA_RD_REQ_MASK)
#define EARC_EXT_ISR_DMA_WR_REQ_MASK (0x8000U)
#define EARC_EXT_ISR_DMA_WR_REQ_SHIFT (15U)
/*! DMA_WR_REQ - Set when DMA write request is asserted.
*/
#define EARC_EXT_ISR_DMA_WR_REQ(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMA_WR_REQ_SHIFT)) & EARC_EXT_ISR_DMA_WR_REQ_MASK)
#define EARC_EXT_ISR_DMAC_BME_BIT_ERR_MASK (0x10000U)
#define EARC_EXT_ISR_DMAC_BME_BIT_ERR_SHIFT (16U)
/*! DMAC_BME_BIT_ERR - Set when DMAC BME data has an error.
*/
#define EARC_EXT_ISR_DMAC_BME_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_DMAC_BME_BIT_ERR_SHIFT)) & EARC_EXT_ISR_DMAC_BME_BIT_ERR_MASK)
#define EARC_EXT_ISR_PREAMBLE_MATCH_INT_MASK (0x20000U)
#define EARC_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT (17U)
/*! PREAMBLE_MATCH_INT - Interrupt to indicate PA PB / DTC CD preamble match was detected.
*/
#define EARC_EXT_ISR_PREAMBLE_MATCH_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_PREAMBLE_MATCH_INT_SHIFT)) & EARC_EXT_ISR_PREAMBLE_MATCH_INT_MASK)
#define EARC_EXT_ISR_M_W_PRE_MISMATCH_MASK (0x40000U)
#define EARC_EXT_ISR_M_W_PRE_MISMATCH_SHIFT (18U)
/*! M_W_PRE_MISMATCH - Set when DMAC preamble of M/W has an error.
*/
#define EARC_EXT_ISR_M_W_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_M_W_PRE_MISMATCH_SHIFT)) & EARC_EXT_ISR_M_W_PRE_MISMATCH_MASK)
#define EARC_EXT_ISR_B_PRE_MISMATCH_MASK (0x80000U)
#define EARC_EXT_ISR_B_PRE_MISMATCH_SHIFT (19U)
/*! B_PRE_MISMATCH - Set when DMAC preamble of B has an error.
*/
#define EARC_EXT_ISR_B_PRE_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_B_PRE_MISMATCH_SHIFT)) & EARC_EXT_ISR_B_PRE_MISMATCH_MASK)
#define EARC_EXT_ISR_UNEXP_PRE_REC_MASK (0x100000U)
#define EARC_EXT_ISR_UNEXP_PRE_REC_SHIFT (20U)
/*! UNEXP_PRE_REC - Set when DMAC preamble was received after unexpected number of input bits.
*/
#define EARC_EXT_ISR_UNEXP_PRE_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_UNEXP_PRE_REC_SHIFT)) & EARC_EXT_ISR_UNEXP_PRE_REC_MASK)
#define EARC_EXT_ISR_SEL_ARC_MODE_MASK (0x200000U)
#define EARC_EXT_ISR_SEL_ARC_MODE_SHIFT (21U)
/*! SEL_ARC_MODE - Set when CMDC SM falls out of eARC mode.
*/
#define EARC_EXT_ISR_SEL_ARC_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_SEL_ARC_MODE_SHIFT)) & EARC_EXT_ISR_SEL_ARC_MODE_MASK)
#define EARC_EXT_ISR_CS_OR_UD_OFLOW_MASK (0x400000U)
#define EARC_EXT_ISR_CS_OR_UD_OFLOW_SHIFT (22U)
/*! CS_OR_UD_OFLOW - Channel status or used data could not be stored.
*/
#define EARC_EXT_ISR_CS_OR_UD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_CS_OR_UD_OFLOW_SHIFT)) & EARC_EXT_ISR_CS_OR_UD_OFLOW_MASK)
#define EARC_EXT_ISR_SPARE_INT_MASK (0xFF800000U)
#define EARC_EXT_ISR_SPARE_INT_SHIFT (23U)
/*! SPARE_INT - Extra interrupt. Currently not driven. Can be set by M0
*/
#define EARC_EXT_ISR_SPARE_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_EXT_ISR_SPARE_INT_SHIFT)) & EARC_EXT_ISR_SPARE_INT_MASK)
/*! @} */
/*! @name IER - Interrupt enable register for M0+ */
/*! @{ */
#define EARC_IER_RX_CMDC_RX_DATA_IE_MASK (0x1U)
#define EARC_IER_RX_CMDC_RX_DATA_IE_SHIFT (0U)
/*! RX_CMDC_RX_DATA_IE - RX mode CMDC Receive data interrupt enable
*/
#define EARC_IER_RX_CMDC_RX_DATA_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_RX_CMDC_RX_DATA_IE_SHIFT)) & EARC_IER_RX_CMDC_RX_DATA_IE_MASK)
#define EARC_IER_RX_CMDC_RESP_TO_ERR_IE_MASK (0x4U)
#define EARC_IER_RX_CMDC_RESP_TO_ERR_IE_SHIFT (2U)
/*! RX_CMDC_RESP_TO_ERR_IE - Recevier mode Response timeout error interrupt enable
*/
#define EARC_IER_RX_CMDC_RESP_TO_ERR_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_RX_CMDC_RESP_TO_ERR_IE_SHIFT)) & EARC_IER_RX_CMDC_RESP_TO_ERR_IE_MASK)
#define EARC_IER_CMDC_SPARE_IE_MASK (0x100U)
#define EARC_IER_CMDC_SPARE_IE_SHIFT (8U)
/*! CMDC_SPARE_IE - Spare Interrupt. Could be used for Loopback
*/
#define EARC_IER_CMDC_SPARE_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_CMDC_SPARE_IE_SHIFT)) & EARC_IER_CMDC_SPARE_IE_MASK)
#define EARC_IER_HPD_TGL_IE_MASK (0x8000U)
#define EARC_IER_HPD_TGL_IE_SHIFT (15U)
/*! HPD_TGL_IE - HPD pin level change interrupt enable
*/
#define EARC_IER_HPD_TGL_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_HPD_TGL_IE_SHIFT)) & EARC_IER_HPD_TGL_IE_MASK)
#define EARC_IER_PA_PB_DET_IE_MASK (0x10000U)
#define EARC_IER_PA_PB_DET_IE_SHIFT (16U)
/*! PA_PB_DET_IE - PA PB detected in Compressed mode interrupt enable
*/
#define EARC_IER_PA_PB_DET_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_PA_PB_DET_IE_SHIFT)) & EARC_IER_PA_PB_DET_IE_MASK)
#define EARC_IER_DATA_BLK_REC_IE_MASK (0x20000U)
#define EARC_IER_DATA_BLK_REC_IE_SHIFT (17U)
/*! DATA_BLK_REC_IE - 60958 block of data received interrupt enable.
*/
#define EARC_IER_DATA_BLK_REC_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_DATA_BLK_REC_IE_SHIFT)) & EARC_IER_DATA_BLK_REC_IE_MASK)
#define EARC_IER_FMT_CHG_IE_MASK (0x40000U)
#define EARC_IER_FMT_CHG_IE_SHIFT (18U)
/*! FMT_CHG_IE - Format Chnage interrupt.
*/
#define EARC_IER_FMT_CHG_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_FMT_CHG_IE_SHIFT)) & EARC_IER_FMT_CHG_IE_MASK)
#define EARC_IER_DMAC_SPARE_IE_MASK (0x80000U)
#define EARC_IER_DMAC_SPARE_IE_SHIFT (19U)
/*! DMAC_SPARE_IE - Spare Interrupt. Could be used for Loopback
*/
#define EARC_IER_DMAC_SPARE_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_DMAC_SPARE_IE_SHIFT)) & EARC_IER_DMAC_SPARE_IE_MASK)
#define EARC_IER_SET_SPDIF_RX_IE_MASK (0x100000U)
#define EARC_IER_SET_SPDIF_RX_IE_SHIFT (20U)
/*! SET_SPDIF_RX_IE - Interrupt enable to set up SPDIF RX mode
*/
#define EARC_IER_SET_SPDIF_RX_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_SPDIF_RX_IE_SHIFT)) & EARC_IER_SET_SPDIF_RX_IE_MASK)
#define EARC_IER_SET_SPDIF_TX_IE_MASK (0x200000U)
#define EARC_IER_SET_SPDIF_TX_IE_SHIFT (21U)
/*! SET_SPDIF_TX_IE - Interrupt enable to set up SPDIF TX mode
*/
#define EARC_IER_SET_SPDIF_TX_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_SPDIF_TX_IE_SHIFT)) & EARC_IER_SET_SPDIF_TX_IE_MASK)
#define EARC_IER_SET_ARC_CM_IE_MASK (0x400000U)
#define EARC_IER_SET_ARC_CM_IE_SHIFT (22U)
/*! SET_ARC_CM_IE - Interrupt enable to set up PHY as Common mode ARC receiver
*/
#define EARC_IER_SET_ARC_CM_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_ARC_CM_IE_SHIFT)) & EARC_IER_SET_ARC_CM_IE_MASK)
#define EARC_IER_SET_ARC_SE_IE_MASK (0x800000U)
#define EARC_IER_SET_ARC_SE_IE_SHIFT (23U)
/*! SET_ARC_SE_IE - Interrupt enable to set up PHY as Single ended mode ARC receiver
*/
#define EARC_IER_SET_ARC_SE_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_SET_ARC_SE_IE_SHIFT)) & EARC_IER_SET_ARC_SE_IE_MASK)
#define EARC_IER_SW_HPD_TGL_IE_MASK (0x1000000U)
#define EARC_IER_SW_HPD_TGL_IE_SHIFT (24U)
/*! SW_HPD_TGL_IE - Interrupt enable to allow SW to assert HPD.
*/
#define EARC_IER_SW_HPD_TGL_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_SW_HPD_TGL_IE_SHIFT)) & EARC_IER_SW_HPD_TGL_IE_MASK)
#define EARC_IER_TEMP_UPDATED_IE_MASK (0x2000000U)
#define EARC_IER_TEMP_UPDATED_IE_SHIFT (25U)
/*! TEMP_UPDATED_IE - Interrupt enable to allow SW to indicate new temperature value is available.
*/
#define EARC_IER_TEMP_UPDATED_IE(x) (((uint32_t)(((uint32_t)(x)) << EARC_IER_TEMP_UPDATED_IE_SHIFT)) & EARC_IER_TEMP_UPDATED_IE_MASK)
/*! @} */
/*! @name ISR - Interrupt status register */
/*! @{ */
#define EARC_ISR_RX_CMDC_RX_DATA_MASK (0x1U)
#define EARC_ISR_RX_CMDC_RX_DATA_SHIFT (0U)
/*! RX_CMDC_RX_DATA - Receiver mode CMDC Receive data
*/
#define EARC_ISR_RX_CMDC_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_RX_CMDC_RX_DATA_SHIFT)) & EARC_ISR_RX_CMDC_RX_DATA_MASK)
#define EARC_ISR_RX_CMDC_RESP_TO_ERR_MASK (0x4U)
#define EARC_ISR_RX_CMDC_RESP_TO_ERR_SHIFT (2U)
/*! RX_CMDC_RESP_TO_ERR - Recevier mode CMDC Response timeout error
*/
#define EARC_ISR_RX_CMDC_RESP_TO_ERR(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_RX_CMDC_RESP_TO_ERR_SHIFT)) & EARC_ISR_RX_CMDC_RESP_TO_ERR_MASK)
#define EARC_ISR_CMDC_SPARE_INT_MASK (0x100U)
#define EARC_ISR_CMDC_SPARE_INT_SHIFT (8U)
/*! CMDC_SPARE_INT - Spare Interrupt
*/
#define EARC_ISR_CMDC_SPARE_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_CMDC_SPARE_INT_SHIFT)) & EARC_ISR_CMDC_SPARE_INT_MASK)
#define EARC_ISR_HPD_TGL_MASK (0x8000U)
#define EARC_ISR_HPD_TGL_SHIFT (15U)
/*! HPD_TGL - HPD pin level change interrupt
*/
#define EARC_ISR_HPD_TGL(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_HPD_TGL_SHIFT)) & EARC_ISR_HPD_TGL_MASK)
#define EARC_ISR_PA_PB_DET_MASK (0x10000U)
#define EARC_ISR_PA_PB_DET_SHIFT (16U)
/*! PA_PB_DET - PA PB detected in Compressed mode
*/
#define EARC_ISR_PA_PB_DET(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_PA_PB_DET_SHIFT)) & EARC_ISR_PA_PB_DET_MASK)
#define EARC_ISR_DATA_BLK_REC_MASK (0x20000U)
#define EARC_ISR_DATA_BLK_REC_SHIFT (17U)
/*! DATA_BLK_REC - 60958 block of data received interrupt.
*/
#define EARC_ISR_DATA_BLK_REC(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_DATA_BLK_REC_SHIFT)) & EARC_ISR_DATA_BLK_REC_MASK)
#define EARC_ISR_FMT_CHG_INT_MASK (0x40000U)
#define EARC_ISR_FMT_CHG_INT_SHIFT (18U)
/*! FMT_CHG_INT - Format Change interrupt.
*/
#define EARC_ISR_FMT_CHG_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_FMT_CHG_INT_SHIFT)) & EARC_ISR_FMT_CHG_INT_MASK)
#define EARC_ISR_DMAC_SPARE_INT_MASK (0x80000U)
#define EARC_ISR_DMAC_SPARE_INT_SHIFT (19U)
/*! DMAC_SPARE_INT - Spare Interrupt
*/
#define EARC_ISR_DMAC_SPARE_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_DMAC_SPARE_INT_SHIFT)) & EARC_ISR_DMAC_SPARE_INT_MASK)
#define EARC_ISR_SET_SPDIF_RX_MODE_MASK (0x100000U)
#define EARC_ISR_SET_SPDIF_RX_MODE_SHIFT (20U)
/*! SET_SPDIF_RX_MODE - Interrupt to set up PHY and controller in SPDIF RX mode.
*/
#define EARC_ISR_SET_SPDIF_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_SPDIF_RX_MODE_SHIFT)) & EARC_ISR_SET_SPDIF_RX_MODE_MASK)
#define EARC_ISR_SET_SPDIF_TX_MODE_MASK (0x200000U)
#define EARC_ISR_SET_SPDIF_TX_MODE_SHIFT (21U)
/*! SET_SPDIF_TX_MODE - Interrupt to set up PHY and controller in SPDIF TX mode.
*/
#define EARC_ISR_SET_SPDIF_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_SPDIF_TX_MODE_SHIFT)) & EARC_ISR_SET_SPDIF_TX_MODE_MASK)
#define EARC_ISR_SET_ARC_CM_INT_MASK (0x400000U)
#define EARC_ISR_SET_ARC_CM_INT_SHIFT (22U)
/*! SET_ARC_CM_INT - Interrupt enable to set up PHY as Common mode ARC receiver
*/
#define EARC_ISR_SET_ARC_CM_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_ARC_CM_INT_SHIFT)) & EARC_ISR_SET_ARC_CM_INT_MASK)
#define EARC_ISR_SET_ARC_SE_INT_MASK (0x800000U)
#define EARC_ISR_SET_ARC_SE_INT_SHIFT (23U)
/*! SET_ARC_SE_INT - Interrupt enable to set up PHY as Single ended mode ARC receiver
*/
#define EARC_ISR_SET_ARC_SE_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SET_ARC_SE_INT_SHIFT)) & EARC_ISR_SET_ARC_SE_INT_MASK)
#define EARC_ISR_SW_HPD_TGL_INT_MASK (0x1000000U)
#define EARC_ISR_SW_HPD_TGL_INT_SHIFT (24U)
/*! SW_HPD_TGL_INT - Interrupt enable to set up PHY as Single ended mode ARC receiver
*/
#define EARC_ISR_SW_HPD_TGL_INT(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_SW_HPD_TGL_INT_SHIFT)) & EARC_ISR_SW_HPD_TGL_INT_MASK)
#define EARC_ISR_TEMP_UPDATED_MASK (0x2000000U)
#define EARC_ISR_TEMP_UPDATED_SHIFT (25U)
/*! TEMP_UPDATED - Interrupt to indicate new temperature value is available.
*/
#define EARC_ISR_TEMP_UPDATED(x) (((uint32_t)(((uint32_t)(x)) << EARC_ISR_TEMP_UPDATED_SHIFT)) & EARC_ISR_TEMP_UPDATED_MASK)
/*! @} */
/*! @name PHY_AI_CTRL - AI interface control register */
/*! @{ */
#define EARC_PHY_AI_CTRL_AI_ADDR_MASK (0xFFU)
#define EARC_PHY_AI_CTRL_AI_ADDR_SHIFT (0U)
/*! AI_ADDR - AI ADDR value
*/
#define EARC_PHY_AI_CTRL_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_ADDR_SHIFT)) & EARC_PHY_AI_CTRL_AI_ADDR_MASK)
#define EARC_PHY_AI_CTRL_AI_RESETN_MASK (0x8000U)
#define EARC_PHY_AI_CTRL_AI_RESETN_SHIFT (15U)
/*! AI_RESETN - AI reset bit
*/
#define EARC_PHY_AI_CTRL_AI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_RESETN_SHIFT)) & EARC_PHY_AI_CTRL_AI_RESETN_MASK)
#define EARC_PHY_AI_CTRL_TOG_0_MASK (0x1000000U)
#define EARC_PHY_AI_CTRL_TOG_0_SHIFT (24U)
/*! TOG_0 - AI toggle bit
*/
#define EARC_PHY_AI_CTRL_TOG_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_0_SHIFT)) & EARC_PHY_AI_CTRL_TOG_0_MASK)
#define EARC_PHY_AI_CTRL_TOG_DONE_0_MASK (0x2000000U)
#define EARC_PHY_AI_CTRL_TOG_DONE_0_SHIFT (25U)
/*! TOG_DONE_0 - AI toggle done bit
*/
#define EARC_PHY_AI_CTRL_TOG_DONE_0(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_DONE_0_SHIFT)) & EARC_PHY_AI_CTRL_TOG_DONE_0_MASK)
#define EARC_PHY_AI_CTRL_TOG_1_MASK (0x4000000U)
#define EARC_PHY_AI_CTRL_TOG_1_SHIFT (26U)
/*! TOG_1 - AI toggle bit
*/
#define EARC_PHY_AI_CTRL_TOG_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_1_SHIFT)) & EARC_PHY_AI_CTRL_TOG_1_MASK)
#define EARC_PHY_AI_CTRL_TOG_DONE_1_MASK (0x8000000U)
#define EARC_PHY_AI_CTRL_TOG_DONE_1_SHIFT (27U)
/*! TOG_DONE_1 - AI toggle done bit
*/
#define EARC_PHY_AI_CTRL_TOG_DONE_1(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_TOG_DONE_1_SHIFT)) & EARC_PHY_AI_CTRL_TOG_DONE_1_MASK)
#define EARC_PHY_AI_CTRL_AI_RWB_MASK (0x80000000U)
#define EARC_PHY_AI_CTRL_AI_RWB_SHIFT (31U)
/*! AI_RWB - AI Read / write control bit
*/
#define EARC_PHY_AI_CTRL_AI_RWB(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_CTRL_AI_RWB_SHIFT)) & EARC_PHY_AI_CTRL_AI_RWB_MASK)
/*! @} */
/*! @name PHY_AI_WDATA - AI interface WDATA register */
/*! @{ */
#define EARC_PHY_AI_WDATA_WDATA_MASK (0xFFFFFFFFU)
#define EARC_PHY_AI_WDATA_WDATA_SHIFT (0U)
/*! WDATA - Write data
*/
#define EARC_PHY_AI_WDATA_WDATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_WDATA_WDATA_SHIFT)) & EARC_PHY_AI_WDATA_WDATA_MASK)
/*! @} */
/*! @name PHY_AI_RDATA - AI interface RDATA register */
/*! @{ */
#define EARC_PHY_AI_RDATA_RDATA_MASK (0xFFFFFFFFU)
#define EARC_PHY_AI_RDATA_RDATA_SHIFT (0U)
/*! RDATA - Read data
*/
#define EARC_PHY_AI_RDATA_RDATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_PHY_AI_RDATA_RDATA_SHIFT)) & EARC_PHY_AI_RDATA_RDATA_MASK)
/*! @} */
/*! @name DPATH_STATUS - Audio XCVR datapath status */
/*! @{ */
#define EARC_DPATH_STATUS_RX_FRM_CNT_MASK (0xFFU)
#define EARC_DPATH_STATUS_RX_FRM_CNT_SHIFT (0U)
/*! RX_FRM_CNT - Count of received frames in a block
*/
#define EARC_DPATH_STATUS_RX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << EARC_DPATH_STATUS_RX_FRM_CNT_SHIFT)) & EARC_DPATH_STATUS_RX_FRM_CNT_MASK)
#define EARC_DPATH_STATUS_TX_FRM_CNT_MASK (0xFF00U)
#define EARC_DPATH_STATUS_TX_FRM_CNT_SHIFT (8U)
/*! TX_FRM_CNT - Count of transmitted frames in a block
*/
#define EARC_DPATH_STATUS_TX_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << EARC_DPATH_STATUS_TX_FRM_CNT_SHIFT)) & EARC_DPATH_STATUS_TX_FRM_CNT_MASK)
/*! @} */
/*! @name RX_CMDC_CTRL - CMDC receiver control register */
/*! @{ */
#define EARC_RX_CMDC_CTRL_COMMA_BITS_MASK (0x1FU)
#define EARC_RX_CMDC_CTRL_COMMA_BITS_SHIFT (0U)
/*! COMMA_BITS - Number of repeating bits in COMMA pattern
*/
#define EARC_RX_CMDC_CTRL_COMMA_BITS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_COMMA_BITS_SHIFT)) & EARC_RX_CMDC_CTRL_COMMA_BITS_MASK)
#define EARC_RX_CMDC_CTRL_COMMA_EN_MASK (0x80U)
#define EARC_RX_CMDC_CTRL_COMMA_EN_SHIFT (7U)
/*! COMMA_EN - Enables COMMA pattern generation
*/
#define EARC_RX_CMDC_CTRL_COMMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_COMMA_EN_SHIFT)) & EARC_RX_CMDC_CTRL_COMMA_EN_MASK)
#define EARC_RX_CMDC_CTRL_RESPONSE_TIME_MASK (0x1F00U)
#define EARC_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT (8U)
/*! RESPONSE_TIME - Transmitter response timeout to a received message
*/
#define EARC_RX_CMDC_CTRL_RESPONSE_TIME(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_RESPONSE_TIME_SHIFT)) & EARC_RX_CMDC_CTRL_RESPONSE_TIME_MASK)
#define EARC_RX_CMDC_CTRL_TURNOVER_TIME_MASK (0xF0000U)
#define EARC_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT (16U)
/*! TURNOVER_TIME - Minimum time before a response is generated
*/
#define EARC_RX_CMDC_CTRL_TURNOVER_TIME(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_TURNOVER_TIME_SHIFT)) & EARC_RX_CMDC_CTRL_TURNOVER_TIME_MASK)
#define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK (0x700000U)
#define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT (20U)
/*! TX_DRIVE_STOP - Transmitter bus release time
*/
#define EARC_RX_CMDC_CTRL_TX_DRIVE_STOP(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_SHIFT)) & EARC_RX_CMDC_CTRL_TX_DRIVE_STOP_MASK)
#define EARC_RX_CMDC_CTRL_LBACK_EN_MASK (0x80000000U)
#define EARC_RX_CMDC_CTRL_LBACK_EN_SHIFT (31U)
/*! LBACK_EN - Loopback enable
*/
#define EARC_RX_CMDC_CTRL_LBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_CTRL_LBACK_EN_SHIFT)) & EARC_RX_CMDC_CTRL_LBACK_EN_MASK)
/*! @} */
/*! @name RX_CMDC_STATUS - eARC receiver CMDC status */
/*! @{ */
#define EARC_RX_CMDC_STATUS_CMDC_STATE_MASK (0xF0000U)
#define EARC_RX_CMDC_STATUS_CMDC_STATE_SHIFT (16U)
/*! CMDC_STATE - Current state of the RX CDMC control state machine
*/
#define EARC_RX_CMDC_STATUS_CMDC_STATE(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_STATUS_CMDC_STATE_SHIFT)) & EARC_RX_CMDC_STATUS_CMDC_STATE_MASK)
/*! @} */
/*! @name RX_CMDC_TX_DATA - CMDC transmit data register */
/*! @{ */
#define EARC_RX_CMDC_TX_DATA_TX_DATA_MASK (0x3FFFFFFU)
#define EARC_RX_CMDC_TX_DATA_TX_DATA_SHIFT (0U)
/*! TX_DATA - Transmit data
*/
#define EARC_RX_CMDC_TX_DATA_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_TX_DATA_TX_DATA_SHIFT)) & EARC_RX_CMDC_TX_DATA_TX_DATA_MASK)
#define EARC_RX_CMDC_TX_DATA_DATA_VALID_MASK (0x80000000U)
#define EARC_RX_CMDC_TX_DATA_DATA_VALID_SHIFT (31U)
/*! DATA_VALID - Transmit Data Valid
*/
#define EARC_RX_CMDC_TX_DATA_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_TX_DATA_DATA_VALID_SHIFT)) & EARC_RX_CMDC_TX_DATA_DATA_VALID_MASK)
/*! @} */
/*! @name RX_CMDC_RX_DATA - CMDC receive data register */
/*! @{ */
#define EARC_RX_CMDC_RX_DATA_RX_DATA_MASK (0x3FFFFFFU)
#define EARC_RX_CMDC_RX_DATA_RX_DATA_SHIFT (0U)
/*! RX_DATA - Receive data
*/
#define EARC_RX_CMDC_RX_DATA_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CMDC_RX_DATA_RX_DATA_SHIFT)) & EARC_RX_CMDC_RX_DATA_RX_DATA_MASK)
/*! @} */
/*! @name RX_DATAPATH_CTRL - Data path control register */
/*! @{ */
#define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK (0x1U)
#define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT (0U)
#define EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_SHIFT)) & EARC_RX_DATAPATH_CTRL_PAPB_FIFO_STATUS_MASK)
#define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK (0x8U)
#define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT (3U)
/*! ECC_VUC_BITS_EN - RX_DATAPATH: Enable VUC bit replacement after ECC correction.
*/
#define EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_SHIFT)) & EARC_RX_DATAPATH_CTRL_ECC_VUC_BITS_EN_MASK)
#define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK (0x10U)
#define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT (4U)
/*! EN_COMP_PARITY_CALC - RX_DATAPATH: Enable Compressed mode Parity calculation.
*/
#define EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_SHIFT)) & EARC_RX_DATAPATH_CTRL_EN_COMP_PARITY_CALC_MASK)
#define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK (0x20U)
#define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT (5U)
/*! RST_PKT_CNT_FIFO - Resets the packet count fifo.
*/
#define EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_SHIFT)) & EARC_RX_DATAPATH_CTRL_RST_PKT_CNT_FIFO_MASK)
#define EARC_RX_DATAPATH_CTRL_STORE_FMT_MASK (0x40U)
#define EARC_RX_DATAPATH_CTRL_STORE_FMT_SHIFT (6U)
/*! STORE_FMT - Receive Data store format.
*/
#define EARC_RX_DATAPATH_CTRL_STORE_FMT(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_STORE_FMT_SHIFT)) & EARC_RX_DATAPATH_CTRL_STORE_FMT_MASK)
#define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK (0x80U)
#define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT (7U)
/*! EN_PARITY_CALC - Enable Parity calculation.
*/
#define EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_SHIFT)) & EARC_RX_DATAPATH_CTRL_EN_PARITY_CALC_MASK)
#define EARC_RX_DATAPATH_CTRL_UDR_MASK (0x100U)
#define EARC_RX_DATAPATH_CTRL_UDR_SHIFT (8U)
/*! UDR - User data reset
*/
#define EARC_RX_DATAPATH_CTRL_UDR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_UDR_SHIFT)) & EARC_RX_DATAPATH_CTRL_UDR_MASK)
#define EARC_RX_DATAPATH_CTRL_CSR_MASK (0x200U)
#define EARC_RX_DATAPATH_CTRL_CSR_SHIFT (9U)
/*! CSR - Channel Status reset
*/
#define EARC_RX_DATAPATH_CTRL_CSR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CSR_SHIFT)) & EARC_RX_DATAPATH_CTRL_CSR_MASK)
#define EARC_RX_DATAPATH_CTRL_UDA_MASK (0x400U)
#define EARC_RX_DATAPATH_CTRL_UDA_SHIFT (10U)
/*! UDA - User Data Acknowledge
*/
#define EARC_RX_DATAPATH_CTRL_UDA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_UDA_SHIFT)) & EARC_RX_DATAPATH_CTRL_UDA_MASK)
#define EARC_RX_DATAPATH_CTRL_CSA_MASK (0x800U)
#define EARC_RX_DATAPATH_CTRL_CSA_SHIFT (11U)
/*! CSA - Channel Status Acknowledge
*/
#define EARC_RX_DATAPATH_CTRL_CSA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CSA_SHIFT)) & EARC_RX_DATAPATH_CTRL_CSA_MASK)
#define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK (0x1000U)
#define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT (12U)
/*! CLR_RX_FIFO - Clear Receive FIFO
*/
#define EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_SHIFT)) & EARC_RX_DATAPATH_CTRL_CLR_RX_FIFO_MASK)
#define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK (0xC000U)
#define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT (14U)
/*! RX_DATA_FMT - Indicates format of data stored in memory.
*/
#define EARC_RX_DATAPATH_CTRL_RX_DATA_FMT(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_SHIFT)) & EARC_RX_DATAPATH_CTRL_RX_DATA_FMT_MASK)
#define EARC_RX_DATAPATH_CTRL_PABS_MASK (0x80000U)
#define EARC_RX_DATAPATH_CTRL_PABS_SHIFT (19U)
/*! PABS - Enable preamble search
*/
#define EARC_RX_DATAPATH_CTRL_PABS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PABS_SHIFT)) & EARC_RX_DATAPATH_CTRL_PABS_MASK)
#define EARC_RX_DATAPATH_CTRL_DTS_CDS_MASK (0x100000U)
#define EARC_RX_DATAPATH_CTRL_DTS_CDS_SHIFT (20U)
/*! DTS_CDS - Enable DTS CD 14 preamble search
*/
#define EARC_RX_DATAPATH_CTRL_DTS_CDS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_DTS_CDS_SHIFT)) & EARC_RX_DATAPATH_CTRL_DTS_CDS_MASK)
#define EARC_RX_DATAPATH_CTRL_BLKC_MASK (0x200000U)
#define EARC_RX_DATAPATH_CTRL_BLKC_SHIFT (21U)
/*! BLKC - Block Compressed data
*/
#define EARC_RX_DATAPATH_CTRL_BLKC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_BLKC_SHIFT)) & EARC_RX_DATAPATH_CTRL_BLKC_MASK)
#define EARC_RX_DATAPATH_CTRL_MUTE_CTRL_MASK (0x400000U)
#define EARC_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT (22U)
/*! MUTE_CTRL - M0+ mute request
*/
#define EARC_RX_DATAPATH_CTRL_MUTE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_MUTE_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_MUTE_CTRL_MASK)
#define EARC_RX_DATAPATH_CTRL_MUTE_MODE_MASK (0x800000U)
#define EARC_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT (23U)
/*! MUTE_MODE - Mute mode control
*/
#define EARC_RX_DATAPATH_CTRL_MUTE_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_MUTE_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_MUTE_MODE_MASK)
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK (0x1000000U)
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT (24U)
/*! FMT_CHG_CTRL - Format Change detection control.
*/
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_FMT_CHG_CTRL_MASK)
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK (0x2000000U)
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT (25U)
/*! FMT_CHG_MODE - Format change detected. Reset HW for next frame
*/
#define EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_FMT_CHG_MODE_MASK)
#define EARC_RX_DATAPATH_CTRL_LAYB_CTRL_MASK (0x4000000U)
#define EARC_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT (26U)
/*! LAYB_CTRL - Layout B mode control
*/
#define EARC_RX_DATAPATH_CTRL_LAYB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_LAYB_CTRL_SHIFT)) & EARC_RX_DATAPATH_CTRL_LAYB_CTRL_MASK)
#define EARC_RX_DATAPATH_CTRL_LAYB_MODE_MASK (0x8000000U)
#define EARC_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT (27U)
/*! LAYB_MODE - Layout B
*/
#define EARC_RX_DATAPATH_CTRL_LAYB_MODE(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_LAYB_MODE_SHIFT)) & EARC_RX_DATAPATH_CTRL_LAYB_MODE_MASK)
#define EARC_RX_DATAPATH_CTRL_PRC_MASK (0x10000000U)
#define EARC_RX_DATAPATH_CTRL_PRC_SHIFT (28U)
/*! PRC - Process Compressed
*/
#define EARC_RX_DATAPATH_CTRL_PRC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_PRC_SHIFT)) & EARC_RX_DATAPATH_CTRL_PRC_MASK)
#define EARC_RX_DATAPATH_CTRL_COMP_MASK (0x20000000U)
#define EARC_RX_DATAPATH_CTRL_COMP_SHIFT (29U)
/*! COMP - Compressed data search mode
*/
#define EARC_RX_DATAPATH_CTRL_COMP(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_COMP_SHIFT)) & EARC_RX_DATAPATH_CTRL_COMP_MASK)
#define EARC_RX_DATAPATH_CTRL_FSM_MASK (0xC0000000U)
#define EARC_RX_DATAPATH_CTRL_FSM_SHIFT (30U)
/*! FSM - IEC60958-1 Frame Synchronization Mode
*/
#define EARC_RX_DATAPATH_CTRL_FSM(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DATAPATH_CTRL_FSM_SHIFT)) & EARC_RX_DATAPATH_CTRL_FSM_MASK)
/*! @} */
/*! @name RX_CS_DATA_BITS - Channel staus bits */
/*! @{ */
#define EARC_RX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU)
#define EARC_RX_CS_DATA_BITS_CS_DATA_SHIFT (0U)
/*! CS_DATA - Channel Status bits
*/
#define EARC_RX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_CS_DATA_BITS_CS_DATA_SHIFT)) & EARC_RX_CS_DATA_BITS_CS_DATA_MASK)
/*! @} */
/* The count of EARC_RX_CS_DATA_BITS */
#define EARC_RX_CS_DATA_BITS_COUNT (6U)
/*! @name RX_USER_DATA_BITS - User data bits */
/*! @{ */
#define EARC_RX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU)
#define EARC_RX_USER_DATA_BITS_U_DATA_SHIFT (0U)
/*! U_DATA - User data bits
*/
#define EARC_RX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_USER_DATA_BITS_U_DATA_SHIFT)) & EARC_RX_USER_DATA_BITS_U_DATA_MASK)
/*! @} */
/* The count of EARC_RX_USER_DATA_BITS */
#define EARC_RX_USER_DATA_BITS_COUNT (6U)
/*! @name RX_DPATH_CNTR_CTRL - DMAC counter control register */
/*! @{ */
#define EARC_RX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U)
#define EARC_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U)
/*! TS_EN - Timestamp counter enable
*/
#define EARC_RX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_TS_EN_MASK)
#define EARC_RX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U)
#define EARC_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U)
/*! TS_INC - Timestamp Increment
*/
#define EARC_RX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_TS_INC_MASK)
#define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U)
#define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U)
/*! RST_BIT_CNTR - Reset bit counter.
*/
#define EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK)
#define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U)
#define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U)
/*! RST_TS_CNTR - Reset timestamp counter.
*/
#define EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & EARC_RX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK)
/*! @} */
/*! @name RX_DPATH_TSCR - Receive Datapath Timestamp Counter Register */
/*! @{ */
#define EARC_RX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU)
#define EARC_RX_DPATH_TSCR_CVAL_SHIFT (0U)
/*! CVAL - Timestamp counter value
*/
#define EARC_RX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_TSCR_CVAL_SHIFT)) & EARC_RX_DPATH_TSCR_CVAL_MASK)
/*! @} */
/*! @name RX_DPATH_BCR - Receive Datapath Bit counter register */
/*! @{ */
#define EARC_RX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU)
#define EARC_RX_DPATH_BCR_CVAL_SHIFT (0U)
/*! CVAL - Bit count value
*/
#define EARC_RX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCR_CVAL_SHIFT)) & EARC_RX_DPATH_BCR_CVAL_MASK)
/*! @} */
/*! @name RX_DPATH_BCTR - Receive datapath Bit count timestamp register. */
/*! @{ */
#define EARC_RX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU)
#define EARC_RX_DPATH_BCTR_BCT_VAL_SHIFT (0U)
/*! BCT_VAL - Bit count timestamp value
*/
#define EARC_RX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCTR_BCT_VAL_SHIFT)) & EARC_RX_DPATH_BCTR_BCT_VAL_MASK)
/*! @} */
/*! @name RX_DPATH_BCRR - Receive datapath Bit read timestamp register. */
/*! @{ */
#define EARC_RX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU)
#define EARC_RX_DPATH_BCRR_BCT_VAL_SHIFT (0U)
/*! BCT_VAL - Bit count timestamp value
*/
#define EARC_RX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_BCRR_BCT_VAL_SHIFT)) & EARC_RX_DPATH_BCRR_BCT_VAL_MASK)
/*! @} */
/*! @name DMAC_PRE_MATCH_VAL - Preamble match value register */
/*! @{ */
#define EARC_DMAC_PRE_MATCH_VAL_PB_VAL_MASK (0xFFFFU)
#define EARC_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT (0U)
/*! PB_VAL - Preamble PB value
*/
#define EARC_DMAC_PRE_MATCH_VAL_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_VAL_PB_VAL_SHIFT)) & EARC_DMAC_PRE_MATCH_VAL_PB_VAL_MASK)
#define EARC_DMAC_PRE_MATCH_VAL_PA_VAL_MASK (0xFFFF0000U)
#define EARC_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT (16U)
/*! PA_VAL - Preamble PA value
*/
#define EARC_DMAC_PRE_MATCH_VAL_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_VAL_PA_VAL_SHIFT)) & EARC_DMAC_PRE_MATCH_VAL_PA_VAL_MASK)
/*! @} */
/*! @name DMAC_DTS_PRE_MATCH_VAL - Preamble match value register */
/*! @{ */
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK (0xFFFFU)
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT (0U)
/*! DTS_PB_VAL - Preamble PB value
*/
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_SHIFT)) & EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PB_VAL_MASK)
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK (0xFFFF0000U)
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT (16U)
/*! DTS_PA_VAL - Preamble PA value
*/
#define EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_SHIFT)) & EARC_DMAC_DTS_PRE_MATCH_VAL_DTS_PA_VAL_MASK)
/*! @} */
/*! @name RX_DPATH_PRE_ERR - Error count for IEC60958-1 Block Synchronization. */
/*! @{ */
#define EARC_RX_DPATH_PRE_ERR_PRE_ERRS_MASK (0xFFFFU)
#define EARC_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT (0U)
/*! PRE_ERRS - Preamble Error counter
*/
#define EARC_RX_DPATH_PRE_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PRE_ERR_PRE_ERRS_SHIFT)) & EARC_RX_DPATH_PRE_ERR_PRE_ERRS_MASK)
#define EARC_RX_DPATH_PRE_ERR_CLEAR_MASK (0x80000000U)
#define EARC_RX_DPATH_PRE_ERR_CLEAR_SHIFT (31U)
/*! CLEAR - Clear bit for error counter.
*/
#define EARC_RX_DPATH_PRE_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PRE_ERR_CLEAR_SHIFT)) & EARC_RX_DPATH_PRE_ERR_CLEAR_MASK)
/*! @} */
/*! @name RX_DPATH_PARITY_ERR - Parity Error count for IEC60958-1 Blocks. */
/*! @{ */
#define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK (0xFFFFU)
#define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT (0U)
/*! PRE_ERRS - Preamble Error counter
*/
#define EARC_RX_DPATH_PARITY_ERR_PRE_ERRS(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_SHIFT)) & EARC_RX_DPATH_PARITY_ERR_PRE_ERRS_MASK)
#define EARC_RX_DPATH_PARITY_ERR_CLEAR_MASK (0x80000000U)
#define EARC_RX_DPATH_PARITY_ERR_CLEAR_SHIFT (31U)
/*! CLEAR - Clear bit for error counter.
*/
#define EARC_RX_DPATH_PARITY_ERR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PARITY_ERR_CLEAR_SHIFT)) & EARC_RX_DPATH_PARITY_ERR_CLEAR_MASK)
/*! @} */
/*! @name RX_DPATH_PKT_CNT - Receive Data packet count. */
/*! @{ */
#define EARC_RX_DPATH_PKT_CNT_VAL_MASK (0x7FFFFFFFU)
#define EARC_RX_DPATH_PKT_CNT_VAL_SHIFT (0U)
/*! VAL - Data packet counter
*/
#define EARC_RX_DPATH_PKT_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_PKT_CNT_VAL_SHIFT)) & EARC_RX_DPATH_PKT_CNT_VAL_MASK)
/*! @} */
/*! @name RX_DPATH_ONE_BIT_ERR_CNT - Receive Data packet Corrected error count. */
/*! @{ */
#define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK (0xFFFFU)
#define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT (0U)
#define EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_SHIFT)) & EARC_RX_DPATH_ONE_BIT_ERR_CNT_VAL_MASK)
/*! @} */
/*! @name DMAC_PRE_MATCH_OFFSET - Preamble match offset value register */
/*! @{ */
#define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK (0xFFFFFFFFU)
#define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT (0U)
/*! PA_OFFSET - Sample count value for PA offset match
*/
#define EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_SHIFT)) & EARC_DMAC_PRE_MATCH_OFFSET_PA_OFFSET_MASK)
/*! @} */
/*! @name TX_DATAPATH_CTRL - Transmit Data path control register */
/*! @{ */
#define EARC_TX_DATAPATH_CTRL_CS_ACK_MASK (0x1U)
#define EARC_TX_DATAPATH_CTRL_CS_ACK_SHIFT (0U)
/*! CS_ACK - Channel Status ACK
*/
#define EARC_TX_DATAPATH_CTRL_CS_ACK(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_CS_ACK_SHIFT)) & EARC_TX_DATAPATH_CTRL_CS_ACK_MASK)
#define EARC_TX_DATAPATH_CTRL_UD_ACK_MASK (0x2U)
#define EARC_TX_DATAPATH_CTRL_UD_ACK_SHIFT (1U)
/*! UD_ACK - User Data ACK
*/
#define EARC_TX_DATAPATH_CTRL_UD_ACK(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_UD_ACK_SHIFT)) & EARC_TX_DATAPATH_CTRL_UD_ACK_MASK)
#define EARC_TX_DATAPATH_CTRL_CS_MOD_MASK (0x4U)
#define EARC_TX_DATAPATH_CTRL_CS_MOD_SHIFT (2U)
/*! CS_MOD - Enable Channel Status insertion
*/
#define EARC_TX_DATAPATH_CTRL_CS_MOD(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_CS_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_CS_MOD_MASK)
#define EARC_TX_DATAPATH_CTRL_UD_MOD_MASK (0x8U)
#define EARC_TX_DATAPATH_CTRL_UD_MOD_SHIFT (3U)
/*! UD_MOD - Enable User Data insertion
*/
#define EARC_TX_DATAPATH_CTRL_UD_MOD(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_UD_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_UD_MOD_MASK)
#define EARC_TX_DATAPATH_CTRL_VLD_MOD_MASK (0x10U)
#define EARC_TX_DATAPATH_CTRL_VLD_MOD_SHIFT (4U)
/*! VLD_MOD - Enable Valid bit insertion
*/
#define EARC_TX_DATAPATH_CTRL_VLD_MOD(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_VLD_MOD_SHIFT)) & EARC_TX_DATAPATH_CTRL_VLD_MOD_MASK)
#define EARC_TX_DATAPATH_CTRL_FRM_VLD_MASK (0x20U)
#define EARC_TX_DATAPATH_CTRL_FRM_VLD_SHIFT (5U)
/*! FRM_VLD - Valid bit value
*/
#define EARC_TX_DATAPATH_CTRL_FRM_VLD(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_FRM_VLD_SHIFT)) & EARC_TX_DATAPATH_CTRL_FRM_VLD_MASK)
#define EARC_TX_DATAPATH_CTRL_EN_PARITY_MASK (0x40U)
#define EARC_TX_DATAPATH_CTRL_EN_PARITY_SHIFT (6U)
/*! EN_PARITY - Enable parity insertion
*/
#define EARC_TX_DATAPATH_CTRL_EN_PARITY(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_EN_PARITY_SHIFT)) & EARC_TX_DATAPATH_CTRL_EN_PARITY_MASK)
#define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK (0x80U)
#define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT (7U)
/*! EN_PREAMBLE - Enable preamble insertion
*/
#define EARC_TX_DATAPATH_CTRL_EN_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_SHIFT)) & EARC_TX_DATAPATH_CTRL_EN_PREAMBLE_MASK)
#define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_MASK (0x400U)
#define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_SHIFT (10U)
/*! TX_CLK_RATE - This bit controls the TX clock rate.
*/
#define EARC_TX_DATAPATH_CTRL_TX_CLK_RATE(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_SHIFT)) & EARC_TX_DATAPATH_CTRL_TX_CLK_RATE_MASK)
#define EARC_TX_DATAPATH_CTRL_FRM_FMT_MASK (0x800U)
#define EARC_TX_DATAPATH_CTRL_FRM_FMT_SHIFT (11U)
/*! FRM_FMT - Frame format of input data
*/
#define EARC_TX_DATAPATH_CTRL_FRM_FMT(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_FRM_FMT_SHIFT)) & EARC_TX_DATAPATH_CTRL_FRM_FMT_MASK)
#define EARC_TX_DATAPATH_CTRL_TX_FORMAT_MASK (0x3000U)
#define EARC_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT (12U)
/*! TX_FORMAT - Transmit data format
*/
#define EARC_TX_DATAPATH_CTRL_TX_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_TX_FORMAT_SHIFT)) & EARC_TX_DATAPATH_CTRL_TX_FORMAT_MASK)
#define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK (0x4000U)
#define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT (14U)
/*! STRT_DATA_TX - Once Comma pattern is successively received, and heartbeat is detected, start TX of DMAC data.
*/
#define EARC_TX_DATAPATH_CTRL_STRT_DATA_TX(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_SHIFT)) & EARC_TX_DATAPATH_CTRL_STRT_DATA_TX_MASK)
/*! @} */
/*! @name TX_CS_DATA_BITS - Channel staus bits */
/*! @{ */
#define EARC_TX_CS_DATA_BITS_CS_DATA_MASK (0xFFFFFFFFU)
#define EARC_TX_CS_DATA_BITS_CS_DATA_SHIFT (0U)
/*! CS_DATA - Channel Status bits / block
*/
#define EARC_TX_CS_DATA_BITS_CS_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_CS_DATA_BITS_CS_DATA_SHIFT)) & EARC_TX_CS_DATA_BITS_CS_DATA_MASK)
/*! @} */
/* The count of EARC_TX_CS_DATA_BITS */
#define EARC_TX_CS_DATA_BITS_COUNT (6U)
/*! @name TX_USER_DATA_BITS - User data bits */
/*! @{ */
#define EARC_TX_USER_DATA_BITS_U_DATA_MASK (0xFFFFFFFFU)
#define EARC_TX_USER_DATA_BITS_U_DATA_SHIFT (0U)
/*! U_DATA - User data bits/block
*/
#define EARC_TX_USER_DATA_BITS_U_DATA(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_USER_DATA_BITS_U_DATA_SHIFT)) & EARC_TX_USER_DATA_BITS_U_DATA_MASK)
/*! @} */
/* The count of EARC_TX_USER_DATA_BITS */
#define EARC_TX_USER_DATA_BITS_COUNT (6U)
/*! @name TX_DPATH_CNTR_CTRL - DMAC counter control register */
/*! @{ */
#define EARC_TX_DPATH_CNTR_CTRL_TS_EN_MASK (0x1U)
#define EARC_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT (0U)
/*! TS_EN - Timestamp counter enable
*/
#define EARC_TX_DPATH_CNTR_CTRL_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_TS_EN_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_TS_EN_MASK)
#define EARC_TX_DPATH_CNTR_CTRL_TS_INC_MASK (0x2U)
#define EARC_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT (1U)
/*! TS_INC - Timestamp Increment
*/
#define EARC_TX_DPATH_CNTR_CTRL_TS_INC(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_TS_INC_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_TS_INC_MASK)
#define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK (0x100U)
#define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT (8U)
/*! RST_BIT_CNTR - Reset bit counter.
*/
#define EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_RST_BIT_CNTR_MASK)
#define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK (0x200U)
#define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT (9U)
/*! RST_TS_CNTR - Reset timestamp counter.
*/
#define EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_SHIFT)) & EARC_TX_DPATH_CNTR_CTRL_RST_TS_CNTR_MASK)
/*! @} */
/*! @name TX_DPATH_TSCR - Transmit Datapath Timestamp Counter Register */
/*! @{ */
#define EARC_TX_DPATH_TSCR_CVAL_MASK (0xFFFFFFFFU)
#define EARC_TX_DPATH_TSCR_CVAL_SHIFT (0U)
/*! CVAL - Timestamp counter value
*/
#define EARC_TX_DPATH_TSCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_TSCR_CVAL_SHIFT)) & EARC_TX_DPATH_TSCR_CVAL_MASK)
/*! @} */
/*! @name TX_DPATH_BCR - Transmit Datapath Bit counter register */
/*! @{ */
#define EARC_TX_DPATH_BCR_CVAL_MASK (0xFFFFFFFFU)
#define EARC_TX_DPATH_BCR_CVAL_SHIFT (0U)
/*! CVAL - Bit count value
*/
#define EARC_TX_DPATH_BCR_CVAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCR_CVAL_SHIFT)) & EARC_TX_DPATH_BCR_CVAL_MASK)
/*! @} */
/*! @name TX_DPATH_BCTR - Transmit datapath Bit count timestamp register. */
/*! @{ */
#define EARC_TX_DPATH_BCTR_BCT_VAL_MASK (0xFFFFFFFFU)
#define EARC_TX_DPATH_BCTR_BCT_VAL_SHIFT (0U)
/*! BCT_VAL - Bit count timestamp value
*/
#define EARC_TX_DPATH_BCTR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCTR_BCT_VAL_SHIFT)) & EARC_TX_DPATH_BCTR_BCT_VAL_MASK)
/*! @} */
/*! @name TX_DPATH_BCRR - Transmmit datapath Bit read timestamp register. */
/*! @{ */
#define EARC_TX_DPATH_BCRR_BCT_VAL_MASK (0xFFFFFFFFU)
#define EARC_TX_DPATH_BCRR_BCT_VAL_SHIFT (0U)
/*! BCT_VAL - Bit count timestamp value
*/
#define EARC_TX_DPATH_BCRR_BCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_TX_DPATH_BCRR_BCT_VAL_SHIFT)) & EARC_TX_DPATH_BCRR_BCT_VAL_MASK)
/*! @} */
/*! @name HPD_DBNC_CTRL - HPD Debounce Control Register */
/*! @{ */
#define EARC_HPD_DBNC_CTRL_VAL_MASK (0xFFFFFFFFU)
#define EARC_HPD_DBNC_CTRL_VAL_SHIFT (0U)
/*! VAL - HDP pin debounce interval
*/
#define EARC_HPD_DBNC_CTRL_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_HPD_DBNC_CTRL_VAL_SHIFT)) & EARC_HPD_DBNC_CTRL_VAL_MASK)
/*! @} */
/*! @name TEMPERATURE - Chip Temperature for eARC PHY */
/*! @{ */
#define EARC_TEMPERATURE_VAL_MASK (0xFFFFFFFFU)
#define EARC_TEMPERATURE_VAL_SHIFT (0U)
/*! VAL - Temperature
*/
#define EARC_TEMPERATURE_VAL(x) (((uint32_t)(((uint32_t)(x)) << EARC_TEMPERATURE_VAL_SHIFT)) & EARC_TEMPERATURE_VAL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group EARC_Register_Masks */
/* EARC - Peripheral instance base addresses */
/** Peripheral AUDIO_XCVR base address */
#define AUDIO_XCVR_BASE (0x30CC0000u)
/** Peripheral AUDIO_XCVR base pointer */
#define AUDIO_XCVR ((EARC_Type *)AUDIO_XCVR_BASE)
/** Array initializer of EARC peripheral base addresses */
#define EARC_BASE_ADDRS { AUDIO_XCVR_BASE }
/** Array initializer of EARC peripheral base pointers */
#define EARC_BASE_PTRS { AUDIO_XCVR }
/*!
* @}
*/ /* end of group EARC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ECSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
* @{
*/
/** ECSPI - Register Layout Typedef */
typedef struct {
__I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */
__O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */
__IO uint32_t CONREG; /**< Control Register, offset: 0x8 */
__IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */
__IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */
__IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */
__IO uint32_t STATREG; /**< Status Register, offset: 0x18 */
__IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */
__IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */
uint8_t RESERVED_0[28];
__O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */
} ECSPI_Type;
/* ----------------------------------------------------------------------------
-- ECSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ECSPI_Register_Masks ECSPI Register Masks
* @{
*/
/*! @name RXDATA - Receive Data Register */
/*! @{ */
#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU)
#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U)
#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK)
/*! @} */
/*! @name TXDATA - Transmit Data Register */
/*! @{ */
#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU)
#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U)
#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK)
/*! @} */
/*! @name CONREG - Control Register */
/*! @{ */
#define ECSPI_CONREG_EN_MASK (0x1U)
#define ECSPI_CONREG_EN_SHIFT (0U)
/*! EN
* 0b0..Disable the block.
* 0b1..Enable the block.
*/
#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK)
#define ECSPI_CONREG_HT_MASK (0x2U)
#define ECSPI_CONREG_HT_SHIFT (1U)
/*! HT
* 0b0..Disable HT mode.
* 0b1..Enable HT mode.
*/
#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK)
#define ECSPI_CONREG_XCH_MASK (0x4U)
#define ECSPI_CONREG_XCH_SHIFT (2U)
/*! XCH
* 0b0..Idle.
* 0b1..Initiates exchange (write) or busy (read).
*/
#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK)
#define ECSPI_CONREG_SMC_MASK (0x8U)
#define ECSPI_CONREG_SMC_SHIFT (3U)
/*! SMC
* 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or
* multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL
* descriptions.
* 0b1..Immediately starts a SPI burst when data is written in TXFIFO.
*/
#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK)
#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U)
#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U)
/*! CHANNEL_MODE
* 0b0000..Slave mode.
* 0b0001..Master mode.
*/
#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK)
#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U)
#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U)
/*! POST_DIVIDER
* 0b0000..Divide by 1.
* 0b0001..Divide by 2.
* 0b0010..Divide by 4.
* 0b1110..Divide by 2 14 .
* 0b1111..Divide by 2 15 .
*/
#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK)
#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U)
#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U)
/*! PRE_DIVIDER
* 0b0000..Divide by 1.
* 0b0001..Divide by 2.
* 0b0010..Divide by 3.
* 0b1101..Divide by 14.
* 0b1110..Divide by 15.
* 0b1111..Divide by 16.
*/
#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK)
#define ECSPI_CONREG_DRCTL_MASK (0x30000U)
#define ECSPI_CONREG_DRCTL_SHIFT (16U)
/*! DRCTL
* 0b00..The SPI_RDY signal is a don't care.
* 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
* 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
* 0b11..Reserved.
*/
#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK)
#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U)
#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U)
/*! CHANNEL_SELECT
* 0b00..Channel 0 is selected. Chip Select (SS) will be asserted.
* 0b01..Reserved.
* 0b10..Reserved.
* 0b11..Reserved.
*/
#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK)
#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U)
#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U)
/*! BURST_LENGTH
* 0b000000000000..A SPI burst contains the 1 LSB in a word.
* 0b000000000001..A SPI burst contains the 2 LSB in a word.
* 0b000000000010..A SPI burst contains the 3 LSB in a word.
* 0b000000011111..A SPI burst contains all 32 bits in a word.
* 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
* 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
* 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
* 0b111111111111..A SPI burst contains 2^7 words.
*/
#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK)
/*! @} */
/*! @name CONFIGREG - Config Register */
/*! @{ */
#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU)
#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U)
/*! SCLK_PHA
* 0b0000..Phase 0 operation.
* 0b0001..Phase 1 operation.
*/
#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK)
#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U)
#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U)
/*! SCLK_POL
* 0b0000..Active high polarity (0 = Idle).
* 0b0001..Active low polarity (1 = Idle).
*/
#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK)
#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U)
#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U)
/*! SS_CTL
* 0b0000..In master mode - only one SPI burst will be transmitted.
* 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be
* transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
* 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is
* equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first
* received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
* 0b0001..Reserved
*/
#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK)
#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U)
#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U)
/*! SS_POL
* 0b0000..Active low.
* 0b0001..Active high.
*/
#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK)
#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U)
#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U)
/*! DATA_CTL
* 0b0000..Stay high.
* 0b0001..Stay low.
*/
#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK)
#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U)
#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U)
/*! SCLK_CTL
* 0b0000..Stay low.
* 0b0001..Stay high.
*/
#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK)
#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U)
#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U)
#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK)
/*! @} */
/*! @name INTREG - Interrupt Control Register */
/*! @{ */
#define ECSPI_INTREG_TEEN_MASK (0x1U)
#define ECSPI_INTREG_TEEN_SHIFT (0U)
/*! TEEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK)
#define ECSPI_INTREG_TDREN_MASK (0x2U)
#define ECSPI_INTREG_TDREN_SHIFT (1U)
/*! TDREN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK)
#define ECSPI_INTREG_TFEN_MASK (0x4U)
#define ECSPI_INTREG_TFEN_SHIFT (2U)
/*! TFEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK)
#define ECSPI_INTREG_RREN_MASK (0x8U)
#define ECSPI_INTREG_RREN_SHIFT (3U)
/*! RREN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK)
#define ECSPI_INTREG_RDREN_MASK (0x10U)
#define ECSPI_INTREG_RDREN_SHIFT (4U)
/*! RDREN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK)
#define ECSPI_INTREG_RFEN_MASK (0x20U)
#define ECSPI_INTREG_RFEN_SHIFT (5U)
/*! RFEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK)
#define ECSPI_INTREG_ROEN_MASK (0x40U)
#define ECSPI_INTREG_ROEN_SHIFT (6U)
/*! ROEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK)
#define ECSPI_INTREG_TCEN_MASK (0x80U)
#define ECSPI_INTREG_TCEN_SHIFT (7U)
/*! TCEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK)
/*! @} */
/*! @name DMAREG - DMA Control Register */
/*! @{ */
#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU)
#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U)
#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK)
#define ECSPI_DMAREG_TEDEN_MASK (0x80U)
#define ECSPI_DMAREG_TEDEN_SHIFT (7U)
/*! TEDEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK)
#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U)
#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U)
#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK)
#define ECSPI_DMAREG_RXDEN_MASK (0x800000U)
#define ECSPI_DMAREG_RXDEN_SHIFT (23U)
/*! RXDEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK)
#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U)
#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U)
#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U)
#define ECSPI_DMAREG_RXTDEN_SHIFT (31U)
/*! RXTDEN
* 0b0..Disable
* 0b1..Enable
*/
#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK)
/*! @} */
/*! @name STATREG - Status Register */
/*! @{ */
#define ECSPI_STATREG_TE_MASK (0x1U)
#define ECSPI_STATREG_TE_SHIFT (0U)
/*! TE
* 0b0..TXFIFO contains one or more words.
* 0b1..TXFIFO is empty.
*/
#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK)
#define ECSPI_STATREG_TDR_MASK (0x2U)
#define ECSPI_STATREG_TDR_SHIFT (1U)
/*! TDR
* 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
* 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
*/
#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK)
#define ECSPI_STATREG_TF_MASK (0x4U)
#define ECSPI_STATREG_TF_SHIFT (2U)
/*! TF
* 0b0..TXFIFO is not Full.
* 0b1..TXFIFO is Full.
*/
#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK)
#define ECSPI_STATREG_RR_MASK (0x8U)
#define ECSPI_STATREG_RR_SHIFT (3U)
/*! RR
* 0b0..No valid data in RXFIFO.
* 0b1..More than 1 word in RXFIFO.
*/
#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK)
#define ECSPI_STATREG_RDR_MASK (0x10U)
#define ECSPI_STATREG_RDR_SHIFT (4U)
/*! RDR
* 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
* 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA condition exists.
* 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
* 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.
*/
#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK)
#define ECSPI_STATREG_RF_MASK (0x20U)
#define ECSPI_STATREG_RF_SHIFT (5U)
/*! RF
* 0b0..Not Full.
* 0b1..Full.
*/
#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK)
#define ECSPI_STATREG_RO_MASK (0x40U)
#define ECSPI_STATREG_RO_SHIFT (6U)
/*! RO
* 0b0..RXFIFO has no overflow.
* 0b1..RXFIFO has overflowed.
*/
#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK)
#define ECSPI_STATREG_TC_MASK (0x80U)
#define ECSPI_STATREG_TC_SHIFT (7U)
/*! TC
* 0b0..Transfer in progress.
* 0b1..Transfer completed.
*/
#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK)
/*! @} */
/*! @name PERIODREG - Sample Period Control Register */
/*! @{ */
#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU)
#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U)
/*! SAMPLE_PERIOD
* 0b000000000000000..0 wait states inserted
* 0b000000000000001..1 wait state inserted
* 0b111111111111110..32766 wait states inserted
* 0b111111111111111..32767 wait states inserted
*/
#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
#define ECSPI_PERIODREG_CSRC_MASK (0x8000U)
#define ECSPI_PERIODREG_CSRC_SHIFT (15U)
/*! CSRC
* 0b0..SPI Clock (SCLK)
* 0b1..Low-Frequency Reference Clock (32.768 KHz)
*/
#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK)
#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U)
#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U)
#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK)
/*! @} */
/*! @name TESTREG - Test Control Register */
/*! @{ */
#define ECSPI_TESTREG_TXCNT_MASK (0x7FU)
#define ECSPI_TESTREG_TXCNT_SHIFT (0U)
#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK)
#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U)
#define ECSPI_TESTREG_RXCNT_SHIFT (8U)
#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK)
#define ECSPI_TESTREG_LBC_MASK (0x80000000U)
#define ECSPI_TESTREG_LBC_SHIFT (31U)
/*! LBC
* 0b0..Not connected.
* 0b1..Transmitter and receiver sections internally connected for Loopback.
*/
#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK)
/*! @} */
/*! @name MSGDATA - Message Data Register */
/*! @{ */
#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU)
#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U)
#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ECSPI_Register_Masks */
/* ECSPI - Peripheral instance base addresses */
/** Peripheral ECSPI1 base address */
#define ECSPI1_BASE (0x30820000u)
/** Peripheral ECSPI1 base pointer */
#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE)
/** Peripheral ECSPI2 base address */
#define ECSPI2_BASE (0x30830000u)
/** Peripheral ECSPI2 base pointer */
#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE)
/** Peripheral ECSPI3 base address */
#define ECSPI3_BASE (0x30840000u)
/** Peripheral ECSPI3 base pointer */
#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE)
/** Array initializer of ECSPI peripheral base addresses */
#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE }
/** Array initializer of ECSPI peripheral base pointers */
#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 }
/** Interrupt vectors for the ECSPI peripheral type */
#define ECSPI_IRQS { NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn }
/*!
* @}
*/ /* end of group ECSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EDDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EDDC_Peripheral_Access_Layer EDDC Peripheral Access Layer
* @{
*/
/** EDDC - Register Layout Typedef */
typedef struct {
__IO uint8_t I2CM_SLAVE; /**< I2C DDC Slave address Configuration Register, offset: 0x0 */
__IO uint8_t I2CM_ADDRESS; /**< I2C DDC Address Configuration Register, offset: 0x1 */
__IO uint8_t I2CM_DATAO; /**< I2C DDC Data Write Register, offset: 0x2 */
__I uint8_t I2CM_DATAI; /**< I2C DDC Data read Register, offset: 0x3 */
__O uint8_t I2CM_OPERATION; /**< I2C DDC RD/RD_EXT/WR Operation Register Read and write operation request., offset: 0x4 */
__IO uint8_t I2CM_INT; /**< I2C DDC Done Interrupt Register This register configures the I2C master interrupts., offset: 0x5 */
__IO uint8_t I2CM_CTLINT; /**< I2C DDC error Interrupt Register This register configures the I2C master arbitration lost and not acknowledge error interrupts., offset: 0x6 */
__IO uint8_t I2CM_DIV; /**< I2C DDC Speed Control Register This register configures the division relation between master and scl clock., offset: 0x7 */
__IO uint8_t I2CM_SEGADDR; /**< I2C DDC Segment Address Configuration Register This register configures the segment address for extended R/W destination and is used for EDID reading operations, particularly for the Extended Data Read Operation for Enhanced DDC., offset: 0x8 */
__IO uint8_t I2CM_SOFTRSTZ; /**< I2C DDC Software Reset Control Register This register resets the I2C master., offset: 0x9 */
__IO uint8_t I2CM_SEGPTR; /**< I2C DDC Segment Pointer Register This register configures the segment pointer for extended RD/WR request., offset: 0xA */
__IO uint8_t I2CM_SS_SCL_HCNT_1_ADDR; /**< I2C DDC Slow Speed SCL High Level Control Register 1, offset: 0xB */
__IO uint8_t I2CM_SS_SCL_HCNT_0_ADDR; /**< I2C DDC Slow Speed SCL High Level Control Register 0, offset: 0xC */
__IO uint8_t I2CM_SS_SCL_LCNT_1_ADDR; /**< I2C DDC Slow Speed SCL Low Level Control Register 1, offset: 0xD */
__IO uint8_t I2CM_SS_SCL_LCNT_0_ADDR; /**< I2C DDC Slow Speed SCL Low Level Control Register 0, offset: 0xE */
__IO uint8_t I2CM_FS_SCL_HCNT_1_ADDR; /**< I2C DDC Fast Speed SCL High Level Control Register 1, offset: 0xF */
__IO uint8_t I2CM_FS_SCL_HCNT_0_ADDR; /**< I2C DDC Fast Speed SCL High Level Control Register 0, offset: 0x10 */
__IO uint8_t I2CM_FS_SCL_LCNT_1_ADDR; /**< I2C DDC Fast Speed SCL Low Level Control Register 1, offset: 0x11 */
__IO uint8_t I2CM_FS_SCL_LCNT_0_ADDR; /**< I2C DDC Fast Speed SCL Low Level Control Register 0, offset: 0x12 */
__IO uint8_t I2CM_SDA_HOLD; /**< I2C DDC SDA Hold Register, offset: 0x13 */
__IO uint8_t I2CM_SCDC_READ_UPDATE; /**< SCDC Control Register This register configures the SCDC update status read through the I2C master interface., offset: 0x14 */
uint8_t RESERVED_0[11];
__I uint8_t I2CM_READ_BUFF0; /**< I2C Master Sequential Read Buffer Register 0, offset: 0x20 */
__I uint8_t I2CM_READ_BUFF1; /**< I2C Master Sequential Read Buffer Register 1, offset: 0x21 */
__I uint8_t I2CM_READ_BUFF2; /**< I2C Master Sequential Read Buffer Register 2, offset: 0x22 */
__I uint8_t I2CM_READ_BUFF3; /**< I2C Master Sequential Read Buffer Register 3, offset: 0x23 */
__I uint8_t I2CM_READ_BUFF4; /**< I2C Master Sequential Read Buffer Register 4, offset: 0x24 */
__I uint8_t I2CM_READ_BUFF5; /**< I2C Master Sequential Read Buffer Register 5, offset: 0x25 */
__I uint8_t I2CM_READ_BUFF6; /**< I2C Master Sequential Read Buffer Register 6, offset: 0x26 */
__I uint8_t I2CM_READ_BUFF7; /**< I2C Master Sequential Read Buffer Register 7, offset: 0x27 */
uint8_t RESERVED_1[8];
__I uint8_t I2CM_SCDC_UPDATE0; /**< I2C SCDC Read Update Register 0, offset: 0x30 */
__I uint8_t I2CM_SCDC_UPDATE1; /**< I2C SCDC Read Update Register 1, offset: 0x31 */
} EDDC_Type;
/* ----------------------------------------------------------------------------
-- EDDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EDDC_Register_Masks EDDC Register Masks
* @{
*/
/*! @name I2CM_SLAVE - I2C DDC Slave address Configuration Register */
/*! @{ */
#define EDDC_I2CM_SLAVE_SLAVEADDR_MASK (0x7FU)
#define EDDC_I2CM_SLAVE_SLAVEADDR_SHIFT (0U)
/*! slaveaddr - Slave address to be sent during read and write normal operations.
*/
#define EDDC_I2CM_SLAVE_SLAVEADDR(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SLAVE_SLAVEADDR_SHIFT)) & EDDC_I2CM_SLAVE_SLAVEADDR_MASK)
/*! @} */
/*! @name I2CM_ADDRESS - I2C DDC Address Configuration Register */
/*! @{ */
#define EDDC_I2CM_ADDRESS_ADDRESS_MASK (0xFFU)
#define EDDC_I2CM_ADDRESS_ADDRESS_SHIFT (0U)
/*! address - Register address for read and write operations
*/
#define EDDC_I2CM_ADDRESS_ADDRESS(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_ADDRESS_ADDRESS_SHIFT)) & EDDC_I2CM_ADDRESS_ADDRESS_MASK)
/*! @} */
/*! @name I2CM_DATAO - I2C DDC Data Write Register */
/*! @{ */
#define EDDC_I2CM_DATAO_DATAO_MASK (0xFFU)
#define EDDC_I2CM_DATAO_DATAO_SHIFT (0U)
/*! datao - Data to be written on register pointed by address[7:0].
*/
#define EDDC_I2CM_DATAO_DATAO(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DATAO_DATAO_SHIFT)) & EDDC_I2CM_DATAO_DATAO_MASK)
/*! @} */
/*! @name I2CM_DATAI - I2C DDC Data read Register */
/*! @{ */
#define EDDC_I2CM_DATAI_DATAI_MASK (0xFFU)
#define EDDC_I2CM_DATAI_DATAI_SHIFT (0U)
/*! datai - Data read from register pointed by address[7:0].
*/
#define EDDC_I2CM_DATAI_DATAI(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DATAI_DATAI_SHIFT)) & EDDC_I2CM_DATAI_DATAI_MASK)
/*! @} */
/*! @name I2CM_OPERATION - I2C DDC RD/RD_EXT/WR Operation Register Read and write operation request. */
/*! @{ */
#define EDDC_I2CM_OPERATION_RD_MASK (0x1U)
#define EDDC_I2CM_OPERATION_RD_SHIFT (0U)
/*! rd - Single byte read operation request
*/
#define EDDC_I2CM_OPERATION_RD(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD_SHIFT)) & EDDC_I2CM_OPERATION_RD_MASK)
#define EDDC_I2CM_OPERATION_RD_EXT_MASK (0x2U)
#define EDDC_I2CM_OPERATION_RD_EXT_SHIFT (1U)
/*! rd_ext - After writing 1'b1 to rd_ext bit a extended data read operation is started (E-DDC read operation).
*/
#define EDDC_I2CM_OPERATION_RD_EXT(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD_EXT_SHIFT)) & EDDC_I2CM_OPERATION_RD_EXT_MASK)
#define EDDC_I2CM_OPERATION_RD8_MASK (0x4U)
#define EDDC_I2CM_OPERATION_RD8_SHIFT (2U)
/*! rd8 - Sequential read operation request.
*/
#define EDDC_I2CM_OPERATION_RD8(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD8_SHIFT)) & EDDC_I2CM_OPERATION_RD8_MASK)
#define EDDC_I2CM_OPERATION_RD8_EXT_MASK (0x8U)
#define EDDC_I2CM_OPERATION_RD8_EXT_SHIFT (3U)
/*! rd8_ext - Extended sequential read operation request.
*/
#define EDDC_I2CM_OPERATION_RD8_EXT(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_RD8_EXT_SHIFT)) & EDDC_I2CM_OPERATION_RD8_EXT_MASK)
#define EDDC_I2CM_OPERATION_WR_MASK (0x10U)
#define EDDC_I2CM_OPERATION_WR_SHIFT (4U)
/*! wr - Single byte write operation request.
*/
#define EDDC_I2CM_OPERATION_WR(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_WR_SHIFT)) & EDDC_I2CM_OPERATION_WR_MASK)
#define EDDC_I2CM_OPERATION_BUSCLEAR_MASK (0x20U)
#define EDDC_I2CM_OPERATION_BUSCLEAR_SHIFT (5U)
/*! busclear - bus clear operation request.
*/
#define EDDC_I2CM_OPERATION_BUSCLEAR(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_OPERATION_BUSCLEAR_SHIFT)) & EDDC_I2CM_OPERATION_BUSCLEAR_MASK)
/*! @} */
/*! @name I2CM_INT - I2C DDC Done Interrupt Register This register configures the I2C master interrupts. */
/*! @{ */
#define EDDC_I2CM_INT_DONE_MASK_MASK (0x4U)
#define EDDC_I2CM_INT_DONE_MASK_SHIFT (2U)
/*! done_mask - Done interrupt mask signal.
*/
#define EDDC_I2CM_INT_DONE_MASK(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_INT_DONE_MASK_SHIFT)) & EDDC_I2CM_INT_DONE_MASK_MASK)
#define EDDC_I2CM_INT_READ_REQ_MASK_MASK (0x40U)
#define EDDC_I2CM_INT_READ_REQ_MASK_SHIFT (6U)
/*! read_req_mask - Read request interruption mask signal.
*/
#define EDDC_I2CM_INT_READ_REQ_MASK(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_INT_READ_REQ_MASK_SHIFT)) & EDDC_I2CM_INT_READ_REQ_MASK_MASK)
/*! @} */
/*! @name I2CM_CTLINT - I2C DDC error Interrupt Register This register configures the I2C master arbitration lost and not acknowledge error interrupts. */
/*! @{ */
#define EDDC_I2CM_CTLINT_ARBITRATION_MASK_MASK (0x4U)
#define EDDC_I2CM_CTLINT_ARBITRATION_MASK_SHIFT (2U)
/*! arbitration_mask - Arbitration error interrupt mask signal.
*/
#define EDDC_I2CM_CTLINT_ARBITRATION_MASK(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_CTLINT_ARBITRATION_MASK_SHIFT)) & EDDC_I2CM_CTLINT_ARBITRATION_MASK_MASK)
#define EDDC_I2CM_CTLINT_NACK_MASK_MASK (0x40U)
#define EDDC_I2CM_CTLINT_NACK_MASK_SHIFT (6U)
/*! nack_mask - Not acknowledge error interrupt mask signal.
*/
#define EDDC_I2CM_CTLINT_NACK_MASK(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_CTLINT_NACK_MASK_SHIFT)) & EDDC_I2CM_CTLINT_NACK_MASK_MASK)
/*! @} */
/*! @name I2CM_DIV - I2C DDC Speed Control Register This register configures the division relation between master and scl clock. */
/*! @{ */
#define EDDC_I2CM_DIV_SPARE_MASK (0x7U)
#define EDDC_I2CM_DIV_SPARE_SHIFT (0U)
/*! spare - Reserved as "spare" bit with no associated functionality.
*/
#define EDDC_I2CM_DIV_SPARE(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DIV_SPARE_SHIFT)) & EDDC_I2CM_DIV_SPARE_MASK)
#define EDDC_I2CM_DIV_FAST_STD_MODE_MASK (0x8U)
#define EDDC_I2CM_DIV_FAST_STD_MODE_SHIFT (3U)
/*! fast_std_mode - Sets the I2C Master to work in Fast Mode or Standard Mode: 1: Fast Mode 0: Standard Mode
*/
#define EDDC_I2CM_DIV_FAST_STD_MODE(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_DIV_FAST_STD_MODE_SHIFT)) & EDDC_I2CM_DIV_FAST_STD_MODE_MASK)
/*! @} */
/*! @name I2CM_SEGADDR - I2C DDC Segment Address Configuration Register This register configures the segment address for extended R/W destination and is used for EDID reading operations, particularly for the Extended Data Read Operation for Enhanced DDC. */
/*! @{ */
#define EDDC_I2CM_SEGADDR_SEG_ADDR_MASK (0x7FU)
#define EDDC_I2CM_SEGADDR_SEG_ADDR_SHIFT (0U)
/*! seg_addr - I2C DDC Segment Address Configuration Register
*/
#define EDDC_I2CM_SEGADDR_SEG_ADDR(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SEGADDR_SEG_ADDR_SHIFT)) & EDDC_I2CM_SEGADDR_SEG_ADDR_MASK)
/*! @} */
/*! @name I2CM_SOFTRSTZ - I2C DDC Software Reset Control Register This register resets the I2C master. */
/*! @{ */
#define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK (0x1U)
#define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT (0U)
/*! i2c_softrstz - I2C Master Software Reset.
*/
#define EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT)) & EDDC_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK)
/*! @} */
/*! @name I2CM_SEGPTR - I2C DDC Segment Pointer Register This register configures the segment pointer for extended RD/WR request. */
/*! @{ */
#define EDDC_I2CM_SEGPTR_SEGPTR_MASK (0xFFU)
#define EDDC_I2CM_SEGPTR_SEGPTR_SHIFT (0U)
/*! segptr - I2C DDC Segment Pointer Register
*/
#define EDDC_I2CM_SEGPTR_SEGPTR(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SEGPTR_SEGPTR_SHIFT)) & EDDC_I2CM_SEGPTR_SEGPTR_MASK)
/*! @} */
/*! @name I2CM_SS_SCL_HCNT_1_ADDR - I2C DDC Slow Speed SCL High Level Control Register 1 */
/*! @{ */
#define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK (0xFFU)
#define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT (0U)
/*! i2cmp_ss_scl_hcnt1 - I2C DDC Slow Speed SCL High Level Control Register 1
*/
#define EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT)) & EDDC_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK)
/*! @} */
/*! @name I2CM_SS_SCL_HCNT_0_ADDR - I2C DDC Slow Speed SCL High Level Control Register 0 */
/*! @{ */
#define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK (0xFFU)
#define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT (0U)
/*! i2cmp_ss_scl_hcnt0 - I2C DDC Slow Speed SCL High Level Control Register 0
*/
#define EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT)) & EDDC_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK)
/*! @} */
/*! @name I2CM_SS_SCL_LCNT_1_ADDR - I2C DDC Slow Speed SCL Low Level Control Register 1 */
/*! @{ */
#define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK (0xFFU)
#define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT (0U)
/*! i2cmp_ss_scl_lcnt1 - I2C DDC Slow Speed SCL Low Level Control Register 1
*/
#define EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT)) & EDDC_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK)
/*! @} */
/*! @name I2CM_SS_SCL_LCNT_0_ADDR - I2C DDC Slow Speed SCL Low Level Control Register 0 */
/*! @{ */
#define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK (0xFFU)
#define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT (0U)
/*! i2cmp_ss_scl_lcnt0 - I2C DDC Slow Speed SCL Low Level Control Register 0
*/
#define EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT)) & EDDC_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK)
/*! @} */
/*! @name I2CM_FS_SCL_HCNT_1_ADDR - I2C DDC Fast Speed SCL High Level Control Register 1 */
/*! @{ */
#define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK (0xFFU)
#define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT (0U)
/*! i2cmp_fs_scl_hcnt1 - I2C DDC Fast Speed SCL High Level Control Register 1
*/
#define EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT)) & EDDC_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK)
/*! @} */
/*! @name I2CM_FS_SCL_HCNT_0_ADDR - I2C DDC Fast Speed SCL High Level Control Register 0 */
/*! @{ */
#define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK (0xFFU)
#define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT (0U)
/*! i2cmp_fs_scl_hcnt0 - I2C DDC Fast Speed SCL High Level Control Register 0
*/
#define EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT)) & EDDC_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK)
/*! @} */
/*! @name I2CM_FS_SCL_LCNT_1_ADDR - I2C DDC Fast Speed SCL Low Level Control Register 1 */
/*! @{ */
#define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK (0xFFU)
#define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT (0U)
/*! i2cmp_fs_scl_lcnt1 - I2C DDC Fast Speed SCL Low Level Control Register 1
*/
#define EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT)) & EDDC_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK)
/*! @} */
/*! @name I2CM_FS_SCL_LCNT_0_ADDR - I2C DDC Fast Speed SCL Low Level Control Register 0 */
/*! @{ */
#define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK (0xFFU)
#define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT (0U)
/*! i2cmp_fs_scl_lcnt0 - I2C DDC Fast Speed SCL Low Level Control Register 0
*/
#define EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT)) & EDDC_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK)
/*! @} */
/*! @name I2CM_SDA_HOLD - I2C DDC SDA Hold Register */
/*! @{ */
#define EDDC_I2CM_SDA_HOLD_OSDA_HOLD_MASK (0xFFU)
#define EDDC_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT (0U)
/*! osda_hold - Defines the number of SFR clock cycles to meet tHD;DAT (300 ns) osda_hold =
* round_to_high_integer (300 ns / (1 / isfrclk_frequency))
*/
#define EDDC_I2CM_SDA_HOLD_OSDA_HOLD(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT)) & EDDC_I2CM_SDA_HOLD_OSDA_HOLD_MASK)
/*! @} */
/*! @name I2CM_SCDC_READ_UPDATE - SCDC Control Register This register configures the SCDC update status read through the I2C master interface. */
/*! @{ */
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_MASK (0x1U)
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_SHIFT (0U)
/*! read_update - When set to 1'b1, a SCDC Update Read is performed and the read data loaded into
* registers i2cm_scdc_update0 and i2cm_scdc_update1.
*/
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_READ_UPDATE_MASK)
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_MASK (0x10U)
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_SHIFT (4U)
/*! read_request_en - Read request enabled.
*/
#define EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_READ_REQUEST_EN_MASK)
#define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_MASK (0x20U)
#define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_SHIFT (5U)
/*! updtrd_vsyncpoll_en - Update read polling enabled.
*/
#define EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_SHIFT)) & EDDC_I2CM_SCDC_READ_UPDATE_UPDTRD_VSYNCPOLL_EN_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF0 - I2C Master Sequential Read Buffer Register 0 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_SHIFT (0U)
/*! i2cm_read_buff0 - Byte 0 of a I2C read buffer sequential read (from address i2cm_address)
*/
#define EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_SHIFT)) & EDDC_I2CM_READ_BUFF0_I2CM_READ_BUFF0_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF1 - I2C Master Sequential Read Buffer Register 1 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_SHIFT (0U)
/*! i2cm_read_buff1 - Byte 1 of a I2C read buffer sequential read (from address i2cm_address+1)
*/
#define EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_SHIFT)) & EDDC_I2CM_READ_BUFF1_I2CM_READ_BUFF1_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF2 - I2C Master Sequential Read Buffer Register 2 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_SHIFT (0U)
/*! i2cm_read_buff2 - Byte 2 of a I2C read buffer sequential read (from address i2cm_address+2)
*/
#define EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_SHIFT)) & EDDC_I2CM_READ_BUFF2_I2CM_READ_BUFF2_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF3 - I2C Master Sequential Read Buffer Register 3 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_SHIFT (0U)
/*! i2cm_read_buff3 - Byte 3 of a I2C read buffer sequential read (from address i2cm_address+3)
*/
#define EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_SHIFT)) & EDDC_I2CM_READ_BUFF3_I2CM_READ_BUFF3_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF4 - I2C Master Sequential Read Buffer Register 4 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_SHIFT (0U)
/*! i2cm_read_buff4 - Byte 4 of a I2C read buffer sequential read (from address i2cm_address+4)
*/
#define EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_SHIFT)) & EDDC_I2CM_READ_BUFF4_I2CM_READ_BUFF4_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF5 - I2C Master Sequential Read Buffer Register 5 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_SHIFT (0U)
/*! i2cm_read_buff5 - Byte 5 of a I2C read buffer sequential read (from address i2cm_address+5)
*/
#define EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_SHIFT)) & EDDC_I2CM_READ_BUFF5_I2CM_READ_BUFF5_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF6 - I2C Master Sequential Read Buffer Register 6 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_SHIFT (0U)
/*! i2cm_read_buff6 - Byte 6 of a I2C read buffer sequential read (from address i2cm_address+6)
*/
#define EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_SHIFT)) & EDDC_I2CM_READ_BUFF6_I2CM_READ_BUFF6_MASK)
/*! @} */
/*! @name I2CM_READ_BUFF7 - I2C Master Sequential Read Buffer Register 7 */
/*! @{ */
#define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_MASK (0xFFU)
#define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_SHIFT (0U)
/*! i2cm_read_buff7 - Byte 7 of a I2C read buffer sequential read (from address i2cm_address+7)
*/
#define EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_SHIFT)) & EDDC_I2CM_READ_BUFF7_I2CM_READ_BUFF7_MASK)
/*! @} */
/*! @name I2CM_SCDC_UPDATE0 - I2C SCDC Read Update Register 0 */
/*! @{ */
#define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_MASK (0xFFU)
#define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_SHIFT (0U)
/*! i2cm_scdc_update0 - Byte 0 of a SCDC I2C update sequential read
*/
#define EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_SHIFT)) & EDDC_I2CM_SCDC_UPDATE0_I2CM_SCDC_UPDATE0_MASK)
/*! @} */
/*! @name I2CM_SCDC_UPDATE1 - I2C SCDC Read Update Register 1 */
/*! @{ */
#define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_MASK (0xFFU)
#define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_SHIFT (0U)
/*! i2cm_scdc_update1 - Byte 1 of a SCDC I2C update sequential read
*/
#define EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1(x) (((uint8_t)(((uint8_t)(x)) << EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_SHIFT)) & EDDC_I2CM_SCDC_UPDATE1_I2CM_SCDC_UPDATE1_MASK)
/*! @} */
/*!
* @}
*/ /* end of group EDDC_Register_Masks */
/* EDDC - Peripheral instance base addresses */
/** Peripheral EDDC base address */
#define EDDC_BASE (0x32FDFE00u)
/** Peripheral EDDC base pointer */
#define EDDC ((EDDC_Type *)EDDC_BASE)
/** Array initializer of EDDC peripheral base addresses */
#define EDDC_BASE_ADDRS { EDDC_BASE }
/** Array initializer of EDDC peripheral base pointers */
#define EDDC_BASE_PTRS { EDDC }
/*!
* @}
*/ /* end of group EDDC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENET Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
* @{
*/
/** ENET - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
__IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
uint8_t RESERVED_1[4];
__IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
__IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
uint8_t RESERVED_2[12];
__IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
uint8_t RESERVED_3[24];
__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
uint8_t RESERVED_4[28];
__IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
uint8_t RESERVED_5[28];
__IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
uint8_t RESERVED_6[60];
__IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
uint8_t RESERVED_7[28];
__IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
__IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
__IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
__IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
uint8_t RESERVED_8[4];
__IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_9[12];
__IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
__IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
__IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
__IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
uint8_t RESERVED_10[28];
__IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
uint8_t RESERVED_11[24];
__IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
__IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
__IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
__IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
__IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
__IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
uint8_t RESERVED_12[8];
__IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
__IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
__IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
uint8_t RESERVED_13[4];
__IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
__IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
__IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
__IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
__IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
__IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
__IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
__IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
__IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
uint8_t RESERVED_14[12];
__IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
__IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
__IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
uint8_t RESERVED_15[8];
__IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
__IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
__IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
__IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
__IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
__IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
uint8_t RESERVED_16[12];
uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
__I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
__I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
__I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
__I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
__I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
__I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
__I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
__I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
__I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
__I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
__I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
__I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
__I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
__I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
__I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
__I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
__I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
__I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
__I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
__I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
__I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
__I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
__I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
__I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
__I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
__I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
__I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
__I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
uint8_t RESERVED_17[12];
__I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
__I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
__I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
__I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
__I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
__I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
__I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
__I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
__I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
__I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
__I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
__I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
__I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
__I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
__I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
__I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
__I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
__I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
__I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
__I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
__I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
__I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
__I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
uint8_t RESERVED_18[284];
__IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
__IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
__IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
__IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
__IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
__IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
__I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
uint8_t RESERVED_19[488];
__IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
struct { /* offset: 0x608, array step: 0x8 */
__IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
__IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
} CHANNEL[4];
} ENET_Type;
/* ----------------------------------------------------------------------------
-- ENET Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Register_Masks ENET Register Masks
* @{
*/
/*! @name EIR - Interrupt Event Register */
/*! @{ */
#define ENET_EIR_RXB1_MASK (0x1U)
#define ENET_EIR_RXB1_SHIFT (0U)
/*! RXB1 - Receive buffer interrupt, class 1
*/
#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
#define ENET_EIR_RXF1_MASK (0x2U)
#define ENET_EIR_RXF1_SHIFT (1U)
/*! RXF1 - Receive frame interrupt, class 1
*/
#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
#define ENET_EIR_TXB1_MASK (0x4U)
#define ENET_EIR_TXB1_SHIFT (2U)
/*! TXB1 - Transmit buffer interrupt, class 1
*/
#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
#define ENET_EIR_TXF1_MASK (0x8U)
#define ENET_EIR_TXF1_SHIFT (3U)
/*! TXF1 - Transmit frame interrupt, class 1
*/
#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
#define ENET_EIR_RXB2_MASK (0x10U)
#define ENET_EIR_RXB2_SHIFT (4U)
/*! RXB2 - Receive buffer interrupt, class 2
*/
#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
#define ENET_EIR_RXF2_MASK (0x20U)
#define ENET_EIR_RXF2_SHIFT (5U)
/*! RXF2 - Receive frame interrupt, class 2
*/
#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
#define ENET_EIR_TXB2_MASK (0x40U)
#define ENET_EIR_TXB2_SHIFT (6U)
/*! TXB2 - Transmit buffer interrupt, class 2
*/
#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
#define ENET_EIR_TXF2_MASK (0x80U)
#define ENET_EIR_TXF2_SHIFT (7U)
/*! TXF2 - Transmit frame interrupt, class 2
*/
#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
#define ENET_EIR_TS_TIMER_MASK (0x8000U)
#define ENET_EIR_TS_TIMER_SHIFT (15U)
/*! TS_TIMER - Timestamp Timer
*/
#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIR_TS_AVAIL_SHIFT (16U)
/*! TS_AVAIL - Transmit Timestamp Available
*/
#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define ENET_EIR_WAKEUP_MASK (0x20000U)
#define ENET_EIR_WAKEUP_SHIFT (17U)
/*! WAKEUP - Node Wakeup Request Indication
*/
#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define ENET_EIR_PLR_MASK (0x40000U)
#define ENET_EIR_PLR_SHIFT (18U)
/*! PLR - Payload Receive Error
*/
#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define ENET_EIR_UN_MASK (0x80000U)
#define ENET_EIR_UN_SHIFT (19U)
/*! UN - Transmit FIFO Underrun
*/
#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define ENET_EIR_RL_MASK (0x100000U)
#define ENET_EIR_RL_SHIFT (20U)
/*! RL - Collision Retry Limit
*/
#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define ENET_EIR_LC_MASK (0x200000U)
#define ENET_EIR_LC_SHIFT (21U)
/*! LC - Late Collision
*/
#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define ENET_EIR_EBERR_MASK (0x400000U)
#define ENET_EIR_EBERR_SHIFT (22U)
/*! EBERR - Ethernet Bus Error
*/
#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define ENET_EIR_MII_MASK (0x800000U)
#define ENET_EIR_MII_SHIFT (23U)
/*! MII - MII Interrupt.
*/
#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define ENET_EIR_RXB_MASK (0x1000000U)
#define ENET_EIR_RXB_SHIFT (24U)
/*! RXB - Receive Buffer Interrupt
*/
#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define ENET_EIR_RXF_MASK (0x2000000U)
#define ENET_EIR_RXF_SHIFT (25U)
/*! RXF - Receive Frame Interrupt
*/
#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define ENET_EIR_TXB_MASK (0x4000000U)
#define ENET_EIR_TXB_SHIFT (26U)
/*! TXB - Transmit Buffer Interrupt
*/
#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define ENET_EIR_TXF_MASK (0x8000000U)
#define ENET_EIR_TXF_SHIFT (27U)
/*! TXF - Transmit Frame Interrupt
*/
#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define ENET_EIR_GRA_MASK (0x10000000U)
#define ENET_EIR_GRA_SHIFT (28U)
/*! GRA - Graceful Stop Complete
*/
#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define ENET_EIR_BABT_MASK (0x20000000U)
#define ENET_EIR_BABT_SHIFT (29U)
/*! BABT - Babbling Transmit Error
*/
#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define ENET_EIR_BABR_MASK (0x40000000U)
#define ENET_EIR_BABR_SHIFT (30U)
/*! BABR - Babbling Receive Error
*/
#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
/*! @} */
/*! @name EIMR - Interrupt Mask Register */
/*! @{ */
#define ENET_EIMR_RXB1_MASK (0x1U)
#define ENET_EIMR_RXB1_SHIFT (0U)
/*! RXB1 - Receive buffer interrupt, class 1
*/
#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
#define ENET_EIMR_RXF1_MASK (0x2U)
#define ENET_EIMR_RXF1_SHIFT (1U)
/*! RXF1 - Receive frame interrupt, class 1
*/
#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
#define ENET_EIMR_TXB1_MASK (0x4U)
#define ENET_EIMR_TXB1_SHIFT (2U)
/*! TXB1 - Transmit buffer interrupt, class 1
*/
#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
#define ENET_EIMR_TXF1_MASK (0x8U)
#define ENET_EIMR_TXF1_SHIFT (3U)
/*! TXF1 - Transmit frame interrupt, class 1
*/
#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
#define ENET_EIMR_RXB2_MASK (0x10U)
#define ENET_EIMR_RXB2_SHIFT (4U)
/*! RXB2 - Receive buffer interrupt, class 2
*/
#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
#define ENET_EIMR_RXF2_MASK (0x20U)
#define ENET_EIMR_RXF2_SHIFT (5U)
/*! RXF2 - Receive frame interrupt, class 2
*/
#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
#define ENET_EIMR_TXB2_MASK (0x40U)
#define ENET_EIMR_TXB2_SHIFT (6U)
/*! TXB2 - Transmit buffer interrupt, class 2
*/
#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
#define ENET_EIMR_TXF2_MASK (0x80U)
#define ENET_EIMR_TXF2_SHIFT (7U)
/*! TXF2 - Transmit frame interrupt, class 2
*/
#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
#define ENET_EIMR_TS_TIMER_SHIFT (15U)
/*! TS_TIMER - TS_TIMER Interrupt Mask
*/
#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
/*! TS_AVAIL - TS_AVAIL Interrupt Mask
*/
#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define ENET_EIMR_WAKEUP_MASK (0x20000U)
#define ENET_EIMR_WAKEUP_SHIFT (17U)
/*! WAKEUP - WAKEUP Interrupt Mask
*/
#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define ENET_EIMR_PLR_MASK (0x40000U)
#define ENET_EIMR_PLR_SHIFT (18U)
/*! PLR - PLR Interrupt Mask
*/
#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define ENET_EIMR_UN_MASK (0x80000U)
#define ENET_EIMR_UN_SHIFT (19U)
/*! UN - UN Interrupt Mask
*/
#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define ENET_EIMR_RL_MASK (0x100000U)
#define ENET_EIMR_RL_SHIFT (20U)
/*! RL - RL Interrupt Mask
*/
#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define ENET_EIMR_LC_MASK (0x200000U)
#define ENET_EIMR_LC_SHIFT (21U)
/*! LC - LC Interrupt Mask
*/
#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define ENET_EIMR_EBERR_MASK (0x400000U)
#define ENET_EIMR_EBERR_SHIFT (22U)
/*! EBERR - EBERR Interrupt Mask
*/
#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define ENET_EIMR_MII_MASK (0x800000U)
#define ENET_EIMR_MII_SHIFT (23U)
/*! MII - MII Interrupt Mask
*/
#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define ENET_EIMR_RXB_MASK (0x1000000U)
#define ENET_EIMR_RXB_SHIFT (24U)
/*! RXB - RXB Interrupt Mask
*/
#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define ENET_EIMR_RXF_MASK (0x2000000U)
#define ENET_EIMR_RXF_SHIFT (25U)
/*! RXF - RXF Interrupt Mask
*/
#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define ENET_EIMR_TXB_MASK (0x4000000U)
#define ENET_EIMR_TXB_SHIFT (26U)
/*! TXB - TXB Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define ENET_EIMR_TXF_MASK (0x8000000U)
#define ENET_EIMR_TXF_SHIFT (27U)
/*! TXF - TXF Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define ENET_EIMR_GRA_MASK (0x10000000U)
#define ENET_EIMR_GRA_SHIFT (28U)
/*! GRA - GRA Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define ENET_EIMR_BABT_MASK (0x20000000U)
#define ENET_EIMR_BABT_SHIFT (29U)
/*! BABT - BABT Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define ENET_EIMR_BABR_MASK (0x40000000U)
#define ENET_EIMR_BABR_SHIFT (30U)
/*! BABR - BABR Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
/*! @} */
/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
/*! @{ */
#define ENET_RDAR_RDAR_MASK (0x1000000U)
#define ENET_RDAR_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
/*! @} */
/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
/*! @{ */
#define ENET_TDAR_TDAR_MASK (0x1000000U)
#define ENET_TDAR_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
/*! @} */
/*! @name ECR - Ethernet Control Register */
/*! @{ */
#define ENET_ECR_RESET_MASK (0x1U)
#define ENET_ECR_RESET_SHIFT (0U)
/*! RESET - Ethernet MAC Reset
*/
#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define ENET_ECR_ETHEREN_MASK (0x2U)
#define ENET_ECR_ETHEREN_SHIFT (1U)
/*! ETHEREN - Ethernet Enable
* 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
* 0b1..MAC is enabled, and reception and transmission are possible.
*/
#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define ENET_ECR_MAGICEN_MASK (0x4U)
#define ENET_ECR_MAGICEN_SHIFT (2U)
/*! MAGICEN - Magic Packet Detection Enable
* 0b0..Magic detection logic disabled.
* 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
*/
#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define ENET_ECR_SLEEP_MASK (0x8U)
#define ENET_ECR_SLEEP_SHIFT (3U)
/*! SLEEP - Sleep Mode Enable
* 0b0..Normal operating mode.
* 0b1..Sleep mode.
*/
#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define ENET_ECR_EN1588_MASK (0x10U)
#define ENET_ECR_EN1588_SHIFT (4U)
/*! EN1588 - EN1588 Enable
* 0b0..Legacy FEC buffer descriptors and functions enabled.
* 0b1..Enhanced frame time-stamping functions enabled.
*/
#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define ENET_ECR_SPEED_MASK (0x20U)
#define ENET_ECR_SPEED_SHIFT (5U)
/*! SPEED
* 0b0..10/100-Mbit/s mode
* 0b1..1000-Mbit/s mode
*/
#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
#define ENET_ECR_DBGEN_MASK (0x40U)
#define ENET_ECR_DBGEN_SHIFT (6U)
/*! DBGEN - Debug Enable
* 0b0..MAC continues operation in debug mode.
* 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
*/
#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define ENET_ECR_DBSWP_MASK (0x100U)
#define ENET_ECR_DBSWP_SHIFT (8U)
/*! DBSWP - Descriptor Byte Swapping Enable
* 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
* 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
*/
#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define ENET_ECR_SVLANEN_MASK (0x200U)
#define ENET_ECR_SVLANEN_SHIFT (9U)
/*! SVLANEN - S-VLAN enable
* 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
* 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
* receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
* classification match comparators, RCMRn.
*/
#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
/*! VLANUSE2ND - VLAN use second tag
* 0b0..Always extract data from the first VLAN tag if it exists.
* 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
* double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
* second tag must be a C-VLAN
*/
#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
#define ENET_ECR_SVLANDBL_MASK (0x800U)
#define ENET_ECR_SVLANDBL_SHIFT (11U)
/*! SVLANDBL - S-VLAN double tag
*/
#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
#define ENET_ECR_TXC_DLY_MASK (0x10000U)
#define ENET_ECR_TXC_DLY_SHIFT (16U)
/*! TXC_DLY - Transmit clock delay
* 0b0..RGMII_TXC is not delayed.
* 0b1..Generate delayed version of RGMII_TXC.
*/
#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
#define ENET_ECR_RXC_DLY_MASK (0x20000U)
#define ENET_ECR_RXC_DLY_SHIFT (17U)
/*! RXC_DLY - Receive clock delay
* 0b0..Use non-delayed version of RGMII_RXC.
* 0b1..Use delayed version of RGMII_RXC.
*/
#define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK)
/*! @} */
/*! @name MMFR - MII Management Frame Register */
/*! @{ */
#define ENET_MMFR_DATA_MASK (0xFFFFU)
#define ENET_MMFR_DATA_SHIFT (0U)
/*! DATA - Management Frame Data
*/
#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define ENET_MMFR_TA_MASK (0x30000U)
#define ENET_MMFR_TA_SHIFT (16U)
/*! TA - Turn Around
*/
#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define ENET_MMFR_RA_MASK (0x7C0000U)
#define ENET_MMFR_RA_SHIFT (18U)
/*! RA - Register Address
*/
#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define ENET_MMFR_PA_MASK (0xF800000U)
#define ENET_MMFR_PA_SHIFT (23U)
/*! PA - PHY Address
*/
#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define ENET_MMFR_OP_MASK (0x30000000U)
#define ENET_MMFR_OP_SHIFT (28U)
/*! OP - Operation Code
*/
#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define ENET_MMFR_ST_MASK (0xC0000000U)
#define ENET_MMFR_ST_SHIFT (30U)
/*! ST - Start Of Frame Delimiter
*/
#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
/*! @} */
/*! @name MSCR - MII Speed Control Register */
/*! @{ */
#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
#define ENET_MSCR_MII_SPEED_SHIFT (1U)
/*! MII_SPEED - MII Speed
*/
#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define ENET_MSCR_DIS_PRE_MASK (0x80U)
#define ENET_MSCR_DIS_PRE_SHIFT (7U)
/*! DIS_PRE - Disable Preamble
* 0b0..Preamble enabled.
* 0b1..Preamble (32 ones) is not prepended to the MII management frame.
*/
#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define ENET_MSCR_HOLDTIME_MASK (0x700U)
#define ENET_MSCR_HOLDTIME_SHIFT (8U)
/*! HOLDTIME - Hold time On MDIO Output
* 0b000..1 internal module clock cycle
* 0b001..2 internal module clock cycles
* 0b010..3 internal module clock cycles
* 0b111..8 internal module clock cycles
*/
#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
/*! @} */
/*! @name MIBC - MIB Control Register */
/*! @{ */
#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
/*! MIB_CLEAR - MIB Clear
* 0b0..See note above.
* 0b1..All statistics counters are reset to 0.
*/
#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
/*! MIB_IDLE - MIB Idle
* 0b0..The MIB block is updating MIB counters.
* 0b1..The MIB block is not currently updating any MIB counters.
*/
#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
#define ENET_MIBC_MIB_DIS_SHIFT (31U)
/*! MIB_DIS - Disable MIB Logic
* 0b0..MIB logic is enabled.
* 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
*/
#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
/*! @} */
/*! @name RCR - Receive Control Register */
/*! @{ */
#define ENET_RCR_LOOP_MASK (0x1U)
#define ENET_RCR_LOOP_SHIFT (0U)
/*! LOOP - Internal Loopback
* 0b0..Loopback disabled.
* 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
*/
#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define ENET_RCR_DRT_MASK (0x2U)
#define ENET_RCR_DRT_SHIFT (1U)
/*! DRT - Disable Receive On Transmit
* 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
* 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
*/
#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define ENET_RCR_MII_MODE_MASK (0x4U)
#define ENET_RCR_MII_MODE_SHIFT (2U)
/*! MII_MODE - Media Independent Interface Mode
* 0b0..Reserved.
* 0b1..RMII mode, as indicated by the RMII_MODE field.
*/
#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define ENET_RCR_PROM_MASK (0x8U)
#define ENET_RCR_PROM_SHIFT (3U)
/*! PROM - Promiscuous Mode
* 0b0..Disabled.
* 0b1..Enabled.
*/
#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define ENET_RCR_BC_REJ_MASK (0x10U)
#define ENET_RCR_BC_REJ_SHIFT (4U)
/*! BC_REJ - Broadcast Frame Reject
*/
#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define ENET_RCR_FCE_MASK (0x20U)
#define ENET_RCR_FCE_SHIFT (5U)
/*! FCE - Flow Control Enable
*/
#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define ENET_RCR_RGMII_EN_MASK (0x40U)
#define ENET_RCR_RGMII_EN_SHIFT (6U)
/*! RGMII_EN - RGMII Mode Enable
* 0b0..MAC configured for non-RGMII operation
* 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
* ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
*/
#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
#define ENET_RCR_RMII_MODE_MASK (0x100U)
#define ENET_RCR_RMII_MODE_SHIFT (8U)
/*! RMII_MODE - RMII Mode Enable
* 0b0..MAC configured for MII mode.
* 0b1..MAC configured for RMII operation.
*/
#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define ENET_RCR_RMII_10T_MASK (0x200U)
#define ENET_RCR_RMII_10T_SHIFT (9U)
/*! RMII_10T
* 0b0..100-Mbit/s operation.
* 0b1..10-Mbit/s operation.
*/
#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define ENET_RCR_PADEN_MASK (0x1000U)
#define ENET_RCR_PADEN_SHIFT (12U)
/*! PADEN - Enable Frame Padding Remove On Receive
* 0b0..No padding is removed on receive by the MAC.
* 0b1..Padding is removed from received frames.
*/
#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define ENET_RCR_PAUFWD_MASK (0x2000U)
#define ENET_RCR_PAUFWD_SHIFT (13U)
/*! PAUFWD - Terminate/Forward Pause Frames
* 0b0..Pause frames are terminated and discarded in the MAC.
* 0b1..Pause frames are forwarded to the user application.
*/
#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define ENET_RCR_CRCFWD_MASK (0x4000U)
#define ENET_RCR_CRCFWD_SHIFT (14U)
/*! CRCFWD - Terminate/Forward Received CRC
* 0b0..The CRC field of received frames is transmitted to the user application.
* 0b1..The CRC field is stripped from the frame.
*/
#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define ENET_RCR_CFEN_MASK (0x8000U)
#define ENET_RCR_CFEN_SHIFT (15U)
/*! CFEN - MAC Control Frame Enable
* 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
* 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
*/
#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
#define ENET_RCR_MAX_FL_SHIFT (16U)
/*! MAX_FL - Maximum Frame Length
*/
#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define ENET_RCR_NLC_MASK (0x40000000U)
#define ENET_RCR_NLC_SHIFT (30U)
/*! NLC - Payload Length Check Disable
* 0b0..The payload length check is disabled.
* 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
*/
#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define ENET_RCR_GRS_MASK (0x80000000U)
#define ENET_RCR_GRS_SHIFT (31U)
/*! GRS - Graceful Receive Stopped
*/
#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
/*! @} */
/*! @name TCR - Transmit Control Register */
/*! @{ */
#define ENET_TCR_GTS_MASK (0x1U)
#define ENET_TCR_GTS_SHIFT (0U)
/*! GTS - Graceful Transmit Stop
*/
#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define ENET_TCR_FDEN_MASK (0x4U)
#define ENET_TCR_FDEN_SHIFT (2U)
/*! FDEN - Full-Duplex Enable
*/
#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
/*! TFC_PAUSE - Transmit Frame Control Pause
* 0b0..No PAUSE frame transmitted.
* 0b1..The MAC stops transmission of data frames after the current transmission is complete.
*/
#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
/*! RFC_PAUSE - Receive Frame Control Pause
*/
#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define ENET_TCR_ADDSEL_MASK (0xE0U)
#define ENET_TCR_ADDSEL_SHIFT (5U)
/*! ADDSEL - Source MAC Address Select On Transmit
* 0b000..Node MAC address programmed on PADDR1/2 registers.
* 0b100..Reserved.
* 0b101..Reserved.
* 0b110..Reserved.
*/
#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define ENET_TCR_ADDINS_MASK (0x100U)
#define ENET_TCR_ADDINS_SHIFT (8U)
/*! ADDINS - Set MAC Address On Transmit
* 0b0..The source MAC address is not modified by the MAC.
* 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
*/
#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define ENET_TCR_CRCFWD_MASK (0x200U)
#define ENET_TCR_CRCFWD_SHIFT (9U)
/*! CRCFWD - Forward Frame From Application With CRC
* 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
* 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
*/
#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
/*! @} */
/*! @name PALR - Physical Address Lower Register */
/*! @{ */
#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
#define ENET_PALR_PADDR1_SHIFT (0U)
/*! PADDR1 - Pause Address
*/
#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
/*! @} */
/*! @name PAUR - Physical Address Upper Register */
/*! @{ */
#define ENET_PAUR_TYPE_MASK (0xFFFFU)
#define ENET_PAUR_TYPE_SHIFT (0U)
/*! TYPE - Type Field In PAUSE Frames
*/
#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
#define ENET_PAUR_PADDR2_SHIFT (16U)
#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
/*! @} */
/*! @name OPD - Opcode/Pause Duration Register */
/*! @{ */
#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
/*! PAUSE_DUR - Pause Duration
*/
#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
#define ENET_OPD_OPCODE_SHIFT (16U)
/*! OPCODE - Opcode Field In PAUSE Frames
*/
#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
/*! @} */
/*! @name TXIC - Transmit Interrupt Coalescing Register */
/*! @{ */
#define ENET_TXIC_ICTT_MASK (0xFFFFU)
#define ENET_TXIC_ICTT_SHIFT (0U)
/*! ICTT - Interrupt coalescing timer threshold
*/
#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
#define ENET_TXIC_ICFT_MASK (0xFF00000U)
#define ENET_TXIC_ICFT_SHIFT (20U)
/*! ICFT - Interrupt coalescing frame count threshold
*/
#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
#define ENET_TXIC_ICCS_MASK (0x40000000U)
#define ENET_TXIC_ICCS_SHIFT (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
* 0b0..Use GMII TX clocks.
* 0b1..Use ENET system clock.
*/
#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
#define ENET_TXIC_ICEN_MASK (0x80000000U)
#define ENET_TXIC_ICEN_SHIFT (31U)
/*! ICEN - Interrupt Coalescing Enable
* 0b0..Disable Interrupt coalescing.
* 0b1..Enable Interrupt coalescing.
*/
#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
/*! @} */
/* The count of ENET_TXIC */
#define ENET_TXIC_COUNT (3U)
/*! @name RXIC - Receive Interrupt Coalescing Register */
/*! @{ */
#define ENET_RXIC_ICTT_MASK (0xFFFFU)
#define ENET_RXIC_ICTT_SHIFT (0U)
/*! ICTT - Interrupt coalescing timer threshold
*/
#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
#define ENET_RXIC_ICFT_MASK (0xFF00000U)
#define ENET_RXIC_ICFT_SHIFT (20U)
/*! ICFT - Interrupt coalescing frame count threshold
*/
#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
#define ENET_RXIC_ICCS_MASK (0x40000000U)
#define ENET_RXIC_ICCS_SHIFT (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
* 0b0..Use MII/GMII TX clocks.
* 0b1..Use ENET system clock.
*/
#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
#define ENET_RXIC_ICEN_MASK (0x80000000U)
#define ENET_RXIC_ICEN_SHIFT (31U)
/*! ICEN - Interrupt Coalescing Enable
* 0b0..Disable Interrupt coalescing.
* 0b1..Enable Interrupt coalescing.
*/
#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
/*! @} */
/* The count of ENET_RXIC */
#define ENET_RXIC_COUNT (3U)
/*! @name IAUR - Descriptor Individual Upper Address Register */
/*! @{ */
#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
#define ENET_IAUR_IADDR1_SHIFT (0U)
#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
/*! @} */
/*! @name IALR - Descriptor Individual Lower Address Register */
/*! @{ */
#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
#define ENET_IALR_IADDR2_SHIFT (0U)
#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
/*! @} */
/*! @name GAUR - Descriptor Group Upper Address Register */
/*! @{ */
#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
#define ENET_GAUR_GADDR1_SHIFT (0U)
#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
/*! @} */
/*! @name GALR - Descriptor Group Lower Address Register */
/*! @{ */
#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
#define ENET_GALR_GADDR2_SHIFT (0U)
#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
/*! @} */
/*! @name TFWR - Transmit FIFO Watermark Register */
/*! @{ */
#define ENET_TFWR_TFWR_MASK (0x3FU)
#define ENET_TFWR_TFWR_SHIFT (0U)
/*! TFWR - Transmit FIFO Write
* 0b000000..64 bytes written.
* 0b000001..64 bytes written.
* 0b000010..128 bytes written.
* 0b000011..192 bytes written.
* 0b111111..4032 bytes written.
*/
#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define ENET_TFWR_STRFWD_MASK (0x100U)
#define ENET_TFWR_STRFWD_SHIFT (8U)
/*! STRFWD - Store And Forward Enable
* 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
* 0b1..Enabled.
*/
#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
/*! @} */
/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
/*! @{ */
#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR1_R_DES_START_SHIFT (3U)
#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
/*! @} */
/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
/*! @{ */
#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR1_X_DES_START_SHIFT (3U)
#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
/*! @} */
/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
/*! @{ */
#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
/*! @{ */
#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR2_R_DES_START_SHIFT (3U)
#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
/*! @} */
/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
/*! @{ */
#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR2_X_DES_START_SHIFT (3U)
#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
/*! @} */
/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
/*! @{ */
#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
/*! @{ */
#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR_R_DES_START_SHIFT (3U)
#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
/*! @} */
/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
/*! @{ */
#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR_X_DES_START_SHIFT (3U)
#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
/*! @} */
/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
/*! @{ */
#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RSFL - Receive FIFO Section Full Threshold */
/*! @{ */
#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU)
#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
*/
#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
/*! @} */
/*! @name RSEM - Receive FIFO Section Empty Threshold */
/*! @{ */
#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU)
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
*/
#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
*/
#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
/*! @} */
/*! @name RAEM - Receive FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU)
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
*/
#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
/*! @} */
/*! @name RAFL - Receive FIFO Almost Full Threshold */
/*! @{ */
#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU)
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
*/
#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
/*! @} */
/*! @name TSEM - Transmit FIFO Section Empty Threshold */
/*! @{ */
#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU)
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
*/
#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
/*! @} */
/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU)
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
*/
#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
/*! @} */
/*! @name TAFL - Transmit FIFO Almost Full Threshold */
/*! @{ */
#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU)
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
*/
#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
/*! @} */
/*! @name TIPG - Transmit Inter-Packet Gap */
/*! @{ */
#define ENET_TIPG_IPG_MASK (0x1FU)
#define ENET_TIPG_IPG_SHIFT (0U)
/*! IPG - Transmit Inter-Packet Gap
*/
#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
/*! @} */
/*! @name FTRL - Frame Truncation Length */
/*! @{ */
#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
/*! TRUNC_FL - Frame Truncation Length
*/
#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
/*! @} */
/*! @name TACC - Transmit Accelerator Function Configuration */
/*! @{ */
#define ENET_TACC_SHIFT16_MASK (0x1U)
#define ENET_TACC_SHIFT16_SHIFT (0U)
/*! SHIFT16 - TX FIFO Shift-16
* 0b0..Disabled.
* 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
* frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
* function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
* extended to a 16-byte header.
*/
#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define ENET_TACC_IPCHK_MASK (0x8U)
#define ENET_TACC_IPCHK_SHIFT (3U)
/*! IPCHK
* 0b0..Checksum is not inserted.
* 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
* be cleared. If a non-IP frame is transmitted the frame is not modified.
*/
#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define ENET_TACC_PROCHK_MASK (0x10U)
#define ENET_TACC_PROCHK_SHIFT (4U)
/*! PROCHK
* 0b0..Checksum not inserted.
* 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
* frame. The checksum field must be cleared. The other frames are not modified.
*/
#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
/*! @} */
/*! @name RACC - Receive Accelerator Function Configuration */
/*! @{ */
#define ENET_RACC_PADREM_MASK (0x1U)
#define ENET_RACC_PADREM_SHIFT (0U)
/*! PADREM - Enable Padding Removal For Short IP Frames
* 0b0..Padding not removed.
* 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
*/
#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define ENET_RACC_IPDIS_MASK (0x2U)
#define ENET_RACC_IPDIS_SHIFT (1U)
/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
* 0b0..Frames with wrong IPv4 header checksum are not discarded.
* 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
* header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
* store and forward mode (RSFL cleared).
*/
#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define ENET_RACC_PRODIS_MASK (0x4U)
#define ENET_RACC_PRODIS_SHIFT (2U)
/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
* 0b0..Frames with wrong checksum are not discarded.
* 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
* is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
* cleared).
*/
#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define ENET_RACC_LINEDIS_MASK (0x40U)
#define ENET_RACC_LINEDIS_SHIFT (6U)
/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
* 0b0..Frames with errors are not discarded.
* 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
*/
#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define ENET_RACC_SHIFT16_MASK (0x80U)
#define ENET_RACC_SHIFT16_SHIFT (7U)
/*! SHIFT16 - RX FIFO Shift-16
* 0b0..Disabled.
* 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
*/
#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
/*! @} */
/*! @name RCMR - Receive Classification Match Register for Class n */
/*! @{ */
#define ENET_RCMR_CMP0_MASK (0x7U)
#define ENET_RCMR_CMP0_SHIFT (0U)
/*! CMP0 - Compare 0
*/
#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
#define ENET_RCMR_CMP1_MASK (0x70U)
#define ENET_RCMR_CMP1_SHIFT (4U)
/*! CMP1 - Compare 1
*/
#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
#define ENET_RCMR_CMP2_MASK (0x700U)
#define ENET_RCMR_CMP2_SHIFT (8U)
/*! CMP2 - Compare 2
*/
#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
#define ENET_RCMR_CMP3_MASK (0x7000U)
#define ENET_RCMR_CMP3_SHIFT (12U)
/*! CMP3 - Compare 3
*/
#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
#define ENET_RCMR_MATCHEN_MASK (0x10000U)
#define ENET_RCMR_MATCHEN_SHIFT (16U)
/*! MATCHEN - Match Enable
* 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
* 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
*/
#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
/*! @} */
/* The count of ENET_RCMR */
#define ENET_RCMR_COUNT (2U)
/*! @name DMACFG - DMA Class Based Configuration */
/*! @{ */
#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
/*! IDLE_SLOPE - Idle slope
*/
#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
/*! DMA_CLASS_EN - DMA class enable
* 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
* requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
* queues are disabled then their frames will be placed in queue 0.
* 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
*/
#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
/*! CALC_NOIPG - Calculate no IPG
* 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
* for a frame when doing bandwidth calculations. This is the default.
* 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
* when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
* frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
* will become more bandwidth than large frames due to the relation of data to IPG overhead).
*/
#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
/*! @} */
/* The count of ENET_DMACFG */
#define ENET_DMACFG_COUNT (2U)
/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
/*! @{ */
#define ENET_RDAR1_RDAR_MASK (0x1000000U)
#define ENET_RDAR1_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
/*! @} */
/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
/*! @{ */
#define ENET_TDAR1_TDAR_MASK (0x1000000U)
#define ENET_TDAR1_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
/*! @} */
/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
/*! @{ */
#define ENET_RDAR2_RDAR_MASK (0x1000000U)
#define ENET_RDAR2_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
/*! @} */
/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
/*! @{ */
#define ENET_TDAR2_TDAR_MASK (0x1000000U)
#define ENET_TDAR2_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
/*! @} */
/*! @name QOS - QOS Scheme */
/*! @{ */
#define ENET_QOS_TX_SCHEME_MASK (0x7U)
#define ENET_QOS_TX_SCHEME_SHIFT (0U)
/*! TX_SCHEME - TX scheme configuration
* 0b000..Credit-based scheme
* 0b001..Round-robin scheme
* 0b010-0b111..Reserved
*/
#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
/*! RX_FLUSH0 - RX Flush Ring 0
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
/*! RX_FLUSH1 - RX Flush Ring 1
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
/*! RX_FLUSH2 - RX Flush Ring 2
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
/*! @} */
/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
/*! TXPKTS - Packet count
*/
#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
/*! TXPKTS - Broadcast packets
*/
#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
/*! TXPKTS - Multicast packets
*/
#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
/*! TXPKTS - Packets with CRC/align error
*/
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
*/
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
*/
#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of packets less than 64 bytes with bad CRC
*/
#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
*/
#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit collisions
*/
#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 64-byte transmit packets
*/
#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 65- to 127-byte transmit packets
*/
#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 128- to 255-byte transmit packets
*/
#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 256- to 511-byte transmit packets
*/
#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 512- to 1023-byte transmit packets
*/
#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 1024- to 2047-byte transmit packets
*/
#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than 2048 bytes
*/
#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
/*! TXOCTS - Number of transmit octets
*/
#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
/*! @} */
/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted OK
*/
#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with one collision
*/
#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with multiple collisions
*/
#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
/*! @{ */
#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with deferral delay
*/
#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with late collision
*/
#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with excessive collisions
*/
#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with transmit FIFO underrun
*/
#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with carrier sense error
*/
#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_SQE - Reserved Statistic Register */
/*! @{ */
#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
/*! COUNT - Number of flow-control pause frames transmitted
*/
#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
*/
#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
/*! COUNT - Number of packets received
*/
#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
/*! @} */
/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
/*! COUNT - Number of receive broadcast packets
*/
#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
/*! COUNT - Number of receive multicast packets
*/
#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with CRC or align error
*/
#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
/*! @} */
/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and good CRC
*/
#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and good CRC
*/
#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
*/
#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
/*! @} */
/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
*/
#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
/*! COUNT - Number of 64-byte receive packets
*/
#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
/*! COUNT - Number of 65- to 127-byte recieve packets
*/
#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
/*! COUNT - Number of 128- to 255-byte recieve packets
*/
#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
/*! COUNT - Number of 256- to 511-byte recieve packets
*/
#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
/*! COUNT - Number of 512- to 1023-byte recieve packets
*/
#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
/*! COUNT - Number of 1024- to 2047-byte recieve packets
*/
#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
/*! COUNT - Number of greater-than-2048-byte recieve packets
*/
#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
/*! COUNT - Number of receive octets
*/
#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
/*! @{ */
#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
/*! COUNT - Frame count
*/
#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received OK
*/
#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received with CRC error
*/
#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received with alignment error
*/
#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
/*! @{ */
#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
/*! COUNT - Receive FIFO overflow count
*/
#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
/*! COUNT - Number of flow-control pause frames received
*/
#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of octets for frames received without error
*/
#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name ATCR - Adjustable Timer Control Register */
/*! @{ */
#define ENET_ATCR_EN_MASK (0x1U)
#define ENET_ATCR_EN_SHIFT (0U)
/*! EN - Enable Timer
* 0b0..The timer stops at the current value.
* 0b1..The timer starts incrementing.
*/
#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define ENET_ATCR_OFFEN_MASK (0x4U)
#define ENET_ATCR_OFFEN_SHIFT (2U)
/*! OFFEN - Enable One-Shot Offset Event
* 0b0..Disable.
* 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
* when the offset event is reached, so no further event occurs until the field is set again. The timer
* offset value must be set before setting this field.
*/
#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define ENET_ATCR_OFFRST_MASK (0x8U)
#define ENET_ATCR_OFFRST_SHIFT (3U)
/*! OFFRST - Reset Timer On Offset Event
* 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
* 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
*/
#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define ENET_ATCR_PEREN_MASK (0x10U)
#define ENET_ATCR_PEREN_SHIFT (4U)
/*! PEREN - Enable Periodical Event
* 0b0..Disable.
* 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
* the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
* setting this bit. Not all devices contain the event signal output. See the chip configuration details.
*/
#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define ENET_ATCR_PINPER_MASK (0x80U)
#define ENET_ATCR_PINPER_SHIFT (7U)
/*! PINPER
* 0b0..Disable.
* 0b1..Enable.
*/
#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define ENET_ATCR_RESTART_MASK (0x200U)
#define ENET_ATCR_RESTART_SHIFT (9U)
/*! RESTART - Reset Timer
*/
#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define ENET_ATCR_CAPTURE_MASK (0x800U)
#define ENET_ATCR_CAPTURE_SHIFT (11U)
/*! CAPTURE - Capture Timer Value
* 0b0..No effect.
* 0b1..The current time is captured and can be read from the ATVR register.
*/
#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define ENET_ATCR_SLAVE_MASK (0x2000U)
#define ENET_ATCR_SLAVE_SHIFT (13U)
/*! SLAVE - Enable Timer Slave Mode
* 0b0..The timer is active and all configuration fields in this register are relevant.
* 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
* CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
*/
#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
/*! @} */
/*! @name ATVR - Timer Value Register */
/*! @{ */
#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
#define ENET_ATVR_ATIME_SHIFT (0U)
#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
/*! @} */
/*! @name ATOFF - Timer Offset Register */
/*! @{ */
#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
#define ENET_ATOFF_OFFSET_SHIFT (0U)
#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
/*! @} */
/*! @name ATPER - Timer Period Register */
/*! @{ */
#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
#define ENET_ATPER_PERIOD_SHIFT (0U)
#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
/*! @} */
/*! @name ATCOR - Timer Correction Register */
/*! @{ */
#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
#define ENET_ATCOR_COR_SHIFT (0U)
/*! COR - Correction Counter Wrap-Around Value
*/
#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
/*! @} */
/*! @name ATINC - Time-Stamping Clock Period Register */
/*! @{ */
#define ENET_ATINC_INC_MASK (0x7FU)
#define ENET_ATINC_INC_SHIFT (0U)
/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
*/
#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
#define ENET_ATINC_INC_CORR_SHIFT (8U)
/*! INC_CORR - Correction Increment Value
*/
#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
/*! @} */
/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
/*! @{ */
#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
/*! @} */
/*! @name TGSR - Timer Global Status Register */
/*! @{ */
#define ENET_TGSR_TF0_MASK (0x1U)
#define ENET_TGSR_TF0_SHIFT (0U)
/*! TF0 - Copy Of Timer Flag For Channel 0
* 0b0..Timer Flag for Channel 0 is clear
* 0b1..Timer Flag for Channel 0 is set
*/
#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define ENET_TGSR_TF1_MASK (0x2U)
#define ENET_TGSR_TF1_SHIFT (1U)
/*! TF1 - Copy Of Timer Flag For Channel 1
* 0b0..Timer Flag for Channel 1 is clear
* 0b1..Timer Flag for Channel 1 is set
*/
#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define ENET_TGSR_TF2_MASK (0x4U)
#define ENET_TGSR_TF2_SHIFT (2U)
/*! TF2 - Copy Of Timer Flag For Channel 2
* 0b0..Timer Flag for Channel 2 is clear
* 0b1..Timer Flag for Channel 2 is set
*/
#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define ENET_TGSR_TF3_MASK (0x8U)
#define ENET_TGSR_TF3_SHIFT (3U)
/*! TF3 - Copy Of Timer Flag For Channel 3
* 0b0..Timer Flag for Channel 3 is clear
* 0b1..Timer Flag for Channel 3 is set
*/
#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
/*! @} */
/*! @name TCSR - Timer Control Status Register */
/*! @{ */
#define ENET_TCSR_TDRE_MASK (0x1U)
#define ENET_TCSR_TDRE_SHIFT (0U)
/*! TDRE - Timer DMA Request Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define ENET_TCSR_TMODE_MASK (0x3CU)
#define ENET_TCSR_TMODE_SHIFT (2U)
/*! TMODE - Timer Mode
* 0b0000..Timer Channel is disabled.
* 0b0001..Timer Channel is configured for Input Capture on rising edge.
* 0b0010..Timer Channel is configured for Input Capture on falling edge.
* 0b0011..Timer Channel is configured for Input Capture on both edges.
* 0b0100..Timer Channel is configured for Output Compare - software only.
* 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
* 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
* 0b0111..Timer Channel is configured for Output Compare - set output on compare.
* 0b1000..Reserved
* 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
* 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
* 0b110x..Reserved
* 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
* 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
*/
#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define ENET_TCSR_TIE_MASK (0x40U)
#define ENET_TCSR_TIE_SHIFT (6U)
/*! TIE - Timer Interrupt Enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define ENET_TCSR_TF_MASK (0x80U)
#define ENET_TCSR_TF_SHIFT (7U)
/*! TF - Timer Flag
* 0b0..Input Capture or Output Compare has not occurred.
* 0b1..Input Capture or Output Compare has occurred.
*/
#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
/*! @} */
/* The count of ENET_TCSR */
#define ENET_TCSR_COUNT (4U)
/*! @name TCCR - Timer Compare Capture Register */
/*! @{ */
#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
#define ENET_TCCR_TCC_SHIFT (0U)
/*! TCC - Timer Capture Compare
*/
#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
/*! @} */
/* The count of ENET_TCCR */
#define ENET_TCCR_COUNT (4U)
/*!
* @}
*/ /* end of group ENET_Register_Masks */
/* ENET - Peripheral instance base addresses */
/** Peripheral ENET1 base address */
#define ENET1_BASE (0x30BE0000u)
/** Peripheral ENET1 base pointer */
#define ENET1 ((ENET_Type *)ENET1_BASE)
/** Array initializer of ENET peripheral base addresses */
#define ENET_BASE_ADDRS { ENET1_BASE }
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASE_PTRS { ENET1 }
/** Interrupt vectors for the ENET peripheral type */
#define ENET_Transmit_IRQS { ENET1_IRQn }
#define ENET_Receive_IRQS { ENET1_IRQn }
#define ENET_Error_IRQS { ENET1_IRQn }
#define ENET_1588_Timer_IRQS { ENET1_1588_Timer_IRQn }
#define ENET_Ts_IRQS { ENET1_1588_Timer_IRQn }
/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT (64U)
/*!
* @}
*/ /* end of group ENET_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENET_QOS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
* @{
*/
/** ENET_QOS - Register Layout Typedef */
typedef struct {
__IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration Register, offset: 0x0 */
__IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */
__IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */
__IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */
__IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table Register 0, offset: 0x10 */
__IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Register 1, offset: 0x14 */
uint8_t RESERVED_0[56];
__IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */
__IO uint32_t MAC_VLAN_TAG_DATA; /**< MAC VLAN Tag Data, offset: 0x54 */
__IO uint32_t MAC_VLAN_HASH_TABLE; /**< MAC VLAN Hash Table, offset: 0x58 */
uint8_t RESERVED_1[4];
__IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
__IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
uint8_t RESERVED_2[8];
__IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
uint8_t RESERVED_3[12];
__IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */
__IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */
__IO uint32_t MAC_TXQ_PRTY_MAP0; /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
__IO uint32_t MAC_TXQ_PRTY_MAP1; /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
__IO uint32_t MAC_RXQ_CTRL[4]; /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
__I uint32_t MAC_INTERRUPT_STATUS; /**< Interrupt Status, offset: 0xB0 */
__IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */
__I uint32_t MAC_RX_TX_STATUS; /**< Receive Transmit Status, offset: 0xB8 */
uint8_t RESERVED_4[4];
__IO uint32_t MAC_PMT_CONTROL_STATUS; /**< PMT Control and Status, offset: 0xC0 */
__IO uint32_t MAC_RWK_PACKET_FILTER; /**< Remote Wakeup Filter, offset: 0xC4 */
uint8_t RESERVED_5[8];
__IO uint32_t MAC_LPI_CONTROL_STATUS; /**< LPI Control and Status, offset: 0xD0 */
__IO uint32_t MAC_LPI_TIMERS_CONTROL; /**< LPI Timers Control, offset: 0xD4 */
__IO uint32_t MAC_LPI_ENTRY_TIMER; /**< Tx LPI Entry Timer Control, offset: 0xD8 */
__IO uint32_t MAC_ONEUS_TIC_COUNTER; /**< One-microsecond Reference Timer, offset: 0xDC */
uint8_t RESERVED_6[24];
__IO uint32_t MAC_PHYIF_CONTROL_STATUS; /**< PHY Interface Control and Status, offset: 0xF8 */
uint8_t RESERVED_7[20];
__I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */
__I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */
uint8_t RESERVED_8[4];
__I uint32_t MAC_HW_FEAT[4]; /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
uint8_t RESERVED_9[212];
__IO uint32_t MAC_MDIO_ADDRESS; /**< MDIO Address, offset: 0x200 */
__IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */
uint8_t RESERVED_10[40];
__IO uint32_t MAC_CSR_SW_CTRL; /**< CSR Software Control, offset: 0x230 */
__IO uint32_t MAC_FPE_CTRL_STS; /**< Frame Preemption Control, offset: 0x234 */
uint8_t RESERVED_11[8];
__I uint32_t MAC_PRESN_TIME_NS; /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
__IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC 1722 Presentation Time, offset: 0x244 */
uint8_t RESERVED_12[184];
struct { /* offset: 0x300, array step: 0x8 */
__IO uint32_t HIGH; /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
__IO uint32_t LOW; /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
} MAC_ADDRESS[64];
uint8_t RESERVED_13[512];
__IO uint32_t MAC_MMC_CONTROL; /**< MMC Control, offset: 0x700 */
__I uint32_t MAC_MMC_RX_INTERRUPT; /**< MMC Rx Interrupt, offset: 0x704 */
__I uint32_t MAC_MMC_TX_INTERRUPT; /**< MMC Tx Interrupt, offset: 0x708 */
__IO uint32_t MAC_MMC_RX_INTERRUPT_MASK; /**< MMC Rx Interrupt Mask, offset: 0x70C */
__IO uint32_t MAC_MMC_TX_INTERRUPT_MASK; /**< MMC Tx Interrupt Mask, offset: 0x710 */
__I uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD; /**< Tx Octet Count Good and Bad, offset: 0x714 */
__I uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD; /**< Tx Packet Count Good and Bad, offset: 0x718 */
__I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD; /**< Tx Broadcast Packets Good, offset: 0x71C */
__I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD; /**< Tx Multicast Packets Good, offset: 0x720 */
__I uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
__I uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
__I uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
__I uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
__I uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
__I uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
__I uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD; /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
__I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
__I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
__I uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS; /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
__I uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
__I uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
__I uint32_t MAC_TX_DEFERRED_PACKETS; /**< Deferred Packets Transmitted, offset: 0x754 */
__I uint32_t MAC_TX_LATE_COLLISION_PACKETS; /**< Late Collision Packets Transmitted, offset: 0x758 */
__I uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
__I uint32_t MAC_TX_CARRIER_ERROR_PACKETS; /**< Carrier Error Packets Transmitted, offset: 0x760 */
__I uint32_t MAC_TX_OCTET_COUNT_GOOD; /**< Bytes Transmitted in Good Packets, offset: 0x764 */
__I uint32_t MAC_TX_PACKET_COUNT_GOOD; /**< Good Packets Transmitted, offset: 0x768 */
__I uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR; /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
__I uint32_t MAC_TX_PAUSE_PACKETS; /**< Pause Packets Transmitted, offset: 0x770 */
__I uint32_t MAC_TX_VLAN_PACKETS_GOOD; /**< Good VLAN Packets Transmitted, offset: 0x774 */
__I uint32_t MAC_TX_OSIZE_PACKETS_GOOD; /**< Good Oversize Packets Transmitted, offset: 0x778 */
uint8_t RESERVED_14[4];
__I uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD; /**< Good and Bad Packets Received, offset: 0x780 */
__I uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD; /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
__I uint32_t MAC_RX_OCTET_COUNT_GOOD; /**< Bytes in Good Packets Received, offset: 0x788 */
__I uint32_t MAC_RX_BROADCAST_PACKETS_GOOD; /**< Good Broadcast Packets Received, offset: 0x78C */
__I uint32_t MAC_RX_MULTICAST_PACKETS_GOOD; /**< Good Multicast Packets Received, offset: 0x790 */
__I uint32_t MAC_RX_CRC_ERROR_PACKETS; /**< CRC Error Packets Received, offset: 0x794 */
__I uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS; /**< Alignment Error Packets Received, offset: 0x798 */
__I uint32_t MAC_RX_RUNT_ERROR_PACKETS; /**< Runt Error Packets Received, offset: 0x79C */
__I uint32_t MAC_RX_JABBER_ERROR_PACKETS; /**< Jabber Error Packets Received, offset: 0x7A0 */
__I uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD; /**< Good Undersize Packets Received, offset: 0x7A4 */
__I uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD; /**< Good Oversize Packets Received, offset: 0x7A8 */
__I uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
__I uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
__I uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
__I uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
__I uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
__I uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
__I uint32_t MAC_RX_UNICAST_PACKETS_GOOD; /**< Good Unicast Packets Received, offset: 0x7C4 */
__I uint32_t MAC_RX_LENGTH_ERROR_PACKETS; /**< Length Error Packets Received, offset: 0x7C8 */
__I uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS; /**< Out-of-range Type Packets Received, offset: 0x7CC */
__I uint32_t MAC_RX_PAUSE_PACKETS; /**< Pause Packets Received, offset: 0x7D0 */
__I uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS; /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
__I uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD; /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
__I uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS; /**< Watchdog Error Packets Received, offset: 0x7DC */
__I uint32_t MAC_RX_RECEIVE_ERROR_PACKETS; /**< Receive Error Packets Received, offset: 0x7E0 */
__I uint32_t MAC_RX_CONTROL_PACKETS_GOOD; /**< Good Control Packets Received, offset: 0x7E4 */
uint8_t RESERVED_15[4];
__I uint32_t MAC_TX_LPI_USEC_CNTR; /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
__I uint32_t MAC_TX_LPI_TRAN_CNTR; /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
__I uint32_t MAC_RX_LPI_USEC_CNTR; /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
__I uint32_t MAC_RX_LPI_TRAN_CNTR; /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
uint8_t RESERVED_16[4];
__IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK; /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
uint8_t RESERVED_17[4];
__I uint32_t MAC_MMC_IPC_RX_INTERRUPT; /**< MMC IPC Receive Interrupt, offset: 0x808 */
uint8_t RESERVED_18[4];
__I uint32_t MAC_RXIPV4_GOOD_PACKETS; /**< Good IPv4 Datagrams Received, offset: 0x810 */
__I uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS; /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
__I uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS; /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
__I uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS; /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
__I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
__I uint32_t MAC_RXIPV6_GOOD_PACKETS; /**< Good IPv6 Datagrams Received, offset: 0x824 */
__I uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS; /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
__I uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS; /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
__I uint32_t MAC_RXUDP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
__I uint32_t MAC_RXUDP_ERROR_PACKETS; /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
__I uint32_t MAC_RXTCP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
__I uint32_t MAC_RXTCP_ERROR_PACKETS; /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
__I uint32_t MAC_RXICMP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
__I uint32_t MAC_RXICMP_ERROR_PACKETS; /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
uint8_t RESERVED_19[8];
__I uint32_t MAC_RXIPV4_GOOD_OCTETS; /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
__I uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
__I uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
__I uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS; /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
__I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
__I uint32_t MAC_RXIPV6_GOOD_OCTETS; /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
__I uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
__I uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
__I uint32_t MAC_RXUDP_GOOD_OCTETS; /**< Bytes Received in Good UDP Segment, offset: 0x870 */
__I uint32_t MAC_RXUDP_ERROR_OCTETS; /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
__I uint32_t MAC_RXTCP_GOOD_OCTETS; /**< Bytes Received in Good TCP Segment, offset: 0x878 */
__I uint32_t MAC_RXTCP_ERROR_OCTETS; /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
__I uint32_t MAC_RXICMP_GOOD_OCTETS; /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
__I uint32_t MAC_RXICMP_ERROR_OCTETS; /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
uint8_t RESERVED_20[24];
__I uint32_t MAC_MMC_FPE_TX_INTERRUPT; /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
__IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK; /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
__I uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR; /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
__I uint32_t MAC_MMC_TX_HOLD_REQ_CNTR; /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
uint8_t RESERVED_21[16];
__I uint32_t MAC_MMC_FPE_RX_INTERRUPT; /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
__IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK; /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
__I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
__I uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR; /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
__I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
__I uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR; /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
uint8_t RESERVED_22[40];
__IO uint32_t MAC_L3_L4_CONTROL0; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
__IO uint32_t MAC_LAYER4_ADDRESS0; /**< Layer 4 Address 0, offset: 0x904 */
uint8_t RESERVED_23[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG0; /**< Layer 3 Address 0 Register 0, offset: 0x910 */
__IO uint32_t MAC_LAYER3_ADDR1_REG0; /**< Layer 3 Address 1 Register 0, offset: 0x914 */
__IO uint32_t MAC_LAYER3_ADDR2_REG0; /**< Layer 3 Address 2 Register 0, offset: 0x918 */
__IO uint32_t MAC_LAYER3_ADDR3_REG0; /**< Layer 3 Address 3 Register 0, offset: 0x91C */
uint8_t RESERVED_24[16];
__IO uint32_t MAC_L3_L4_CONTROL1; /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
__IO uint32_t MAC_LAYER4_ADDRESS1; /**< Layer 4 Address 0, offset: 0x934 */
uint8_t RESERVED_25[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG1; /**< Layer 3 Address 0 Register 1, offset: 0x940 */
__IO uint32_t MAC_LAYER3_ADDR1_REG1; /**< Layer 3 Address 1 Register 1, offset: 0x944 */
__IO uint32_t MAC_LAYER3_ADDR2_REG1; /**< Layer 3 Address 2 Register 1, offset: 0x948 */
__IO uint32_t MAC_LAYER3_ADDR3_REG1; /**< Layer 3 Address 3 Register 1, offset: 0x94C */
uint8_t RESERVED_26[16];
__IO uint32_t MAC_L3_L4_CONTROL2; /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
__IO uint32_t MAC_LAYER4_ADDRESS2; /**< Layer 4 Address 2, offset: 0x964 */
uint8_t RESERVED_27[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x970 */
__IO uint32_t MAC_LAYER3_ADDR1_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x974 */
__IO uint32_t MAC_LAYER3_ADDR2_REG2; /**< Layer 3 Address 2 Register 2, offset: 0x978 */
__IO uint32_t MAC_LAYER3_ADDR3_REG2; /**< Layer 3 Address 3 Register 2, offset: 0x97C */
uint8_t RESERVED_28[16];
__IO uint32_t MAC_L3_L4_CONTROL3; /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
__IO uint32_t MAC_LAYER4_ADDRESS3; /**< Layer 4 Address 3, offset: 0x994 */
uint8_t RESERVED_29[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG3; /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
__IO uint32_t MAC_LAYER3_ADDR1_REG3; /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
__IO uint32_t MAC_LAYER3_ADDR2_REG3; /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
__IO uint32_t MAC_LAYER3_ADDR3_REG3; /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
uint8_t RESERVED_30[16];
__IO uint32_t MAC_L3_L4_CONTROL4; /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
__IO uint32_t MAC_LAYER4_ADDRESS4; /**< Layer 4 Address 4, offset: 0x9C4 */
uint8_t RESERVED_31[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG4; /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
__IO uint32_t MAC_LAYER3_ADDR1_REG4; /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
__IO uint32_t MAC_LAYER3_ADDR2_REG4; /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
__IO uint32_t MAC_LAYER3_ADDR3_REG4; /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
uint8_t RESERVED_32[16];
__IO uint32_t MAC_L3_L4_CONTROL5; /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
__IO uint32_t MAC_LAYER4_ADDRESS5; /**< Layer 4 Address 5, offset: 0x9F4 */
uint8_t RESERVED_33[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG5; /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
__IO uint32_t MAC_LAYER3_ADDR1_REG5; /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
__IO uint32_t MAC_LAYER3_ADDR2_REG5; /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
__IO uint32_t MAC_LAYER3_ADDR3_REG5; /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
uint8_t RESERVED_34[16];
__IO uint32_t MAC_L3_L4_CONTROL6; /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
__IO uint32_t MAC_LAYER4_ADDRESS6; /**< Layer 4 Address 6, offset: 0xA24 */
uint8_t RESERVED_35[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG6; /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
__IO uint32_t MAC_LAYER3_ADDR1_REG6; /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
__IO uint32_t MAC_LAYER3_ADDR2_REG6; /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
__IO uint32_t MAC_LAYER3_ADDR3_REG6; /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
uint8_t RESERVED_36[16];
__IO uint32_t MAC_L3_L4_CONTROL7; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
__IO uint32_t MAC_LAYER4_ADDRESS7; /**< Layer 4 Address 7, offset: 0xA54 */
uint8_t RESERVED_37[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG7; /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
__IO uint32_t MAC_LAYER3_ADDR1_REG7; /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
__IO uint32_t MAC_LAYER3_ADDR2_REG7; /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
__IO uint32_t MAC_LAYER3_ADDR3_REG7; /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
uint8_t RESERVED_38[144];
__IO uint32_t MAC_TIMESTAMP_CONTROL; /**< Timestamp Control, offset: 0xB00 */
__IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< Subsecond Increment, offset: 0xB04 */
__I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< System Time Seconds, offset: 0xB08 */
__I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< System Time Nanoseconds, offset: 0xB0C */
__IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< System Time Seconds Update, offset: 0xB10 */
__IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
__IO uint32_t MAC_TIMESTAMP_ADDEND; /**< Timestamp Addend, offset: 0xB18 */
__IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
__I uint32_t MAC_TIMESTAMP_STATUS; /**< Timestamp Status, offset: 0xB20 */
uint8_t RESERVED_39[12];
__I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
__I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
uint8_t RESERVED_40[8];
__IO uint32_t MAC_AUXILIARY_CONTROL; /**< Auxiliary Timestamp Control, offset: 0xB40 */
uint8_t RESERVED_41[4];
__I uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
__I uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS; /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
__IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR; /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR; /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
__IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
__IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
__I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< Timestamp Ingress Latency, offset: 0xB68 */
__I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< Timestamp Egress Latency, offset: 0xB6C */
__IO uint32_t MAC_PPS_CONTROL; /**< PPS Control, offset: 0xB70 */
uint8_t RESERVED_42[12];
__IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS; /**< PPS0 Target Time Seconds, offset: 0xB80 */
__IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS; /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
__IO uint32_t MAC_PPS0_INTERVAL; /**< PPS0 Interval, offset: 0xB88 */
__IO uint32_t MAC_PPS0_WIDTH; /**< PPS0 Width, offset: 0xB8C */
__IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS; /**< PPS1 Target Time Seconds, offset: 0xB90 */
__IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS; /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
__IO uint32_t MAC_PPS1_INTERVAL; /**< PPS1 Interval, offset: 0xB98 */
__IO uint32_t MAC_PPS1_WIDTH; /**< PPS1 Width, offset: 0xB9C */
__IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS; /**< PPS2 Target Time Seconds, offset: 0xBA0 */
__IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS; /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
__IO uint32_t MAC_PPS2_INTERVAL; /**< PPS2 Interval, offset: 0xBA8 */
__IO uint32_t MAC_PPS2_WIDTH; /**< PPS2 Width, offset: 0xBAC */
__IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS; /**< PPS3 Target Time Seconds, offset: 0xBB0 */
__IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS; /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
__IO uint32_t MAC_PPS3_INTERVAL; /**< PPS3 Interval, offset: 0xBB8 */
__IO uint32_t MAC_PPS3_WIDTH; /**< PPS3 Width, offset: 0xBBC */
__IO uint32_t MAC_PTO_CONTROL; /**< PTP Offload Engine Control, offset: 0xBC0 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY0; /**< Source Port Identity 0, offset: 0xBC4 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY1; /**< Source Port Identity 1, offset: 0xBC8 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY2; /**< Source Port Identity 2, offset: 0xBCC */
__IO uint32_t MAC_LOG_MESSAGE_INTERVAL; /**< Log Message Interval, offset: 0xBD0 */
uint8_t RESERVED_43[44];
__IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */
uint8_t RESERVED_44[4];
__IO uint32_t MTL_DBG_CTL; /**< FIFO Debug Access Control and Status, offset: 0xC08 */
__IO uint32_t MTL_DBG_STS; /**< FIFO Debug Status, offset: 0xC0C */
__IO uint32_t MTL_FIFO_DEBUG_DATA; /**< FIFO Debug Data, offset: 0xC10 */
uint8_t RESERVED_45[12];
__I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */
uint8_t RESERVED_46[12];
__IO uint32_t MTL_RXQ_DMA_MAP0; /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
__IO uint32_t MTL_RXQ_DMA_MAP1; /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
uint8_t RESERVED_47[8];
__IO uint32_t MTL_TBS_CTRL; /**< Time Based Scheduling Control, offset: 0xC40 */
uint8_t RESERVED_48[12];
__IO uint32_t MTL_EST_CONTROL; /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
uint8_t RESERVED_49[4];
__IO uint32_t MTL_EST_STATUS; /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
uint8_t RESERVED_50[4];
__IO uint32_t MTL_EST_SCH_ERROR; /**< EST Scheduling Error, offset: 0xC60 */
__IO uint32_t MTL_EST_FRM_SIZE_ERROR; /**< EST Frame Size Error, offset: 0xC64 */
__I uint32_t MTL_EST_FRM_SIZE_CAPTURE; /**< EST Frame Size Capture, offset: 0xC68 */
uint8_t RESERVED_51[4];
__IO uint32_t MTL_EST_INTR_ENABLE; /**< EST Interrupt Enable, offset: 0xC70 */
uint8_t RESERVED_52[12];
__IO uint32_t MTL_EST_GCL_CONTROL; /**< EST GCL Control, offset: 0xC80 */
__IO uint32_t MTL_EST_GCL_DATA; /**< EST GCL Data, offset: 0xC84 */
uint8_t RESERVED_53[8];
__IO uint32_t MTL_FPE_CTRL_STS; /**< Frame Preemption Control and Status, offset: 0xC90 */
__IO uint32_t MTL_FPE_ADVANCE; /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
uint8_t RESERVED_54[8];
__IO uint32_t MTL_RXP_CONTROL_STATUS; /**< RXP Control Status, offset: 0xCA0 */
__IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS; /**< RXP Interrupt Control Status, offset: 0xCA4 */
__I uint32_t MTL_RXP_DROP_CNT; /**< RXP Drop Count, offset: 0xCA8 */
__I uint32_t MTL_RXP_ERROR_CNT; /**< RXP Error Count, offset: 0xCAC */
__IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
__IO uint32_t MTL_RXP_INDIRECT_ACC_DATA; /**< RXP Indirect Access Data, offset: 0xCB4 */
uint8_t RESERVED_55[72];
struct { /* offset: 0xD00, array step: 0x40 */
__IO uint32_t MTL_TXQX_OP_MODE; /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
__I uint32_t MTL_TXQX_UNDRFLW; /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
__I uint32_t MTL_TXQX_DBG; /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
uint8_t RESERVED_0[4];
__IO uint32_t MTL_TXQX_ETS_CTRL; /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40 */
__I uint32_t MTL_TXQX_ETS_STAT; /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
__IO uint32_t MTL_TXQX_QNTM_WGHT; /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
__IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40 */
__IO uint32_t MTL_TXQX_HI_CRDT; /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40 */
__IO uint32_t MTL_TXQX_LO_CRDT; /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40 */
uint8_t RESERVED_1[4];
__IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
__IO uint32_t MTL_RXQX_OP_MODE; /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
__I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
__I uint32_t MTL_RXQX_DBG; /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
__IO uint32_t MTL_RXQX_CTRL; /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
} MTL_QUEUE[5];
uint8_t RESERVED_56[448];
__IO uint32_t DMA_MODE; /**< DMA Bus Mode, offset: 0x1000 */
__IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */
__I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */
__I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */
__I uint32_t DMA_DEBUG_STATUS1; /**< DMA Debug Status 1, offset: 0x1010 */
uint8_t RESERVED_57[44];
__IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL; /**< AXI LPI Entry Interval Control, offset: 0x1040 */
uint8_t RESERVED_58[12];
__IO uint32_t DMA_TBS_CTRL; /**< TBS Control, offset: 0x1050 */
uint8_t RESERVED_59[172];
struct { /* offset: 0x1100, array step: 0x80 */
__IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
__IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
__IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
uint8_t RESERVED_0[8];
__IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
uint8_t RESERVED_1[4];
__IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
__IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
uint8_t RESERVED_2[4];
__IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
__IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
__IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
__IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
__IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
uint8_t RESERVED_3[4];
__I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
uint8_t RESERVED_4[4];
__I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
uint8_t RESERVED_5[4];
__I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
uint8_t RESERVED_6[4];
__I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
__I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
__I uint32_t DMA_CHX_RXP_ACCEPT_CNT; /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
__I uint32_t DMA_CHX_RX_ERI_CNT; /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
uint8_t RESERVED_7[16];
} DMA_CH[5];
} ENET_QOS_Type;
/* ----------------------------------------------------------------------------
-- ENET_QOS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
* @{
*/
/*! @name MAC_CONFIGURATION - MAC Configuration Register */
/*! @{ */
#define ENET_QOS_MAC_CONFIGURATION_RE_MASK (0x1U)
#define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT (0U)
/*! RE - Receiver Enable
* 0b0..Receiver is disabled
* 0b1..Receiver is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_TE_MASK (0x2U)
#define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT (1U)
/*! TE - Transmitter Enable
* 0b0..Transmitter is disabled
* 0b1..Transmitter is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU)
#define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U)
/*! PRELEN - Preamble Length for Transmit packets
* 0b10..3 bytes of preamble
* 0b01..5 bytes of preamble
* 0b00..7 bytes of preamble
* 0b11..Reserved
*/
#define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DC_MASK (0x10U)
#define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT (4U)
/*! DC - Deferral Check
* 0b0..Deferral check function is disabled
* 0b1..Deferral check function is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
#define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U)
#define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U)
/*! BL - Back-Off Limit
* 0b11..k = min(n,1)
* 0b00..k = min(n,10)
* 0b10..k = min(n,4)
* 0b01..k = min(n,8)
*/
#define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U)
#define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U)
/*! DR - Disable Retry
* 0b1..Disable Retry
* 0b0..Enable Retry
*/
#define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U)
#define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U)
/*! DCRS - Disable Carrier Sense During Transmission
* 0b1..Disable Carrier Sense During Transmission
* 0b0..Enable Carrier Sense During Transmission
*/
#define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U)
#define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U)
/*! DO - Disable Receive Own
* 0b1..Disable Receive Own
* 0b0..Enable Receive Own
*/
#define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK (0x800U)
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT (11U)
/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
* 0b0..ECRSFD is disabled
* 0b1..ECRSFD is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_LM_MASK (0x1000U)
#define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT (12U)
/*! LM - Loopback Mode
* 0b0..Loopback is disabled
* 0b1..Loopback is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U)
#define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U)
/*! DM - Duplex Mode
* 0b1..Full-duplex mode
* 0b0..Half-duplex mode
*/
#define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
#define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U)
#define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U)
/*! FES - Speed
* 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
* 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
*/
#define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
#define ENET_QOS_MAC_CONFIGURATION_PS_MASK (0x8000U)
#define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT (15U)
/*! PS - Port Select
* 0b0..For 1000 or 2500 Mbps operations
* 0b1..For 10 or 100 Mbps operations
*/
#define ENET_QOS_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_JE_MASK (0x10000U)
#define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT (16U)
/*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
* (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
* status.
* 0b0..Jumbo packet is disabled
* 0b1..Jumbo packet is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U)
#define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U)
/*! JD - Jabber Disable
* 0b1..Jabber is disabled
* 0b0..Jabber is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_BE_MASK (0x40000U)
#define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT (18U)
/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
* transmission in the GMII half-duplex mode.
* 0b0..Packet Burst is disabled
* 0b1..Packet Burst is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U)
#define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U)
/*! WD - Watchdog Disable
* 0b1..Watchdog is disabled
* 0b0..Watchdog is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_ACS_MASK (0x100000U)
#define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT (20U)
/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
* on the incoming packets only if the value of the length field is less than 1,536 bytes.
* 0b0..Automatic Pad or CRC Stripping is disabled
* 0b1..Automatic Pad or CRC Stripping is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_CST_MASK (0x200000U)
#define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT (21U)
/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
* packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
* the packet to the application.
* 0b0..CRC stripping for Type packets is disabled
* 0b1..CRC stripping for Type packets is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
#define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK (0x400000U)
#define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT (22U)
/*! S2KP - IEEE 802.
* 0b0..Support upto 2K packet is disabled
* 0b1..Support upto 2K packet is Enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U)
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT (23U)
/*! GPSLCE - Giant Packet Size Limit Control Enable
* 0b0..Giant Packet Size Limit Control is disabled
* 0b1..Giant Packet Size Limit Control is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U)
#define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U)
/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
* 0b111..40 bit times IPG
* 0b110..48 bit times IPG
* 0b101..56 bit times IPG
* 0b100..64 bit times IPG
* 0b011..72 bit times IPG
* 0b010..80 bit times IPG
* 0b001..88 bit times IPG
* 0b000..96 bit times IPG
*/
#define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
#define ENET_QOS_MAC_CONFIGURATION_IPC_MASK (0x8000000U)
#define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT (27U)
/*! IPC - Checksum Offload
* 0b0..IP header/payload checksum checking is disabled
* 0b1..IP header/payload checksum checking is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
#define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U)
#define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U)
/*! SARC - Source Address Insertion or Replacement Control
* 0b010..Contents of MAC Addr-0 inserted in SA field
* 0b011..Contents of MAC Addr-0 replaces SA field
* 0b110..Contents of MAC Addr-1 inserted in SA field
* 0b111..Contents of MAC Addr-1 replaces SA field
* 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
*/
#define ENET_QOS_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
/*! @} */
/*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
/*! @{ */
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
/*! GPSL - Giant Packet Size Limit
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
/*! DCRCC - Disable CRC Checking for Received Packets
* 0b1..CRC Checking is disabled
* 0b0..CRC Checking is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
/*! SPEN - Slow Protocol Detection Enable
* 0b0..Slow Protocol Detection is disabled
* 0b1..Slow Protocol Detection is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
/*! USP - Unicast Slow Protocol Packet Detect
* 0b0..Unicast Slow Protocol Packet Detection is disabled
* 0b1..Unicast Slow Protocol Packet Detection is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
/*! PDC - Packet Duplication Control
* 0b0..Packet Duplication Control is disabled
* 0b1..Packet Duplication Control is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
/*! EIPGEN - Extended Inter-Packet Gap Enable
* 0b0..Extended Inter-Packet Gap is disabled
* 0b1..Extended Inter-Packet Gap is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
/*! EIPG - Extended Inter-Packet Gap
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
/*! @} */
/*! @name MAC_PACKET_FILTER - MAC Packet Filter */
/*! @{ */
#define ENET_QOS_MAC_PACKET_FILTER_PR_MASK (0x1U)
#define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT (0U)
/*! PR - Promiscuous Mode
* 0b0..Promiscuous Mode is disabled
* 0b1..Promiscuous Mode is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK (0x2U)
#define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT (1U)
/*! HUC - Hash Unicast
* 0b0..Hash Unicast is disabled
* 0b1..Hash Unicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK (0x4U)
#define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT (2U)
/*! HMC - Hash Multicast
* 0b0..Hash Multicast is disabled
* 0b1..Hash Multicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK (0x8U)
#define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT (3U)
/*! DAIF - DA Inverse Filtering
* 0b0..DA Inverse Filtering is disabled
* 0b1..DA Inverse Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_PM_MASK (0x10U)
#define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT (4U)
/*! PM - Pass All Multicast
* 0b0..Pass All Multicast is disabled
* 0b1..Pass All Multicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U)
#define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U)
/*! DBF - Disable Broadcast Packets
* 0b1..Disable Broadcast Packets
* 0b0..Enable Broadcast Packets
*/
#define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK (0xC0U)
#define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT (6U)
/*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
* unicast and multicast Pause packets).
* 0b00..MAC filters all control packets from reaching the application
* 0b10..MAC forwards all control packets to the application even if they fail the Address filter
* 0b11..MAC forwards the control packets that pass the Address filter
* 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
*/
#define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK (0x100U)
#define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT (8U)
/*! SAIF - SA Inverse Filtering
* 0b0..SA Inverse Filtering is disabled
* 0b1..SA Inverse Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK (0x200U)
#define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT (9U)
/*! SAF - Source Address Filter Enable
* 0b0..SA Filtering is disabled
* 0b1..SA Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK (0x400U)
#define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT (10U)
/*! HPF - Hash or Perfect Filter
* 0b0..Hash or Perfect Filter is disabled
* 0b1..Hash or Perfect Filter is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK (0x10000U)
#define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT (16U)
/*! VTFE - VLAN Tag Filter Enable
* 0b0..VLAN Tag Filter is disabled
* 0b1..VLAN Tag Filter is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK (0x100000U)
#define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT (20U)
/*! IPFE - Layer 3 and Layer 4 Filter Enable
* 0b0..Layer 3 and Layer 4 Filters are disabled
* 0b1..Layer 3 and Layer 4 Filters are enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U)
#define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U)
/*! DNTU - Drop Non-TCP/UDP over IP Packets
* 0b1..Drop Non-TCP/UDP over IP Packets
* 0b0..Forward Non-TCP/UDP over IP Packets
*/
#define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_RA_MASK (0x80000000U)
#define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT (31U)
/*! RA - Receive All
* 0b0..Receive All is disabled
* 0b1..Receive All is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
/*! @} */
/*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
/*! @{ */
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U)
/*! WTO - Watchdog Timeout
* 0b1000..10 KB
* 0b1001..11 KB
* 0b1010..12 KB
* 0b1011..13 KB
* 0b1100..14 KB
* 0b1101..15 KB
* 0b1110..16383 Bytes
* 0b0000..2 KB
* 0b0001..3 KB
* 0b0010..4 KB
* 0b0011..5 KB
* 0b0100..6 KB
* 0b0101..7 KB
* 0b0110..8 KB
* 0b0111..9 KB
* 0b1111..Reserved
*/
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U)
/*! PWE - Programmable Watchdog Enable
* 0b0..Programmable Watchdog is disabled
* 0b1..Programmable Watchdog is enabled
*/
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
/*! @} */
/*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
/*! @{ */
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
/*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table.
*/
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
/*! @} */
/*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
/*! @{ */
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
/*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table.
*/
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
/*! @} */
/*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
/*! @{ */
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U)
/*! OB - Operation Busy
* 0b0..Operation Busy is disabled
* 0b1..Operation Busy is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U)
/*! CT - Command Type
* 0b1..Read operation
* 0b0..Write operation
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK (0x7CU)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U)
/*! OFS - Offset
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U)
/*! VTIM - VLAN Tag Inverse Match Enable
* 0b0..VLAN Tag Inverse Match is disabled
* 0b1..VLAN Tag Inverse Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U)
/*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
* packets (Type = 0x88A8) as valid VLAN tagged packets.
* 0b0..S-VLAN is disabled
* 0b1..S-VLAN is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U)
/*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
* outer VLAN Tag in received packet.
* 0b11..Always strip
* 0b00..Do not strip
* 0b10..Strip if VLAN filter fails
* 0b01..Strip if VLAN filter passes
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U)
/*! EVLRXS - Enable VLAN Tag in Rx status
* 0b0..VLAN Tag in Rx status is disabled
* 0b1..VLAN Tag in Rx status is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U)
/*! VTHM - VLAN Tag Hash Table Match Enable
* 0b0..VLAN Tag Hash Table Match is disabled
* 0b1..VLAN Tag Hash Table Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U)
/*! EDVLP - Enable Double VLAN Processing
* 0b0..Double VLAN Processing is disabled
* 0b1..Double VLAN Processing is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U)
/*! ERIVLT - ERIVLT
* 0b0..Inner VLAN tag is disabled
* 0b1..Inner VLAN tag is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U)
/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
* on inner VLAN Tag in received packet.
* 0b11..Always strip
* 0b00..Do not strip
* 0b10..Strip if VLAN filter fails
* 0b01..Strip if VLAN filter passes
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
* 0b0..Inner VLAN Tag in Rx status is disabled
* 0b1..Inner VLAN Tag in Rx status is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
/*! @} */
/*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
/*! @{ */
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT (0U)
/*! VID - VLAN Tag ID
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U)
/*! VEN - VLAN Tag Enable
* 0b0..VLAN Tag is disabled
* 0b1..VLAN Tag is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U)
/*! ETV - 12bits or 16bits VLAN comparison
* 0b1..12 bit VLAN comparison
* 0b0..16 bit VLAN comparison
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U)
/*! DOVLTC - Disable VLAN Type Comparison
* 0b1..VLAN type comparison is disabled
* 0b0..VLAN type comparison is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U)
/*! ERSVLM - Enable S-VLAN Match for received Frames
* 0b0..Receive S-VLAN Match is disabled
* 0b1..Receive S-VLAN Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U)
/*! ERIVLT - Enable Inner VLAN Tag Comparison
* 0b0..Inner VLAN tag comparison is disabled
* 0b1..Inner VLAN tag comparison is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
/*! DMACHEN - DMA Channel Number Enable
* 0b0..DMA Channel Number is disabled
* 0b1..DMA Channel Number is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK (0xE000000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U)
/*! DMACHN - DMA Channel Number
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
/*! @} */
/*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
/*! @{ */
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U)
/*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table.
*/
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
/*! @} */
/*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
/*! @{ */
#define ENET_QOS_MAC_VLAN_INCL_VLT_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT (0U)
/*! VLT - VLAN Tag for Transmit Packets
*/
#define ENET_QOS_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLC_MASK (0x30000U)
#define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT (16U)
/*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
* replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
* (bytes 15 and 16) of all transmitted packets with VLAN tags.
* 0b01..VLAN tag deletion
* 0b10..VLAN tag insertion
* 0b00..No VLAN tag deletion, insertion, or replacement
* 0b11..VLAN tag replacement
*/
#define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLP_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT (18U)
/*! VLP - VLAN Priority Control
* 0b0..VLAN Priority Control is disabled
* 0b1..VLAN Priority Control is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
#define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK (0x80000U)
#define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT (19U)
/*! CSVL - C-VLAN or S-VLAN
* 0b0..C-VLAN type (0x8100) is inserted or replaced
* 0b1..S-VLAN type (0x88A8) is inserted or replaced
*/
#define ENET_QOS_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK (0x100000U)
#define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT (20U)
/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
* replaced in Tx packet should be taken from: - The Tx descriptor
* 0b0..VLAN Tag Input is disabled
* 0b1..VLAN Tag Input is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
#define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK (0x200000U)
#define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT (21U)
/*! CBTI - Channel based tag insertion
* 0b0..Channel based tag insertion is disabled
* 0b1..Channel based tag insertion is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
#define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK (0x7000000U)
#define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT (24U)
/*! ADDR - Address
*/
#define ENET_QOS_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
#define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK (0x40000000U)
#define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT (30U)
/*! RDWR - Read write control
* 0b0..Read operation of indirect access
* 0b1..Write operation of indirect access
*/
#define ENET_QOS_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
#define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U)
#define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U)
/*! BUSY - Busy
* 0b1..Busy status detected
* 0b0..Busy status not detected
*/
#define ENET_QOS_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
/*! @} */
/*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
/*! @{ */
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U)
/*! VLT - VLAN Tag for Transmit Packets
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U)
/*! VLC - VLAN Tag Control in Transmit Packets
* 0b01..VLAN tag deletion
* 0b10..VLAN tag insertion
* 0b00..No VLAN tag deletion, insertion, or replacement
* 0b11..VLAN tag replacement
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U)
/*! VLP - VLAN Priority Control
* 0b0..VLAN Priority Control is disabled
* 0b1..VLAN Priority Control is enabled
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U)
/*! CSVL - C-VLAN or S-VLAN
* 0b0..C-VLAN type (0x8100) is inserted
* 0b1..S-VLAN type (0x88A8) is inserted
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U)
/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
* replaced in Tx packet should be taken from: - The Tx descriptor
* 0b0..VLAN Tag Input is disabled
* 0b1..VLAN Tag Input is enabled
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
/*! @} */
/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
/*! @{ */
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
/*! FCB_BPA - Flow Control Busy or Backpressure Activate
* 0b0..Flow Control Busy or Backpressure Activate is disabled
* 0b1..Flow Control Busy or Backpressure Activate is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
/*! TFE - Transmit Flow Control Enable
* 0b0..Transmit Flow Control is disabled
* 0b1..Transmit Flow Control is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
/*! PLT - Pause Low Threshold
* 0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
* 0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
* 0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
* 0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
* 0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
* 0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
* 0b110..Reserved
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
/*! DZPQ - Disable Zero-Quanta Pause
* 0b1..Zero-Quanta Pause packet generation is disabled
* 0b0..Zero-Quanta Pause packet generation is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
/*! PT - Pause Time
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT (5U)
/*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
/*! @{ */
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
/*! RFE - Receive Flow Control Enable
* 0b0..Receive Flow Control is disabled
* 0b1..Receive Flow Control is enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
/*! UP - Unicast Pause Packet Detect
* 0b0..Unicast Pause Packet Detect disabled
* 0b1..Unicast Pause Packet Detect enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK (0x100U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT (8U)
/*! PFCE - Priority Based Flow Control Enable
* 0b0..Priority Based Flow Control is disabled
* 0b1..Priority Based Flow Control is enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
/*! @} */
/*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
/*! @{ */
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U)
/*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
* 0b0..Unicast Address Filter Fail Packets Queuing is disabled
* 0b1..Unicast Address Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK (0xEU)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U)
/*! UFFQ - Unicast Address Filter Fail Packets Queue.
*/
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U)
/*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
* 0b0..Multicast Address Filter Fail Packets Queuing is disabled
* 0b1..Multicast Address Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK (0xE00U)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U)
/*! MFFQ - Multicast Address Filter Fail Packets Queue.
*/
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U)
/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
* 0b0..VLAN tag Filter Fail Packets Queuing is disabled
* 0b1..VLAN tag Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK (0xE0000U)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U)
/*! VFFQ - VLAN Tag Filter Fail Packets Queue
*/
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
/*! @} */
/*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
/*! @{ */
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK (0xFFU)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT (0U)
/*! PSTQ0 - Priorities Selected in Transmit Queue 0
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK (0xFF00U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT (8U)
/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK (0xFF0000U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT (16U)
/*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK (0xFF000000U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT (24U)
/*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
/*! @} */
/*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
/*! @{ */
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK (0xFFU)
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT (0U)
/*! PSTQ4 - Priorities Selected in Transmit Queue 4
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
/*! @} */
/*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
/*! @{ */
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
/*! AVCPQ - AV Untagged Control Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
/*! PSRQ0 - Priorities Selected in the Receive Queue 0
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK (0xFFU)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT (0U)
/*! PSRQ4 - Priorities Selected in the Receive Queue 4
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
/*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
/*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK (0x70U)
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT (4U)
/*! PTPQ - PTP Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK (0x30U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT (4U)
/*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK (0xC0U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT (6U)
/*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK (0x700U)
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT (8U)
/*! DCBCPQ - DCB Control Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
/*! PSRQ1 - Priorities Selected in the Receive Queue 1
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK (0x300U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT (8U)
/*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
#define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
/*! UPQ - Untagged Packet Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
/*! MCBCQ - Multicast and Broadcast Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
/*! PSRQ2 - Priorities Selected in the Receive Queue 2
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
/*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
* packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
* to Rx Queue specified in MCBCQ field.
* 0b0..Multicast and Broadcast Queue is disabled
* 0b1..Multicast and Broadcast Queue is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U)
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT (21U)
/*! TACPQE - Tagged AV Control Packets Queuing Enable.
* 0b0..Tagged AV Control Packets Queuing is disabled
* 0b1..Tagged AV Control Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U)
#define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT (22U)
/*! TPQC - Tagged PTP over Ethernet Packets Queuing Control.
*/
#define ENET_QOS_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U)
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT (24U)
/*! FPRQ - Frame Preemption Residue Queue
*/
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
/*! PSRQ3 - Priorities Selected in the Receive Queue 3
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_RXQ_CTRL */
#define ENET_QOS_MAC_RXQ_CTRL_COUNT (4U)
/*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
/*! @{ */
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
/*! RGSMIIIS - RGMII or SMII Interrupt Status
* 0b1..RGMII or SMII Interrupt Status is active
* 0b0..RGMII or SMII Interrupt Status is not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
/*! PHYIS - PHY Interrupt
* 0b1..PHY Interrupt detected
* 0b0..PHY Interrupt not detected
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
/*! PMTIS - PMT Interrupt Status
* 0b1..PMT Interrupt status active
* 0b0..PMT Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
/*! LPIIS - LPI Interrupt Status
* 0b1..LPI Interrupt status active
* 0b0..LPI Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
/*! MMCIS - MMC Interrupt Status
* 0b1..MMC Interrupt status active
* 0b0..MMC Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
/*! MMCRXIS - MMC Receive Interrupt Status
* 0b1..MMC Receive Interrupt status active
* 0b0..MMC Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
/*! MMCTXIS - MMC Transmit Interrupt Status
* 0b1..MMC Transmit Interrupt status active
* 0b0..MMC Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
* 0b1..MMC Receive Checksum Offload Interrupt status active
* 0b0..MMC Receive Checksum Offload Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
/*! TSIS - Timestamp Interrupt Status
* 0b1..Timestamp Interrupt status active
* 0b0..Timestamp Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
/*! TXSTSIS - Transmit Status Interrupt
* 0b1..Transmit Interrupt status active
* 0b0..Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
/*! RXSTSIS - Receive Status Interrupt
* 0b1..Receive Interrupt status active
* 0b0..Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
/*! FPEIS - Frame Preemption Interrupt Status
* 0b1..Frame Preemption Interrupt status active
* 0b0..Frame Preemption Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
/*! MDIOIS - MDIO Interrupt Status
* 0b1..MDIO Interrupt status active
* 0b0..MDIO Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
/*! MFTIS - MMC FPE Transmit Interrupt Status
* 0b1..MMC FPE Transmit Interrupt status active
* 0b0..MMC FPE Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
/*! MFRIS - MMC FPE Receive Interrupt Status
* 0b1..MMC FPE Receive Interrupt status active
* 0b0..MMC FPE Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
/*! @} */
/*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
/*! @{ */
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
/*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
* 0b0..RGMII or SMII Interrupt is disabled
* 0b1..RGMII or SMII Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
/*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
* 0b0..PHY Interrupt is disabled
* 0b1..PHY Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
/*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
* 0b0..PMT Interrupt is disabled
* 0b1..PMT Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
/*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
* 0b0..LPI Interrupt is disabled
* 0b1..LPI Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
/*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
* 0b0..Timestamp Interrupt is disabled
* 0b1..Timestamp Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
/*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
* 0b0..Timestamp Status Interrupt is disabled
* 0b1..Timestamp Status Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
/*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
* 0b0..Receive Status Interrupt is disabled
* 0b1..Receive Status Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
/*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
* 0b0..Frame Preemption Interrupt is disabled
* 0b1..Frame Preemption Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
/*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
* 0b0..MDIO Interrupt is disabled
* 0b1..MDIO Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
/*! @} */
/*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
/*! @{ */
#define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK (0x1U)
#define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT (0U)
/*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
* happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
* and JD bit is reset in the MAC_CONFIGURATION register.
* 0b1..Transmit Jabber Timeout occurred
* 0b0..No Transmit Jabber Timeout
*/
#define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK (0x2U)
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U)
/*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
* 0b1..No carrier
* 0b0..Carrier is present
*/
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK (0x4U)
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT (2U)
/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
* signal was inactive for one or more transmission clock periods during packet transmission.
* 0b1..Loss of carrier
* 0b0..Carrier is present
*/
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U)
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U)
/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
* DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
* ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
* when Jumbo packet is enabled).
* 0b1..Excessive deferral
* 0b0..No Excessive deferral
*/
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK (0x10U)
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT (4U)
/*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the packet transmission aborted because a collision occurred after the collision
* window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
* Extension in GMII mode).
* 0b1..Late collision is sensed
* 0b0..No collision
*/
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U)
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U)
/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
* bit indicates that the transmission aborted after 16 successive collisions while attempting
* to transmit the current packet.
* 0b1..Excessive collision is sensed
* 0b0..No collision
*/
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK (0x100U)
#define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT (8U)
/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
* bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
* MAC_CONFIGURATION register.
* 0b1..Receive watchdog timed out
* 0b0..No receive watchdog timeout
*/
#define ENET_QOS_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
/*! @} */
/*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
/*! @{ */
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
/*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
* receives the expected magic packet or remote wake-up packet.
* 0b0..Power down is disabled
* 0b1..Power down is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
/*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
* 0b0..Magic Packet is disabled
* 0b1..Magic Packet is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
* generated when the MAC receives a remote wake-up packet.
* 0b0..Remote wake-up packet is disabled
* 0b1..Remote wake-up packet is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
/*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
* event is generated because of the reception of a magic packet.
* 0b1..Magic packet is received
* 0b0..No Magic packet is received
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
/*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
* management event is generated because of the reception of a remote wake-up packet.
* 0b1..Remote wake-up packet is received
* 0b0..Remote wake-up packet is received
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
* address recognition is detected as a remote wake-up packet.
* 0b0..Global unicast is disabled
* 0b1..Global unicast is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
* MAC receiver drops all received frames until it receives the expected Wake-up frame.
* 0b0..Remote Wake-up Packet Forwarding is disabled
* 0b1..Remote Wake-up Packet Forwarding is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
* 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
* register pointer.
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
* remote wake-up packet filter register pointer is reset to 3'b000.
* 0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
* 0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
/*! @} */
/*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
/*! @{ */
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
/*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter.
*/
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
/*! @} */
/*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
/*! @{ */
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
* entered the LPI state because of the setting of the LPIEN bit.
* 0b1..Transmit LPI entry detected
* 0b0..Transmit LPI entry not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
* the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
* 0b1..Transmit LPI exit detected
* 0b0..Transmit LPI exit not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
* an LPI pattern and entered the LPI state.
* 0b1..Receive LPI entry detected
* 0b0..Receive LPI entry not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
* receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
* normal reception.
* 0b1..Receive LPI exit detected
* 0b0..Receive LPI exit not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
* LPI pattern on the GMII or MII interface.
* 0b1..Transmit LPI state detected
* 0b0..Transmit LPI state not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
* pattern on the GMII or MII interface.
* 0b1..Receive LPI state detected
* 0b0..Receive LPI state not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
* 0b0..LPI state is disabled
* 0b1..LPI state is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
* 0b0..link is down
* 0b1..link is okay (UP)
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
/*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
* SMII Receive paths to be used for activating the LPI LS TIMER.
* 0b0..PHY Link Status is disabled
* 0b1..PHY Link Status is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
* out of the LPI mode on the Transmit side.
* 0b0..LPI Tx Automate is disabled
* 0b1..LPI Tx Automate is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
* 0b0..LPI Timer is disabled
* 0b1..LPI Timer is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
* sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
* 0b0..LPI Tx Clock Stop is disabled
* 0b1..LPI Tx Clock Stop is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
/*! @} */
/*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
/*! @{ */
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
* waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
* transmission.
*/
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
* status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
*/
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
/*! @} */
/*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
/*! @{ */
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U)
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
* mode, after it has transmitted all the frames.
*/
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
/*! @} */
/*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
/*! @{ */
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
*/
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
/*! @} */
/*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
/*! @{ */
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
/*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
* of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
* SGMII port.
* 0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
* 0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
/*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
* configuration in the RGMII, SGMII, or SMII interface.
* 0b0..Link down
* 0b1..Link up
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
/*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
* 0b1..Full-duplex mode
* 0b0..Half-duplex mode
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
/*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
* 0b10..125 MHz
* 0b00..2.5 MHz
* 0b01..25 MHz
* 0b11..Reserved
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
/*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
* 0b1..Link up
* 0b0..Link down
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
/*! @} */
/*! @name MAC_VERSION - MAC Version */
/*! @{ */
#define ENET_QOS_MAC_VERSION_SNPSVER_MASK (0xFFU)
#define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT (0U)
/*! SNPSVER - Synopsys-defined Version
*/
#define ENET_QOS_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
#define ENET_QOS_MAC_VERSION_USERVER_MASK (0xFF00U)
#define ENET_QOS_MAC_VERSION_USERVER_SHIFT (8U)
/*! USERVER - User-defined Version (8'h10)
*/
#define ENET_QOS_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
/*! @} */
/*! @name MAC_DEBUG - MAC Debug */
/*! @{ */
#define ENET_QOS_MAC_DEBUG_RPESTS_MASK (0x1U)
#define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U)
/*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
* the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
* Idle state.
* 0b1..MAC GMII or MII Receive Protocol Engine Status detected
* 0b0..MAC GMII or MII Receive Protocol Engine Status not detected
*/
#define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
#define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK (0x6U)
#define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT (1U)
/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
* the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
* Controller module.
*/
#define ENET_QOS_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
#define ENET_QOS_MAC_DEBUG_TPESTS_MASK (0x10000U)
#define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT (16U)
/*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
* the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
* the Idle state.
* 0b1..MAC GMII or MII Transmit Protocol Engine Status detected
* 0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
*/
#define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
#define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U)
#define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U)
/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
* 0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
* 0b00..Idle state
* 0b11..Transferring input packet for transmission
* 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
*/
#define ENET_QOS_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
/*! @} */
/*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
/*! @{ */
#define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U)
#define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U)
/*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
* 0b1..10 or 100 Mbps support
* 0b0..No 10 or 100 Mbps support
*/
#define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U)
#define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U)
/*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
* 0b011..16 Extended Rx VLAN Filters
* 0b100..24 Extended Rx VLAN Filters
* 0b101..32 Extended Rx VLAN Filters
* 0b001..4 Extended Rx VLAN Filters
* 0b010..8 Extended Rx VLAN Filters
* 0b000..No Extended Rx VLAN Filters
* 0b110..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
/*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
* bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
* 0b00011..1024 bytes
* 0b00000..128 bytes
* 0b01010..128 KB
* 0b00111..16384 bytes
* 0b00100..2048 bytes
* 0b00001..256 bytes
* 0b01011..256 KB
* 0b01000..32 KB
* 0b00101..4096 bytes
* 0b00010..512 bytes
* 0b01001..64 KB
* 0b00110..8192 bytes
* 0b01100..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
#define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
/*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
* 0b0000..1 MTL Rx Queue
* 0b0001..2 MTL Rx Queues
* 0b0010..3 MTL Rx Queues
* 0b0011..4 MTL Rx Queues
* 0b0100..5 MTL Rx Queues
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U)
#define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U)
/*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
* 0b1..1000 Mbps support
* 0b0..No 1000 Mbps support
*/
#define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U)
#define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U)
/*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
* 0b1..Half-duplex support
* 0b0..No Half-duplex support
*/
#define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK (0x8U)
#define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U)
/*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
* SGMII, or RTBI PHY interface option is selected
* 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
* 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
*/
#define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK (0x10U)
#define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U)
/*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
* Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
* 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
* 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U)
#define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U)
/*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
* 0b1..VLAN Hash Filter selected
* 0b0..VLAN Hash Filter not selected
*/
#define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
#define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U)
/*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
* 0b1..Double VLAN option is selected
* 0b0..Double VLAN option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
#define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U)
/*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
* 0b1..SMA (MDIO) Interface selected
* 0b0..SMA (MDIO) Interface not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U)
/*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
* 0b1..Single Port RAM feature is selected
* 0b0..Single Port RAM feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
#define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
#define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
/*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
* 0b1..PMT Remote Wake-up Packet Enable option is selected
* 0b0..PMT Remote Wake-up Packet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
/*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
* bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
* 0b00011..1024 bytes
* 0b00000..128 bytes
* 0b01010..128 KB
* 0b00111..16384 bytes
* 0b00100..2048 bytes
* 0b00001..256 bytes
* 0b01000..32 KB
* 0b00101..4096 bytes
* 0b00010..512 bytes
* 0b01001..64 KB
* 0b00110..8192 bytes
* 0b01011..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
#define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
/*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
* 0b0000..1 MTL Tx Queue
* 0b0001..2 MTL Tx Queues
* 0b0010..3 MTL Tx Queues
* 0b0011..4 MTL Tx Queues
* 0b0100..5 MTL Tx Queues
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
#define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
/*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
* 0b1..PMT Magic Packet Enable option is selected
* 0b0..PMT Magic Packet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
#define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
/*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
* 0b1..RMON Module Enable option is selected
* 0b0..RMON Module Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
/*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
* 0b1..ARP Offload Enable option is selected
* 0b0..ARP Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK (0x200U)
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U)
/*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
* Broadcast/Multicast Packet Duplication feature is selected.
* 0b1..Broadcast/Multicast Packet Duplication feature is selected
* 0b0..Broadcast/Multicast Packet Duplication feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK (0x400U)
#define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U)
/*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
* Programmable Receive Parser option is selected.
* 0b1..Flexible Receive Parser feature is selected
* 0b0..Flexible Receive Parser feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK (0x1800U)
#define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U)
/*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
* bytes of the packet data to be Parsed by Flexible Receive Parser.
* 0b01..128 Bytes
* 0b10..256 Bytes
* 0b00..64 Bytes
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
#define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U)
#define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U)
/*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
* 0b1..One-Step Timestamping feature is selected
* 0b0..One-Step Timestamping feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
#define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U)
/*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
* 0b1..PTP Offload feature is selected
* 0b0..PTP Offload feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
/*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
* 0b0000..1 MTL Rx Channel
* 0b0001..2 MTL Rx Channels
* 0b0010..3 MTL Rx Channels
* 0b0011..4 MTL Rx Channels
* 0b0100..5 MTL Rx Channels
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
#define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U)
/*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
* 0b1..IEEE 1588-2008 Timestamp Enable option is selected
* 0b0..IEEE 1588-2008 Timestamp Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
/*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
* 0b1..IEEE 1588 High Word Register option is selected
* 0b0..IEEE 1588 High Word Register option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
#define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
#define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U)
/*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
* Ethernet (EEE) option is selected
* 0b1..Energy Efficient Ethernet Enable option is selected
* 0b0..Energy Efficient Ethernet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPES_MASK (0x6000U)
#define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U)
/*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
* Entries supported by Flexible Receive Parser.
* 0b01..128 Entries
* 0b10..256 Entries
* 0b00..64 Entries
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
#define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT (14U)
/*! ADDR64 - Address Width.
* 0b00..32
* 0b01..40
* 0b10..48
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
/*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
* TCP/IP Checksum Insertion option is selected
* 0b1..Transmit Checksum Offload Enable option is selected
* 0b0..Transmit Checksum Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U)
/*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
* 0b1..DCB Feature is selected
* 0b0..DCB Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U)
/*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
* Enhancements to Scheduling Traffic feature is selected.
* 0b1..Enable Enhancements to Scheduling Traffic feature is selected
* 0b0..Enable Enhancements to Scheduling Traffic feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
/*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
* 0b1..Receive Checksum Offload Enable option is selected
* 0b0..Receive Checksum Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U)
#define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U)
/*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
* 0b101..1024
* 0b010..128
* 0b011..256
* 0b100..512
* 0b001..64
* 0b000..No Depth configured
* 0b110..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
#define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U)
#define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U)
/*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
* 0b1..Split Header Feature is selected
* 0b0..Split Header Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U)
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U)
/*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
* selected for Enable Additional 1-31 MAC Address Registers option
*/
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
#define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U)
/*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
* Offloading for TCP/IP Packets option is selected
* 0b1..TCP Segmentation Offload Feature is selected
* 0b0..TCP Segmentation Offload Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
/*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
* 0b0000..1 MTL Tx Channel
* 0b0001..2 MTL Tx Channels
* 0b0010..3 MTL Tx Channels
* 0b0011..4 MTL Tx Channels
* 0b0100..5 MTL Tx Channels
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
/*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
* 0b1..DMA Debug Registers option is selected
* 0b0..DMA Debug Registers option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
#define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
#define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U)
/*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
* 0b1..AV Feature is selected
* 0b0..AV Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK (0x300000U)
#define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT (20U)
/*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
* width of the Configured Time Interval Field
* 0b00..Width not configured
* 0b01..16
* 0b10..20
* 0b11..24
*/
#define ENET_QOS_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
#define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK (0x200000U)
#define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U)
/*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
* Bridging option on Rx Side Only is selected.
* 0b1..Rx Side Only AV Feature is selected
* 0b0..Rx Side Only AV Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U)
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U)
/*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
* MAC Address Registers (32-63) option is selected
* 0b1..MAC Addresses 32-63 Select option is selected
* 0b0..MAC Addresses 32-63 Select option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_POUOST_MASK (0x800000U)
#define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U)
/*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
* step timestamp for PTP over UDP/IP feature is selected.
* 0b1..One Step for PTP over UDP/IP Feature is selected
* 0b0..One Step for PTP over UDP/IP Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
/*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
* 0b10..128
* 0b11..256
* 0b01..64
* 0b00..No hash table
*/
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U)
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U)
/*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
* MAC Address Registers (64-127) option is selected
* 0b1..MAC Addresses 64-127 Select option is selected
* 0b0..MAC Addresses 64-127 Select option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
/*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
* 0b001..1 PPS output
* 0b010..2 PPS output
* 0b011..3 PPS output
* 0b100..4 PPS output
* 0b000..No PPS output
* 0b101..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
/*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
* time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
* 0b10..Both
* 0b01..External
* 0b00..Internal
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U)
#define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U)
/*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
* 0b1..Frame Preemption Enable feature is selected
* 0b0..Frame Preemption Enable feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U)
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U)
/*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
* 0b0001..1 L3 or L4 Filter
* 0b0010..2 L3 or L4 Filters
* 0b0011..3 L3 or L4 Filters
* 0b0100..4 L3 or L4 Filters
* 0b0101..5 L3 or L4 Filters
* 0b0110..6 L3 or L4 Filters
* 0b0111..7 L3 or L4 Filters
* 0b1000..8 L3 or L4 Filters
* 0b0000..No L3 or L4 Filter
*/
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U)
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U)
/*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
* VLAN Insertion on Tx option is selected
* 0b1..Source Address or VLAN Insertion Enable option is selected
* 0b0..Source Address or VLAN Insertion Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
#define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U)
#define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U)
/*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
* 0b1..Time Based Scheduling Enable feature is selected
* 0b0..Time Based Scheduling Enable feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
/*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
* this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
* 0b000..GMII or MII
* 0b111..RevMII
* 0b001..RGMII
* 0b100..RMII
* 0b101..RTBI
* 0b010..SGMII
* 0b110..SMII
* 0b011..TBI
*/
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U)
#define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U)
/*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
* 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
* 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
* 0b01..Only "ECC protection for external memory" feature is selected
* 0b00..No Safety features selected
*/
#define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
* 0b001..1 auxiliary input
* 0b010..2 auxiliary input
* 0b011..3 auxiliary input
* 0b100..4 auxiliary input
* 0b000..No auxiliary input
* 0b101..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_HW_FEAT */
#define ENET_QOS_MAC_HW_FEAT_COUNT (4U)
/*! @name MAC_MDIO_ADDRESS - MDIO Address */
/*! @{ */
#define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK (0x1U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT (0U)
/*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
* 0b0..GMII Busy is disabled
* 0b1..GMII Busy is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK (0x2U)
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT (1U)
/*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
* 0b0..Clause 45 PHY is disabled
* 0b1..Clause 45 PHY is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U)
/*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
* 0b0..GMII Operation Command 0 is disabled
* 0b1..GMII Operation Command 0 is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U)
/*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
* RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
* Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
* and Read commands are valid.
* 0b0..GMII Operation Command 1 is disabled
* 0b1..GMII Operation Command 1 is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U)
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U)
/*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
* before read, write, or post-read increment address packets.
* 0b0..Skip Address Packet is disabled
* 0b1..Skip Address Packet is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK (0xF00U)
#define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT (8U)
/*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
* according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
* clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
* = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
* - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
* MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
* clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
* applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT (12U)
/*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
* generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT (16U)
/*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT (21U)
/*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT (26U)
/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
* the MAC informs the completion of a read or write command at the end of frame transfer (before
* the trailing clocks are transmitted).
* 0b0..Back to Back transactions disabled
* 0b1..Back to Back transactions enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT (27U)
/*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
* and transmits MDIO frames with only 1 preamble bit.
* 0b0..Preamble Suppression disabled
* 0b1..Preamble Suppression enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
/*! @} */
/*! @name MAC_MDIO_DATA - MAC MDIO Data */
/*! @{ */
#define ENET_QOS_MAC_MDIO_DATA_GD_MASK (0xFFFFU)
#define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT (0U)
/*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
* Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
* Management Write operation.
*/
#define ENET_QOS_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
#define ENET_QOS_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT (16U)
/*! RA - Register Address This field is valid only when C45E is set.
*/
#define ENET_QOS_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
/*! @} */
/*! @name MAC_CSR_SW_CTRL - CSR Software Control */
/*! @{ */
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U)
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U)
/*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
* fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
* clear it.
* 0b0..Register Clear on Write 1 is disabled
* 0b1..Register Clear on Write 1 is enabled
*/
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
/*! @} */
/*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
/*! @{ */
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U)
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U)
/*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
* 0b0..Tx Frame Preemption is disabled
* 0b1..Tx Frame Preemption is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK (0x2U)
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT (1U)
/*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
* 0b0..Send Verify mPacket is disabled
* 0b1..Send Verify mPacket is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U)
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U)
/*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
* 0b0..Send Respond mPacket is disabled
* 0b1..Send Respond mPacket is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U)
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
/*! S1_SET_0 - Synopsys Reserved, Must be set to "0".
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U)
/*! RVER - Received Verify Frame Set when a Verify mPacket is received.
* 0b1..Received Verify Frame
* 0b0..Not received Verify Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U)
/*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
* 0b1..Received Respond Frame
* 0b0..Not received Respond Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U)
/*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
* 0b1..transmitted Verify Frame
* 0b0..Not transmitted Verify Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U)
/*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
* 0b1..transmitted Respond Frame
* 0b0..Not transmitted Respond Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
/*! @} */
/*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
/*! @{ */
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U)
/*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
* rollover equivalent time of the PTP System Time in ns
*/
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
/*! @} */
/*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
/*! @{ */
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U)
/*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time.
*/
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
/*! @} */
/*! @name HIGH - MAC Address0 High..MAC Address63 High */
/*! @{ */
#define ENET_QOS_HIGH_ADDRHI_MASK (0xFFFFU)
#define ENET_QOS_HIGH_ADDRHI_SHIFT (0U)
/*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address.
*/
#define ENET_QOS_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
#define ENET_QOS_HIGH_DCS_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define ENET_QOS_HIGH_DCS_SHIFT (16U)
/*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
* contains the binary representation of the DMA Channel number to which an Rx packet whose DA
* matches the MAC Address(#i) content is routed.
*/
#define ENET_QOS_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define ENET_QOS_HIGH_MBC_MASK (0x3F000000U)
#define ENET_QOS_HIGH_MBC_SHIFT (24U)
/*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes.
*/
#define ENET_QOS_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
#define ENET_QOS_HIGH_SA_MASK (0x40000000U)
#define ENET_QOS_HIGH_SA_SHIFT (30U)
/*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
* fields of the received packet.
* 0b0..Compare with Destination Address
* 0b1..Compare with Source Address
*/
#define ENET_QOS_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
#define ENET_QOS_HIGH_AE_MASK (0x80000000U)
#define ENET_QOS_HIGH_AE_SHIFT (31U)
/*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
* 0b0..INVALID : This bit must be always set to 1
* 0b1..This bit is always set to 1
*/
#define ENET_QOS_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
/*! @} */
/* The count of ENET_QOS_HIGH */
#define ENET_QOS_HIGH_COUNT (64U)
/*! @name LOW - MAC Address0 Low..MAC Address63 Low */
/*! @{ */
#define ENET_QOS_LOW_ADDRLO_MASK (0xFFFFFFFFU)
#define ENET_QOS_LOW_ADDRLO_SHIFT (0U)
/*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address.
*/
#define ENET_QOS_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
/*! @} */
/* The count of ENET_QOS_LOW */
#define ENET_QOS_LOW_COUNT (64U)
/*! @name MAC_MMC_CONTROL - MMC Control */
/*! @{ */
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK (0x1U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT (0U)
/*! CNTRST - Counters Reset When this bit is set, all counters are reset.
* 0b0..Counters are not reset
* 0b1..All counters are reset
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
/*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
* 0b0..Counter Stop Rollover is disabled
* 0b1..Counter Stop Rollover is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK (0x4U)
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT (2U)
/*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
* 0b0..Reset on Read is disabled
* 0b1..Reset on Read is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U)
/*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
* 0b0..MMC Counter Freeze is disabled
* 0b1..MMC Counter Freeze is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK (0x10U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT (4U)
/*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
* full or almost half according to the CNTPRSTLVL bit.
* 0b0..Counters Preset is disabled
* 0b1..Counters Preset is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
/*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
* 0b0..Full-Half Preset is disabled
* 0b1..Full-Half Preset is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK (0x100U)
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT (8U)
/*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
* 0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
* 0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
/*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
* rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
/*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
* rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
* 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
/*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
* rxoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
/*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
* rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
/*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
* rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
/*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
* rxcrcerror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
/*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
* the rxalignmenterror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
/*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
* rxrunterror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Runt Packet Counter Interrupt Status detected
* 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
/*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
* rxjabbererror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
/*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
* the rxundersize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
/*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
* rxoversize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
/*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
* when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
/*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
* is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
/*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
/*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
/*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
/*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
/*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
* rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
/*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
* rxlengtherror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
/*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
* 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
/*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
* rxpausepackets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Pause Packet Counter Interrupt Status detected
* 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
/*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
* rxfifooverflow counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
* 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
/*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
* rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
/*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
* rxwatchdog error counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
/*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
* rxrcverror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
/*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
* rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Control Packet Counter Interrupt Status detected
* 0b0..MMC Receive Control Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
/*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
* Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
* 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
/*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
* Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive LPI transition Counter Interrupt Status detected
* 0b0..MMC Receive LPI transition Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
/*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
* txoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
/*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
* txpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
/*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
* txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
/*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
* txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
/*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
* when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
/*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
* reaches the maximum value.
* 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
/*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
/*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
/*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
/*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
* the maximum value.
* 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
/*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
* the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
/*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
* the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
/*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
* the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
/*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
* the txunderflowerror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
/*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
* when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
/*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
* set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
/*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
* txdeferred counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
/*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
* the txlatecol counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
/*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
* when the txexesscol counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
/*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
* txcarriererror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
/*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
* txoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Octet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
/*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
* txpacketcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
/*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
* when the txexcessdef counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
/*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
* txpausepacketserror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
/*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
* txvlanpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
/*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
* the txoversize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
/*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
* Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
* 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
/*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
* Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit LPI transition Counter Interrupt Status detected
* 0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
/*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
/*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
/*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
/*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
/*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
/*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
/*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
/*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxrunterror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
/*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
/*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
/*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
/*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
/*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
/*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
/*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
/*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
/*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
* 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
/*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
/*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
/*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
/*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxpausepackets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
/*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
/*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
/*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
/*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
/*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
/*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
* interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
* 0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
/*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
* interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive LPI transition counter interrupt Mask is disabled
* 0b1..MMC Receive LPI transition counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
/*! @} */
/*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
/*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
/*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
/*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
/*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
/*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
/*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
/*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
/*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
/*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
/*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
/*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
/*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
/*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
/*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txunderflowerror counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
/*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
/*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
/*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
/*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
/*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
/*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
/*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
* when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
/*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
/*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
/*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
/*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
/*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
/*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
* interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
* 0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
/*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
* interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
* 0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
/*! @} */
/*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
/*! @{ */
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
/*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
* exclusive of preamble and retried bytes, in good and bad packets.
*/
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
/*! @} */
/*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
/*! @{ */
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
/*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
* transmitted, exclusive of retried packets.
*/
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
/*! @} */
/*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
/*! @{ */
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
/*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted.
*/
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
/*! @} */
/*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
/*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
/*! @} */
/*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
/*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
* transmitted with length 64 bytes, exclusive of preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
/*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
* and retried packets.
*/
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
/*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
/*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
/*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
* and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
/*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
* and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
/*! @} */
/*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
/*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
/*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
/*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted.
*/
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
/*! @{ */
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
/*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error.
*/
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
/*! @} */
/*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
/*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
* transmitted packets after a single collision in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
/*! @} */
/*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
/*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
* transmitted packets after multiple collisions in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
/*! @} */
/*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
/*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
* a deferral in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
/*! @} */
/*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
/*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error.
*/
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
/*! @} */
/*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
/*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
* because of excessive (16) collision errors.
*/
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
/*! @} */
/*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
/*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
* carrier sense error (no carrier or loss of carrier).
*/
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
/*! @} */
/*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
/*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets.
*/
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
/*! @} */
/*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
/*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted.
*/
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
/*! @} */
/*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
/*! @{ */
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
/*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
* because of excessive deferral error (deferred for more than two max-sized packet times).
*/
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
/*! @} */
/*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
/*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted.
*/
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
/*! @} */
/*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
/*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted.
*/
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
/*! @} */
/*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
/*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
* errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
* 2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
*/
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
/*! @} */
/*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
/*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received.
*/
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
/*! @} */
/*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
/*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
* of preamble, in good and bad packets.
*/
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
/*! @} */
/*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
/*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets.
*/
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
/*! @} */
/*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
/*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received.
*/
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
/*! @} */
/*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
/*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received.
*/
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
/*! @} */
/*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
/*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error.
*/
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
/*! @} */
/*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
/*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error.
*/
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
/*! @} */
/*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
/*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
* (length less than 64 bytes and CRC error) error.
*/
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
/*! @} */
/*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
/*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
* with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
* error.
*/
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
/*! @} */
/*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
/*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
* length less than 64 bytes, without any errors.
*/
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
/*! @} */
/*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
/*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
* errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
* packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
*/
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
/*! @} */
/*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
/*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
* packets received with length 64 bytes, exclusive of the preamble.
*/
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
/*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
*/
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
/*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
/*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
/*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
* and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
/*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
* packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
/*! @} */
/*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
/*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received.
*/
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
/*! @} */
/*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
/*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
* length error (Length Type field not equal to packet size), for all packets with valid length field.
*/
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
/*! @} */
/*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
/*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
* with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
*/
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
/*! @} */
/*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
/*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received.
*/
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
/*! @} */
/*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
/*! @{ */
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
/*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow.
*/
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
/*! @} */
/*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
/*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received.
*/
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
/*! @} */
/*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
/*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
* error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
* JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
* WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
* MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
*/
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
/*! @} */
/*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
/*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
* Receive error or Packet Extension error on the GMII or MII interface.
*/
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
/*! @} */
/*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
/*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received.
*/
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
/*! @} */
/*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
/*! @{ */
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
/*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted.
*/
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
/*! @} */
/*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
/*! @{ */
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
/*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred.
*/
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
/*! @} */
/*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
/*! @{ */
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
/*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted.
*/
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
/*! @} */
/*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
/*! @{ */
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
/*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred.
*/
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
/*! @} */
/*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
/*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
/*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
/*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
/*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
/*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
/*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
/*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
/*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
/*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
/*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
/*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
/*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
/*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
/*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
/*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
/*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
/*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
/*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
/*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
/*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
/*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
/*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
/*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
/*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
/*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
/*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
/*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
/*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
/*! @} */
/*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
/*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
* rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
/*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
* when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
/*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
* when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
/*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
* the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
/*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
* is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
/*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
* rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
/*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
* when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
/*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
* when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
/*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
* rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
/*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
* rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
/*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
* rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
/*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
* rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
/*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
* rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
/*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
* rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
/*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
* rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
/*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
* the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
/*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
* the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
/*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
* the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
/*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
* is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
/*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
* rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
/*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
* the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
/*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
* the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
/*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
* rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
/*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
* rxudp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
/*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
* rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
/*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
* rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
/*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
* rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
/*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
* rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
/*! @} */
/*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
/*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
/*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
* received with header (checksum, length, or version mismatch) errors.
*/
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
/*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
* received that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
/*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation.
*/
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
/*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
* IPv4 datagrams received that had a UDP payload with checksum disabled.
*/
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
/*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
/*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
* received with header (length or version mismatch) errors.
*/
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
/*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
* received that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
/*! @} */
/*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
/*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload.
*/
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
/*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
* whose UDP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
/*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload.
*/
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
/*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
* whose TCP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
/*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload.
*/
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
/*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
* received whose ICMP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
/*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
* datagrams encapsulating TCP, UDP, or ICMP data.
*/
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
/*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
* in IPv4 datagrams with header errors (checksum, length, version mismatch).
*/
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
/*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
* datagrams that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
/*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams.
*/
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
/*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
* received in a UDP segment that had the UDP checksum disabled.
*/
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
/*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
* datagrams encapsulating TCP, UDP, or ICMP data.
*/
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
/*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
* in IPv6 datagrams with header errors (length, version mismatch).
*/
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
/*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
* datagrams that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
/*! @} */
/*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
/*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment.
*/
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
/*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
/*! @} */
/*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
/*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment.
*/
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
/*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
/*! @} */
/*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
/*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment.
*/
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
/*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
/*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
* Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Tx FPE Fragment Counter Interrupt status detected
* 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
/*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
* counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Tx Hold Request Counter Interrupt Status detected
* 0b0..MMC Tx Hold Request Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
/*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
* the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
/*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
* when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
/*! @} */
/*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
/*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
* been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
* during FPE Enabled configuration.
*/
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
/*! @} */
/*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
/*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC.
*/
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
/*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
* Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
* 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
/*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
* Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
* 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
/*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
* Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
* 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
/*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
* Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
* 0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
/*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
* interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
/*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
* when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
/*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
* when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
/*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
* Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
* 0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
/*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
* reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
/*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
* unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
* was no preceding preempted frame.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
/*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
* successfully reassembled and delivered to MAC.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
/*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
* due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
* Enabled configuration.
*/
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
/*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
/*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
/*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
/*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
/*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
/*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
/*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
/*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
/*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
/*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
/*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
/*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
/*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
/*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
/*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
/*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
/*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
/*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
/*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
/*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
/*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
/*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
/*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
/*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
/*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
/*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
/*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
/*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
/*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
/*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
/*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
/*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
/*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
/*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
/*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
/*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
/*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
/*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
/*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
/*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
/*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
/*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
/*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
/*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
/*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
/*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
/*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
/*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
/*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
/*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
/*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
/*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
/*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
/*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
/*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
/*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
/*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
/*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
/*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
/*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
/*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
/*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
/*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
/*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
/*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
/*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
/*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
/*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
/*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
/*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
/*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
/*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
/*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
/*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
/*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
/*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
/*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
/*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
/*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
/*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
/*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
/*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
/*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
/*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
/*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
/*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
/*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
/*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
/*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
/*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
/*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
/*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
/*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
/*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
/*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
/*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
/*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
/*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
/*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
/*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
/*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
/*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
/*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
/*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
/*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
/*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
/*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
/*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
/*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
/*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
/*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
/*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
/*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
/*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
/*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
/*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
/*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
/*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
/*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
/*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
/*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
/*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
/*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
/*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
/*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
/*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
/*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
/*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
/*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
/*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
/*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
/*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
/*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
/*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
/*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
/*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
/*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
/*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
/*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
/*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
/*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
/*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
/*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
/*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
/*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
/*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
/*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
/*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
/*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
/*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
/*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
/*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
/*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
/*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
/*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
/*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
/*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
/*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
/*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
/*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
* 0b0..Timestamp is disabled
* 0b1..Timestamp is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
* 0b0..Coarse method is used to update system timestamp
* 0b1..Fine method is used to update system timestamp
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
* with the value specified in the MAC_System_Time_Seconds_Update and
* MAC_System_Time_Nanoseconds_Update registers.
* 0b0..Timestamp is not initialized
* 0b1..Timestamp is initialized
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
* with the value specified in MAC_System_Time_Seconds_Update and
* MAC_System_Time_Nanoseconds_Update registers.
* 0b0..Timestamp is not updated
* 0b1..Timestamp is updated
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
/*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
* register is updated in the PTP block for fine correction.
* 0b0..Addend Register is not updated
* 0b1..Addend Register is updated
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
/*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
* 0b0..Presentation Time Generation is disabled
* 0b1..Presentation Time Generation is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
* enabled for all packets received by the MAC.
* 0b0..Timestamp for All Packets disabled
* 0b1..Timestamp for All Packets enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
* register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
* the timestamp (High) seconds.
* 0b0..Timestamp Digital or Binary Rollover Control is disabled
* 0b1..Timestamp Digital or Binary Rollover Control is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
* 1588 version 2 format is used to process the PTP packets.
* 0b0..PTP Packet Processing for Version 2 Format is disabled
* 0b1..PTP Packet Processing for Version 2 Format is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
* processes the PTP packets encapsulated directly in the Ethernet packets.
* 0b0..Processing of PTP over Ethernet Packets is disabled
* 0b1..Processing of PTP over Ethernet Packets is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
* receiver processes the PTP packets encapsulated in IPv6-UDP packets.
* 0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
* 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
* receiver processes the PTP packets encapsulated in IPv4-UDP packets.
* 0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
* 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
/*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
* snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
* 0b0..Timestamp Snapshot for Event Messages is disabled
* 0b1..Timestamp Snapshot for Event Messages is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
* is taken only for the messages that are relevant to the master node.
* 0b0..Snapshot for Messages Relevant to Master is disabled
* 0b1..Snapshot for Messages Relevant to Master is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
* decide the set of PTP packet types for which snapshot needs to be taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
* address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
* directly sent over Ethernet.
* 0b0..MAC Address for PTP Packet Filtering is disabled
* 0b1..MAC Address for PTP Packet Filtering is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK (0x80000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
/*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
* the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
* correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
* operation.
* 0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
* 0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
/*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
* reference System Time input for the following: - To take the timestamp provided as status - To insert
* the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
* enabled.
* 0b0..External System Time Input is disabled
* 0b1..External System Time Input is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
/*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
* transmit timestamp status even if it is not read by the software.
* 0b0..Transmit Timestamp Status Mode is disabled
* 0b1..Transmit Timestamp Status Mode is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
/*! AV8021ASMEN - AV 802.
* 0b0..AV 802.1AS Mode is disabled
* 0b1..AV 802.1AS Mode is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
/*! @} */
/*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
/*! @{ */
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
/*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
* represented in nanoseconds multiplied by 2^8.
*/
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
/*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
* cycle (of clk_ptp_i) with the contents of the sub-second register.
*/
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
/*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
* System Time maintained by the MAC.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
/*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
/*! TSS - Timestamp Seconds The value in this field is the seconds part of the update.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
/*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
/*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
* 0b0..Add time
* 0b1..Subtract time
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
/*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
* Accumulator register to achieve time synchronization.
*/
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
/*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
/*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
* the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
* 0b1..Timestamp Seconds Overflow status detected
* 0b0..Timestamp Seconds Overflow status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
/*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
* time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
* MAC_PPS0_Target_Time_Nanoseconds registers.
* 0b1..Timestamp Target Time Reached status detected
* 0b0..Timestamp Target Time Reached status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
/*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
* 0b1..Auxiliary Timestamp Trigger Snapshot status detected
* 0b0..Auxiliary Timestamp Trigger Snapshot status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
/*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
/*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
* the value of system time is greater than or equal to the value specified in the
* MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
/*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
/*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
* the value of system time is greater than or equal to the value specified in the
* MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
/*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
/*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
* that the value of system time is greater than or equal to the value specified in the
* MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
/*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
/*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
* transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
* the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
* 0b1..Tx Timestamp Status Interrupt status detected
* 0b0..Tx Timestamp Status Interrupt status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
/*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
* trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
/*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
* timestamp snapshot FIFO is full and external trigger was set.
* 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
* 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
/*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO.
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
/*! @} */
/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
/*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
* of the Transmit packet's captured timestamp.
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
/*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
* following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
* register is reset - The timestamp of the previous packet is overwritten with timestamp of the
* current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
* 0b1..Transmit Timestamp Status Missed status detected
* 0b0..Transmit Timestamp Status Missed status not detected
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
/*! @} */
/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
/*! @{ */
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
/*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
* field of Transmit packet's captured timestamp.
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
/*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
* 0b0..Auxiliary Snapshot FIFO Clear is disabled
* 0b1..Auxiliary Snapshot FIFO Clear is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
/*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
/*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
/*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
/*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
/*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp.
*/
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
/*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp.
*/
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
/*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
* asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
/*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
* asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
/*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
* defined by the Ingress Correction expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
/*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
* correction value as defined by the Egress Correction expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
/*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
* part of the ingress path correction value as defined by the "Ingress Correction" expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
/*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
* part of the egress path correction value as defined by the "Egress Correction" expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
/*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
* nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
* ingress timestamp is taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
/*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
* sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
* where the ingress timestamp is taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
/*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
* sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
* the output ports (phy_txd_o) of the MAC.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
/*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
* nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
* ports (phy_txd_o) of the MAC.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
/*! @} */
/*! @name MAC_PPS_CONTROL - PPS Control */
/*! @{ */
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
/*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U)
/*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
* 0b0..Flexible PPS Output Mode is disabled
* 0b1..Flexible PPS Output Mode is enabled
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
/*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
* registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
* output signal:
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U)
/*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
* 0b1..0th PPS instance is enabled to operate in MCGR mode
* 0b0..0th PPS instance is enabled to operate in PPS mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U)
/*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
/*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
* registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U)
/*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
* 0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
* 0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U)
/*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
/*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
* registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U)
/*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
* 0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
* 0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U)
/*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
/*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
* registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U)
/*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode.
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
/*! @} */
/*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
/*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
/*! @} */
/*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
/*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
/*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
/*! @} */
/*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
/*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
/*! @} */
/*! @name MAC_PPS0_WIDTH - PPS0 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U)
/*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
/*! @} */
/*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
/*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
/*! @} */
/*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
/*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
/*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
/*! @} */
/*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
/*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
/*! @} */
/*! @name MAC_PPS1_WIDTH - PPS1 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U)
/*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
/*! @} */
/*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
/*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
/*! @} */
/*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
/*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
/*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
/*! @} */
/*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
/*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
/*! @} */
/*! @name MAC_PPS2_WIDTH - PPS2 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U)
/*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
/*! @} */
/*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
/*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
/*! @} */
/*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
/*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
/*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
/*! @} */
/*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
/*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
/*! @} */
/*! @name MAC_PPS3_WIDTH - PPS3 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U)
/*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
/*! @} */
/*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
/*! @{ */
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK (0x1U)
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT (0U)
/*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
* 0b0..PTP Offload feature is disabled
* 0b1..PTP Offload feature is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK (0x2U)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT (1U)
/*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
* periodically based on interval programmed or trigger from application, when the MAC is
* programmed to be in Clock Master mode.
* 0b0..Automatic PTP SYNC message is disabled
* 0b1..Automatic PTP SYNC message is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK (0x4U)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT (2U)
/*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
* is generated periodically based on interval programmed or trigger from application, when the
* MAC is programmed to be in Peer-to-Peer Transparent mode.
* 0b0..Automatic PTP Pdelay_Req message is disabled
* 0b1..Automatic PTP Pdelay_Req message is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK (0x10U)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
/*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
* 0b0..Automatic PTP SYNC message Trigger is disabled
* 0b1..Automatic PTP SYNC message Trigger is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
/*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
* 0b0..Automatic PTP Pdelay_Req message Trigger is disabled
* 0b1..Automatic PTP Pdelay_Req message Trigger is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK (0x40U)
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT (6U)
/*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
* Request and Delay response is not generated for received SYNC and Delay request packet
* respectively, as required by the programmed mode.
* 0b1..PTO Delay Request/Response response generation is disabled
* 0b0..PTO Delay Request/Response response generation is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK (0x80U)
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT (7U)
/*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
* Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
* request packet, as required by the programmed mode.
* 0b1..Peer Delay Response response generation is disabled
* 0b0..Peer Delay Response response generation is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_DN_MASK (0xFF00U)
#define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT (8U)
/*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating.
*/
#define ENET_QOS_MAC_PTO_CONTROL_DN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
/*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
/*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
/*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
/*! @} */
/*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
/*! @{ */
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
/*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
* message when the PTP node is Master.
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
/*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
* 0b110..Reserved
* 0b000..DelayReq generated for every received SYNC
* 0b100..for every 16 SYNC messages
* 0b001..DelayReq generated every alternate reception of SYNC
* 0b101..for every 32 SYNC messages
* 0b010..for every 4 SYNC messages
* 0b011..for every 8 SYNC messages
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
/*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node.
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
/*! @} */
/*! @name MTL_OPERATION_MODE - MTL Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U)
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
* 0b0..Drop Transmit Status is disabled
* 0b1..Drop Transmit Status is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK (0x4U)
#define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT (2U)
/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
* 0b0..Strict priority (SP)
* 0b1..Weighted Strict Priority (WSP)
*/
#define ENET_QOS_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U)
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
* 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
* 0b11..Strict priority algorithm
* 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
* 0b00..WRR algorithm
*/
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
/*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
* 0b0..Counters Preset is disabled
* 0b1..Counters Preset is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U)
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
* 0b0..Counters are not reset
* 0b1..All counters are reset
*/
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK (0x8000U)
#define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT (15U)
/*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
* 0b0..Flexible Rx parser is disabled
* 0b1..Flexible Rx parser is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_FRPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
/*! @} */
/*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
/*! @{ */
#define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK (0x1U)
#define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT (0U)
/*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
* 0b0..FIFO Debug Access is disabled
* 0b1..FIFO Debug Access is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK (0x2U)
#define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT (1U)
/*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
* the FIFO is read, write, and debug access.
* 0b0..Debug Mode Access to FIFO is disabled
* 0b1..Debug Mode Access to FIFO is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
#define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU)
#define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U)
/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
* 0b11..All four bytes are valid
* 0b10..Byte 0, Byte 1, and Byte 2 are valid
* 0b01..Byte 0 and Byte 1 are valid
* 0b00..Byte 0 valid
*/
#define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U)
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U)
/*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
* 0b01..Control Word/Normal Status
* 0b11..EOP Data/EOP
* 0b00..Packet Data
* 0b10..SOP Data/Last Status
*/
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
#define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK (0x100U)
#define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT (8U)
/*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
* 0b0..Reset All Pointers is disabled
* 0b1..Reset All Pointers is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
#define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK (0x200U)
#define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT (9U)
/*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
* currently-selected FIFO are reset when FIFO Debug Access is enabled.
* 0b0..Reset Pointers of Selected FIFO is disabled
* 0b1..Reset Pointers of Selected FIFO is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK (0x400U)
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT (10U)
/*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
* 0b0..FIFO Read is disabled
* 0b1..FIFO Read is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK (0x800U)
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT (11U)
/*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
* FIFO when FIFO Debug Access is enabled.
* 0b0..FIFO Write is disabled
* 0b1..FIFO Write is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U)
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U)
/*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
* 0b11..Rx FIFO
* 0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
* 0b00..Tx FIFO
* 0b01..Tx Status FIFO (only read access when SLVMOD is set)
*/
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
#define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK (0x4000U)
#define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT (14U)
/*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
* generated when EOP of received packet is written to the Rx FIFO.
* 0b0..Receive Packet Available Interrupt Status is disabled
* 0b1..Receive Packet Available Interrupt Status is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
#define ENET_QOS_MTL_DBG_CTL_STSIE_MASK (0x8000U)
#define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT (15U)
/*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
* generated when Transmit status is available in slave mode.
* 0b0..Transmit Packet Available Interrupt Status is disabled
* 0b1..Transmit Packet Available Interrupt Status is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_STSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
/*! @} */
/*! @name MTL_DBG_STS - FIFO Debug Status */
/*! @{ */
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK (0x1U)
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT (0U)
/*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
* MAC and content of the following fields is not valid: - All other fields of this register - All
* fields of the MTL_FIFO_DEBUG_DATA register
* 0b1..FIFO Busy detected
* 0b0..FIFO Busy not detected
*/
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
#define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U)
#define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U)
/*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
* 0b01..Control Word/Normal Status
* 0b11..EOP Data/EOP
* 0b00..Packet Data
* 0b10..SOP Data/Last Status
*/
#define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
#define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U)
#define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U)
/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
* 0b11..All four bytes are valid
* 0b10..Byte 0, Byte 1, and Byte 2 are valid
* 0b01..Byte 0 and Byte 1 are valid
* 0b00..Byte 0 valid
*/
#define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
#define ENET_QOS_MTL_DBG_STS_PKTI_MASK (0x100U)
#define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U)
/*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
* written the EOP of received packet to the Rx FIFO.
* 0b1..Receive Packet Available Interrupt Status detected
* 0b0..Receive Packet Available Interrupt Status not detected
*/
#define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
#define ENET_QOS_MTL_DBG_STS_STSI_MASK (0x200U)
#define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U)
/*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
* mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
* 0b1..Transmit Status Available Interrupt Status detected
* 0b0..Transmit Status Available Interrupt Status not detected
*/
#define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
#define ENET_QOS_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U)
#define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT (15U)
/*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO.
*/
#define ENET_QOS_MTL_DBG_STS_LOCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
/*! @} */
/*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
/*! @{ */
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
/*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
* data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
*/
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
/*! @} */
/*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
/*! @{ */
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
* 0b1..Queue 0 Interrupt status detected
* 0b0..Queue 0 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
* 0b1..Queue 1 Interrupt status detected
* 0b0..Queue 1 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
/*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
* 0b1..Queue 2 Interrupt status detected
* 0b0..Queue 2 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
/*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
* 0b1..Queue 3 Interrupt status detected
* 0b0..Queue 3 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
/*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
* 0b1..Queue 4 Interrupt status detected
* 0b0..Queue 4 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
/*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
* 0b1..Debug Interrupt status detected
* 0b0..Debug Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
/*! ESTIS - EST (TAS- 802.
* 0b1..EST (TAS- 802.1Qbv) Interrupt status detected
* 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
/*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
* 0b1..MTL Rx Parser Interrupt status detected
* 0b0..MTL Rx Parser Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
/*! @} */
/*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
/*! @{ */
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x7U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
* in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q0DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 0 disabled for DA-based DMA Channel Selection
* 0b1..Queue 0 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x700U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q1DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 1 disabled for DA-based DMA Channel Selection
* 0b1..Queue 1 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK (0x70000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
/*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q2DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK (0x100000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
/*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 2 disabled for DA-based DMA Channel Selection
* 0b1..Queue 2 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK (0x7000000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
/*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q3DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK (0x10000000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
/*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
* indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
* in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
* or the Ethernet DA address.
* 0b0..Queue 3 disabled for DA-based DMA Channel Selection
* 0b1..Queue 3 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
/*! @} */
/*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
/*! @{ */
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK (0x7U)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
/*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
* in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q4DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK (0x10U)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
/*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 4 disabled for DA-based DMA Channel Selection
* 0b1..Queue 4 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
/*! @} */
/*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
/*! @{ */
#define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK (0x1U)
#define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT (0U)
/*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
* is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
* current list.
* 0b0..EST offset Mode is disabled
* 0b1..EST offset Mode is enabled
*/
#define ENET_QOS_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK (0x2U)
#define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT (1U)
/*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
* 0b0..LEOS field is invalid
* 0b1..LEOS field is valid
*/
#define ENET_QOS_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK (0x70U)
#define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT (4U)
/*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time.
*/
#define ENET_QOS_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U)
#define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT (8U)
/*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
* Launch time to compute the Launch Expiry time.
*/
#define ENET_QOS_MTL_TBS_CTRL_LEOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
/*! @} */
/*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
/*! @{ */
#define ENET_QOS_MTL_EST_CONTROL_EEST_MASK (0x1U)
#define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT (0U)
/*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
* 0b0..EST is disabled
* 0b1..EST is enabled
*/
#define ENET_QOS_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
#define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK (0x2U)
#define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT (1U)
/*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
* that it currently owns (SWOL) and the hardware should switch to the new list based on the new
* BTR.
* 0b0..Switch to S/W owned list is disabled
* 0b1..Switch to S/W owned list is enabled
*/
#define ENET_QOS_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
#define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK (0x10U)
#define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U)
/*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
* Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
* 0b1..Do not Drop frames during Frame Size Error
* 0b0..Drop frames during Frame Size Error
*/
#define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
#define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK (0x20U)
#define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT (5U)
/*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
* to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
* field of this register) GCL iterations are dropped.
* 0b0..Do not Drop Frames causing Scheduling Error
* 0b1..Drop Frames causing Scheduling Error
*/
#define ENET_QOS_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
#define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK (0xC0U)
#define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U)
/*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
* reporting an HLBS error defined in EST_STATUS register.
* 0b10..16 iterations
* 0b11..32 iterations
* 0b00..4 iterations
* 0b01..8 iterations
*/
#define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
#define ENET_QOS_MTL_EST_CONTROL_TILS_MASK (0x700U)
#define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT (8U)
/*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
* programmed Time Interval values used in the Gate Control Lists.
*/
#define ENET_QOS_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
#define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U)
#define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT (12U)
/*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
* added to the current time to compensate for all the implementation pipeline delays such as the CDC
* sync delay, buffering delays, data path delays etc.
*/
#define ENET_QOS_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
#define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U)
#define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT (24U)
/*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds.
*/
#define ENET_QOS_MTL_EST_CONTROL_PTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
/*! @} */
/*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
/*! @{ */
#define ENET_QOS_MTL_EST_STATUS_SWLC_MASK (0x1U)
#define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U)
/*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
* switched to the SWOL, and the SWOL bit has been updated to that effect.
* 0b1..Switch to S/W owned list Complete detected
* 0b0..Switch to S/W owned list Complete not detected
*/
#define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
#define ENET_QOS_MTL_EST_STATUS_BTRE_MASK (0x2U)
#define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U)
/*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
* value is less than current time.
* 0b1..BTR Error detected
* 0b0..BTR Error not detected
*/
#define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
#define ENET_QOS_MTL_EST_STATUS_HLBF_MASK (0x4U)
#define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT (2U)
/*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
* Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
* equal to the duration needed for frame size (or frame fragment size when preemption is
* enabled) transmission.
* 0b1..Head-Of-Line Blocking due to Frame Size detected
* 0b0..Head-Of-Line Blocking due to Frame Size not detected
*/
#define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
#define ENET_QOS_MTL_EST_STATUS_HLBS_MASK (0x8U)
#define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U)
/*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
* and get scheduled even after 4 iterations of the GCL.
* 0b1..Head-Of-Line Blocking due to Scheduling detected
* 0b0..Head-Of-Line Blocking due to Scheduling not detected
*/
#define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
#define ENET_QOS_MTL_EST_STATUS_CGCE_MASK (0x10U)
#define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT (4U)
/*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
* programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
* Cycle Time (CTR).
* 0b1..Constant Gate Control Error detected
* 0b0..Constant Gate Control Error not detected
*/
#define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
#define ENET_QOS_MTL_EST_STATUS_SWOL_MASK (0x80U)
#define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U)
/*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
* when "1" indicates the Gate Control list "1" is owned by the software.
* 0b1..Gate control list number "1" is owned by software
* 0b0..Gate control list number "0" is owned by software
*/
#define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
#define ENET_QOS_MTL_EST_STATUS_BTRL_MASK (0xF00U)
#define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT (8U)
/*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
* =< New BTR + (N * New Cycle Time) becomes true.
*/
#define ENET_QOS_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
#define ENET_QOS_MTL_EST_STATUS_CGSN_MASK (0xF0000U)
#define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT (16U)
/*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list.
*/
#define ENET_QOS_MTL_EST_STATUS_CGSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
/*! @} */
/*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
/*! @{ */
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK (0x1FU)
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U)
/*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
* error/timeout described in HLBS field of status register.
*/
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
/*! @} */
/*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
/*! @{ */
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
/*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
* error described in HLBF field of status register.
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
/*! @} */
/*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
/*! @{ */
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
/*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
* indicated in HBFQ field of this register.
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
/*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
* experiencing HLBF error (see HLBF field of status register).
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
/*! @} */
/*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
/*! @{ */
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U)
/*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
* change is successful and the hardware has switched to the new list.
* 0b0..Interrupt for Switch List is disabled
* 0b1..Interrupt for Switch List is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U)
/*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
* 0b0..Interrupt for BTR Error is disabled
* 0b1..Interrupt for BTR Error is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U)
/*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
* due to Frame Size error occurs and is indicated in the status.
* 0b0..Interrupt for HLBF is disabled
* 0b1..Interrupt for HLBF is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U)
/*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
* due to Scheduling issue and is indicated in the status.
* 0b0..Interrupt for HLBS is disabled
* 0b1..Interrupt for HLBS is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U)
/*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
* Error occurs and is indicated in the status.
* 0b0..Interrupt for CGCE is disabled
* 0b1..Interrupt for CGCE is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
/*! @} */
/*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
/*! @{ */
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U)
/*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
* 0b0..Start Read/Write Op disabled
* 0b1..Start Read/Write Op enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U)
/*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
* 0b1..Read Operation
* 0b0..Write Operation
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U)
/*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
* related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
* 0b0..Gate Control Related Registers are disabled
* 0b1..Gate Control Related Registers are enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U)
/*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
* Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
* used to determine which bank to use.
* 0b0..Debug Mode is disabled
* 0b1..Debug Mode is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U)
/*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
* Bank 0 (GCL0 and corresponding Time related registers).
* 0b0..R/W in debug mode should be directed to Bank 0
* 0b1..R/W in debug mode should be directed to Bank 1
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK (0x1FF00U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U)
/*! ADDR - Gate Control List Address: (GCLA when GCRR is "0").
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U)
/*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
* registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
* 0b0..ERR0 is disabled
* 0b1..ERR1 is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
/*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
* enables the ECC error injection feature.
* 0b0..EST ECC Inject Error is disabled
* 0b1..EST ECC Inject Error is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
/*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
* following are the errors inserted based on the value encoded in this field.
* 0b00..Insert 1 bit error
* 0b11..Insert 1 bit error in address field
* 0b01..Insert 2 bit errors
* 0b10..Insert 3 bit errors
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
/*! @} */
/*! @name MTL_EST_GCL_DATA - EST GCL Data */
/*! @{ */
#define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT (0U)
/*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register.
*/
#define ENET_QOS_MTL_EST_GCL_DATA_GCD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
/*! @} */
/*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
/*! @{ */
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U)
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U)
/*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
* bytes over 64 bytes required in non-final fragments of preempted frames.
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK (0x1F00U)
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT (8U)
/*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
* preemptable, when '0' Queue is classified as express.
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U)
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U)
/*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
* 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
* 0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
/*! @} */
/*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
/*! @{ */
#define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU)
#define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT (0U)
/*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
* the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
* transmission or any preemptable frames that are queued for transmission.
*/
#define ENET_QOS_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
#define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U)
#define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT (16U)
/*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
* to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
* absence of there being any express frames available for transmission.
*/
#define ENET_QOS_MTL_FPE_ADVANCE_RADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
/*! @} */
/*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
/*! NVE - Number of valid entries in the Instruction table This control indicates the number of
* valid entries in the Instruction Memory.
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
/*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
* parsable entries in the Instruction Memory.
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
/*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
* and waiting for a new packet for processing.
* 0b1..RX Parser in Idle state
* 0b0..RX Parser not in Idle state
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
/*! @} */
/*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
/*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
* address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
* this bit is set to 1.
* 0b1..Number of Valid Entries Overflow Interrupt Status detected
* 0b0..Number of Valid Entries Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
/*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
* number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
* MTL_RXP_CONTROL register),then this bit is set to 1.
* 0b1..Number of Parsable Entries Overflow Interrupt Status detected
* 0b0..Number of Parsable Entries Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
/*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
* 'Frame Offset' found to be more than EOF offset, then then this bit is set.
* 0b1..Frame Offset Overflow Interrupt Status detected
* 0b0..Frame Offset Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
/*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
* packet by setting RF=1 in the instruction memory, then this bit is set to 1.
* 0b1..Packet Dropped due to RF Interrupt Status detected
* 0b0..Packet Dropped due to RF Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
/*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
* 0b0..Number of Valid Entries Overflow Interrupt is disabled
* 0b1..Number of Valid Entries Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
/*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
* 0b0..Number of Parsable Entries Overflow Interrupt is disabled
* 0b1..Number of Parsable Entries Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
/*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
* 0b0..Frame Offset Overflow Interrupt is disabled
* 0b1..Frame Offset Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
/*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
* 0b0..Packet Drop due to RF Interrupt is disabled
* 0b1..Packet Drop due to RF Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
/*! @} */
/*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
/*! @{ */
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U)
/*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1.
*/
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
/*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
* MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
* 0b1..Rx Parser Drop count overflow occurred
* 0b0..Rx Parser Drop count overflow not occurred
*/
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
/*! @} */
/*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
/*! @{ */
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U)
/*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
* following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
* address > EOF data entry address The counter is cleared when the register is read.
*/
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
/*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
* MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
* 0b1..Rx Parser Error count overflow occurred
* 0b0..Rx Parser Error count overflow not occurred
*/
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
/*! @} */
/*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
/*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table.
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
/*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
* 0b0..Read operation to the Rx Parser Memory
* 0b1..Write operation to the Rx Parser Memory
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
/*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
* indicates to start the Read/Write operation from/to the Rx Parser Memory.
* 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
* 0b0..hardware not busy
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
/*! @} */
/*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
/*! @{ */
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
/*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command.
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
/*! @} */
/*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
* 0b0..Flush Transmit Queue is disabled
* 0b1..Flush Transmit Queue is enabled
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
* 0b0..Transmit Store and Forward is disabled
* 0b1..Transmit Store and Forward is enabled
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
* 0b00..Not enabled
* 0b10..Enabled
* 0b01..Enable in AV mode (Reserved in non-AV)
* 0b11..Reserved
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
* 0b011..128
* 0b100..192
* 0b101..256
* 0b000..32
* 0b110..384
* 0b111..512
* 0b001..64
* 0b010..96
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_OP_MODE */
#define ENET_QOS_MTL_TXQX_OP_MODE_COUNT (5U)
/*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
/*! @{ */
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
* controller because of Tx Queue Underflow.
*/
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
* Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
* 0b1..Overflow detected for Underflow Packet Counter
* 0b0..Overflow not detected for Underflow Packet Counter
*/
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
#define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT (5U)
/*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
/*! @{ */
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
* indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
* of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
* when PFC is enabled - Reception of 802.
* 0b1..Transmit Queue in Pause status is detected
* 0b0..Transmit Queue in Pause status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
* 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
* 0b00..Idle state
* 0b01..Read state (transferring data to the MAC transmitter)
* 0b10..Waiting for pending Tx Status from the MAC transmitter
*/
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
* Queue Write Controller is active, and it is transferring the data to the Tx Queue.
* 0b1..MTL Tx Queue Write Controller status is detected
* 0b0..MTL Tx Queue Write Controller status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
* is not empty and some data is left for transmission.
* 0b1..MTL Tx Queue Not Empty status is detected
* 0b0..MTL Tx Queue Not Empty status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
* 0b1..MTL Tx Status FIFO Full status is detected
* 0b0..MTL Tx Status FIFO Full status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
#define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
*/
#define ENET_QOS_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U)
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT (20U)
/*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
* number of status in the Tx Status FIFO of this queue.
*/
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_DBG */
#define ENET_QOS_MTL_TXQX_DBG_COUNT (5U)
/*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
/*! @{ */
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
/*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
* algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
* selected for Queue 1 traffic.
* 0b0..CBS Algorithm is disabled
* 0b1..CBS Algorithm is enabled
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
/*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
* shaper algorithm logic is not reset to zero when there is positive credit and no packet to
* transmit in Channel 1.
* 0b0..Credit Control is disabled
* 0b1..Credit Control is enabled
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
/*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
* number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
* average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
* computed for Queue.
* 0b100..16 slots
* 0b000..1 slot
* 0b001..2 slots
* 0b010..4 slots
* 0b011..8 slots
* 0b101..Reserved
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
#define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT (5U)
/*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
/*! @{ */
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
/*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot.
*/
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
#define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT (5U)
/*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
/*! @{ */
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
/*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
* traffic, this field contains the quantum value in bytes to be added to credit during every queue
* scanning cycle.
*/
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT (5U)
/*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
/*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
* sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
*/
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT (5U)
/*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
/*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
* required for the credit-based shaper algorithm.
*/
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
#define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT (5U)
/*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
/*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
* required for the credit-based shaper algorithm.
*/
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
#define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT (5U)
/*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
/*! @{ */
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
* had an underflow while transmitting the packet.
* 0b1..Transmit Queue Underflow Interrupt Status detected
* 0b0..Transmit Queue Underflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
* 0b1..Average Bits Per Slot Interrupt Status detected
* 0b0..Average Bits Per Slot Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
* 0b0..Transmit Queue Underflow Interrupt Status is disabled
* 0b1..Transmit Queue Underflow Interrupt Status is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
* sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
* 0b0..Average Bits Per Slot Interrupt is disabled
* 0b1..Average Bits Per Slot Interrupt is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
* an overflow while receiving the packet.
* 0b1..Receive Queue Overflow Interrupt Status detected
* 0b0..Receive Queue Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
* 0b0..Receive Queue Overflow Interrupt is disabled
* 0b1..Receive Queue Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT (5U)
/*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
* (in bytes): The received packet is transferred to the application or DMA when the packet size
* within the MTL Rx queue is larger than the threshold.
* 0b11..128
* 0b01..32
* 0b00..64
* 0b10..96
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
* good packets (packets with no error and length less than 64 bytes), including pad-bytes and
* CRC.
* 0b0..Forward Undersized Good Packets is disabled
* 0b1..Forward Undersized Good Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
* (CRC error, GMII_ER, watchdog timeout, or overflow).
* 0b0..Forward Error Packets is disabled
* 0b1..Forward Error Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
/*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
* from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
* of this register.
* 0b0..Receive Queue Store and Forward is disabled
* 0b1..Receive Queue Store and Forward is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
* does not drop the packets which only have the errors detected by the Receive Checksum Offload
* engine.
* 0b1..Dropping of TCP/IP Checksum Error Packets is disabled
* 0b0..Dropping of TCP/IP Checksum Error Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U)
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U)
/*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
* based on the fill-level of Rx queue, is enabled.
* 0b0..Hardware Flow Control is disabled
* 0b1..Hardware Flow Control is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT (8U)
/*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
* the threshold (fill-level of Rx queue) at which the flow control is activated: For more
* information on encoding for this field, see RFD.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT (14U)
/*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
* control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
* activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
/*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_OP_MODE */
#define ENET_QOS_MTL_RXQX_OP_MODE_COUNT (5U)
/*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
/*! @{ */
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
* DWC_ether_qos because of Receive queue overflow.
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
* Overflow Packet Counter field crossed the maximum limit.
* 0b1..Overflow Counter overflow detected
* 0b0..Overflow Counter overflow not detected
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
/*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
* DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
/*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
* Missed Packet Counter crossed the maximum limit.
* 0b1..Missed Packet Counter overflow detected
* 0b0..Missed Packet Counter overflow not detected
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
/*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
/*! @{ */
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
* Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
* 0b1..MTL Rx Queue Write Controller Active Status detected
* 0b0..MTL Rx Queue Write Controller Active Status not detected
*/
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
* 0b11..Flushing the packet data and status
* 0b00..Idle state
* 0b01..Reading packet data
* 0b10..Reading packet status (or timestamp)
*/
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
* 0b10..Rx Queue fill-level above flow-control activate threshold
* 0b01..Rx Queue fill-level below flow-control deactivate threshold
* 0b00..Rx Queue empty
* 0b11..Rx Queue full
*/
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
#define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
*/
#define ENET_QOS_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_DBG */
#define ENET_QOS_MTL_RXQX_DBG_COUNT (5U)
/*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
/*! @{ */
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
*/
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
* the packet data to the ARI interface such that the entire packet data of currently-selected
* queue is transmitted before switching to other queue.
* 0b0..Receive Queue Packet Arbitration is disabled
* 0b1..Receive Queue Packet Arbitration is enabled
*/
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_CTRL */
#define ENET_QOS_MTL_RXQX_CTRL_COUNT (5U)
/*! @name DMA_MODE - DMA Bus Mode */
/*! @{ */
#define ENET_QOS_DMA_MODE_SWR_MASK (0x1U)
#define ENET_QOS_DMA_MODE_SWR_SHIFT (0U)
/*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
* all internal registers of the DMA, MTL, and MAC.
* 0b0..Software Reset is disabled
* 0b1..Software Reset is enabled
*/
#define ENET_QOS_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
#define ENET_QOS_DMA_MODE_DSPW_MASK (0x100U)
#define ENET_QOS_DMA_MODE_DSPW_SHIFT (8U)
/*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
* 0b0..Descriptor Posted Write is disabled
* 0b1..Descriptor Posted Write is enabled
*/
#define ENET_QOS_DMA_MODE_DSPW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
#define ENET_QOS_DMA_MODE_INTM_MASK (0x30000U)
#define ENET_QOS_DMA_MODE_INTM_SHIFT (16U)
/*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
* 0b00..See above description
* 0b01..See above description
* 0b10..See above description
* 0b11..Reserved
*/
#define ENET_QOS_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
/*! @} */
/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
/*! @{ */
#define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK (0x1U)
#define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT (0U)
/*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
* of specified lengths as given below.
* 0b0..Fixed Burst Length is disabled
* 0b1..Fixed Burst Length is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK (0x2U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U)
/*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 4 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 4
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK (0x4U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U)
/*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 8 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 8
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK (0x8U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U)
/*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 16 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 16
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK (0x400U)
#define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT (10U)
/*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
* when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
* the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
* 0b0..Automatic AXI LPI is disabled
* 0b1..Automatic AXI LPI is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_AALE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
#define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
/*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
* address-aligned burst transfers on Read and Write channels.
* 0b0..Address-Aligned Beats is disabled
* 0b1..Address-Aligned Beats is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK (0x2000U)
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT (13U)
/*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
* performed by the EQOS-AXI master do not cross 1 KB boundary.
* 0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
* 0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
/*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface.
*/
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
/*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
* outstanding request on the AXI write interface.
*/
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
/*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
* the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
* is received.
* 0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
* 0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK (0x80000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U)
/*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
* by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
* controller.
* 0b0..Low Power Interface (LPI) is disabled
* 0b1..Low Power Interface (LPI) is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
/*! @} */
/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
/*! @{ */
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
* 0b1..DMA Channel 0 Interrupt Status detected
* 0b0..DMA Channel 0 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
* 0b1..DMA Channel 1 Interrupt Status detected
* 0b0..DMA Channel 1 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
/*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
* 0b1..DMA Channel 2 Interrupt Status detected
* 0b0..DMA Channel 2 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
/*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
* 0b1..DMA Channel 3 Interrupt Status detected
* 0b0..DMA Channel 3 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
/*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
* 0b1..DMA Channel 4 Interrupt Status detected
* 0b0..DMA Channel 4 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
* 0b1..MTL Interrupt Status detected
* 0b0..MTL Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
* 0b1..MAC Interrupt Status detected
* 0b0..MAC Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
/*! @} */
/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
/*! @{ */
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
/*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
* AXI master is active, and it is transferring data.
* 0b1..AXI Master Write Channel or AHB Master Status detected
* 0b0..AXI Master Write Channel or AHB Master Status not detected
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x2U)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
/*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
* the AXI master is active, and it is transferring the data.
* 0b1..AXI Master Read Channel Status detected
* 0b0..AXI Master Read Channel Status not detected
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U)
/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U)
/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U)
/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U)
/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U)
/*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U)
/*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
/*! @} */
/*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
/*! @{ */
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U)
/*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U)
/*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U)
/*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U)
/*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
/*! @} */
/*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
/*! @{ */
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
/*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
* for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
* clock cycles
*/
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
/*! @} */
/*! @name DMA_TBS_CTRL - TBS Control */
/*! @{ */
#define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK (0x1U)
#define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT (0U)
/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
* 0b0..Fetch Time Offset is invalid
* 0b1..Fetch Time Offset is valid
*/
#define ENET_QOS_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
#define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK (0x70U)
#define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT (4U)
/*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN.
*/
#define ENET_QOS_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
#define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U)
#define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT (8U)
/*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
* Launch time to compute the Fetch Time.
*/
#define ENET_QOS_DMA_TBS_CTRL_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
/*! @} */
/*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
#define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
* DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
* 0b0..8xPBL mode is disabled
* 0b1..8xPBL mode is enabled
*/
#define ENET_QOS_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
#define ENET_QOS_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
#define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT (18U)
/*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
* the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
*/
#define ENET_QOS_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CTRL */
#define ENET_QOS_DMA_CHX_CTRL_COUNT (5U)
/*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
#define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
* 0b1..Start Transmission Command
* 0b0..Stop Transmission Command
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
/*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
* packet of the Transmit data even before the status for the first packet is obtained.
* 0b0..Operate on Second Packet disabled
* 0b1..Operate on Second Packet enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT (15U)
/*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
* locations in the MTL before initiating a transfer.
* 0b0..Ignore PBL Requirement is disabled
* 0b1..Ignore PBL Requirement is enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
* transferred in one DMA block data transfer.
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U)
/*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
* Descriptors that are 32 Bytes for both Normal and Context Descriptors.
* 0b0..Enhanced Descriptor is disabled
* 0b1..Enhanced Descriptor is enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TX_CTRL */
#define ENET_QOS_DMA_CHX_TX_CTRL_COUNT (5U)
/*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
#define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
* the Receive list and processes the incoming packets.
* 0b1..Start Receive
* 0b0..Stop Receive
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0xEU)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U)
/*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF0U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
/*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
* transferred in one DMA block data transfer.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
/*! RPF - Rx Packet Flush.
* 0b0..Rx Packet Flush is disabled
* 0b1..Rx Packet Flush is enabled
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_CTRL */
#define ENET_QOS_DMA_CHX_RX_CTRL_COUNT (5U)
/*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
/*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list.
*/
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT (5U)
/*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
/*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list.
*/
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT (5U)
/*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
/*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring.
*/
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT (5U)
/*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
/*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring.
*/
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT (5U)
/*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
/*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring.
*/
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
/*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
/*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring.
*/
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
/*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
/*! @{ */
#define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK (0x1U)
#define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT (0U)
/*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
* 0b0..Transmit Interrupt is disabled
* 0b1..Transmit Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK (0x2U)
#define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT (1U)
/*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
* 0b0..Transmit Stopped is disabled
* 0b1..Transmit Stopped is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
#define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
/*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
* Transmit Buffer Unavailable interrupt is enabled.
* 0b0..Transmit Buffer Unavailable is disabled
* 0b1..Transmit Buffer Unavailable is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK (0x40U)
#define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT (6U)
/*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
* 0b0..Receive Interrupt is disabled
* 0b1..Receive Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
#define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
/*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
* Receive Buffer Unavailable interrupt is enabled.
* 0b0..Receive Buffer Unavailable is disabled
* 0b1..Receive Buffer Unavailable is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK (0x100U)
#define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT (8U)
/*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
* 0b0..Receive Stopped is disabled
* 0b1..Receive Stopped is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
#define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
/*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
* Watchdog Timeout interrupt is enabled.
* 0b0..Receive Watchdog Timeout is disabled
* 0b1..Receive Watchdog Timeout is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
#define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
/*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
* 0b0..Early Transmit Interrupt is disabled
* 0b1..Early Transmit Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
#define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
/*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
* 0b0..Early Receive Interrupt is disabled
* 0b1..Early Receive Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
#define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
/*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
* 0b0..Fatal Bus Error is disabled
* 0b1..Fatal Bus Error is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK (0x2000U)
#define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT (13U)
/*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
* 0b0..Context Descriptor Error is disabled
* 0b1..Context Descriptor Error is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
#define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT (14U)
/*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
* 0b0..Abnormal Interrupt Summary is disabled
* 0b1..Abnormal Interrupt Summary is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT (15U)
/*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
* 0b0..Normal Interrupt Summary is disabled
* 0b1..Normal Interrupt Summary is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_INT_EN */
#define ENET_QOS_DMA_CHX_INT_EN_COUNT (5U)
/*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
/*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
* cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
*/
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
/*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
* clock cycles corresponding to one unit in RWT field.
*/
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT (5U)
/*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
/*! @{ */
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
* programmed in the Tx descriptor with the current reference given in the RSN field.
* 0b0..Slot Comparison is disabled
* 0b1..Slot Comparison is enabled
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
/*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
* when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
* number given in the RSN field or - ahead of the reference slot number by up to two slots This
* bit is applicable only when the ESC bit is set.
* 0b0..Advance Slot Check is disabled
* 0b1..Advance Slot Check is enabled
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
/*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
* fetches the scheduled packets.
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
/*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
/*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
/*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
/*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT (5U)
/*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
/*! @{ */
#define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U)
#define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U)
/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
* 0b1..Transmit Interrupt status detected
* 0b0..Transmit Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
#define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U)
#define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U)
/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
* 0b1..Transmit Process Stopped status detected
* 0b0..Transmit Process Stopped status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
#define ENET_QOS_DMA_CHX_STAT_TBU_MASK (0x4U)
#define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U)
/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
* descriptor in the Transmit list, and the DMA cannot acquire it.
* 0b1..Transmit Buffer Unavailable status detected
* 0b0..Transmit Buffer Unavailable status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
#define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U)
#define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U)
/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
* 0b1..Receive Interrupt status detected
* 0b0..Receive Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
#define ENET_QOS_DMA_CHX_STAT_RBU_MASK (0x80U)
#define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U)
/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
* descriptor in the Receive list, and the DMA cannot acquire it.
* 0b1..Receive Buffer Unavailable status detected
* 0b0..Receive Buffer Unavailable status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
#define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U)
#define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U)
/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
* 0b1..Receive Process Stopped status detected
* 0b0..Receive Process Stopped status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
#define ENET_QOS_DMA_CHX_STAT_RWT_MASK (0x200U)
#define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U)
/*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
* bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
* 0b1..Receive Watchdog Timeout status detected
* 0b0..Receive Watchdog Timeout status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
#define ENET_QOS_DMA_CHX_STAT_ETI_MASK (0x400U)
#define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U)
/*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
* transfer of packet data to the MTL TXFIFO memory.
* 0b1..Early Transmit Interrupt status detected
* 0b0..Early Transmit Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
#define ENET_QOS_DMA_CHX_STAT_ERI_MASK (0x800U)
#define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U)
/*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
* transfer of packet data to the memory.
* 0b1..Early Receive Interrupt status detected
* 0b0..Early Receive Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
#define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U)
#define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U)
/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
* 0b1..Fatal Bus Error status detected
* 0b0..Fatal Bus Error status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
#define ENET_QOS_DMA_CHX_STAT_CDE_MASK (0x2000U)
#define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT (13U)
/*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
* descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
* descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
* with either of the buffer address as ones which is considered to be invalid.
* 0b1..Context Descriptor Error status detected
* 0b0..Context Descriptor Error status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
#define ENET_QOS_DMA_CHX_STAT_AIS_MASK (0x4000U)
#define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT (14U)
/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
* following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
* register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
* Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
* Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
* 0b1..Abnormal Interrupt Summary status detected
* 0b0..Abnormal Interrupt Summary status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
#define ENET_QOS_DMA_CHX_STAT_NIS_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT (15U)
/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
* following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
* register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
* Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
* enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
* 0b1..Normal Interrupt Summary status detected
* 0b0..Normal Interrupt Summary status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
#define ENET_QOS_DMA_CHX_STAT_TEB_MASK (0x70000U)
#define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT (16U)
/*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error.
*/
#define ENET_QOS_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
#define ENET_QOS_DMA_CHX_STAT_REB_MASK (0x380000U)
#define ENET_QOS_DMA_CHX_STAT_REB_SHIFT (19U)
/*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error.
*/
#define ENET_QOS_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_STAT */
#define ENET_QOS_DMA_CHX_STAT_COUNT (5U)
/*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
/*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
* dropped by the DMA either because of bus error or because of programming RPF field in
* DMA_CH2_RX_CONTROL register.
*/
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
/*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
* 0b1..Miss Frame Counter overflow occurred
* 0b0..Miss Frame Counter overflow not occurred
*/
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT (5U)
/*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
/*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1.
*/
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
/*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
* Counter field crossed the maximum limit.
* 0b1..Rx Parser Accept Counter overflow occurred
* 0b0..Rx Parser Accept Counter overflow not occurred
*/
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT (5U)
/*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU)
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U)
/*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
* for burst transfer completed by the Rx DMA from the start of packet transfer.
*/
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT (5U)
/*!
* @}
*/ /* end of group ENET_QOS_Register_Masks */
/* ENET_QOS - Peripheral instance base addresses */
/** Peripheral ENET_QOS base address */
#define ENET_QOS_BASE (0x30BF0000u)
/** Peripheral ENET_QOS base pointer */
#define ENET_QOS ((ENET_QOS_Type *)ENET_QOS_BASE)
/** Array initializer of ENET_QOS peripheral base addresses */
#define ENET_QOS_BASE_ADDRS { ENET_QOS_BASE }
/** Array initializer of ENET_QOS peripheral base pointers */
#define ENET_QOS_BASE_PTRS { ENET_QOS }
/** Interrupt vectors for the ENET_QOS peripheral type */
#define ENET_QOS_IRQS { ENET_QOS_IRQn }
#define ENET_QOS_PMT_IRQS { ENET_QOS_PMT_IRQn }
/*!
* @}
*/ /* end of group ENET_QOS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
* @{
*/
/** FLEXSPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
__IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
__IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
__IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
__IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
__IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
__IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
__IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_0[32];
__IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
__IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
__IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_1[4];
__IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
uint8_t RESERVED_2[8];
__IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
__IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
uint8_t RESERVED_3[8];
__IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
__IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */
__IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
__IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
__IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_4[24];
__I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
__I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
__I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
__I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
__I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
__I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
uint8_t RESERVED_5[8];
__I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
__O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
__IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
} FLEXSPI_Type;
/* ----------------------------------------------------------------------------
-- FLEXSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
* @{
*/
/*! @name MCR0 - Module Control Register 0 */
/*! @{ */
#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
/*! SWRESET - Software Reset
*/
#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
/*! MDIS - Module Disable
*/
#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
* 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
* 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
* 0b10..Reserved
* 0b11..Flash provided Read strobe and input from DQS pad
*/
#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
* 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
* 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
*/
#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
* 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
* 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
*/
#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
* 0b000..Divided by 1
* 0b001..Divided by 2
* 0b010..Divided by 3
* 0b011..Divided by 4
* 0b100..Divided by 5
* 0b101..Divided by 6
* 0b110..Divided by 7
* 0b111..Divided by 8
*/
#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
/*! HSEN - Half Speed Serial Flash access Enable.
* 0b0..Disable divide by 2 of serial flash clock for half speed commands.
* 0b1..Enable divide by 2 of serial flash clock for half speed commands.
*/
#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
/*! DOZEEN - Doze mode enable bit
* 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
* 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
*/
#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
* 0b0..Disable.
* 0b1..Enable.
*/
#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
* external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
* enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
* 0b0..Disable.
* 0b1..Enable.
*/
#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U)
#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U)
/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
* disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
* is correctly executed.
* 0b0..Disable.
* 0b1..Enable.
*/
#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
/*! IPGRANTWAIT - Time out wait cycle for IP command grant.
*/
#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
*/
#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */
/*! @name MCR1 - Module Control Register 1 */
/*! @{ */
#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */
/*! @name MCR2 - Module Control Register 2 */
/*! @{ */
#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
* automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
* AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
* mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
* 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
* 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
*/
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
* written with 0x1. This bit will be auto-cleared immediately.
*/
#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
* 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
* A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
* FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
* ignored.
* 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
*/
#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
* A_SCLK). In this case, port B flash access is not available. After changing the value of this
* field, MCR0[SWRESET] should be set.
* 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
* 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
*/
#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
*/
#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */
/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */
#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
* 0b0..Flash will be accessed in Individual mode.
* 0b1..Flash will be accessed in Parallel mode.
*/
#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
* 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
* 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
*/
#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
* of AHB write access, refer for more details about AHB bufferable write.
* 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
* ready after all data is transmitted to External device and AHB command finished.
* 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
* granted by arbitrator and will not wait for AHB command finished.
*/
#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
/*! PREFETCHEN - AHB Read Prefetch Enable.
*/
#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
* 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
* 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
* burst required to meet the alignment requirement.
*/
#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
/*! @} */
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
*/
#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
*/
#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
*/
#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
*/
#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U)
#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U)
/*! DATALEARNFAILEN - Data Learning failed interrupt enable.
*/
#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
*/
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
*/
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
/*! @} */
/*! @name INTR - Interrupt Register */
/*! @{ */
#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
* generated when there is IPCMDGE or IPCMDERR interrupt generated.
*/
#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
*/
#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
*/
#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
* IP command, this command will be ignored and not executed at all.
*/
#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
* AHB command, this command will be ignored and not executed at all.
*/
#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
/*! IPRXWA - IP RX FIFO watermark available interrupt.
*/
#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
/*! IPTXWE - IP TX FIFO watermark empty interrupt.
*/
#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U)
#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U)
/*! DATALEARNFAIL - Data Learning failed interrupt.
*/
#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
*/
#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
*/
#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
/*! SEQTIMEOUT - Sequence execution timeout interrupt.
*/
#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
/*! @} */
/*! @name LUTKEY - LUT Key Register */
/*! @{ */
#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
/*! KEY - The Key to lock or unlock LUT.
*/
#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */
/*! @name LUTCR - LUT Control Register */
/*! @{ */
#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
/*! LOCK - Lock LUT
*/
#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
/*! UNLOCK - Unlock LUT
*/
#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
/*! @} */
/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
/*! BUFSZ - AHB RX Buffer Size in 64 bits.
*/
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
*/
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned.
*/
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
*/
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */
/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT (8U)
/*! @name FLSHCR0 - Flash Control Register 0 */
/*! @{ */
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
/*! FLSHSZ - Flash Size in KByte.
*/
#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT (4U)
/*! @name FLSHCR1 - Flash Control Register 1 */
/*! @{ */
#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
/*! TCSS - Serial Flash CS setup time.
*/
#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
/*! TCSH - Serial Flash CS Hold time.
*/
#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
/*! WA - Word Addressable.
*/
#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
/*! CAS - Column Address Size.
*/
#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
/*! CSINTERVALUNIT - CS interval unit
* 0b0..The CS interval unit is 1 serial clock cycle
* 0b1..The CS interval unit is 256 serial clock cycle
*/
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
* deassertion and flash device Chip selection assertion. If external flash has a limitation on
* the interval between command sequences, this field should be set accordingly. If there is no
* limitation, set this field with value 0x0.
*/
#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT (4U)
/*! @name FLSHCR2 - Flash Control Register 2 */
/*! @{ */
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
*/
#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
*/
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
*/
#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
*/
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
/*! AWRWAITUNIT - AWRWAIT unit
* 0b000..The AWRWAIT unit is 2 ahb clock cycle
* 0b001..The AWRWAIT unit is 8 ahb clock cycle
* 0b010..The AWRWAIT unit is 32 ahb clock cycle
* 0b011..The AWRWAIT unit is 128 ahb clock cycle
* 0b100..The AWRWAIT unit is 512 ahb clock cycle
* 0b101..The AWRWAIT unit is 2048 ahb clock cycle
* 0b110..The AWRWAIT unit is 8192 ahb clock cycle
* 0b111..The AWRWAIT unit is 32768 ahb clock cycle
*/
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
* Refer Programmable Sequence Engine for details.
*/
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT (4U)
/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */
#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
* 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
* burst start address alignment when flash is accessed in individual mode.
* 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
* burst start address alignment when flash is accessed in individual mode.
*/
#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
* memory device on port A, this bit must be set.
* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
*/
#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
* memory device on port B, this bit must be set.
* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
*/
#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
/*! @} */
/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */
#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
/*! SFAR - Serial Flash Address for IP command.
*/
#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */
/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */
#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
*/
#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
/*! ISEQID - Sequence Index in LUT for IP command.
*/
#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
*/
#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
/*! IPAREN - Parallel mode Enabled for IP command.
* 0b0..Flash will be accessed in Individual mode.
* 0b1..Flash will be accessed in Parallel mode.
*/
#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */
/*! @name IPCMD - IP Command Register */
/*! @{ */
#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
/*! TRG - Setting this bit will trigger an IP Command.
*/
#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */
/*! @name DLPR - Data Learn Pattern Register */
/*! @{ */
#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU)
#define FLEXSPI_DLPR_DLP_SHIFT (0U)
/*! DLP - Data Learning Pattern.
*/
#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
/*! @} */
/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
*/
#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
* 0b0..IP RX FIFO would be read by processor.
* 0b1..IP RX FIFO would be read by DMA.
*/
#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
*/
#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */
/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
*/
#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
* 0b0..IP TX FIFO would be filled by processor.
* 0b1..IP TX FIFO would be filled by DMA.
*/
#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
*/
#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */
/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */
#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
/*! DLLEN - DLL calibration enable.
*/
#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
* DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
* action is edge triggered, so software need to clear this bit after set this bit (no delay
* limitation).
*/
#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock).
*/
#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
*/
#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
*/
#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */
/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT (2U)
/*! @name STS0 - Status Register 0 */
/*! @{ */
#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
* sequence executing on FlexSPI interface.
*/
#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
* sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
* (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
* this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
*/
#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
* by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
* 0b00..Triggered by AHB read command (triggered by AHB read).
* 0b01..Triggered by AHB write command (triggered by AHB Write).
* 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
* 0b11..Triggered by suspended command (resumed).
*/
#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U)
#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U)
/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
*/
#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U)
#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U)
/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning.
*/
#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
/*! @} */
/*! @name STS1 - Status Register 1 */
/*! @{ */
#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
* will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
*/
#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
* cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
* 0b0000..No error.
* 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
* 0b0011..There is unknown instruction opcode in the sequence.
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
* 0b1110..Sequence execution timeout.
*/
#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
* cleared when INTR[IPCMDERR] is write-1-clear(w1c).
*/
#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
* cleared when INTR[IPCMDERR] is write-1-clear(w1c).
* 0b0000..No error.
* 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
* 0b0011..There is unknown instruction opcode in the sequence.
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
* 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
* 0b1110..Sequence execution timeout.
* 0b1111..Flash boundary crossed.
*/
#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */
/*! @name STS2 - Status Register 2 */
/*! @{ */
#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
/*! ASLVLOCK - Flash A sample clock slave delay line locked.
*/
#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
/*! AREFLOCK - Flash A sample clock reference delay line locked.
*/
#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
*/
#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
*/
#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
/*! BSLVLOCK - Flash B sample clock slave delay line locked.
*/
#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
/*! BREFLOCK - Flash B sample clock reference delay line locked.
*/
#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
*/
#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
*/
#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */
/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
*/
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
/*! BUFID - AHB RX BUF ID for suspended command sequence.
*/
#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
/*! DATLFT - Left Data size for suspended command sequence (in byte).
*/
#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */
/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
/*! FILL - Fill level of IP RX FIFO.
*/
#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
*/
#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */
/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
/*! FILL - Fill level of IP TX FIFO.
*/
#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
*/
#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */
/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
/*! RXDATA - RX Data
*/
#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT (32U)
/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
/*! TXDATA - TX Data
*/
#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT (32U)
/*! @name LUT - LUT 0..LUT 127 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
/*! OPERAND0 - OPERAND0
*/
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
/*! NUM_PADS0 - NUM_PADS0
*/
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
/*! OPCODE0 - OPCODE
*/
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
/*! OPERAND1 - OPERAND1
*/
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
/*! NUM_PADS1 - NUM_PADS1
*/
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
/*! OPCODE1 - OPCODE1
*/
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */
/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT (128U)
/*!
* @}
*/ /* end of group FLEXSPI_Register_Masks */
/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI base address */
#define FLEXSPI_BASE (0x30BB0000u)
/** Peripheral FLEXSPI base pointer */
#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS { FLEXSPI }
/*!
* @}
*/ /* end of group FLEXSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FRAMECOMPOSER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FRAMECOMPOSER_Peripheral_Access_Layer FRAMECOMPOSER Peripheral Access Layer
* @{
*/
/** FRAMECOMPOSER - Register Layout Typedef */
typedef struct {
__IO uint8_t FC_INVIDCONF; /**< Frame Composer Input Video Configuration and HDCP Keepout Register, offset: 0x0 */
__IO uint8_t FC_INHACTIV0; /**< Frame Composer Input Video HActive Pixels Register 0, offset: 0x1 */
__IO uint8_t FC_INHACTIV1; /**< Frame Composer Input Video HActive Pixels Register 1, offset: 0x2 */
__IO uint8_t FC_INHBLANK0; /**< Frame Composer Input Video HBlank Pixels Register 0, offset: 0x3 */
__IO uint8_t FC_INHBLANK1; /**< Frame Composer Input Video HBlank Pixels Register 1, offset: 0x4 */
__IO uint8_t FC_INVACTIV0; /**< Frame Composer Input Video VActive Pixels Register 0, offset: 0x5 */
__IO uint8_t FC_INVACTIV1; /**< Frame Composer Input Video VActive Pixels Register 1, offset: 0x6 */
__IO uint8_t FC_INVBLANK; /**< Frame Composer Input Video VBlank Pixels Register, offset: 0x7 */
__IO uint8_t FC_HSYNCINDELAY0; /**< Frame Composer Input Video HSync Front Porch Register 0, offset: 0x8 */
__IO uint8_t FC_HSYNCINDELAY1; /**< Frame Composer Input Video HSync Front Porch Register 1, offset: 0x9 */
__IO uint8_t FC_HSYNCINWIDTH0; /**< Frame Composer Input Video HSync Width Register 0, offset: 0xA */
__IO uint8_t FC_HSYNCINWIDTH1; /**< Frame Composer Input Video HSync Width Register 1, offset: 0xB */
__IO uint8_t FC_VSYNCINDELAY; /**< Frame Composer Input Video VSync Front Porch Register, offset: 0xC */
__IO uint8_t FC_VSYNCINWIDTH; /**< Frame Composer Input Video VSync Width Register, offset: 0xD */
__IO uint8_t FC_INFREQ0; /**< Frame Composer Input Video Refresh Rate Register 0, offset: 0xE */
__IO uint8_t FC_INFREQ1; /**< Frame Composer Input Video Refresh Rate Register 1, offset: 0xF */
__IO uint8_t FC_INFREQ2; /**< Frame Composer Input Video Refresh Rate Register 2, offset: 0x10 */
__IO uint8_t FC_CTRLDUR; /**< Frame Composer Control Period Duration Register, offset: 0x11 */
__IO uint8_t FC_EXCTRLDUR; /**< Frame Composer Extended Control Period Duration Register, offset: 0x12 */
__IO uint8_t FC_EXCTRLSPAC; /**< Frame Composer Extended Control Period Maximum Spacing Register, offset: 0x13 */
__IO uint8_t FC_CH0PREAM; /**< Frame Composer Channel 0 Non-Preamble Data Register, offset: 0x14 */
__IO uint8_t FC_CH1PREAM; /**< Frame Composer Channel 1 Non-Preamble Data Register, offset: 0x15 */
__IO uint8_t FC_CH2PREAM; /**< Frame Composer Channel 2 Non-Preamble Data Register, offset: 0x16 */
__IO uint8_t FC_AVICONF3; /**< Frame Composer AVI Packet Configuration Register 3, offset: 0x17 */
__IO uint8_t FC_GCP; /**< Frame Composer GCP Packet Configuration Register, offset: 0x18 */
__IO uint8_t FC_AVICONF0; /**< Frame Composer AVI Packet Configuration Register 0, offset: 0x19 */
__IO uint8_t FC_AVICONF1; /**< Frame Composer AVI Packet Configuration Register 1, offset: 0x1A */
__IO uint8_t FC_AVICONF2; /**< Frame Composer AVI Packet Configuration Register 2, offset: 0x1B */
__IO uint8_t FC_AVIVID; /**< Frame Composer AVI Packet VIC Register, offset: 0x1C */
uint8_t RESERVED_0[8];
__IO uint8_t FC_AUDICONF0; /**< Frame Composer AUD Packet Configuration Register 0, offset: 0x25 */
__IO uint8_t FC_AUDICONF1; /**< Frame Composer AUD Packet Configuration Register 1, offset: 0x26 */
__IO uint8_t FC_AUDICONF2; /**< Frame Composer AUD Packet Configuration Register 2, offset: 0x27 */
__IO uint8_t FC_AUDICONF3; /**< Frame Composer AUD Packet Configuration Register 3, offset: 0x28 */
__IO uint8_t FC_VSDIEEEID0; /**< Frame Composer VSI Packet Data IEEE Register 0, offset: 0x29 */
__IO uint8_t FC_VSDSIZE; /**< Frame Composer VSI Packet Data Size Register, offset: 0x2A */
uint8_t RESERVED_1[5];
__IO uint8_t FC_VSDIEEEID1; /**< Frame Composer VSI Packet Data IEEE Register 1, offset: 0x30 */
__IO uint8_t FC_VSDIEEEID2; /**< Frame Composer VSI Packet Data IEEE Register 2, offset: 0x31 */
uint8_t RESERVED_2[48];
__IO uint8_t FC_SPDDEVICEINF; /**< Frame Composer SPD Packet Data Source Product Descriptor Register, offset: 0x62 */
__IO uint8_t FC_AUDSCONF; /**< Frame Composer Audio Sample Flat and Layout Configuration Register, offset: 0x63 */
__I uint8_t FC_AUDSSTAT; /**< Frame Composer Audio Sample Flat and Layout Status Register, offset: 0x64 */
__IO uint8_t FC_AUDSV; /**< Frame Composer Audio Sample Validity Flag Register, offset: 0x65 */
__IO uint8_t FC_AUDSU; /**< Frame Composer Audio Sample User Flag Register, offset: 0x66 */
__IO uint8_t FC_AUDSCHNL0; /**< Frame Composer Audio Sample Channel Status Configuration Register 0, offset: 0x67 */
__IO uint8_t FC_AUDSCHNL1; /**< Frame Composer Audio Sample Channel Status Configuration Register 1, offset: 0x68 */
__IO uint8_t FC_AUDSCHNL2; /**< Frame Composer Audio Sample Channel Status Configuration Register 2, offset: 0x69 */
__IO uint8_t FC_AUDSCHNL3; /**< Frame Composer Audio Sample Channel Status Configuration Register 3, offset: 0x6A */
__IO uint8_t FC_AUDSCHNL4; /**< Frame Composer Audio Sample Channel Status Configuration Register 4, offset: 0x6B */
__IO uint8_t FC_AUDSCHNL5; /**< Frame Composer Audio Sample Channel Status Configuration Register 5, offset: 0x6C */
__IO uint8_t FC_AUDSCHNL6; /**< Frame Composer Audio Sample Channel Status Configuration Register 6, offset: 0x6D */
__IO uint8_t FC_AUDSCHNL7; /**< Frame Composer Audio Sample Channel Status Configuration Register 7, offset: 0x6E */
__IO uint8_t FC_AUDSCHNL8; /**< Frame Composer Audio Sample Channel Status Configuration Register 8, offset: 0x6F */
uint8_t RESERVED_3[3];
__IO uint8_t FC_CTRLQHIGH; /**< Frame Composer Number of High Priority Packets Attended Configuration Register, offset: 0x73 */
__IO uint8_t FC_CTRLQLOW; /**< Frame Composer Number of Low Priority Packets Attended Configuration Register, offset: 0x74 */
__IO uint8_t FC_ACP0; /**< Frame Composer ACP Packet Type Configuration Register 0, offset: 0x75 */
uint8_t RESERVED_4[12];
__IO uint8_t FC_ACP16; /**< Frame Composer ACP Packet Body Configuration Register 16, offset: 0x82 */
__IO uint8_t FC_ACP15; /**< Frame Composer ACP Packet Body Configuration Register 15, offset: 0x83 */
__IO uint8_t FC_ACP14; /**< Frame Composer ACP Packet Body Configuration Register 14, offset: 0x84 */
__IO uint8_t FC_ACP13; /**< Frame Composer ACP Packet Body Configuration Register 13, offset: 0x85 */
__IO uint8_t FC_ACP12; /**< Frame Composer ACP Packet Body Configuration Register 12, offset: 0x86 */
__IO uint8_t FC_ACP11; /**< Frame Composer ACP Packet Body Configuration Register 11, offset: 0x87 */
__IO uint8_t FC_ACP10; /**< Frame Composer ACP Packet Body Configuration Register 10, offset: 0x88 */
__IO uint8_t FC_ACP9; /**< Frame Composer ACP Packet Body Configuration Register 9, offset: 0x89 */
__IO uint8_t FC_ACP8; /**< Frame Composer ACP Packet Body Configuration Register 8, offset: 0x8A */
__IO uint8_t FC_ACP7; /**< Frame Composer ACP Packet Body Configuration Register 7, offset: 0x8B */
__IO uint8_t FC_ACP6; /**< Frame Composer ACP Packet Body Configuration Register 6, offset: 0x8C */
__IO uint8_t FC_ACP5; /**< Frame Composer ACP Packet Body Configuration Register 5, offset: 0x8D */
__IO uint8_t FC_ACP4; /**< Frame Composer ACP Packet Body Configuration Register 4, offset: 0x8E */
__IO uint8_t FC_ACP3; /**< Frame Composer ACP Packet Body Configuration Register 3, offset: 0x8F */
__IO uint8_t FC_ACP2; /**< Frame Composer ACP Packet Body Configuration Register 2, offset: 0x90 */
__IO uint8_t FC_ACP1; /**< Frame Composer ACP Packet Body Configuration Register 1, offset: 0x91 */
__IO uint8_t FC_ISCR1_0; /**< Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration Register, offset: 0x92 */
__IO uint8_t FC_ISCR1_16; /**< Frame Composer ISRC1 Packet Body Register 16, offset: 0x93 */
__IO uint8_t FC_ISCR1_15; /**< Frame Composer ISRC1 Packet Body Register 15, offset: 0x94 */
__IO uint8_t FC_ISCR1_14; /**< Frame Composer ISRC1 Packet Body Register 14, offset: 0x95 */
__IO uint8_t FC_ISCR1_13; /**< Frame Composer ISRC1 Packet Body Register 13, offset: 0x96 */
__IO uint8_t FC_ISCR1_12; /**< Frame Composer ISRC1 Packet Body Register 12, offset: 0x97 */
__IO uint8_t FC_ISCR1_11; /**< Frame Composer ISRC1 Packet Body Register 11, offset: 0x98 */
__IO uint8_t FC_ISCR1_10; /**< Frame Composer ISRC1 Packet Body Register 10, offset: 0x99 */
__IO uint8_t FC_ISCR1_9; /**< Frame Composer ISRC1 Packet Body Register 9, offset: 0x9A */
__IO uint8_t FC_ISCR1_8; /**< Frame Composer ISRC1 Packet Body Register 8, offset: 0x9B */
__IO uint8_t FC_ISCR1_7; /**< Frame Composer ISRC1 Packet Body Register 7, offset: 0x9C */
__IO uint8_t FC_ISCR1_6; /**< Frame Composer ISRC1 Packet Body Register 6, offset: 0x9D */
__IO uint8_t FC_ISCR1_5; /**< Frame Composer ISRC1 Packet Body Register 5, offset: 0x9E */
__IO uint8_t FC_ISCR1_4; /**< Frame Composer ISRC1 Packet Body Register 4, offset: 0x9F */
__IO uint8_t FC_ISCR1_3; /**< Frame Composer ISRC1 Packet Body Register 3, offset: 0xA0 */
__IO uint8_t FC_ISCR1_2; /**< Frame Composer ISRC1 Packet Body Register 2, offset: 0xA1 */
__IO uint8_t FC_ISCR1_1; /**< Frame Composer ISRC1 Packet Body Register 1, offset: 0xA2 */
__IO uint8_t FC_ISCR2_15; /**< Frame Composer ISRC2 Packet Body Register 15, offset: 0xA3 */
__IO uint8_t FC_ISCR2_14; /**< Frame Composer ISRC2 Packet Body Register 14, offset: 0xA4 */
__IO uint8_t FC_ISCR2_13; /**< Frame Composer ISRC2 Packet Body Register 13, offset: 0xA5 */
__IO uint8_t FC_ISCR2_12; /**< Frame Composer ISRC2 Packet Body Register 12, offset: 0xA6 */
__IO uint8_t FC_ISCR2_11; /**< Frame Composer ISRC2 Packet Body Register 11, offset: 0xA7 */
__IO uint8_t FC_ISCR2_10; /**< Frame Composer ISRC2 Packet Body Register 10, offset: 0xA8 */
__IO uint8_t FC_ISCR2_9; /**< Frame Composer ISRC2 Packet Body Register 9, offset: 0xA9 */
__IO uint8_t FC_ISCR2_8; /**< Frame Composer ISRC2 Packet Body Register 8, offset: 0xAA */
__IO uint8_t FC_ISCR2_7; /**< Frame Composer ISRC2 Packet Body Register 7, offset: 0xAB */
__IO uint8_t FC_ISCR2_6; /**< Frame Composer ISRC2 Packet Body Register 6, offset: 0xAC */
__IO uint8_t FC_ISCR2_5; /**< Frame Composer ISRC2 Packet Body Register 5, offset: 0xAD */
__IO uint8_t FC_ISCR2_4; /**< Frame Composer ISRC2 Packet Body Register 4, offset: 0xAE */
__IO uint8_t FC_ISCR2_3; /**< Frame Composer ISRC2 Packet Body Register 3, offset: 0xAF */
__IO uint8_t FC_ISCR2_2; /**< Frame Composer ISRC2 Packet Body Register 2, offset: 0xB0 */
__IO uint8_t FC_ISCR2_1; /**< Frame Composer ISRC2 Packet Body Register 1, offset: 0xB1 */
__IO uint8_t FC_ISCR2_0; /**< Frame Composer ISRC2 Packet Body Register 0, offset: 0xB2 */
__IO uint8_t FC_DATAUTO0; /**< Frame Composer Data Island Auto Packet Scheduling Register 0 Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD, ISRC2, ISRC1 and ACP packets., offset: 0xB3 */
__IO uint8_t FC_DATAUTO1; /**< Frame Composer Data Island Auto Packet Scheduling Register 1 Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets., offset: 0xB4 */
__IO uint8_t FC_DATAUTO2; /**< Frame Composer Data Island Auto packet scheduling Register 2 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets., offset: 0xB5 */
__O uint8_t FC_DATMAN; /**< Frame Composer Data Island Manual Packet Request Register Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested., offset: 0xB6 */
__IO uint8_t FC_DATAUTO3; /**< Frame Composer Data Island Auto Packet Scheduling Register 3 Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP, AUDI and ACR packets., offset: 0xB7 */
__IO uint8_t FC_RDRB0; /**< Frame Composer Round Robin ACR Packet Insertion Register 0 Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xB8 */
__IO uint8_t FC_RDRB1; /**< Frame Composer Round Robin ACR Packet Insertion Register 1 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the ACR packet insertion on data island when FC is on RDRB mode this packet., offset: 0xB9 */
__IO uint8_t FC_RDRB2; /**< Frame Composer Round Robin AUDI Packet Insertion Register 2 Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBA */
__IO uint8_t FC_RDRB3; /**< Frame Composer Round Robin AUDI Packet Insertion Register 3 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AUDI packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBB */
__IO uint8_t FC_RDRB4; /**< Frame Composer Round Robin GCP Packet Insertion Register 4 Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBC */
__IO uint8_t FC_RDRB5; /**< Frame Composer Round Robin GCP Packet Insertion Register 5 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the GCP packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBD */
__IO uint8_t FC_RDRB6; /**< Frame Composer Round Robin AVI Packet Insertion Register 6 Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data island when FC is on RDRB mode for this packet., offset: 0xBE */
__IO uint8_t FC_RDRB7; /**< Frame Composer Round Robin AVI Packet Insertion Register 7 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AVI packet insertion on data island when FC is on RDRB mode this packet., offset: 0xBF */
__IO uint8_t FC_RDRB8; /**< Frame Composer Round Robin AMP Packet Insertion Register 8, offset: 0xC0 */
__IO uint8_t FC_RDRB9; /**< Frame Composer Round Robin AMP Packet Insertion Register 9, offset: 0xC1 */
__IO uint8_t FC_RDRB10; /**< Frame Composer Round Robin NTSC VBI Packet Insertion Register 10, offset: 0xC2 */
__IO uint8_t FC_RDRB11; /**< Frame Composer Round Robin NTSC VBI Packet Insertion Register 11, offset: 0xC3 */
__IO uint8_t FC_RDRB12; /**< Frame Composer Round Robin DRM Packet Insertion Register 12, offset: 0xC4 */
__IO uint8_t FC_RDRB13; /**< Frame Composer Round Robin DRM Packet Insertion Register 13, offset: 0xC5 */
uint8_t RESERVED_5[12];
__IO uint8_t FC_MASK0; /**< Frame Composer Packet Interrupt Mask Register 0, offset: 0xD2 */
uint8_t RESERVED_6[3];
__IO uint8_t FC_MASK1; /**< Frame Composer Packet Interrupt Mask Register 1, offset: 0xD6 */
uint8_t RESERVED_7[3];
__IO uint8_t FC_MASK2; /**< Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2, offset: 0xDA */
uint8_t RESERVED_8[5];
__IO uint8_t FC_PRCONF; /**< Frame Composer Pixel Repetition Configuration Register, offset: 0xE0 */
__IO uint8_t FC_SCRAMBLER_CTRL; /**< Frame Composer Scrambler Control, offset: 0xE1 */
__IO uint8_t FC_MULTISTREAM_CTRL; /**< Frame Composer Multi-Stream Audio Control, offset: 0xE2 */
__IO uint8_t FC_PACKET_TX_EN; /**< Frame Composer Packet Transmission Control, offset: 0xE3 */
uint8_t RESERVED_9[4];
__IO uint8_t FC_ACTSPC_HDLR_CFG; /**< Frame Composer Active Space Control, offset: 0xE8 */
__IO uint8_t FC_INVACT_2D_0; /**< Frame Composer Input Video 2D VActive Pixels Register 0, offset: 0xE9 */
__IO uint8_t FC_INVACT_2D_1; /**< Frame Composer Input Video VActive pixels Register 1, offset: 0xEA */
uint8_t RESERVED_10[21];
__I uint8_t FC_GMD_STAT; /**< Frame Composer GMD Packet Status Register Gamut metadata packet status bit information for no_current_gmd, next_gmd_field, gmd_packet_sequence and current_gamut_seq_num., offset: 0x100 */
__IO uint8_t FC_GMD_EN; /**< Frame Composer GMD Packet Enable Register This register enables Gamut metadata (GMD) packet transmission., offset: 0x101 */
__O uint8_t FC_GMD_UP; /**< Frame Composer GMD Packet Update Register This register performs an GMD packet content update according to the configured packet body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB)., offset: 0x102 */
__IO uint8_t FC_GMD_CONF; /**< Frame Composer GMD Packet Schedule Configuration Register This register configures the number of GMD packets to be inserted per frame (starting always in the line where the active Vsync appears) and the line spacing between the transmitted GMD packets., offset: 0x103 */
__IO uint8_t FC_GMD_HB; /**< Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits., offset: 0x104 */
uint8_t RESERVED_11[35];
__IO uint8_t FC_AMP_HB1; /**< Frame Composer AMP Packet Header Register 1, offset: 0x128 */
__IO uint8_t FC_AMP_HB2; /**< Frame Composer AMP Packet Header Register 2, offset: 0x129 */
uint8_t RESERVED_12[30];
__IO uint8_t FC_NVBI_HB1; /**< Frame Composer NTSC VBI Packet Header Register 1, offset: 0x148 */
__IO uint8_t FC_NVBI_HB2; /**< Frame Composer NTSC VBI Packet Header Register 2, offset: 0x149 */
uint8_t RESERVED_13[29];
__O uint8_t FC_DRM_UP; /**< Frame Composer DRM Packet Update Register This register performs an DRM packet content update according to the configured packet body (FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB)., offset: 0x167 */
uint8_t RESERVED_14[152];
__IO uint8_t FC_DBGFORCE; /**< Frame Composer video/audio Force Enable Register This register allows to force the controller to output audio and video data the values configured in the FC_DBGAUD and FC_DBGTMDS registers., offset: 0x200 */
__IO uint8_t FC_DBGAUD0CH0; /**< Frame Composer Audio Data Channel 0 Register 0 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x201 */
__IO uint8_t FC_DBGAUD1CH0; /**< Frame Composer Audio Data Channel 0 Register 1 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x202 */
__IO uint8_t FC_DBGAUD2CH0; /**< Frame Composer Audio Data Channel 0 Register 2 Configures the audio fixed data to be used in channel 0 when in fixed audio selection., offset: 0x203 */
__IO uint8_t FC_DBGAUD0CH1; /**< Frame Composer Audio Data Channel 1 Register 0 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x204 */
__IO uint8_t FC_DBGAUD1CH1; /**< Frame Composer Audio Data Channel 1 Register 1 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x205 */
__IO uint8_t FC_DBGAUD2CH1; /**< Frame Composer Audio Data Channel 1 Register 2 Configures the audio fixed data to be used in channel 1 when in fixed audio selection., offset: 0x206 */
__IO uint8_t FC_DBGAUD0CH2; /**< Frame Composer Audio Data Channel 2 Register 0 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x207 */
__IO uint8_t FC_DBGAUD1CH2; /**< Frame Composer Audio Data Channel 2 Register 1 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x208 */
__IO uint8_t FC_DBGAUD2CH2; /**< Frame Composer Audio Data Channel 2 Register 2 Configures the audio fixed data to be used in channel 2 when in fixed audio selection., offset: 0x209 */
__IO uint8_t FC_DBGAUD0CH3; /**< Frame Composer Audio Data Channel 3 Register 0 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20A */
__IO uint8_t FC_DBGAUD1CH3; /**< Frame Composer Audio Data Channel 3 Register 1 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20B */
__IO uint8_t FC_DBGAUD2CH3; /**< Frame Composer Audio Data Channel 3 Register 2 Configures the audio fixed data to be used in channel 3 when in fixed audio selection., offset: 0x20C */
__IO uint8_t FC_DBGAUD0CH4; /**< Frame Composer Audio Data Channel 4 Register 0 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20D */
__IO uint8_t FC_DBGAUD1CH4; /**< Frame Composer Audio Data Channel 4 Register 1 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20E */
__IO uint8_t FC_DBGAUD2CH4; /**< Frame Composer Audio Data Channel 4 Register 2 Configures the audio fixed data to be used in channel 4 when in fixed audio selection., offset: 0x20F */
__IO uint8_t FC_DBGAUD0CH5; /**< Frame Composer Audio Data Channel 5 Register 0 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x210 */
__IO uint8_t FC_DBGAUD1CH5; /**< Frame Composer Audio Data Channel 5 Register 1 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x211 */
__IO uint8_t FC_DBGAUD2CH5; /**< Frame Composer Audio Data Channel 5 Register 2 Configures the audio fixed data to be used in channel 5 when in fixed audio selection., offset: 0x212 */
__IO uint8_t FC_DBGAUD0CH6; /**< Frame Composer Audio Data Channel 6 Register 0 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x213 */
__IO uint8_t FC_DBGAUD1CH6; /**< Frame Composer Audio Data Channel 6 Register 1 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x214 */
__IO uint8_t FC_DBGAUD2CH6; /**< Frame Composer Audio Data Channel 6 Register 2 Configures the audio fixed data to be used in channel 6 when in fixed audio selection., offset: 0x215 */
__IO uint8_t FC_DBGAUD0CH7; /**< Frame Composer Audio Data Channel 7 Register 0 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x216 */
__IO uint8_t FC_DBGAUD1CH7; /**< Frame Composer Audio Data Channel 7 Register 1 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x217 */
__IO uint8_t FC_DBGAUD2CH7; /**< Frame Composer Audio Data Channel 7 Register 2 Configures the audio fixed data to be used in channel 7 when in fixed audio selection., offset: 0x218 */
} FRAMECOMPOSER_Type;
/* ----------------------------------------------------------------------------
-- FRAMECOMPOSER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FRAMECOMPOSER_Register_Masks FRAMECOMPOSER Register Masks
* @{
*/
/*! @name FC_INVIDCONF - Frame Composer Input Video Configuration and HDCP Keepout Register */
/*! @{ */
#define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_MASK (0x1U)
#define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_SHIFT (0U)
/*! in_I_P - Input video mode: 1b: Interlaced 0b: Progressive
*/
#define FRAMECOMPOSER_FC_INVIDCONF_IN_I_P(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_IN_I_P_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK (0x2U)
#define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_SHIFT (1U)
/*! r_v_blank_in_osc - Used for CEA861-D modes with fractional Vblank (for example, modes 5, 6, 7, 10, 11, 20, 21, and 22).
*/
#define FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_MASK (0x8U)
#define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_SHIFT (3U)
/*! DVI_modez - Active low 0b: DVI mode selected 1b: HDMI mode selected
*/
#define FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_DVI_MODEZ_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_MASK (0x10U)
#define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_SHIFT (4U)
/*! de_in_polarity - Data enable input polarity 1b: Active high 0b: Active low
*/
#define FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_DE_IN_POLARITY_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK (0x20U)
#define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_SHIFT (5U)
/*! hsync_in_polarity - Hsync input polarity 1b: Active high 0b: Active low
*/
#define FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK (0x40U)
#define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_SHIFT (6U)
/*! vsync_in_polarity - Vsync input polarity 1b: Active high 0b: Active low
*/
#define FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK)
#define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_MASK (0x80U)
#define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_SHIFT (7U)
/*! HDCP_keepout - Start/stop HDCP keepout window generation 1b: Active
*/
#define FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_SHIFT)) & FRAMECOMPOSER_FC_INVIDCONF_HDCP_KEEPOUT_MASK)
/*! @} */
/*! @name FC_INHACTIV0 - Frame Composer Input Video HActive Pixels Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_SHIFT (0U)
/*! H_in_activ - Input video Horizontal active pixel region width.
*/
#define FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV0_H_IN_ACTIV_MASK)
/*! @} */
/*! @name FC_INHACTIV1 - Frame Composer Input Video HActive Pixels Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_MASK (0xFU)
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_SHIFT (0U)
/*! H_in_activ - Input video Horizontal active pixel region width
*/
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_MASK)
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_MASK (0x10U)
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_SHIFT (4U)
/*! H_in_activ_12 - Input video Horizontal active pixel region width (0 .
*/
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_12_MASK)
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_MASK (0x20U)
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_SHIFT (5U)
/*! H_in_activ_13 - Input video Horizontal active pixel region width (0 .
*/
#define FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_SHIFT)) & FRAMECOMPOSER_FC_INHACTIV1_H_IN_ACTIV_13_MASK)
/*! @} */
/*! @name FC_INHBLANK0 - Frame Composer Input Video HBlank Pixels Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_SHIFT (0U)
/*! H_in_blank - Input video Horizontal blanking pixel region width.
*/
#define FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK0_H_IN_BLANK_MASK)
/*! @} */
/*! @name FC_INHBLANK1 - Frame Composer Input Video HBlank Pixels Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_MASK (0x3U)
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_SHIFT (0U)
/*! H_in_blank - Input video Horizontal blanking pixel region width this bit field holds bits 9:8 of
* number of Horizontal blanking pixels.
*/
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_MASK)
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_MASK (0x1CU)
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_SHIFT (2U)
/*! H_in_blank_12 - Input video Horizontal blanking pixel region width If configuration parameter
* DWC_HDMI_TX_14 = True (1), this bit field holds bit 12:10 of number of horizontal blanking
* pixels.
*/
#define FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_SHIFT)) & FRAMECOMPOSER_FC_INHBLANK1_H_IN_BLANK_12_MASK)
/*! @} */
/*! @name FC_INVACTIV0 - Frame Composer Input Video VActive Pixels Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_SHIFT (0U)
/*! V_in_activ - Input video Vertical active pixel region width.
*/
#define FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV0_V_IN_ACTIV_MASK)
/*! @} */
/*! @name FC_INVACTIV1 - Frame Composer Input Video VActive Pixels Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_MASK (0x7U)
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_SHIFT (0U)
/*! V_in_activ - Input video Vertical active pixel region width.
*/
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_MASK)
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_MASK (0x18U)
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_SHIFT (3U)
/*! V_in_activ_12_11 - Input video Vertical active pixel region width.
*/
#define FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_SHIFT)) & FRAMECOMPOSER_FC_INVACTIV1_V_IN_ACTIV_12_11_MASK)
/*! @} */
/*! @name FC_INVBLANK - Frame Composer Input Video VBlank Pixels Register */
/*! @{ */
#define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_SHIFT (0U)
/*! V_in_blank - Input video Vertical blanking pixel region width.
*/
#define FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_SHIFT)) & FRAMECOMPOSER_FC_INVBLANK_V_IN_BLANK_MASK)
/*! @} */
/*! @name FC_HSYNCINDELAY0 - Frame Composer Input Video HSync Front Porch Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_MASK (0xFFU)
#define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_SHIFT (0U)
/*! H_in_delay - Input video Hsync active edge delay.
*/
#define FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY0_H_IN_DELAY_MASK)
/*! @} */
/*! @name FC_HSYNCINDELAY1 - Frame Composer Input Video HSync Front Porch Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_MASK (0x7U)
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_SHIFT (0U)
/*! H_in_delay - Input video Horizontal active edge delay.
*/
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_MASK)
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_MASK (0x18U)
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_SHIFT (3U)
/*! H_in_delay_12 - Input video Horizontal active edge delay.
*/
#define FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINDELAY1_H_IN_DELAY_12_MASK)
/*! @} */
/*! @name FC_HSYNCINWIDTH0 - Frame Composer Input Video HSync Width Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_MASK (0xFFU)
#define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_SHIFT (0U)
/*! H_in_width - Input video Hsync active pulse width.
*/
#define FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH0_H_IN_WIDTH_MASK)
/*! @} */
/*! @name FC_HSYNCINWIDTH1 - Frame Composer Input Video HSync Width Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_MASK (0x1U)
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_SHIFT (0U)
/*! H_in_width - Input video Hsync active pulse width.
*/
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_MASK)
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_MASK (0x2U)
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_SHIFT (1U)
/*! H_in_width_9 - Input video Hsync active pulse width.
*/
#define FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_SHIFT)) & FRAMECOMPOSER_FC_HSYNCINWIDTH1_H_IN_WIDTH_9_MASK)
/*! @} */
/*! @name FC_VSYNCINDELAY - Frame Composer Input Video VSync Front Porch Register */
/*! @{ */
#define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_MASK (0xFFU)
#define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_SHIFT (0U)
/*! V_in_delay - Input video Vsync active edge delay.
*/
#define FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_SHIFT)) & FRAMECOMPOSER_FC_VSYNCINDELAY_V_IN_DELAY_MASK)
/*! @} */
/*! @name FC_VSYNCINWIDTH - Frame Composer Input Video VSync Width Register */
/*! @{ */
#define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_MASK (0x3FU)
#define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_SHIFT (0U)
/*! V_in_width - Input video Vsync active pulse width.
*/
#define FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_SHIFT)) & FRAMECOMPOSER_FC_VSYNCINWIDTH_V_IN_WIDTH_MASK)
/*! @} */
/*! @name FC_INFREQ0 - Frame Composer Input Video Refresh Rate Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_INFREQ0_INFREQ_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INFREQ0_INFREQ_SHIFT (0U)
/*! infreq - Video refresh rate in Hz*1E3 format.
*/
#define FRAMECOMPOSER_FC_INFREQ0_INFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ0_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ0_INFREQ_MASK)
/*! @} */
/*! @name FC_INFREQ1 - Frame Composer Input Video Refresh Rate Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_INFREQ1_INFREQ_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INFREQ1_INFREQ_SHIFT (0U)
/*! infreq - Video refresh rate in Hz*1E3 format.
*/
#define FRAMECOMPOSER_FC_INFREQ1_INFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ1_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ1_INFREQ_MASK)
/*! @} */
/*! @name FC_INFREQ2 - Frame Composer Input Video Refresh Rate Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_INFREQ2_INFREQ_MASK (0xFU)
#define FRAMECOMPOSER_FC_INFREQ2_INFREQ_SHIFT (0U)
/*! infreq - Video refresh rate in Hz*1E3 format.
*/
#define FRAMECOMPOSER_FC_INFREQ2_INFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INFREQ2_INFREQ_SHIFT)) & FRAMECOMPOSER_FC_INFREQ2_INFREQ_MASK)
/*! @} */
/*! @name FC_CTRLDUR - Frame Composer Control Period Duration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_MASK (0xFFU)
#define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_SHIFT (0U)
/*! ctrlperiodduration - Configuration of the control period minimum duration (minimum of 12 pixel clock cycles; refer to HDMI 1.
*/
#define FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_SHIFT)) & FRAMECOMPOSER_FC_CTRLDUR_CTRLPERIODDURATION_MASK)
/*! @} */
/*! @name FC_EXCTRLDUR - Frame Composer Extended Control Period Duration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_MASK (0xFFU)
#define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_SHIFT (0U)
/*! exctrlperiodduration - Configuration of the extended control period minimum duration (minimum of 32 pixel clock cycles; refer to HDMI 1.
*/
#define FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_SHIFT)) & FRAMECOMPOSER_FC_EXCTRLDUR_EXCTRLPERIODDURATION_MASK)
/*! @} */
/*! @name FC_EXCTRLSPAC - Frame Composer Extended Control Period Maximum Spacing Register */
/*! @{ */
#define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_MASK (0xFFU)
#define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_SHIFT (0U)
/*! exctrlperiodspacing - Configuration of the maximum spacing between consecutive extended control
* periods (maximum of 50ms; refer to the applicable HDMI specification).
*/
#define FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_SHIFT)) & FRAMECOMPOSER_FC_EXCTRLSPAC_EXCTRLPERIODSPACING_MASK)
/*! @} */
/*! @name FC_CH0PREAM - Frame Composer Channel 0 Non-Preamble Data Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_MASK (0xFFU)
#define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_SHIFT (0U)
/*! ch0_preamble_filter - When in control mode, configures 8 bits that fill the channel 0 data lines
* not used to transmit the preamble (for more clarification, refer to the HDMI 1.
*/
#define FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH0PREAM_CH0_PREAMBLE_FILTER_MASK)
/*! @} */
/*! @name FC_CH1PREAM - Frame Composer Channel 1 Non-Preamble Data Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_MASK (0x3FU)
#define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_SHIFT (0U)
/*! ch1_preamble_filter - When in control mode, configures 6 bits that fill the channel 1 data lines
* not used to transmit the preamble (for more clarification, refer to the HDMI 1.
*/
#define FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH1PREAM_CH1_PREAMBLE_FILTER_MASK)
/*! @} */
/*! @name FC_CH2PREAM - Frame Composer Channel 2 Non-Preamble Data Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_MASK (0x3FU)
#define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_SHIFT (0U)
/*! ch2_preamble_filter - When in control mode, configures 6 bits that fill the channel 2 data lines
* not used to transmit the preamble (for more clarification, refer to the HDMI 1.
*/
#define FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_SHIFT)) & FRAMECOMPOSER_FC_CH2PREAM_CH2_PREAMBLE_FILTER_MASK)
/*! @} */
/*! @name FC_AVICONF3 - Frame Composer AVI Packet Configuration Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_AVICONF3_CN_MASK (0x3U)
#define FRAMECOMPOSER_FC_AVICONF3_CN_SHIFT (0U)
/*! CN - IT content type according to CEA the specification
*/
#define FRAMECOMPOSER_FC_AVICONF3_CN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF3_CN_SHIFT)) & FRAMECOMPOSER_FC_AVICONF3_CN_MASK)
#define FRAMECOMPOSER_FC_AVICONF3_YQ_MASK (0xCU)
#define FRAMECOMPOSER_FC_AVICONF3_YQ_SHIFT (2U)
/*! YQ - YCbCr Quantization range according to the CEA specification
*/
#define FRAMECOMPOSER_FC_AVICONF3_YQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF3_YQ_SHIFT)) & FRAMECOMPOSER_FC_AVICONF3_YQ_MASK)
/*! @} */
/*! @name FC_GCP - Frame Composer GCP Packet Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_MASK (0x1U)
#define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_SHIFT (0U)
/*! clear_avmute - Value of "clear_avmute" in the GCP packet
*/
#define FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_SHIFT)) & FRAMECOMPOSER_FC_GCP_CLEAR_AVMUTE_MASK)
#define FRAMECOMPOSER_FC_GCP_SET_AVMUTE_MASK (0x2U)
#define FRAMECOMPOSER_FC_GCP_SET_AVMUTE_SHIFT (1U)
/*! set_avmute - Value of "set_avmute" in the GCP packet Once the AVmute is set, the frame composer
* schedules the GCP packet with AVmute set in the packet scheduler to be sent once (may only be
* transmitted between the active edge of VSYNC and 384 pixels following this edge).
*/
#define FRAMECOMPOSER_FC_GCP_SET_AVMUTE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_SET_AVMUTE_SHIFT)) & FRAMECOMPOSER_FC_GCP_SET_AVMUTE_MASK)
#define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_MASK (0x4U)
#define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_SHIFT (2U)
/*! default_phase - Value of "default_phase" in the GCP packet.
*/
#define FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_SHIFT)) & FRAMECOMPOSER_FC_GCP_DEFAULT_PHASE_MASK)
/*! @} */
/*! @name FC_AVICONF0 - Frame Composer AVI Packet Configuration Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_MASK (0x3U)
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_SHIFT (0U)
/*! rgc_ycc_indication - Y1,Y0 RGB or YCbCr indicator
*/
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_MASK)
#define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_MASK (0xCU)
#define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_SHIFT (2U)
/*! bar_information - Bar information data valid
*/
#define FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_BAR_INFORMATION_MASK)
#define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_MASK (0x30U)
#define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_SHIFT (4U)
/*! scan_information - Scan information
*/
#define FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_SCAN_INFORMATION_MASK)
#define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_MASK (0x40U)
#define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_SHIFT (6U)
/*! active_format_present - Active format present
*/
#define FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_ACTIVE_FORMAT_PRESENT_MASK)
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_MASK (0x80U)
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_SHIFT (7U)
/*! rgc_ycc_indication_2 - Y2, Bit 2 of rgc_ycc_indication
*/
#define FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_SHIFT)) & FRAMECOMPOSER_FC_AVICONF0_RGC_YCC_INDICATION_2_MASK)
/*! @} */
/*! @name FC_AVICONF1 - Frame Composer AVI Packet Configuration Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK (0xFU)
#define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_SHIFT (0U)
/*! active_aspect_ratio - Active aspect ratio
*/
#define FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK)
#define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_MASK (0x30U)
#define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_SHIFT (4U)
/*! picture_aspect_ratio - Picture aspect ratio
*/
#define FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_PICTURE_ASPECT_RATIO_MASK)
#define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_MASK (0xC0U)
#define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_SHIFT (6U)
/*! Colorimetry - Colorimetry
*/
#define FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_SHIFT)) & FRAMECOMPOSER_FC_AVICONF1_COLORIMETRY_MASK)
/*! @} */
/*! @name FC_AVICONF2 - Frame Composer AVI Packet Configuration Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_MASK (0x3U)
#define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_SHIFT (0U)
/*! non_uniform_picture_scaling - Non-uniform picture scaling
*/
#define FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_NON_UNIFORM_PICTURE_SCALING_MASK)
#define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_MASK (0xCU)
#define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_SHIFT (2U)
/*! quantization_range - Quantization range
*/
#define FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_QUANTIZATION_RANGE_MASK)
#define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_MASK (0x70U)
#define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_SHIFT (4U)
/*! extended_colorimetry - Extended colorimetry
*/
#define FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_EXTENDED_COLORIMETRY_MASK)
#define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_MASK (0x80U)
#define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_SHIFT (7U)
/*! it_content - IT content
*/
#define FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_SHIFT)) & FRAMECOMPOSER_FC_AVICONF2_IT_CONTENT_MASK)
/*! @} */
/*! @name FC_AVIVID - Frame Composer AVI Packet VIC Register */
/*! @{ */
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_MASK (0x7FU)
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_SHIFT (0U)
/*! fc_avivid - Configures the AVI InfoFrame Video Identification code.
*/
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_SHIFT)) & FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_MASK)
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_MASK (0x80U)
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_SHIFT (7U)
/*! fc_avivid_7 - Bit 7 of fc_avivid register
*/
#define FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_SHIFT)) & FRAMECOMPOSER_FC_AVIVID_FC_AVIVID_7_MASK)
/*! @} */
/*! @name FC_AUDICONF0 - Frame Composer AUD Packet Configuration Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDICONF0_CT_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDICONF0_CT_SHIFT (0U)
/*! CT - Coding Type
*/
#define FRAMECOMPOSER_FC_AUDICONF0_CT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF0_CT_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF0_CT_MASK)
#define FRAMECOMPOSER_FC_AUDICONF0_CC_MASK (0x70U)
#define FRAMECOMPOSER_FC_AUDICONF0_CC_SHIFT (4U)
/*! CC - Channel count
*/
#define FRAMECOMPOSER_FC_AUDICONF0_CC(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF0_CC_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF0_CC_MASK)
/*! @} */
/*! @name FC_AUDICONF1 - Frame Composer AUD Packet Configuration Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDICONF1_SF_MASK (0x7U)
#define FRAMECOMPOSER_FC_AUDICONF1_SF_SHIFT (0U)
/*! SF - Sampling frequency
*/
#define FRAMECOMPOSER_FC_AUDICONF1_SF(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF1_SF_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF1_SF_MASK)
#define FRAMECOMPOSER_FC_AUDICONF1_SS_MASK (0x30U)
#define FRAMECOMPOSER_FC_AUDICONF1_SS_SHIFT (4U)
/*! SS - Sampling size
*/
#define FRAMECOMPOSER_FC_AUDICONF1_SS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF1_SS_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF1_SS_MASK)
/*! @} */
/*! @name FC_AUDICONF2 - Frame Composer AUD Packet Configuration Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDICONF2_CA_MASK (0xFFU)
#define FRAMECOMPOSER_FC_AUDICONF2_CA_SHIFT (0U)
/*! CA - Channel allocation
*/
#define FRAMECOMPOSER_FC_AUDICONF2_CA(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF2_CA_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF2_CA_MASK)
/*! @} */
/*! @name FC_AUDICONF3 - Frame Composer AUD Packet Configuration Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDICONF3_LSV_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDICONF3_LSV_SHIFT (0U)
/*! LSV - Level shift value (for down mixing)
*/
#define FRAMECOMPOSER_FC_AUDICONF3_LSV(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_LSV_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_LSV_MASK)
#define FRAMECOMPOSER_FC_AUDICONF3_DM_INH_MASK (0x10U)
#define FRAMECOMPOSER_FC_AUDICONF3_DM_INH_SHIFT (4U)
/*! DM_INH - Down mix enable
*/
#define FRAMECOMPOSER_FC_AUDICONF3_DM_INH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_DM_INH_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_DM_INH_MASK)
#define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_MASK (0x60U)
#define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_SHIFT (5U)
/*! LFEPBL - LFE playback information LFEPBL1, LFEPBL0 LFE playback level as compared to the other channels.
*/
#define FRAMECOMPOSER_FC_AUDICONF3_LFEPBL(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_SHIFT)) & FRAMECOMPOSER_FC_AUDICONF3_LFEPBL_MASK)
/*! @} */
/*! @name FC_VSDIEEEID0 - Frame Composer VSI Packet Data IEEE Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_MASK (0xFFU)
#define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_SHIFT (0U)
/*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier.
*/
#define FRAMECOMPOSER_FC_VSDIEEEID0_IEEE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID0_IEEE_MASK)
/*! @} */
/*! @name FC_VSDSIZE - Frame Composer VSI Packet Data Size Register */
/*! @{ */
#define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_MASK (0x1FU)
#define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_SHIFT (0U)
/*! VSDSIZE - Packet size as described in the HDMI Vendor Specific InfoFrame (from the HDMI specification).
*/
#define FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_SHIFT)) & FRAMECOMPOSER_FC_VSDSIZE_VSDSIZE_MASK)
/*! @} */
/*! @name FC_VSDIEEEID1 - Frame Composer VSI Packet Data IEEE Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_MASK (0xFFU)
#define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_SHIFT (0U)
/*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier.
*/
#define FRAMECOMPOSER_FC_VSDIEEEID1_IEEE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID1_IEEE_MASK)
/*! @} */
/*! @name FC_VSDIEEEID2 - Frame Composer VSI Packet Data IEEE Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_MASK (0xFFU)
#define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_SHIFT (0U)
/*! IEEE - This register configures the Vendor Specific InfoFrame IEEE registration identifier.
*/
#define FRAMECOMPOSER_FC_VSDIEEEID2_IEEE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_SHIFT)) & FRAMECOMPOSER_FC_VSDIEEEID2_IEEE_MASK)
/*! @} */
/*! @name FC_SPDDEVICEINF - Frame Composer SPD Packet Data Source Product Descriptor Register */
/*! @{ */
#define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_MASK (0xFFU)
#define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_SHIFT (0U)
/*! fc_spddeviceinf - Frame Composer SPD Packet Data Source Product Descriptor Register
*/
#define FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_SHIFT)) & FRAMECOMPOSER_FC_SPDDEVICEINF_FC_SPDDEVICEINF_MASK)
/*! @} */
/*! @name FC_AUDSCONF - Frame Composer Audio Sample Flat and Layout Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK (0x1U)
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_SHIFT (0U)
/*! aud_packet_layout - Set the audio packet layout to be sent in the packet: 1b: layout 1 0b:
* layout 0 If DWC_HDMI_TX_20 is defined and register field fc_multistream_ctrl.
*/
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK)
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_SHIFT (4U)
/*! aud_packet_sampflt - Set the audio packet sample flat value to be sent on the packet.
*/
#define FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCONF_AUD_PACKET_SAMPFLT_MASK)
/*! @} */
/*! @name FC_AUDSSTAT - Frame Composer Audio Sample Flat and Layout Status Register */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_SHIFT (0U)
/*! packet_sampprs - Shows the data sample present indication of the last Audio sample packet sent by the HDMI TX Controller.
*/
#define FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_SHIFT)) & FRAMECOMPOSER_FC_AUDSSTAT_PACKET_SAMPPRS_MASK)
/*! @} */
/*! @name FC_AUDSV - Frame Composer Audio Sample Validity Flag Register */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSV_V0L_MASK (0x1U)
#define FRAMECOMPOSER_FC_AUDSV_V0L_SHIFT (0U)
/*! V0l - Set validity bit "V" for Channel 0, Left
*/
#define FRAMECOMPOSER_FC_AUDSV_V0L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V0L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V0L_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V1L_MASK (0x2U)
#define FRAMECOMPOSER_FC_AUDSV_V1L_SHIFT (1U)
/*! V1l - Set validity bit "V" for Channel 1, Left
*/
#define FRAMECOMPOSER_FC_AUDSV_V1L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V1L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V1L_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V2L_MASK (0x4U)
#define FRAMECOMPOSER_FC_AUDSV_V2L_SHIFT (2U)
/*! V2l - Set validity bit "V" for Channel 2, Left
*/
#define FRAMECOMPOSER_FC_AUDSV_V2L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V2L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V2L_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V3L_MASK (0x8U)
#define FRAMECOMPOSER_FC_AUDSV_V3L_SHIFT (3U)
/*! V3l - Set validity bit "V" for Channel 3, Left
*/
#define FRAMECOMPOSER_FC_AUDSV_V3L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V3L_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V3L_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V0R_MASK (0x10U)
#define FRAMECOMPOSER_FC_AUDSV_V0R_SHIFT (4U)
/*! V0r - Set validity bit "V" for Channel 0, Right
*/
#define FRAMECOMPOSER_FC_AUDSV_V0R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V0R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V0R_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V1R_MASK (0x20U)
#define FRAMECOMPOSER_FC_AUDSV_V1R_SHIFT (5U)
/*! V1r - Set validity bit "V" for Channel 1, Right
*/
#define FRAMECOMPOSER_FC_AUDSV_V1R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V1R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V1R_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V2R_MASK (0x40U)
#define FRAMECOMPOSER_FC_AUDSV_V2R_SHIFT (6U)
/*! V2r - Set validity bit "V" for Channel 2, Right
*/
#define FRAMECOMPOSER_FC_AUDSV_V2R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V2R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V2R_MASK)
#define FRAMECOMPOSER_FC_AUDSV_V3R_MASK (0x80U)
#define FRAMECOMPOSER_FC_AUDSV_V3R_SHIFT (7U)
/*! V3r - Set validity bit "V" for Channel 3, Right
*/
#define FRAMECOMPOSER_FC_AUDSV_V3R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSV_V3R_SHIFT)) & FRAMECOMPOSER_FC_AUDSV_V3R_MASK)
/*! @} */
/*! @name FC_AUDSU - Frame Composer Audio Sample User Flag Register */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSU_U0L_MASK (0x1U)
#define FRAMECOMPOSER_FC_AUDSU_U0L_SHIFT (0U)
/*! U0l - Set user bit "U" for Channel 0, Left
*/
#define FRAMECOMPOSER_FC_AUDSU_U0L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U0L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U0L_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U1L_MASK (0x2U)
#define FRAMECOMPOSER_FC_AUDSU_U1L_SHIFT (1U)
/*! U1l - Set user bit "U" for Channel 1, Left
*/
#define FRAMECOMPOSER_FC_AUDSU_U1L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U1L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U1L_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U2L_MASK (0x4U)
#define FRAMECOMPOSER_FC_AUDSU_U2L_SHIFT (2U)
/*! U2l - Set user bit "U" for Channel 2, Left
*/
#define FRAMECOMPOSER_FC_AUDSU_U2L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U2L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U2L_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U3L_MASK (0x8U)
#define FRAMECOMPOSER_FC_AUDSU_U3L_SHIFT (3U)
/*! U3l - Set user bit "U" for Channel 3, Left
*/
#define FRAMECOMPOSER_FC_AUDSU_U3L(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U3L_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U3L_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U0R_MASK (0x10U)
#define FRAMECOMPOSER_FC_AUDSU_U0R_SHIFT (4U)
/*! U0r - Set user bit "U" for Channel 0, Right
*/
#define FRAMECOMPOSER_FC_AUDSU_U0R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U0R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U0R_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U1R_MASK (0x20U)
#define FRAMECOMPOSER_FC_AUDSU_U1R_SHIFT (5U)
/*! U1r - Set user bit "U" for Channel 1, Right
*/
#define FRAMECOMPOSER_FC_AUDSU_U1R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U1R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U1R_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U2R_MASK (0x40U)
#define FRAMECOMPOSER_FC_AUDSU_U2R_SHIFT (6U)
/*! U2r - Set user bit "U" for Channel 2, Right
*/
#define FRAMECOMPOSER_FC_AUDSU_U2R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U2R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U2R_MASK)
#define FRAMECOMPOSER_FC_AUDSU_U3R_MASK (0x80U)
#define FRAMECOMPOSER_FC_AUDSU_U3R_SHIFT (7U)
/*! U3r - Set user bit "U" for Channel 3, Right
*/
#define FRAMECOMPOSER_FC_AUDSU_U3R(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSU_U3R_SHIFT)) & FRAMECOMPOSER_FC_AUDSU_U3R_MASK)
/*! @} */
/*! @name FC_AUDSCHNL0 - Frame Composer Audio Sample Channel Status Configuration Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_MASK (0x1U)
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_SHIFT (0U)
/*! oiec_copyright - IEC Copyright indication
*/
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_COPYRIGHT_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_MASK (0x30U)
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_SHIFT (4U)
/*! oiec_cgmsa - CGMS-A
*/
#define FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL0_OIEC_CGMSA_MASK)
/*! @} */
/*! @name FC_AUDSCHNL1 - Frame Composer Audio Sample Channel Status Configuration Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_MASK (0xFFU)
#define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_SHIFT (0U)
/*! oiec_categorycode - Category code
*/
#define FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL1_OIEC_CATEGORYCODE_MASK)
/*! @} */
/*! @name FC_AUDSCHNL2 - Frame Composer Audio Sample Channel Status Configuration Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_SHIFT (0U)
/*! oiec_sourcenumber - Source number
*/
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_SOURCENUMBER_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_MASK (0x70U)
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_SHIFT (4U)
/*! oiec_pcmaudiomode - PCM audio mode
*/
#define FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL2_OIEC_PCMAUDIOMODE_MASK)
/*! @} */
/*! @name FC_AUDSCHNL3 - Frame Composer Audio Sample Channel Status Configuration Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_SHIFT (0U)
/*! oiec_channelnumcr0 - Channel number for first right sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR0_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_SHIFT (4U)
/*! oiec_channelnumcr1 - Channel number for second right sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL3_OIEC_CHANNELNUMCR1_MASK)
/*! @} */
/*! @name FC_AUDSCHNL4 - Frame Composer Audio Sample Channel Status Configuration Register 4 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_SHIFT (0U)
/*! oiec_channelnumcr2 - Channel number for third right sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR2_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_SHIFT (4U)
/*! oiec_channelnumcr3 - Channel number for fourth right sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL4_OIEC_CHANNELNUMCR3_MASK)
/*! @} */
/*! @name FC_AUDSCHNL5 - Frame Composer Audio Sample Channel Status Configuration Register 5 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_SHIFT (0U)
/*! oiec_channelnumcl0 - Channel number for first left sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL0_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_SHIFT (4U)
/*! oiec_channelnumcl1 - Channel number for second left sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL5_OIEC_CHANNELNUMCL1_MASK)
/*! @} */
/*! @name FC_AUDSCHNL6 - Frame Composer Audio Sample Channel Status Configuration Register 6 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_SHIFT (0U)
/*! oiec_channelnumcl2 - Channel number for third left sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL2_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_SHIFT (4U)
/*! oiec_channelnumcl3 - Channel number for fourth left sample
*/
#define FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL6_OIEC_CHANNELNUMCL3_MASK)
/*! @} */
/*! @name FC_AUDSCHNL7 - Frame Composer Audio Sample Channel Status Configuration Register 7 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_SHIFT (0U)
/*! oiec_sampfreq - Sampling frequency
*/
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_MASK (0x30U)
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_SHIFT (4U)
/*! oiec_clkaccuracy - Clock accuracy
*/
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_CLKACCURACY_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_MASK (0xC0U)
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_SHIFT (6U)
/*! oiec_sampfreq_ext - Sampling frequency (channel status bits 31 and 30)
*/
#define FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL7_OIEC_SAMPFREQ_EXT_MASK)
/*! @} */
/*! @name FC_AUDSCHNL8 - Frame Composer Audio Sample Channel Status Configuration Register 8 */
/*! @{ */
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_MASK (0xFU)
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_SHIFT (0U)
/*! oiec_wordlength - Word length configuration
*/
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_WORDLENGTH_MASK)
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_MASK (0xF0U)
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_SHIFT (4U)
/*! oiec_origsampfreq - Original sampling frequency
*/
#define FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_SHIFT)) & FRAMECOMPOSER_FC_AUDSCHNL8_OIEC_ORIGSAMPFREQ_MASK)
/*! @} */
/*! @name FC_CTRLQHIGH - Frame Composer Number of High Priority Packets Attended Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_MASK (0x1FU)
#define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_SHIFT (0U)
/*! onhighattended - Configures the number of high priority packets or audio sample packets
* consecutively attended before checking low priority queue status.
*/
#define FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_SHIFT)) & FRAMECOMPOSER_FC_CTRLQHIGH_ONHIGHATTENDED_MASK)
/*! @} */
/*! @name FC_CTRLQLOW - Frame Composer Number of Low Priority Packets Attended Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_MASK (0x1FU)
#define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_SHIFT (0U)
/*! onlowattended - Configures the number of low priority packets or null packets consecutively
* attended before checking high priority queue status or audio samples availability.
*/
#define FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_SHIFT)) & FRAMECOMPOSER_FC_CTRLQLOW_ONLOWATTENDED_MASK)
/*! @} */
/*! @name FC_ACP0 - Frame Composer ACP Packet Type Configuration Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP0_ACPTYPE_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP0_ACPTYPE_SHIFT (0U)
/*! acptype - Configures the ACP packet type.
*/
#define FRAMECOMPOSER_FC_ACP0_ACPTYPE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP0_ACPTYPE_SHIFT)) & FRAMECOMPOSER_FC_ACP0_ACPTYPE_MASK)
/*! @} */
/*! @name FC_ACP16 - Frame Composer ACP Packet Body Configuration Register 16 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP16_FC_ACP16_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP16_FC_ACP16_SHIFT (0U)
/*! fc_acp16 - Frame Composer ACP Packet Body Configuration Register 16
*/
#define FRAMECOMPOSER_FC_ACP16_FC_ACP16(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP16_FC_ACP16_SHIFT)) & FRAMECOMPOSER_FC_ACP16_FC_ACP16_MASK)
/*! @} */
/*! @name FC_ACP15 - Frame Composer ACP Packet Body Configuration Register 15 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP15_FC_ACP15_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP15_FC_ACP15_SHIFT (0U)
/*! fc_acp15 - Frame Composer ACP Packet Body Configuration Register 15
*/
#define FRAMECOMPOSER_FC_ACP15_FC_ACP15(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP15_FC_ACP15_SHIFT)) & FRAMECOMPOSER_FC_ACP15_FC_ACP15_MASK)
/*! @} */
/*! @name FC_ACP14 - Frame Composer ACP Packet Body Configuration Register 14 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP14_FC_ACP14_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP14_FC_ACP14_SHIFT (0U)
/*! fc_acp14 - Frame Composer ACP Packet Body Configuration Register 14
*/
#define FRAMECOMPOSER_FC_ACP14_FC_ACP14(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP14_FC_ACP14_SHIFT)) & FRAMECOMPOSER_FC_ACP14_FC_ACP14_MASK)
/*! @} */
/*! @name FC_ACP13 - Frame Composer ACP Packet Body Configuration Register 13 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP13_FC_ACP13_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP13_FC_ACP13_SHIFT (0U)
/*! fc_acp13 - Frame Composer ACP Packet Body Configuration Register 13
*/
#define FRAMECOMPOSER_FC_ACP13_FC_ACP13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP13_FC_ACP13_SHIFT)) & FRAMECOMPOSER_FC_ACP13_FC_ACP13_MASK)
/*! @} */
/*! @name FC_ACP12 - Frame Composer ACP Packet Body Configuration Register 12 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP12_FC_ACP12_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP12_FC_ACP12_SHIFT (0U)
/*! fc_acp12 - Frame Composer ACP Packet Body Configuration Register 12
*/
#define FRAMECOMPOSER_FC_ACP12_FC_ACP12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP12_FC_ACP12_SHIFT)) & FRAMECOMPOSER_FC_ACP12_FC_ACP12_MASK)
/*! @} */
/*! @name FC_ACP11 - Frame Composer ACP Packet Body Configuration Register 11 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP11_FC_ACP11_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP11_FC_ACP11_SHIFT (0U)
/*! fc_acp11 - Frame Composer ACP Packet Body Configuration Register 11
*/
#define FRAMECOMPOSER_FC_ACP11_FC_ACP11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP11_FC_ACP11_SHIFT)) & FRAMECOMPOSER_FC_ACP11_FC_ACP11_MASK)
/*! @} */
/*! @name FC_ACP10 - Frame Composer ACP Packet Body Configuration Register 10 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP10_FC_ACP10_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP10_FC_ACP10_SHIFT (0U)
/*! fc_acp10 - Frame Composer ACP Packet Body Configuration Register 10
*/
#define FRAMECOMPOSER_FC_ACP10_FC_ACP10(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP10_FC_ACP10_SHIFT)) & FRAMECOMPOSER_FC_ACP10_FC_ACP10_MASK)
/*! @} */
/*! @name FC_ACP9 - Frame Composer ACP Packet Body Configuration Register 9 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP9_FC_ACP9_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP9_FC_ACP9_SHIFT (0U)
/*! fc_acp9 - Frame Composer ACP Packet Body Configuration Register 9
*/
#define FRAMECOMPOSER_FC_ACP9_FC_ACP9(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP9_FC_ACP9_SHIFT)) & FRAMECOMPOSER_FC_ACP9_FC_ACP9_MASK)
/*! @} */
/*! @name FC_ACP8 - Frame Composer ACP Packet Body Configuration Register 8 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP8_FC_ACP8_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP8_FC_ACP8_SHIFT (0U)
/*! fc_acp8 - Frame Composer ACP Packet Body Configuration Register 8
*/
#define FRAMECOMPOSER_FC_ACP8_FC_ACP8(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP8_FC_ACP8_SHIFT)) & FRAMECOMPOSER_FC_ACP8_FC_ACP8_MASK)
/*! @} */
/*! @name FC_ACP7 - Frame Composer ACP Packet Body Configuration Register 7 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP7_FC_ACP7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP7_FC_ACP7_SHIFT (0U)
/*! fc_acp7 - Frame Composer ACP Packet Body Configuration Register 7
*/
#define FRAMECOMPOSER_FC_ACP7_FC_ACP7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP7_FC_ACP7_SHIFT)) & FRAMECOMPOSER_FC_ACP7_FC_ACP7_MASK)
/*! @} */
/*! @name FC_ACP6 - Frame Composer ACP Packet Body Configuration Register 6 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP6_FC_ACP6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP6_FC_ACP6_SHIFT (0U)
/*! fc_acp6 - Frame Composer ACP Packet Body Configuration Register 6
*/
#define FRAMECOMPOSER_FC_ACP6_FC_ACP6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP6_FC_ACP6_SHIFT)) & FRAMECOMPOSER_FC_ACP6_FC_ACP6_MASK)
/*! @} */
/*! @name FC_ACP5 - Frame Composer ACP Packet Body Configuration Register 5 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP5_FC_ACP5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP5_FC_ACP5_SHIFT (0U)
/*! fc_acp5 - Frame Composer ACP Packet Body Configuration Register 5
*/
#define FRAMECOMPOSER_FC_ACP5_FC_ACP5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP5_FC_ACP5_SHIFT)) & FRAMECOMPOSER_FC_ACP5_FC_ACP5_MASK)
/*! @} */
/*! @name FC_ACP4 - Frame Composer ACP Packet Body Configuration Register 4 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP4_FC_ACP4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP4_FC_ACP4_SHIFT (0U)
/*! fc_acp4 - Frame Composer ACP Packet Body Configuration Register 4
*/
#define FRAMECOMPOSER_FC_ACP4_FC_ACP4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP4_FC_ACP4_SHIFT)) & FRAMECOMPOSER_FC_ACP4_FC_ACP4_MASK)
/*! @} */
/*! @name FC_ACP3 - Frame Composer ACP Packet Body Configuration Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP3_FC_ACP3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP3_FC_ACP3_SHIFT (0U)
/*! fc_acp3 - Frame Composer ACP Packet Body Configuration Register 3
*/
#define FRAMECOMPOSER_FC_ACP3_FC_ACP3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP3_FC_ACP3_SHIFT)) & FRAMECOMPOSER_FC_ACP3_FC_ACP3_MASK)
/*! @} */
/*! @name FC_ACP2 - Frame Composer ACP Packet Body Configuration Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP2_FC_ACP2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP2_FC_ACP2_SHIFT (0U)
/*! fc_acp2 - Frame Composer ACP Packet Body Configuration Register 2
*/
#define FRAMECOMPOSER_FC_ACP2_FC_ACP2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP2_FC_ACP2_SHIFT)) & FRAMECOMPOSER_FC_ACP2_FC_ACP2_MASK)
/*! @} */
/*! @name FC_ACP1 - Frame Composer ACP Packet Body Configuration Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_ACP1_FC_ACP1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ACP1_FC_ACP1_SHIFT (0U)
/*! fc_acp1 - Frame Composer ACP Packet Body Configuration Register 1
*/
#define FRAMECOMPOSER_FC_ACP1_FC_ACP1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACP1_FC_ACP1_SHIFT)) & FRAMECOMPOSER_FC_ACP1_FC_ACP1_MASK)
/*! @} */
/*! @name FC_ISCR1_0 - Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_MASK (0x1U)
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_SHIFT (0U)
/*! isrc_cont - ISRC1 Indication of packet continuation (ISRC2 will be transmitted)
*/
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_CONT_MASK)
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_MASK (0x2U)
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_SHIFT (1U)
/*! isrc_valid - ISRC1 Valid control signal
*/
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_VALID_MASK)
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_MASK (0x1CU)
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_SHIFT (2U)
/*! isrc_status - ISRC1 Status signal
*/
#define FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_0_ISRC_STATUS_MASK)
/*! @} */
/*! @name FC_ISCR1_16 - Frame Composer ISRC1 Packet Body Register 16 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_SHIFT (0U)
/*! fc_iscr1_16 - Frame Composer ISRC1 Packet Body Register 16; configures ISRC1 packet body of the ISRC1 packet
*/
#define FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_16_FC_ISCR1_16_MASK)
/*! @} */
/*! @name FC_ISCR1_15 - Frame Composer ISRC1 Packet Body Register 15 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_SHIFT (0U)
/*! fc_iscr1_15 - Frame Composer ISRC1 Packet Body Register 15
*/
#define FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_15_FC_ISCR1_15_MASK)
/*! @} */
/*! @name FC_ISCR1_14 - Frame Composer ISRC1 Packet Body Register 14 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_SHIFT (0U)
/*! fc_iscr1_14 - Frame Composer ISRC1 Packet Body Register 14
*/
#define FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_14_FC_ISCR1_14_MASK)
/*! @} */
/*! @name FC_ISCR1_13 - Frame Composer ISRC1 Packet Body Register 13 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_SHIFT (0U)
/*! fc_iscr1_13 - Frame Composer ISRC1 Packet Body Register 13
*/
#define FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_13_FC_ISCR1_13_MASK)
/*! @} */
/*! @name FC_ISCR1_12 - Frame Composer ISRC1 Packet Body Register 12 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_SHIFT (0U)
/*! fc_iscr1_12 - Frame Composer ISRC1 Packet Body Register 12
*/
#define FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_12_FC_ISCR1_12_MASK)
/*! @} */
/*! @name FC_ISCR1_11 - Frame Composer ISRC1 Packet Body Register 11 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_SHIFT (0U)
/*! fc_iscr1_11 - Frame Composer ISRC1 Packet Body Register 11
*/
#define FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_11_FC_ISCR1_11_MASK)
/*! @} */
/*! @name FC_ISCR1_10 - Frame Composer ISRC1 Packet Body Register 10 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_SHIFT (0U)
/*! fc_iscr1_10 - Frame Composer ISRC1 Packet Body Register 10
*/
#define FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_10_FC_ISCR1_10_MASK)
/*! @} */
/*! @name FC_ISCR1_9 - Frame Composer ISRC1 Packet Body Register 9 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_SHIFT (0U)
/*! fc_iscr1_9 - Frame Composer ISRC1 Packet Body Register 9
*/
#define FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_9_FC_ISCR1_9_MASK)
/*! @} */
/*! @name FC_ISCR1_8 - Frame Composer ISRC1 Packet Body Register 8 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_SHIFT (0U)
/*! fc_iscr1_8 - Frame Composer ISRC1 Packet Body Register 8
*/
#define FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_8_FC_ISCR1_8_MASK)
/*! @} */
/*! @name FC_ISCR1_7 - Frame Composer ISRC1 Packet Body Register 7 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_SHIFT (0U)
/*! fc_iscr1_7 - Frame Composer ISRC1 Packet Body Register 7
*/
#define FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_7_FC_ISCR1_7_MASK)
/*! @} */
/*! @name FC_ISCR1_6 - Frame Composer ISRC1 Packet Body Register 6 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_SHIFT (0U)
/*! fc_iscr1_6 - Frame Composer ISRC1 Packet Body Register 6
*/
#define FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_6_FC_ISCR1_6_MASK)
/*! @} */
/*! @name FC_ISCR1_5 - Frame Composer ISRC1 Packet Body Register 5 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_SHIFT (0U)
/*! fc_iscr1_5 - Frame Composer ISRC1 Packet Body Register 5
*/
#define FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_5_FC_ISCR1_5_MASK)
/*! @} */
/*! @name FC_ISCR1_4 - Frame Composer ISRC1 Packet Body Register 4 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_SHIFT (0U)
/*! fc_iscr1_4 - Frame Composer ISRC1 Packet Body Register 4
*/
#define FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_4_FC_ISCR1_4_MASK)
/*! @} */
/*! @name FC_ISCR1_3 - Frame Composer ISRC1 Packet Body Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_SHIFT (0U)
/*! fc_iscr1_3 - Frame Composer ISRC1 Packet Body Register 3
*/
#define FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_3_FC_ISCR1_3_MASK)
/*! @} */
/*! @name FC_ISCR1_2 - Frame Composer ISRC1 Packet Body Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_SHIFT (0U)
/*! fc_iscr1_2 - Frame Composer ISRC1 Packet Body Register 2
*/
#define FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_2_FC_ISCR1_2_MASK)
/*! @} */
/*! @name FC_ISCR1_1 - Frame Composer ISRC1 Packet Body Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_SHIFT (0U)
/*! fc_iscr1_1 - Frame Composer ISRC1 Packet Body Register 1
*/
#define FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_SHIFT)) & FRAMECOMPOSER_FC_ISCR1_1_FC_ISCR1_1_MASK)
/*! @} */
/*! @name FC_ISCR2_15 - Frame Composer ISRC2 Packet Body Register 15 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_SHIFT (0U)
/*! fc_iscr2_15 - Frame Composer ISRC2 Packet Body Register 15; configures the ISRC2 packet body of the ISRC2 packet
*/
#define FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_15_FC_ISCR2_15_MASK)
/*! @} */
/*! @name FC_ISCR2_14 - Frame Composer ISRC2 Packet Body Register 14 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_SHIFT (0U)
/*! fc_iscr2_14 - Frame Composer ISRC2 Packet Body Register 14
*/
#define FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_14_FC_ISCR2_14_MASK)
/*! @} */
/*! @name FC_ISCR2_13 - Frame Composer ISRC2 Packet Body Register 13 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_SHIFT (0U)
/*! fc_iscr2_13 - Frame Composer ISRC2 Packet Body Register 13
*/
#define FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_13_FC_ISCR2_13_MASK)
/*! @} */
/*! @name FC_ISCR2_12 - Frame Composer ISRC2 Packet Body Register 12 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_SHIFT (0U)
/*! fc_iscr2_12 - Frame Composer ISRC2 Packet Body Register 12
*/
#define FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_12_FC_ISCR2_12_MASK)
/*! @} */
/*! @name FC_ISCR2_11 - Frame Composer ISRC2 Packet Body Register 11 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_SHIFT (0U)
/*! fc_iscr2_11 - Frame Composer ISRC2 Packet Body Register 11
*/
#define FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_11_FC_ISCR2_11_MASK)
/*! @} */
/*! @name FC_ISCR2_10 - Frame Composer ISRC2 Packet Body Register 10 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_SHIFT (0U)
/*! fc_iscr2_10 - Frame Composer ISRC2 Packet Body Register 10
*/
#define FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_10_FC_ISCR2_10_MASK)
/*! @} */
/*! @name FC_ISCR2_9 - Frame Composer ISRC2 Packet Body Register 9 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_SHIFT (0U)
/*! fc_iscr2_9 - Frame Composer ISRC2 Packet Body Register 9
*/
#define FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_9_FC_ISCR2_9_MASK)
/*! @} */
/*! @name FC_ISCR2_8 - Frame Composer ISRC2 Packet Body Register 8 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_SHIFT (0U)
/*! fc_iscr2_8 - Frame Composer ISRC2 Packet Body Register 8
*/
#define FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_8_FC_ISCR2_8_MASK)
/*! @} */
/*! @name FC_ISCR2_7 - Frame Composer ISRC2 Packet Body Register 7 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_SHIFT (0U)
/*! fc_iscr2_7 - Frame Composer ISRC2 Packet Body Register 7
*/
#define FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_7_FC_ISCR2_7_MASK)
/*! @} */
/*! @name FC_ISCR2_6 - Frame Composer ISRC2 Packet Body Register 6 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_SHIFT (0U)
/*! fc_iscr2_6 - Frame Composer ISRC2 Packet Body Register 6
*/
#define FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_6_FC_ISCR2_6_MASK)
/*! @} */
/*! @name FC_ISCR2_5 - Frame Composer ISRC2 Packet Body Register 5 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_SHIFT (0U)
/*! fc_iscr2_5 - Frame Composer ISRC2 Packet Body Register 5
*/
#define FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_5_FC_ISCR2_5_MASK)
/*! @} */
/*! @name FC_ISCR2_4 - Frame Composer ISRC2 Packet Body Register 4 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_SHIFT (0U)
/*! fc_iscr2_4 - Frame Composer ISRC2 Packet Body Register 4
*/
#define FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_4_FC_ISCR2_4_MASK)
/*! @} */
/*! @name FC_ISCR2_3 - Frame Composer ISRC2 Packet Body Register 3 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_SHIFT (0U)
/*! fc_iscr2_3 - Frame Composer ISRC2 Packet Body Register 3
*/
#define FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_3_FC_ISCR2_3_MASK)
/*! @} */
/*! @name FC_ISCR2_2 - Frame Composer ISRC2 Packet Body Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_SHIFT (0U)
/*! fc_iscr2_2 - Frame Composer ISRC2 Packet Body Register 2
*/
#define FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_2_FC_ISCR2_2_MASK)
/*! @} */
/*! @name FC_ISCR2_1 - Frame Composer ISRC2 Packet Body Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_SHIFT (0U)
/*! fc_iscr2_1 - Frame Composer ISRC2 Packet Body Register 1
*/
#define FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_1_FC_ISCR2_1_MASK)
/*! @} */
/*! @name FC_ISCR2_0 - Frame Composer ISRC2 Packet Body Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_SHIFT (0U)
/*! fc_iscr2_0 - Frame Composer ISRC2 Packet Body Register 0
*/
#define FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_SHIFT)) & FRAMECOMPOSER_FC_ISCR2_0_FC_ISCR2_0_MASK)
/*! @} */
/*! @name FC_DATAUTO0 - Frame Composer Data Island Auto Packet Scheduling Register 0 Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD, ISRC2, ISRC1 and ACP packets. */
/*! @{ */
#define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_MASK (0x1U)
#define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_SHIFT (0U)
/*! acp_auto - Enables ACP automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ACP_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_MASK (0x2U)
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_SHIFT (1U)
/*! iscr1_auto - Enables ISRC1 automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ISCR1_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_MASK (0x4U)
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_SHIFT (2U)
/*! iscr2_auto - Enables ISRC2 automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_ISCR2_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_MASK (0x8U)
#define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_SHIFT (3U)
/*! vsd_auto - Enables VSD automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_VSD_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_MASK (0x10U)
#define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_SHIFT (4U)
/*! spd_auto - Enables SPD automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO0_SPD_AUTO_MASK)
/*! @} */
/*! @name FC_DATAUTO1 - Frame Composer Data Island Auto Packet Scheduling Register 1 Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets. */
/*! @{ */
#define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_SHIFT (0U)
/*! auto_frame_interpolation - Packet frame interpolation for automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO1_AUTO_FRAME_INTERPOLATION_MASK)
/*! @} */
/*! @name FC_DATAUTO2 - Frame Composer Data Island Auto packet scheduling Register 2 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the listed packets. */
/*! @{ */
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_SHIFT (0U)
/*! auto_line_spacing - Packets line spacing, for automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO2_AUTO_LINE_SPACING_MASK)
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_MASK (0xF0U)
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_SHIFT (4U)
/*! auto_frame_packets - Packets per frame, for automatic packet scheduling
*/
#define FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO2_AUTO_FRAME_PACKETS_MASK)
/*! @} */
/*! @name FC_DATMAN - Frame Composer Data Island Manual Packet Request Register Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1 and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested. */
/*! @{ */
#define FRAMECOMPOSER_FC_DATMAN_ACP_TX_MASK (0x1U)
#define FRAMECOMPOSER_FC_DATMAN_ACP_TX_SHIFT (0U)
/*! acp_tx - ACP packet
*/
#define FRAMECOMPOSER_FC_DATMAN_ACP_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ACP_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ACP_TX_MASK)
#define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_MASK (0x2U)
#define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_SHIFT (1U)
/*! iscr1_tx - ISRC1 packet
*/
#define FRAMECOMPOSER_FC_DATMAN_ISCR1_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ISCR1_TX_MASK)
#define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_MASK (0x4U)
#define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_SHIFT (2U)
/*! iscr2_tx - ISRC2 packet
*/
#define FRAMECOMPOSER_FC_DATMAN_ISCR2_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_ISCR2_TX_MASK)
#define FRAMECOMPOSER_FC_DATMAN_VSD_TX_MASK (0x8U)
#define FRAMECOMPOSER_FC_DATMAN_VSD_TX_SHIFT (3U)
/*! vsd_tx - VSD packet
*/
#define FRAMECOMPOSER_FC_DATMAN_VSD_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_VSD_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_VSD_TX_MASK)
#define FRAMECOMPOSER_FC_DATMAN_SPD_TX_MASK (0x10U)
#define FRAMECOMPOSER_FC_DATMAN_SPD_TX_SHIFT (4U)
/*! spd_tx - SPD packet
*/
#define FRAMECOMPOSER_FC_DATMAN_SPD_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_SPD_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_SPD_TX_MASK)
#define FRAMECOMPOSER_FC_DATMAN_NULL_TX_MASK (0x20U)
#define FRAMECOMPOSER_FC_DATMAN_NULL_TX_SHIFT (5U)
/*! null_tx - Null packet
*/
#define FRAMECOMPOSER_FC_DATMAN_NULL_TX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATMAN_NULL_TX_SHIFT)) & FRAMECOMPOSER_FC_DATMAN_NULL_TX_MASK)
/*! @} */
/*! @name FC_DATAUTO3 - Frame Composer Data Island Auto Packet Scheduling Register 3 Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP, AUDI and ACR packets. */
/*! @{ */
#define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_MASK (0x1U)
#define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_SHIFT (0U)
/*! acr_auto - Enables ACR packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_ACR_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_MASK (0x2U)
#define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_SHIFT (1U)
/*! audi_auto - Enables AUDI packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AUDI_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_MASK (0x4U)
#define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_SHIFT (2U)
/*! gcp_auto - Enables GCP packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_GCP_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_MASK (0x8U)
#define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_SHIFT (3U)
/*! avi_auto - Enables AVI packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AVI_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_MASK (0x10U)
#define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_SHIFT (4U)
/*! amp_auto - Enables AMP packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_AMP_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_MASK (0x20U)
#define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_SHIFT (5U)
/*! nvbi_auto - Enables NTSC VBI packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_NVBI_AUTO_MASK)
#define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_MASK (0x40U)
#define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_SHIFT (6U)
/*! drm_auto - Enables DRM packet insertion
*/
#define FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_SHIFT)) & FRAMECOMPOSER_FC_DATAUTO3_DRM_AUTO_MASK)
/*! @} */
/*! @name FC_RDRB0 - Frame Composer Round Robin ACR Packet Insertion Register 0 Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data island when FC is on RDRB mode for this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_SHIFT (0U)
/*! ACRframeinterpolation - ACR Frame interpolation
*/
#define FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB0_ACRFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB1 - Frame Composer Round Robin ACR Packet Insertion Register 1 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the ACR packet insertion on data island when FC is on RDRB mode this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_SHIFT (0U)
/*! ACRpacketlinespacing - ACR packet line spacing
*/
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB1_ACRPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_SHIFT (4U)
/*! ACRpacketsinframe - ACR packets in frame
*/
#define FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB1_ACRPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB2 - Frame Composer Round Robin AUDI Packet Insertion Register 2 Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data island when FC is on RDRB mode for this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_SHIFT (0U)
/*! AUDIframeinterpolation - Audio frame interpolation
*/
#define FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB2_AUDIFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB3 - Frame Composer Round Robin AUDI Packet Insertion Register 3 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AUDI packet insertion on data island when FC is on RDRB mode this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_SHIFT (0U)
/*! AUDIpacketlinespacing - Audio packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB3_AUDIPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_SHIFT (4U)
/*! AUDIpacketsinframe - Audio packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB3_AUDIPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB4 - Frame Composer Round Robin GCP Packet Insertion Register 4 Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data island when FC is on RDRB mode for this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_SHIFT (0U)
/*! GCPframeinterpolation - Frames interpolated between GCP packets
*/
#define FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB4_GCPFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB5 - Frame Composer Round Robin GCP Packet Insertion Register 5 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the GCP packet insertion on data island when FC is on RDRB mode this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_SHIFT (0U)
/*! GCPpacketlinespacing - GCP packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB5_GCPPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_SHIFT (4U)
/*! GCPpacketsinframe - GCP packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB5_GCPPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB6 - Frame Composer Round Robin AVI Packet Insertion Register 6 Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data island when FC is on RDRB mode for this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_SHIFT (0U)
/*! AVIframeinterpolation - Frames interpolated between AVI packets
*/
#define FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB6_AVIFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB7 - Frame Composer Round Robin AVI Packet Insertion Register 7 Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for the AVI packet insertion on data island when FC is on RDRB mode this packet. */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_SHIFT (0U)
/*! AVIpacketlinespacing - AVI packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB7_AVIPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_SHIFT (4U)
/*! AVIpacketsinframe - AVI packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB7_AVIPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB8 - Frame Composer Round Robin AMP Packet Insertion Register 8 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_SHIFT (0U)
/*! AMPframeinterpolation - AMP frame interpolation
*/
#define FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB8_AMPFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB9 - Frame Composer Round Robin AMP Packet Insertion Register 9 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_SHIFT (0U)
/*! AMPpacketlinespacing - AMP packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB9_AMPPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_SHIFT (4U)
/*! AMPpacketsinframe - AMP packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB9_AMPPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB10 - Frame Composer Round Robin NTSC VBI Packet Insertion Register 10 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_SHIFT (0U)
/*! NVBIframeinterpolation - NTSC VBI frame interpolation
*/
#define FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB10_NVBIFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB11 - Frame Composer Round Robin NTSC VBI Packet Insertion Register 11 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_SHIFT (0U)
/*! NVBIpacketlinespacing - NTSC VBI packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB11_NVBIPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_SHIFT (4U)
/*! NVBIpacketsinframe - NTSC VBI packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB11_NVBIPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_RDRB12 - Frame Composer Round Robin DRM Packet Insertion Register 12 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_SHIFT (0U)
/*! DRMframeinterpolation - DRM frame interpolation
*/
#define FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_SHIFT)) & FRAMECOMPOSER_FC_RDRB12_DRMFRAMEINTERPOLATION_MASK)
/*! @} */
/*! @name FC_RDRB13 - Frame Composer Round Robin DRM Packet Insertion Register 13 */
/*! @{ */
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_SHIFT (0U)
/*! DRMpacketlinespacing - DRM packets line spacing
*/
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_RDRB13_DRMPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_SHIFT (4U)
/*! DRMpacketsinframe - DRM packets per frame
*/
#define FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_RDRB13_DRMPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_MASK0 - Frame Composer Packet Interrupt Mask Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_MASK0_NULL_MASK (0x1U)
#define FRAMECOMPOSER_FC_MASK0_NULL_SHIFT (0U)
/*! NULL - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_NULL(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_NULL_SHIFT)) & FRAMECOMPOSER_FC_MASK0_NULL_MASK)
#define FRAMECOMPOSER_FC_MASK0_ACR_MASK (0x2U)
#define FRAMECOMPOSER_FC_MASK0_ACR_SHIFT (1U)
/*! ACR - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_ACR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_ACR_SHIFT)) & FRAMECOMPOSER_FC_MASK0_ACR_MASK)
#define FRAMECOMPOSER_FC_MASK0_AUDS_MASK (0x4U)
#define FRAMECOMPOSER_FC_MASK0_AUDS_SHIFT (2U)
/*! AUDS - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_AUDS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_AUDS_SHIFT)) & FRAMECOMPOSER_FC_MASK0_AUDS_MASK)
#define FRAMECOMPOSER_FC_MASK0_NVBI_MASK (0x8U)
#define FRAMECOMPOSER_FC_MASK0_NVBI_SHIFT (3U)
/*! NVBI - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_NVBI(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_NVBI_SHIFT)) & FRAMECOMPOSER_FC_MASK0_NVBI_MASK)
#define FRAMECOMPOSER_FC_MASK0_MAS_MASK (0x10U)
#define FRAMECOMPOSER_FC_MASK0_MAS_SHIFT (4U)
/*! MAS - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_MAS(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_MAS_SHIFT)) & FRAMECOMPOSER_FC_MASK0_MAS_MASK)
#define FRAMECOMPOSER_FC_MASK0_HBR_MASK (0x20U)
#define FRAMECOMPOSER_FC_MASK0_HBR_SHIFT (5U)
/*! HBR - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_HBR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_HBR_SHIFT)) & FRAMECOMPOSER_FC_MASK0_HBR_MASK)
#define FRAMECOMPOSER_FC_MASK0_ACP_MASK (0x40U)
#define FRAMECOMPOSER_FC_MASK0_ACP_SHIFT (6U)
/*! ACP - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_ACP(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_ACP_SHIFT)) & FRAMECOMPOSER_FC_MASK0_ACP_MASK)
#define FRAMECOMPOSER_FC_MASK0_AUDI_MASK (0x80U)
#define FRAMECOMPOSER_FC_MASK0_AUDI_SHIFT (7U)
/*! AUDI - Mask bit for FC_INT0.
*/
#define FRAMECOMPOSER_FC_MASK0_AUDI(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK0_AUDI_SHIFT)) & FRAMECOMPOSER_FC_MASK0_AUDI_MASK)
/*! @} */
/*! @name FC_MASK1 - Frame Composer Packet Interrupt Mask Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_MASK1_GCP_MASK (0x1U)
#define FRAMECOMPOSER_FC_MASK1_GCP_SHIFT (0U)
/*! GCP - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_GCP(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_GCP_SHIFT)) & FRAMECOMPOSER_FC_MASK1_GCP_MASK)
#define FRAMECOMPOSER_FC_MASK1_AVI_MASK (0x2U)
#define FRAMECOMPOSER_FC_MASK1_AVI_SHIFT (1U)
/*! AVI - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_AVI(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_AVI_SHIFT)) & FRAMECOMPOSER_FC_MASK1_AVI_MASK)
#define FRAMECOMPOSER_FC_MASK1_AMP_MASK (0x4U)
#define FRAMECOMPOSER_FC_MASK1_AMP_SHIFT (2U)
/*! AMP - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_AMP(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_AMP_SHIFT)) & FRAMECOMPOSER_FC_MASK1_AMP_MASK)
#define FRAMECOMPOSER_FC_MASK1_SPD_MASK (0x8U)
#define FRAMECOMPOSER_FC_MASK1_SPD_SHIFT (3U)
/*! SPD - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_SPD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_SPD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_SPD_MASK)
#define FRAMECOMPOSER_FC_MASK1_VSD_MASK (0x10U)
#define FRAMECOMPOSER_FC_MASK1_VSD_SHIFT (4U)
/*! VSD - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_VSD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_VSD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_VSD_MASK)
#define FRAMECOMPOSER_FC_MASK1_ISCR2_MASK (0x20U)
#define FRAMECOMPOSER_FC_MASK1_ISCR2_SHIFT (5U)
/*! ISCR2 - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_ISCR2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_ISCR2_SHIFT)) & FRAMECOMPOSER_FC_MASK1_ISCR2_MASK)
#define FRAMECOMPOSER_FC_MASK1_ISCR1_MASK (0x40U)
#define FRAMECOMPOSER_FC_MASK1_ISCR1_SHIFT (6U)
/*! ISCR1 - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_ISCR1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_ISCR1_SHIFT)) & FRAMECOMPOSER_FC_MASK1_ISCR1_MASK)
#define FRAMECOMPOSER_FC_MASK1_GMD_MASK (0x80U)
#define FRAMECOMPOSER_FC_MASK1_GMD_SHIFT (7U)
/*! GMD - Mask bit for FC_INT1.
*/
#define FRAMECOMPOSER_FC_MASK1_GMD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK1_GMD_SHIFT)) & FRAMECOMPOSER_FC_MASK1_GMD_MASK)
/*! @} */
/*! @name FC_MASK2 - Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
#define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
/*! HighPriority_overflow - Mask bit for FC_INT2.
*/
#define FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_SHIFT)) & FRAMECOMPOSER_FC_MASK2_HIGHPRIORITY_OVERFLOW_MASK)
#define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
#define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
/*! LowPriority_overflow - Mask bit for FC_INT2.
*/
#define FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_SHIFT)) & FRAMECOMPOSER_FC_MASK2_LOWPRIORITY_OVERFLOW_MASK)
#define FRAMECOMPOSER_FC_MASK2_DRM_MASK (0x10U)
#define FRAMECOMPOSER_FC_MASK2_DRM_SHIFT (4U)
/*! DRM - Mask bit for FC_INT2.
*/
#define FRAMECOMPOSER_FC_MASK2_DRM(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MASK2_DRM_SHIFT)) & FRAMECOMPOSER_FC_MASK2_DRM_MASK)
/*! @} */
/*! @name FC_PRCONF - Frame Composer Pixel Repetition Configuration Register */
/*! @{ */
#define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_MASK (0xFU)
#define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_SHIFT (0U)
/*! output_pr_factor - Configures the video pixel repetition ratio to be sent on the AVI InfoFrame.
*/
#define FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_SHIFT)) & FRAMECOMPOSER_FC_PRCONF_OUTPUT_PR_FACTOR_MASK)
#define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_MASK (0xF0U)
#define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_SHIFT (4U)
/*! incoming_pr_factor - Configures the input video pixel repetition.
*/
#define FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_SHIFT)) & FRAMECOMPOSER_FC_PRCONF_INCOMING_PR_FACTOR_MASK)
/*! @} */
/*! @name FC_SCRAMBLER_CTRL - Frame Composer Scrambler Control */
/*! @{ */
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_MASK (0x1U)
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_SHIFT (0U)
/*! scrambler_on - When set (1'b1), this field activates the HDMI 2.
*/
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_SHIFT)) & FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_ON_MASK)
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_MASK (0x10U)
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_SHIFT (4U)
/*! scrambler_ucp_line - Debug register.
*/
#define FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_SHIFT)) & FRAMECOMPOSER_FC_SCRAMBLER_CTRL_SCRAMBLER_UCP_LINE_MASK)
/*! @} */
/*! @name FC_MULTISTREAM_CTRL - Frame Composer Multi-Stream Audio Control */
/*! @{ */
#define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_MASK (0x1U)
#define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_SHIFT (0U)
/*! fc_mas_packet_en - This field, when set (1'b1), activates the HDMI 2.
*/
#define FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_SHIFT)) & FRAMECOMPOSER_FC_MULTISTREAM_CTRL_FC_MAS_PACKET_EN_MASK)
/*! @} */
/*! @name FC_PACKET_TX_EN - Frame Composer Packet Transmission Control */
/*! @{ */
#define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_MASK (0x1U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_SHIFT (0U)
/*! acr_tx_en - ACR packet transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_ACR_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_MASK (0x2U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_SHIFT (1U)
/*! gcp_tx_en - GCP transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_GCP_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_MASK (0x4U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_SHIFT (2U)
/*! avi_tx_en - AVI packet transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AVI_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_MASK (0x8U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_SHIFT (3U)
/*! audi_tx_en - AUDI packet transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AUDI_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_MASK (0x10U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_SHIFT (4U)
/*! aut_tx_en - ACP, SPD, VSIF, ISRC1, and SRC2 packet transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AUT_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_MASK (0x20U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_SHIFT (5U)
/*! amp_tx_en - AMP transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_AMP_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_MASK (0x40U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_SHIFT (6U)
/*! nvbi_tx_en - NTSC VBI transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_NVBI_TX_EN_MASK)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_MASK (0x80U)
#define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_SHIFT (7U)
/*! drm_tx_en - DRM transmission control 1b: Transmission enabled 0b: Transmission disabled
*/
#define FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_SHIFT)) & FRAMECOMPOSER_FC_PACKET_TX_EN_DRM_TX_EN_MASK)
/*! @} */
/*! @name FC_ACTSPC_HDLR_CFG - Frame Composer Active Space Control */
/*! @{ */
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_MASK (0x1U)
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_SHIFT (0U)
/*! actspc_hdlr_en - Active Space Handler Control 1b: Fixed active space value mode enabled.
*/
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_SHIFT)) & FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_EN_MASK)
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_MASK (0x2U)
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_SHIFT (1U)
/*! actspc_hdlr_tgl - Active Space handler control 1b: Active space 1 value is different from Active Space 2 value.
*/
#define FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_SHIFT)) & FRAMECOMPOSER_FC_ACTSPC_HDLR_CFG_ACTSPC_HDLR_TGL_MASK)
/*! @} */
/*! @name FC_INVACT_2D_0 - Frame Composer Input Video 2D VActive Pixels Register 0 */
/*! @{ */
#define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_SHIFT (0U)
/*! fc_invact_2d_0 - 2D Input video vertical active pixel region width.
*/
#define FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_SHIFT)) & FRAMECOMPOSER_FC_INVACT_2D_0_FC_INVACT_2D_0_MASK)
/*! @} */
/*! @name FC_INVACT_2D_1 - Frame Composer Input Video VActive pixels Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_MASK (0xFU)
#define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_SHIFT (0U)
/*! fc_invact_2d_1 - 2D Input video vertical active pixel region width.
*/
#define FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_SHIFT)) & FRAMECOMPOSER_FC_INVACT_2D_1_FC_INVACT_2D_1_MASK)
/*! @} */
/*! @name FC_GMD_STAT - Frame Composer GMD Packet Status Register Gamut metadata packet status bit information for no_current_gmd, next_gmd_field, gmd_packet_sequence and current_gamut_seq_num. */
/*! @{ */
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_MASK (0xFU)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_SHIFT (0U)
/*! igmdcurrent_gamut_seq_num - Gamut scheduling: Current Gamut packet sequence number
*/
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDCURRENT_GAMUT_SEQ_NUM_MASK)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_MASK (0x30U)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_SHIFT (4U)
/*! igmdpacket_seq - Gamut scheduling: Gamut packet sequence
*/
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDPACKET_SEQ_MASK)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_MASK (0x40U)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_SHIFT (6U)
/*! igmddnext_field - Gamut scheduling: Gamut Next field
*/
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDDNEXT_FIELD_MASK)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_MASK (0x80U)
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_SHIFT (7U)
/*! igmdno_crnt_gbd - Gamut scheduling: No current gamut data
*/
#define FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_SHIFT)) & FRAMECOMPOSER_FC_GMD_STAT_IGMDNO_CRNT_GBD_MASK)
/*! @} */
/*! @name FC_GMD_EN - Frame Composer GMD Packet Enable Register This register enables Gamut metadata (GMD) packet transmission. */
/*! @{ */
#define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_MASK (0x1U)
#define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_SHIFT (0U)
/*! gmdenabletx - Gamut Metadata packet transmission enable (1b)
*/
#define FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_SHIFT)) & FRAMECOMPOSER_FC_GMD_EN_GMDENABLETX_MASK)
/*! @} */
/*! @name FC_GMD_UP - Frame Composer GMD Packet Update Register This register performs an GMD packet content update according to the configured packet body (FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB). */
/*! @{ */
#define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_MASK (0x1U)
#define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_SHIFT (0U)
/*! gmdupdatepacket - Gamut Metadata packet update
*/
#define FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_SHIFT)) & FRAMECOMPOSER_FC_GMD_UP_GMDUPDATEPACKET_MASK)
/*! @} */
/*! @name FC_GMD_CONF - Frame Composer GMD Packet Schedule Configuration Register This register configures the number of GMD packets to be inserted per frame (starting always in the line where the active Vsync appears) and the line spacing between the transmitted GMD packets. */
/*! @{ */
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_MASK (0xFU)
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_SHIFT (0U)
/*! gmdpacketlinespacing - Number of line spacing between the transmitted GMD packets
*/
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_SHIFT)) & FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETLINESPACING_MASK)
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_MASK (0xF0U)
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_SHIFT (4U)
/*! gmdpacketsinframe - Number of GMD packets per frame or video field (profile P0)
*/
#define FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_SHIFT)) & FRAMECOMPOSER_FC_GMD_CONF_GMDPACKETSINFRAME_MASK)
/*! @} */
/*! @name FC_GMD_HB - Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits. */
/*! @{ */
#define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_MASK (0xFU)
#define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_SHIFT (0U)
/*! gmdaffected_gamut_seq_num - Affected gamut sequence number
*/
#define FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_SHIFT)) & FRAMECOMPOSER_FC_GMD_HB_GMDAFFECTED_GAMUT_SEQ_NUM_MASK)
#define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_MASK (0x70U)
#define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_SHIFT (4U)
/*! gmdgbd_profile - GMD profile bits.
*/
#define FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_SHIFT)) & FRAMECOMPOSER_FC_GMD_HB_GMDGBD_PROFILE_MASK)
/*! @} */
/*! @name FC_AMP_HB1 - Frame Composer AMP Packet Header Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_SHIFT (0U)
/*! fc_amp_hb0 - Frame Composer AMP Packet Header Register 1
*/
#define FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_SHIFT)) & FRAMECOMPOSER_FC_AMP_HB1_FC_AMP_HB0_MASK)
/*! @} */
/*! @name FC_AMP_HB2 - Frame Composer AMP Packet Header Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_SHIFT (0U)
/*! fc_amp_hb1 - Frame Composer AMP Packet Header Register 2
*/
#define FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_SHIFT)) & FRAMECOMPOSER_FC_AMP_HB2_FC_AMP_HB1_MASK)
/*! @} */
/*! @name FC_NVBI_HB1 - Frame Composer NTSC VBI Packet Header Register 1 */
/*! @{ */
#define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_SHIFT (0U)
/*! fc_nvbi_hb0 - Frame Composer NTSC VBI Packet Header Register 1
*/
#define FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_SHIFT)) & FRAMECOMPOSER_FC_NVBI_HB1_FC_NVBI_HB0_MASK)
/*! @} */
/*! @name FC_NVBI_HB2 - Frame Composer NTSC VBI Packet Header Register 2 */
/*! @{ */
#define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_SHIFT (0U)
/*! fc_nvbi_hb1 - Frame Composer NTSC VBI Packet Header Register 2
*/
#define FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_SHIFT)) & FRAMECOMPOSER_FC_NVBI_HB2_FC_NVBI_HB1_MASK)
/*! @} */
/*! @name FC_DRM_UP - Frame Composer DRM Packet Update Register This register performs an DRM packet content update according to the configured packet body (FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB). */
/*! @{ */
#define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_MASK (0x1U)
#define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_SHIFT (0U)
/*! drmpacketupdate - DRM packet update
*/
#define FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_SHIFT)) & FRAMECOMPOSER_FC_DRM_UP_DRMPACKETUPDATE_MASK)
/*! @} */
/*! @name FC_DBGFORCE - Frame Composer video/audio Force Enable Register This register allows to force the controller to output audio and video data the values configured in the FC_DBGAUD and FC_DBGTMDS registers. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_MASK (0x1U)
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_SHIFT (0U)
/*! forcevideo - Force fixed video output with FC_DBGTMDSx register contents.
*/
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_SHIFT)) & FRAMECOMPOSER_FC_DBGFORCE_FORCEVIDEO_MASK)
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_MASK (0x10U)
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_SHIFT (4U)
/*! forceaudio - Force fixed audio output with FC_DBGAUDxCHx register contents.
*/
#define FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_SHIFT)) & FRAMECOMPOSER_FC_DBGFORCE_FORCEAUDIO_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH0 - Frame Composer Audio Data Channel 0 Register 0 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_SHIFT (0U)
/*! fc_dbgaud0ch0 - Frame Composer Audio Data Channel 0 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH0_FC_DBGAUD0CH0_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH0 - Frame Composer Audio Data Channel 0 Register 1 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_SHIFT (0U)
/*! fc_dbgaud1ch0 - Frame Composer Audio Data Channel 0 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH0_FC_DBGAUD1CH0_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH0 - Frame Composer Audio Data Channel 0 Register 2 Configures the audio fixed data to be used in channel 0 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_SHIFT (0U)
/*! fc_dbgaud2ch0 - Frame Composer Audio Data Channel 0 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH0_FC_DBGAUD2CH0_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH1 - Frame Composer Audio Data Channel 1 Register 0 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_SHIFT (0U)
/*! fc_dbgaud0ch1 - Frame Composer Audio Data Channel 1 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH1_FC_DBGAUD0CH1_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH1 - Frame Composer Audio Data Channel 1 Register 1 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_SHIFT (0U)
/*! fc_dbgaud1ch1 - Frame Composer Audio Data Channel 1 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH1_FC_DBGAUD1CH1_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH1 - Frame Composer Audio Data Channel 1 Register 2 Configures the audio fixed data to be used in channel 1 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_SHIFT (0U)
/*! fc_dbgaud2ch1 - Frame Composer Audio Data Channel 1 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH1_FC_DBGAUD2CH1_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH2 - Frame Composer Audio Data Channel 2 Register 0 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_SHIFT (0U)
/*! fc_dbgaud0ch2 - Frame Composer Audio Data Channel 2 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH2_FC_DBGAUD0CH2_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH2 - Frame Composer Audio Data Channel 2 Register 1 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_SHIFT (0U)
/*! fc_dbgaud1ch2 - Frame Composer Audio Data Channel 2 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH2_FC_DBGAUD1CH2_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH2 - Frame Composer Audio Data Channel 2 Register 2 Configures the audio fixed data to be used in channel 2 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_SHIFT (0U)
/*! fc_dbgaud2ch2 - Frame Composer Audio Data Channel 2 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH2_FC_DBGAUD2CH2_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH3 - Frame Composer Audio Data Channel 3 Register 0 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_SHIFT (0U)
/*! fc_dbgaud0ch3 - Frame Composer Audio Data Channel 3 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH3_FC_DBGAUD0CH3_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH3 - Frame Composer Audio Data Channel 3 Register 1 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_SHIFT (0U)
/*! fc_dbgaud1ch3 - Frame Composer Audio Data Channel 3 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH3_FC_DBGAUD1CH3_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH3 - Frame Composer Audio Data Channel 3 Register 2 Configures the audio fixed data to be used in channel 3 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_SHIFT (0U)
/*! fc_dbgaud2ch3 - Frame Composer Audio Data Channel 3 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH3_FC_DBGAUD2CH3_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH4 - Frame Composer Audio Data Channel 4 Register 0 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_SHIFT (0U)
/*! fc_dbgaud0ch4 - Frame Composer Audio Data Channel 4 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH4_FC_DBGAUD0CH4_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH4 - Frame Composer Audio Data Channel 4 Register 1 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_SHIFT (0U)
/*! fc_dbgaud1ch4 - Frame Composer Audio Data Channel 4 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH4_FC_DBGAUD1CH4_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH4 - Frame Composer Audio Data Channel 4 Register 2 Configures the audio fixed data to be used in channel 4 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_SHIFT (0U)
/*! fc_dbgaud2ch4 - Frame Composer Audio Data Channel 4 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH4_FC_DBGAUD2CH4_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH5 - Frame Composer Audio Data Channel 5 Register 0 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_SHIFT (0U)
/*! fc_dbgaud0ch5 - Frame Composer Audio Data Channel 5 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH5_FC_DBGAUD0CH5_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH5 - Frame Composer Audio Data Channel 5 Register 1 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_SHIFT (0U)
/*! fc_dbgaud1ch5 - Frame Composer Audio Data Channel 5 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH5_FC_DBGAUD1CH5_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH5 - Frame Composer Audio Data Channel 5 Register 2 Configures the audio fixed data to be used in channel 5 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_SHIFT (0U)
/*! fc_dbgaud2ch5 - Frame Composer Audio Data Channel 5 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH5_FC_DBGAUD2CH5_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH6 - Frame Composer Audio Data Channel 6 Register 0 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_SHIFT (0U)
/*! fc_dbgaud0ch6 - Frame Composer Audio Data Channel 6 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH6_FC_DBGAUD0CH6_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH6 - Frame Composer Audio Data Channel 6 Register 1 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_SHIFT (0U)
/*! fc_dbgaud1ch6 - Frame Composer Audio Data Channel 6 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH6_FC_DBGAUD1CH6_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH6 - Frame Composer Audio Data Channel 6 Register 2 Configures the audio fixed data to be used in channel 6 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_SHIFT (0U)
/*! fc_dbgaud2ch6 - Frame Composer Audio Data Channel 6 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH6_FC_DBGAUD2CH6_MASK)
/*! @} */
/*! @name FC_DBGAUD0CH7 - Frame Composer Audio Data Channel 7 Register 0 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_SHIFT (0U)
/*! fc_dbgaud0ch7 - Frame Composer Audio Data Channel 7 Register 0
*/
#define FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD0CH7_FC_DBGAUD0CH7_MASK)
/*! @} */
/*! @name FC_DBGAUD1CH7 - Frame Composer Audio Data Channel 7 Register 1 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_SHIFT (0U)
/*! fc_dbgaud1ch7 - Frame Composer Audio Data Channel 7 Register 1
*/
#define FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD1CH7_FC_DBGAUD1CH7_MASK)
/*! @} */
/*! @name FC_DBGAUD2CH7 - Frame Composer Audio Data Channel 7 Register 2 Configures the audio fixed data to be used in channel 7 when in fixed audio selection. */
/*! @{ */
#define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_MASK (0xFFU)
#define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_SHIFT (0U)
/*! fc_dbgaud2ch7 - Frame Composer Audio Data Channel 7 Register 2
*/
#define FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7(x) (((uint8_t)(((uint8_t)(x)) << FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_SHIFT)) & FRAMECOMPOSER_FC_DBGAUD2CH7_FC_DBGAUD2CH7_MASK)
/*! @} */
/*!
* @}
*/ /* end of group FRAMECOMPOSER_Register_Masks */
/* FRAMECOMPOSER - Peripheral instance base addresses */
/** Peripheral FRAMECOMPOSER base address */
#define FRAMECOMPOSER_BASE (0x32FD9000u)
/** Peripheral FRAMECOMPOSER base pointer */
#define FRAMECOMPOSER ((FRAMECOMPOSER_Type *)FRAMECOMPOSER_BASE)
/** Array initializer of FRAMECOMPOSER peripheral base addresses */
#define FRAMECOMPOSER_BASE_ADDRS { FRAMECOMPOSER_BASE }
/** Array initializer of FRAMECOMPOSER peripheral base pointers */
#define FRAMECOMPOSER_BASE_PTRS { FRAMECOMPOSER }
/*!
* @}
*/ /* end of group FRAMECOMPOSER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GLUE_USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GLUE_USB_Peripheral_Access_Layer GLUE_USB Peripheral Access Layer
* @{
*/
/** GLUE_USB - Register Layout Typedef */
typedef struct {
__IO uint32_t USB_CTL0_ADDR; /**< USB_CTL0_ADDR, offset: 0x0 */
__IO uint32_t USB_CTL1_ADDR; /**< USB_CTL1_ADDR, offset: 0x4 */
uint8_t RESERVED_0[24];
__I uint32_t USB_STS0_ADDR; /**< USB_STS0_ADDR, offset: 0x20 */
uint8_t RESERVED_1[28];
__IO uint32_t PHY_CTL0_ADDR; /**< PHY_CTL0_ADDR, offset: 0x40 */
__IO uint32_t PHY_CTL1_ADDR; /**< PHY_CTL1_ADDR, offset: 0x44 */
__IO uint32_t PHY_CTL2_ADDR; /**< PHY_CTL2_ADDR, offset: 0x48 */
__IO uint32_t PHY_CTL3_ADDR; /**< PHY_CTL3_ADDR, offset: 0x4C */
__IO uint32_t PHY_CTL4_ADDR; /**< PHY_CTL4_ADDR, offset: 0x50 */
__IO uint32_t PHY_CTL5_ADDR; /**< PHY_CTL5_ADDR, offset: 0x54 */
__IO uint32_t PHY_CTL6_ADDR; /**< PHY_CTL6_ADDR, offset: 0x58 */
uint8_t RESERVED_2[36];
__IO uint32_t PHY_STS0_ADDR; /**< PHY_STS0_ADDR, offset: 0x80 */
} GLUE_USB_Type;
/* ----------------------------------------------------------------------------
-- GLUE_USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GLUE_USB_Register_Masks GLUE_USB Register Masks
* @{
*/
/*! @name USB_CTL0_ADDR - USB_CTL0_ADDR */
/*! @{ */
#define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_MASK (0x40U)
#define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_SHIFT (6U)
/*! host_u2_port_disable - USB 2.0 Port Disable control.
* 0b0..Port Enabled
* 0b1..Port Disabled. When '1', this signal stops reporting connect/disconnect events the port and keeps the port in disabled state.
*/
#define GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_U2_PORT_DISABLE_MASK)
#define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_MASK (0x80U)
#define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_SHIFT (7U)
/*! host_u3_port_disable - USB 3.0 SS Port Disable control.
* 0b0..Port Enabled
* 0b1..Port Disabled
*/
#define GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_U3_PORT_DISABLE_MASK)
#define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_MASK (0xF00U)
#define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_SHIFT (8U)
/*! bus_filter_bypass - Bus Filter Bypass.
*/
#define GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_BUS_FILTER_BYPASS_MASK)
#define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_MASK (0x1000U)
#define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT (12U)
/*! host_port_power_control_present - This port defines the bit [3] of Capability Parameters (HCCPARAMS).
* 0b0..Indicates that the port does not have port power switches.
* 0b1..Indicates that the port has port power switches.
*/
#define GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HOST_PORT_POWER_CONTROL_PRESENT_MASK)
#define GLUE_USB_USB_CTL0_ADDR_XHC_BME_MASK (0x4000U)
#define GLUE_USB_USB_CTL0_ADDR_XHC_BME_SHIFT (14U)
/*! xhc_bme - Disable the bus mastering capability of the xHC
* 0b0..Bus mastering capability is disabled. The host controller cannot use the bus master interface.
* 0b1..Bus mastering capability is enabled.
*/
#define GLUE_USB_USB_CTL0_ADDR_XHC_BME(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_XHC_BME_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_XHC_BME_MASK)
#define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_MASK (0x3F0000U)
#define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_SHIFT (16U)
/*! fladj_30mhz_reg - HS Jitter Adjustment.
*/
#define GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_FLADJ_30MHZ_REG_MASK)
#define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_MASK (0xC00000U)
#define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_SHIFT (22U)
/*! hub_port_perm_attach - Indicates if the device attached to a downstream port is permanently attached or not.
* 0b00..Not permanently attached
* 0b01..Permanently attached
*/
#define GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_HUB_PORT_PERM_ATTACH_MASK)
#define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_MASK (0x1000000U)
#define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_SHIFT (24U)
/*! utmi_iddig_sel - iddig source select signal
* 0b0..USB PHY ID0
* 0b1..GPIO PAD
*/
#define GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_UTMI_IDDIG_SEL_MASK)
#define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_MASK (0x2000000U)
#define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_SHIFT (25U)
/*! StartRxDetU3RxDet - StartRxdetU3RxDet of USB 3.0 SS Ports
*/
#define GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_STARTRXDETU3RXDET_MASK)
#define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_MASK (0x4000000U)
#define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_SHIFT (26U)
/*! DisRxDetU3RxDet - DisRxDetU3RxDet of USB 3.0 SS Ports
*/
#define GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_SHIFT)) & GLUE_USB_USB_CTL0_ADDR_DISRXDETU3RXDET_MASK)
/*! @} */
/*! @name USB_CTL1_ADDR - USB_CTL1_ADDR */
/*! @{ */
#define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_MASK (0x10000U)
#define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_SHIFT (16U)
/*! oc_polarity - Overcurrent polarity
* 0b0..Active high
* 0b1..Active low
*/
#define GLUE_USB_USB_CTL1_ADDR_OC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_SHIFT)) & GLUE_USB_USB_CTL1_ADDR_OC_POLARITY_MASK)
#define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_MASK (0x20000U)
#define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_SHIFT (17U)
/*! power_polarity - Power polarity
* 0b0..Active high
* 0b1..Active low
*/
#define GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_SHIFT)) & GLUE_USB_USB_CTL1_ADDR_POWER_POLARITY_MASK)
/*! @} */
/*! @name USB_STS0_ADDR - USB_STS0_ADDR */
/*! @{ */
#define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_MASK (0xFFFU)
#define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_SHIFT (0U)
/*! host_current_belt - Current BELT Value
*/
#define GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_SHIFT)) & GLUE_USB_USB_STS0_ADDR_HOST_CURRENT_BELT_MASK)
#define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_MASK (0x1000U)
#define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_SHIFT (12U)
/*! host_system_err - Host System Error
*/
#define GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_SHIFT)) & GLUE_USB_USB_STS0_ADDR_HOST_SYSTEM_ERR_MASK)
#define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_MASK (0x2000U)
#define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_SHIFT (13U)
/*! bc_chirp_on - When asserted indicates an imminent chirp signal.
*/
#define GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_SHIFT)) & GLUE_USB_USB_STS0_ADDR_BC_CHIRP_ON_MASK)
#define GLUE_USB_USB_STS0_ADDR_PME_GENERATION_MASK (0x4000U)
#define GLUE_USB_USB_STS0_ADDR_PME_GENERATION_SHIFT (14U)
/*! pme_generation - PME# Generation.
*/
#define GLUE_USB_USB_STS0_ADDR_PME_GENERATION(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_PME_GENERATION_SHIFT)) & GLUE_USB_USB_STS0_ADDR_PME_GENERATION_MASK)
#define GLUE_USB_USB_STS0_ADDR_IDDIG_MASK (0x8000U)
#define GLUE_USB_USB_STS0_ADDR_IDDIG_SHIFT (15U)
/*! IDDIG - This controller signal indicates whether the connected plug is a mini-A or mini-B plug.
* 0b0..Connected plug is a mini-A plug.
* 0b1..Connected plug is a mini-B plug.
*/
#define GLUE_USB_USB_STS0_ADDR_IDDIG(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_IDDIG_SHIFT)) & GLUE_USB_USB_STS0_ADDR_IDDIG_MASK)
#define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_MASK (0x10000U)
#define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_SHIFT (16U)
/*! DisRxDetU3RxDet_ack - DisRxDetU3RxDet_ack of USB 3.0 SS Ports
*/
#define GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_SHIFT)) & GLUE_USB_USB_STS0_ADDR_DISRXDETU3RXDET_ACK_MASK)
/*! @} */
/*! @name PHY_CTL0_ADDR - PHY_CTL0_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_MASK (0x4U)
#define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_SHIFT (2U)
/*! ref_ssp_en - Reference Clock Enable for SS function.
*/
#define GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_REF_SSP_EN_MASK)
#define GLUE_USB_PHY_CTL0_ADDR_FSEL_MASK (0x7E0U)
#define GLUE_USB_PHY_CTL0_ADDR_FSEL_SHIFT (5U)
/*! fsel - fsel
* 0b100111..100MHz ref clock
* 0b101010..24MHz ref clock
*/
#define GLUE_USB_PHY_CTL0_ADDR_FSEL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_FSEL_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_FSEL_MASK)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_EN_MASK (0x800U)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_EN_SHIFT (11U)
/*! ssc_en - Spread Spectrum Enable
*/
#define GLUE_USB_PHY_CTL0_ADDR_SSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_EN_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_EN_MASK)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_MASK (0x1FF000U)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_SHIFT (12U)
/*! ssc_ref_clk_sel - Spread Spectrum Reference Clock Shifting
*/
#define GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_REF_CLK_SEL_MASK)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_MASK (0xE00000U)
#define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_SHIFT (21U)
/*! ssc_range - Spread Spectrum Clock Range
* 0b000..4980
* 0b001..4492
* 0b010..4003
*/
#define GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_SHIFT)) & GLUE_USB_PHY_CTL0_ADDR_SSC_RANGE_MASK)
/*! @} */
/*! @name PHY_CTL1_ADDR - PHY_CTL1_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_MASK (0x1U)
#define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_SHIFT (0U)
/*! phy_reset - USB3.0 PHY Signal
*/
#define GLUE_USB_PHY_CTL1_ADDR_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_PHY_RESET_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_COMMONONN_MASK (0x2U)
#define GLUE_USB_PHY_CTL1_ADDR_COMMONONN_SHIFT (1U)
/*! COMMONONN - Common Block Power-Down Control
*/
#define GLUE_USB_PHY_CTL1_ADDR_COMMONONN(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_COMMONONN_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_COMMONONN_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_MASK (0x8000U)
#define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_SHIFT (15U)
/*! rtune_req - Resistor Tune Request
*/
#define GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_RTUNE_REQ_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_ACAENB0_MASK (0x10000U)
#define GLUE_USB_PHY_CTL1_ADDR_ACAENB0_SHIFT (16U)
/*! ACAENB0 - Battery Charging Source Select
*/
#define GLUE_USB_PHY_CTL1_ADDR_ACAENB0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_ACAENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_ACAENB0_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_DCDENB0_MASK (0x20000U)
#define GLUE_USB_PHY_CTL1_ADDR_DCDENB0_SHIFT (17U)
/*! DCDENB0 - Data Contact Detection Enable
*/
#define GLUE_USB_PHY_CTL1_ADDR_DCDENB0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_DCDENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_DCDENB0_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_MASK (0x40000U)
#define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_SHIFT (18U)
/*! CHRGSEL0 - Battery Charging Source Select
*/
#define GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_CHRGSEL0_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_MASK (0x80000U)
#define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_SHIFT (19U)
/*! VDATSRCENB0 - Battery Charging Sourcing Select
*/
#define GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_VDATSRCENB0_MASK)
#define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_MASK (0x100000U)
#define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_SHIFT (20U)
/*! VDATDETENB0 - Battery Charging Attach/Connect Detection Enable
*/
#define GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_SHIFT)) & GLUE_USB_PHY_CTL1_ADDR_VDATDETENB0_MASK)
/*! @} */
/*! @name PHY_CTL2_ADDR - PHY_CTL2_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_MASK (0x20U)
#define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_SHIFT (5U)
/*! FSDATAEXT0 - USB 1.1 SE0 Generation
*/
#define GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSDATAEXT0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_MASK (0x40U)
#define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_SHIFT (6U)
/*! FSSE0EXT0 - USB 1.1 Transmit Data
*/
#define GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSSE0EXT0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_MASK (0x80U)
#define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_SHIFT (7U)
/*! FSXCVROWNER0 - UTMI+/Serial Interface Select
*/
#define GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_FSXCVROWNER0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_MASK (0x100U)
#define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_SHIFT (8U)
/*! TXENABLEN0 - USB 1.1 Data Enable
*/
#define GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_TXENABLEN0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_MASK (0x400U)
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_SHIFT (10U)
/*! VBUSVLDEXT0 - External VBUS Valid Indicator
*/
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXT0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_MASK (0x800U)
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_SHIFT (11U)
/*! VBUSVLDEXTSEL0 - Selects the VBUSVLDEXTn input or the internal Session Valid comparator to
* indicate when the VBUSn signal on the USB cable is valid.
*/
#define GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_VBUSVLDEXTSEL0_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_MASK (0x4000U)
#define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_SHIFT (14U)
/*! utmi_idpullup - Analog ID Input Sample Enable
*/
#define GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_UTMI_IDPULLUP_MASK)
#define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_MASK (0x10000U)
#define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_SHIFT (16U)
/*! rx0loslfpsen - RX LOS LFPS Filter Enable
*/
#define GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_SHIFT)) & GLUE_USB_PHY_CTL2_ADDR_RX0LOSLFPSEN_MASK)
/*! @} */
/*! @name PHY_CTL3_ADDR - PHY_CTL3_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_MASK (0x7U)
#define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_SHIFT (0U)
/*! COMPIDISTUNE - Disconnect Threshold Adjustment.
* 0b111..+ 15.54%
* 0b110..+ 11.86%
* 0b101..+ 7.52%
* 0b100..+ 4.08
* 0b011..0 (default)
* 0b010..- 3.04%
* 0b001..- 6.5%
* 0b000..- 9.01%
*/
#define GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_COMPIDISTUNE_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TUNE0_MASK (0x38U)
#define GLUE_USB_PHY_CTL3_ADDR_TUNE0_SHIFT (3U)
/*! TUNE0 - VBUS Valid Threshold Adjustment
*/
#define GLUE_USB_PHY_CTL3_ADDR_TUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_MASK (0x1C0U)
#define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_SHIFT (6U)
/*! SQRXTUNE0 - Squelch Threshold Adjustment
* 0b111..- 22.32%
* 0b110..- 16.07%
* 0b101..- 10.71%
* 0b100..- 5.36%
* 0b011..0 (default)
* 0b010..+ 5.36%
* 0b001..+ 10.71%
* 0b000..+ 16.07%
*/
#define GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_SQRXTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_MASK (0x1E00U)
#define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_SHIFT (9U)
/*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment
* 0b1111..- 3.5%
* 0b0111..- 1.7%
* 0b0011..0 (default)
* 0b0001..+ 1.8%
* 0b0000..+ 3.5%
*/
#define GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXFSLSTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_MASK (0x6000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_SHIFT (13U)
/*! TXSHXSTUNE0 - Transmitter High-Speed Crossover Adjustment.
* 0b11..0 (default)
* 0b10..+ 14 mV
* 0b01..- 16 mV
* 0b00..Reserved
*/
#define GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXSHXSTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_MASK (0x18000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_SHIFT (15U)
/*! TXPREEMPMPTUNE0 - HS Transmitter Pre-Emphasis Current Control
* 0b11..3x pre-emphasis current
* 0b10..2x pre-emphasis current
* 0b01..1x pre-emphasis current
* 0b00..Disabled (default)
*/
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXPREEMPMPTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_MASK (0x20000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_SHIFT (17U)
#define GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXPREEMPULSETUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_MASK (0xC0000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_SHIFT (18U)
#define GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXRESTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_MASK (0x300000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_SHIFT (20U)
/*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment
* 0b11..- 3%
* 0b10..- 1%
* 0b01..0 (default)
* 0b00..+ 3%
*/
#define GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXRISETUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_MASK (0x3C00000U)
#define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_SHIFT (22U)
/*! TXREFTUNE0 - HS DC Voltage Level Adjustment
* 0b1111..+ 24%
* 0b1110..+ 22%
* 0b1101..+ 20%
* 0b1100..+ 18%
* 0b1011..+ 16%
* 0b1010..+ 14%
* 0b1001..+ 12%
* 0b1000..+ 10
* 0b0111..+ 8%
* 0b0110..+ 6%
* 0b0101..+ 4%
* 0b0100..+ 2%
* 0b0011..0 (default)
* 0b0010..- 2%
* 0b0001..- 4%
* 0b0000..- 6%
*/
#define GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TXREFTUNE0_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_MASK (0x1C000000U)
#define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_SHIFT (26U)
/*! ios_bias - Loss-of-Signal Detector Threshold Level Control
*/
#define GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_IOS_BIAS_MASK)
#define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_MASK (0xE0000000U)
#define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_SHIFT (29U)
/*! tx_vboost_lvl - TX Voltage Boost Level
*/
#define GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_SHIFT)) & GLUE_USB_PHY_CTL3_ADDR_TX_VBOOST_LVL_MASK)
/*! @} */
/*! @name PHY_CTL4_ADDR - PHY_CTL4_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_MASK (0x7FE0U)
#define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_SHIFT (5U)
/*! pcs_rx_los_msk_val - Configurable Loss-of-Signal Mask Width
*/
#define GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_RX_LOS_MSK_VAL_MASK)
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_MASK (0x1F8000U)
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_SHIFT (15U)
/*! pcs_tx_deemph_3b5db - TX De-Emphasis at 3.5 dB
*/
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_3B5DB_MASK)
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_MASK (0x7E00000U)
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_SHIFT (21U)
/*! pcs_tx_deemph_6db - TX De-Emphasis at 6 dB
*/
#define GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_SHIFT)) & GLUE_USB_PHY_CTL4_ADDR_PCS_TX_DEEMPH_6DB_MASK)
/*! @} */
/*! @name PHY_CTL5_ADDR - PHY_CTL5_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_MASK (0x7FU)
#define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_SHIFT (0U)
/*! pcs_tx_swing_full - TX Amplitude (Full Swing Mode)
*/
#define GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_SHIFT)) & GLUE_USB_PHY_CTL5_ADDR_PCS_TX_SWING_FULL_MASK)
/*! @} */
/*! @name PHY_CTL6_ADDR - PHY_CTL6_ADDR */
/*! @{ */
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_MASK (0x4U)
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_SHIFT (2U)
/*! lane0_tx2rx_loopbk - Loopback
*/
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_SHIFT)) & GLUE_USB_PHY_CTL6_ADDR_LANE0_TX2RX_LOOPBK_MASK)
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_MASK (0x8U)
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_SHIFT (3U)
/*! lane0_ext_pclk_req - External PIPE Clock Enable Request
*/
#define GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_SHIFT)) & GLUE_USB_PHY_CTL6_ADDR_LANE0_EXT_PCLK_REQ_MASK)
/*! @} */
/*! @name PHY_STS0_ADDR - PHY_STS0_ADDR */
/*! @{ */
#define GLUE_USB_PHY_STS0_ADDR_CHGDET0_MASK (0x10U)
#define GLUE_USB_PHY_STS0_ADDR_CHGDET0_SHIFT (4U)
/*! CHGDET0 - Battery Charger Detection Output
*/
#define GLUE_USB_PHY_STS0_ADDR_CHGDET0(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_CHGDET0_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_CHGDET0_MASK)
#define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_MASK (0x40U)
#define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_SHIFT (6U)
/*! rtune_ack - Resistor Tune Acknowledge. While asserted, indicates that a resistor tune is still in progress.
*/
#define GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_RTUNE_ACK_MASK)
#define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_MASK (0x40000000U)
#define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_SHIFT (30U)
/*! pipe_clk_vld - USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set.
*/
#define GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_PIPE_CLK_VLD_MASK)
#define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_MASK (0x80000000U)
#define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_SHIFT (31U)
/*! utmi_clk_vld - USB3.0 PHY Signal synchronised by USB bus clock.After PHY and core reset pipe clock is stable if this bit is set.
*/
#define GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_SHIFT)) & GLUE_USB_PHY_STS0_ADDR_UTMI_CLK_VLD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GLUE_USB_Register_Masks */
/* GLUE_USB - Peripheral instance base addresses */
/** Peripheral USB1_GLUE base address */
#define USB1_GLUE_BASE (0x381F0000u)
/** Peripheral USB1_GLUE base pointer */
#define USB1_GLUE ((GLUE_USB_Type *)USB1_GLUE_BASE)
/** Peripheral USB2_GLUE base address */
#define USB2_GLUE_BASE (0x382F0000u)
/** Peripheral USB2_GLUE base pointer */
#define USB2_GLUE ((GLUE_USB_Type *)USB2_GLUE_BASE)
/** Array initializer of GLUE_USB peripheral base addresses */
#define GLUE_USB_BASE_ADDRS { USB1_GLUE_BASE, USB2_GLUE_BASE }
/** Array initializer of GLUE_USB peripheral base pointers */
#define GLUE_USB_BASE_PTRS { USB1_GLUE, USB2_GLUE }
/*!
* @}
*/ /* end of group GLUE_USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
* @{
*/
/** GPC - Register Layout Typedef */
typedef struct {
__IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */
__IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */
__IO uint32_t LPCR_M7; /**< Low power control register of CPU1, offset: 0x8 */
uint8_t RESERVED_0[8];
__IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */
__IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */
uint8_t RESERVED_1[4];
__IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */
__IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */
__IO uint32_t PGC_ACK_SEL_M7; /**< PGC acknowledge signal selection of M7 platform, offset: 0x28 */
__IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */
__IO uint32_t IMR_CORE0_A53[5]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 5 of A53 core0, array offset: 0x30, array step: 0x4 */
__IO uint32_t IMR_CORE1_A53[5]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 5 of A53 core1, array offset: 0x44, array step: 0x4 */
__IO uint32_t IMR_M7[5]; /**< IRQ masking register 1 of M7..IRQ masking register 5 of M7, array offset: 0x58, array step: 0x4 */
uint8_t RESERVED_2[20];
__I uint32_t ISR_A53[5]; /**< IRQ status register 1 of A53..IRQ status register 5 of A53, array offset: 0x80, array step: 0x4 */
__I uint32_t ISR_M7[5]; /**< IRQ status register 1 of M7..IRQ status register 5 of M7, array offset: 0x94, array step: 0x4 */
uint8_t RESERVED_3[40];
__IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xD0 */
__IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xD4 */
__IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xD8 */
__IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xDC */
__IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0xE0 */
__IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0xE4 */
uint8_t RESERVED_4[32];
__I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x108 */
__I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x10C, array step: 0x4 */
__I uint32_t M7_MIX_PGC_PUP_STATUS[3]; /**< M7 MIX PGC software up trigger status register, array offset: 0x118, array step: 0x4 */
__I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x124, array step: 0x4 */
__I uint32_t M7_PU_PGC_PUP_STATUS[3]; /**< M7 PU PGC software up trigger status register, array offset: 0x130, array step: 0x4 */
__I uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x13C */
__I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x140, array step: 0x4 */
__I uint32_t M7_MIX_PGC_PDN_STATUS[3]; /**< M7 MIX PGC software power down trigger status register, array offset: 0x14C, array step: 0x4 */
__I uint32_t A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x158, array step: 0x4 */
__I uint32_t M7_PU_PGC_PDN_STATUS[3]; /**< M7 PU PGC software down trigger status, array offset: 0x164, array step: 0x4 */
__IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x170 */
__IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x174 */
__IO uint32_t M7_MIX_PDN_FLG; /**< M7 MIX PDN FLG, offset: 0x178 */
__IO uint32_t M7_PU_PDN_FLG; /**< M7 PU PDN FLG, offset: 0x17C */
__IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x180 */
uint8_t RESERVED_5[12];
__IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x190 */
__IO uint32_t IMR_CORE2_A53[5]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 5 of A53 core2, array offset: 0x194, array step: 0x4 */
__IO uint32_t IMR_CORE3_A53[5]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 5 of A53 core3, array offset: 0x1A8, array step: 0x4 */
__IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1BC */
__IO uint32_t ACK_SEL_A53_PU1; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1C0 */
__IO uint32_t ACK_SEL_M7_PU; /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1C4 */
__IO uint32_t ACK_SEL_M7_PU1; /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1C8 */
__IO uint32_t PGC_CPU_A53_MAPPING; /**< PGC CPU A53 mapping, offset: 0x1CC */
__IO uint32_t PGC_CPU_M7_MAPPING; /**< PGC CPU M7 mapping, offset: 0x1D0 */
uint8_t RESERVED_6[44];
__IO uint32_t SLT_CFG[27]; /**< Slot configure register for CPUs, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_7[20];
struct { /* offset: 0x280, array step: 0x8 */
__IO uint32_t SLT_CFG_PU; /**< Slot configure register for PGC PUs, array offset: 0x280, array step: 0x8 */
__IO uint32_t SLT_CFG_PU1; /**< Extended slot configure register for PGC PUs, array offset: 0x284, array step: 0x8 */
} SLTn_CFG_PU[27];
} GPC_Type;
/* ----------------------------------------------------------------------------
-- GPC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_Register_Masks GPC Register Masks
* @{
*/
/*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */
/*! @{ */
#define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U)
#define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U)
/*! LPM0
* 0b00..Remain in RUN mode
* 0b01..Transfer to WAIT mode
* 0b10..Transfer to STOP mode
* 0b11..Reserved
*/
#define GPC_LPCR_A53_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK)
#define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU)
#define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U)
/*! LPM1
* 0b00..Remain in RUN mode
* 0b01..Transfer to WAIT mode
* 0b10..Transfer to STOP mode
* 0b11..Reserved
*/
#define GPC_LPCR_A53_BSC_LPM1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK)
#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK (0x40U)
#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT (6U)
/*! MST0_LPM_HSK_MASK - MASTER0 LPM handshake mask
* 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0
* 0b1..disable MASTER0 LPM handshake, mask ACK from MASTER0
*/
#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK)
#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK (0x80U)
#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT (7U)
/*! MST1_LPM_HSK_MASK - MASTER1 LPM handshake mask
* 0b0..enable MASTER1 LPM handshake, wait ACK from MASTER1
* 0b1..disable MASTER1 LPM handshake, mask ACK from MASTER1
*/
#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK)
#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK (0x100U)
#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT (8U)
/*! MST2_LPM_HSK_MASK - MASTER2 LPM handshake mask
* 0b0..enable MASTER2 LPM handshake, wait ACK from MASTER2
* 0b1..disable MASTER2 LPM handshake, mask ACK from MASTER2
*/
#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT)) & GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK)
#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U)
#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U)
/*! CPU_CLK_ON_LPM
* 0b0..A53 clock disabled on wait/stop mode
* 0b1..A53 clock enabled on wait/stop mode
*/
#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK)
#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U)
#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U)
/*! MASK_CORE0_WFI
* 0b0..WFI for CORE0 is not masked
* 0b1..WFI for CORE0 is masked
*/
#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK)
#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U)
#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U)
/*! MASK_CORE1_WFI
* 0b0..WFI for CORE1 is not masked
* 0b1..WFI for CORE1 is masked
*/
#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK)
#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U)
#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U)
/*! MASK_CORE2_WFI
* 0b0..WFI for CORE2 is not masked
* 0b1..WFI for CORE2 is masked
*/
#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK)
#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U)
#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U)
/*! MASK_CORE3_WFI
* 0b0..WFI for CORE3 is not masked
* 0b1..WFI for CORE3 is masked
*/
#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U)
/*! IRQ_SRC_C2
* 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
* 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
*/
#define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U)
/*! IRQ_SRC_C3
* 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more specific information.
* 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during low power mode when this bit is set to 1'b1.
*/
#define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK)
#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U)
#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U)
/*! MASK_SCU_WFI
* 0b0..WFI for SCU is not masked
* 0b1..WFI for SCU is masked
*/
#define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK)
#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U)
#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U)
/*! MASK_L2CC_WFI
* 0b0..WFI for L2 cache controller is not masked
* 0b1..WFI for L2 cache controller is masked
*/
#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U)
/*! IRQ_SRC_C0
* 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for more specific information
* 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power mode when this bit is set to 1'b1
*/
#define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U)
#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U)
/*! IRQ_SRC_C1
* 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for more specific information
* 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power mode when this bit is set to 1'b1
*/
#define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK)
#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U)
#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U)
/*! IRQ_SRC_A53_WUP
* 0b0..LPM wakeup source be "OR" result of
* LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting
* 0b1..LPM wakeup source from external INT[127:0], masked by IMR0
*/
#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK)
#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U)
#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U)
/*! MASK_DSM_TRIGGER
* 0b0..DSM trigger of A53 platform will not be masked
* 0b1..DSM trigger of A53 platform will be masked
*/
#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK)
/*! @} */
/*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */
/*! @{ */
#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U)
#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U)
/*! EN_C0_WFI_PDN
* 0b0..CORE0 will not be power down with WFI request
* 0b1..CORE0 will be power down with WFI request
*/
#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U)
#define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U)
/*! EN_C0_PDN
* 0b0..CORE0 will not be power down with low power mode request
* 0b1..CORE0 will be power down with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C0_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U)
#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U)
/*! EN_C1_WFI_PDN
* 0b0..CORE1 will not be power down with WFI request
* 0b1..CORE1 will be power down with WFI request
*/
#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U)
#define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U)
/*! EN_C1_PDN
* 0b0..CORE1 will not be power down with low power mode request
* 0b1..CORE1 will be power down with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C1_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U)
#define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U)
/*! EN_PLAT_PDN
* 0b0..SCU and L2 cache RAM will not be power down with low power mode request
* 0b1..SCU and L2 cache RAM will be power down with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U)
#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U)
/*! EN_L2_WFI_PDN
* 0b0..SCU and L2 will not be power down with WFI request
* 0b1..SCU and L2 will be power down with WFI request (default)
*/
#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U)
#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U)
/*! EN_C0_IRQ_PUP
* 0b0..CORE0 will not power up with IRQ request
* 0b1..CORE0 will power up with IRQ request
*/
#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U)
#define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U)
/*! EN_C0_PUP
* 0b0..CORE0 will not power up with low power mode request
* 0b1..CORE0 will power up with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C0_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U)
#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U)
/*! EN_C1_IRQ_PUP
* 0b0..CORE1 will not power up with IRQ request
* 0b1..CORE1 will power up with IRQ request
*/
#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U)
#define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U)
/*! EN_C1_PUP
* 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
* 0b1..CORE1 will power up with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C1_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U)
#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U)
/*! EN_C2_WFI_PDN
* 0b0..CORE2 will not be power down with WFI request
* 0b1..CORE2 will be power down with WFI request
*/
#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U)
#define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U)
/*! EN_C2_PDN
* 0b0..CORE2 will not be power down with low power mode request
* 0b1..CORE2 will be power down with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C2_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U)
#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U)
/*! EN_C3_WFI_PDN
* 0b0..CORE3 will not be power down with WFI request
* 0b1..CORE3 will be power down with WFI request
*/
#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U)
#define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U)
/*! EN_C3_PDN
* 0b0..CORE3 will not be power down with low power mode request
* 0b1..CORE3 will be power down with low power mode request
*/
#define GPC_LPCR_A53_AD_EN_C3_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK)
#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U)
#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U)
/*! EN_C2_IRQ_PUP
* 0b0..CORE2 will not power up with IRQ request
* 0b1..CORE2 will power up with IRQ request
*/
#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U)
#define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U)
/*! EN_C2_PUP
* 0b0..CORE2 will not power up with lower power mode request
* 0b1..CORE2 will power up with low power mode request (only used wake up from CPU_OFF)
*/
#define GPC_LPCR_A53_AD_EN_C2_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U)
#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U)
/*! EN_C3_IRQ_PUP
* 0b0..CORE3 will not power up with IRQ request
* 0b1..CORE3 will power up with IRQ request
*/
#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK)
#define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U)
#define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U)
/*! EN_C3_PUP
* 0b0..CORE3 will not power up with lower power mode request
* 0b1..CORE3 will power up with low power mode request (only used wake up from CPU_OFF)
*/
#define GPC_LPCR_A53_AD_EN_C3_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK)
#define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U)
#define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U)
/*! L2PGE
* 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
* 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode)
*/
#define GPC_LPCR_A53_AD_L2PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK)
/*! @} */
/*! @name LPCR_M7 - Low power control register of CPU1 */
/*! @{ */
#define GPC_LPCR_M7_LPM0_MASK (0x3U)
#define GPC_LPCR_M7_LPM0_SHIFT (0U)
/*! LPM0
* 0b00..Remain in RUN mode
* 0b01..Transfer to WAIT mode
* 0b10..Transfer to STOP mode
* 0b11..Reserved
*/
#define GPC_LPCR_M7_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_LPM0_SHIFT)) & GPC_LPCR_M7_LPM0_MASK)
#define GPC_LPCR_M7_EN_M7_PDN_MASK (0x4U)
#define GPC_LPCR_M7_EN_M7_PDN_SHIFT (2U)
#define GPC_LPCR_M7_EN_M7_PDN(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PDN_SHIFT)) & GPC_LPCR_M7_EN_M7_PDN_MASK)
#define GPC_LPCR_M7_EN_M7_PUP_MASK (0x8U)
#define GPC_LPCR_M7_EN_M7_PUP_SHIFT (3U)
#define GPC_LPCR_M7_EN_M7_PUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PUP_SHIFT)) & GPC_LPCR_M7_EN_M7_PUP_MASK)
#define GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK (0x4000U)
#define GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT (14U)
/*! CPU_CLK_ON_LPM
* 0b0..M7 clock disabled on wait/stop mode.
* 0b1..M7 clock enabled on wait/stop mode.
*/
#define GPC_LPCR_M7_CPU_CLK_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK)
#define GPC_LPCR_M7_MASK_M7_WFI_MASK (0x10000U)
#define GPC_LPCR_M7_MASK_M7_WFI_SHIFT (16U)
/*! MASK_M7_WFI
* 0b0..WFI for M7 is not masked
* 0b1..WFI for M7 is masked
*/
#define GPC_LPCR_M7_MASK_M7_WFI(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_M7_WFI_SHIFT)) & GPC_LPCR_M7_MASK_M7_WFI_MASK)
#define GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK (0x80000000U)
#define GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT (31U)
/*! MASK_DSM_TRIGGER
* 0b0..DSM trigger of M7 platform will not be masked
* 0b1..DSM trigger of M7 platform will be masked
*/
#define GPC_LPCR_M7_MASK_DSM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK)
/*! @} */
/*! @name SLPCR - System low power control register */
/*! @{ */
#define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U)
#define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U)
/*! BYPASS_PMIC_READY
* 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby voltage was enabled
* 0b1..Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power mode if standby voltage was enabled
*/
#define GPC_SLPCR_BYPASS_PMIC_READY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK)
#define GPC_SLPCR_SBYOS_MASK (0x2U)
#define GPC_SLPCR_SBYOS_SHIFT (1U)
/*! SBYOS
* 0b0..On chip oscillator will not be powered down, after next entrance to DSM.
* 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external
* oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count
* GPC will continue with the exit from DSM process.
*/
#define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK)
#define GPC_SLPCR_VSTBY_MASK (0x4U)
#define GPC_SLPCR_VSTBY_SHIFT (2U)
/*! VSTBY
* 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain negated - '0')
* 0b1..Voltage will be changed to standby voltage after next entrance to stop mode.
*/
#define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK)
#define GPC_SLPCR_STBY_COUNT_MASK (0x38U)
#define GPC_SLPCR_STBY_COUNT_SHIFT (3U)
/*! STBY_COUNT
* 0b000..GPC will wait 4 ckil clock cycles
* 0b001..GPC will wait 8 ckil clock cycles
* 0b010..GPC will wait 16 ckil clock cycles
* 0b011..GPC will wait 32 ckil clock cycles
* 0b100..GPC will wait 64 ckil clock cycles
* 0b101..GPC will wait 128 ckil clock cycles
* 0b110..GPC will wait 256 ckil clock cycles
* 0b111..GPC will wait 512 ckil clock cycles
*/
#define GPC_SLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK)
#define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U)
#define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U)
/*! COSC_PWRDOWN
* 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
* 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
*/
#define GPC_SLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK)
#define GPC_SLPCR_COSC_EN_MASK (0x80U)
#define GPC_SLPCR_COSC_EN_SHIFT (7U)
/*! COSC_EN
* 0b0..Disable on-chip oscillator
* 0b1..Enable on-chip oscillator
*/
#define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK)
#define GPC_SLPCR_OSCCNT_MASK (0xFF00U)
#define GPC_SLPCR_OSCCNT_SHIFT (8U)
/*! OSCCNT
* 0b00000000..count 1 ckil
* 0b11111111..count 256 ckils
*/
#define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK)
#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U)
#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U)
#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK)
#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U)
#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U)
#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK)
#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK (0x40000U)
#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT (18U)
#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK)
#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK (0x80000U)
#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT (19U)
#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK)
#define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U)
#define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U)
/*! DISABLE_A53_IS_DSM
* 0b0..Enable A53 isolation signal in DSM
* 0b1..Disable A53 isolation signal in DSM
*/
#define GPC_SLPCR_DISABLE_A53_IS_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK)
#define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U)
#define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U)
/*! REG_BYPASS_COUNT
* 0b000000..no delay
* 0b000001..1 CKIL clock period delay
* 0b111111..63 CKIL clock period delay
*/
#define GPC_SLPCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK)
#define GPC_SLPCR_RBC_EN_MASK (0x40000000U)
#define GPC_SLPCR_RBC_EN_SHIFT (30U)
/*! RBC_EN
* 0b0..REG_BYPASS_COUNTER disabled
* 0b1..REG_BYPASS_COUNTER enabled
*/
#define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK)
#define GPC_SLPCR_EN_DSM_MASK (0x80000000U)
#define GPC_SLPCR_EN_DSM_SHIFT (31U)
/*! EN_DSM
* 0b0..DSM disabled
* 0b1..DSM enabled
*/
#define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK)
/*! @} */
/*! @name MST_CPU_MAPPING - MASTER LPM Handshake */
/*! @{ */
#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U)
#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U)
/*! MST0_CPU_MAPPING - MASTER0 CPU Mapping
* 0b0..GPC will not send out power off requirement
* 0b1..GPC will send out power off requirement
*/
#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK)
#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK (0x2U)
#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT (1U)
/*! MST1_CPU_MAPPING - MASTER1 CPU Mapping
* 0b0..GPC will not send out power off requirement
* 0b1..GPC will send out power off requirement
*/
#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK)
#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK (0x4U)
#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT (2U)
/*! MST2_CPU_MAPPING - MASTER2 CPU Mapping
* 0b0..GPC will not send out power off requirement
* 0b1..GPC will send out power off requirement
*/
#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT)) & GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK)
/*! @} */
/*! @name MLPCR - Memory low power control register */
/*! @{ */
#define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U)
#define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U)
/*! MEMLP_CTL_DIS
* 0b0..Enable RAM low power control
* 0b1..Disable RAM low power control
*/
#define GPC_MLPCR_MEMLP_CTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK)
#define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U)
#define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U)
/*! MEMLP_RET_SEL
* 0b0..retention mode 2
* 0b1..retention mode 1
*/
#define GPC_MLPCR_MEMLP_RET_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK)
#define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U)
#define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U)
/*! ROMLP_PDN_DIS
* 0b0..Enable ROM shut down control(should also enable RAM low power control);
* 0b1..Disable ROM shut down control
*/
#define GPC_MLPCR_ROMLP_PDN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK)
#define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U)
#define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U)
#define GPC_MLPCR_MEMLP_ENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK)
#define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U)
#define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U)
#define GPC_MLPCR_MEM_EXT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK)
#define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U)
#define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U)
#define GPC_MLPCR_MEMLP_RET_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK)
/*! @} */
/*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */
/*! @{ */
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U)
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U)
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x2U)
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (1U)
#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x4U)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (2U)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x8U)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (3U)
#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x10U)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (4U)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20U)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (5U)
#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x40U)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (6U)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x80U)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (7U)
#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x100U)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (8U)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x200U)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (9U)
#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK (0x1000U)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT (12U)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK (0x2000U)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT (13U)
#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x40000000U)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (30U)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U)
#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name PGC_ACK_SEL_M7 - PGC acknowledge signal selection of M7 platform */
/*! @{ */
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK (0x1U)
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT (0U)
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK (0x2U)
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT (1U)
#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK (0x1000U)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT (12U)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK (0x2000U)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT (13U)
#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK (0x40000000U)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT (30U)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK (0x80000000U)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT (31U)
#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT)) & GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name MISC - GPC Miscellaneous register */
/*! @{ */
#define GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK (0x1U)
#define GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT (0U)
/*! M7_SLEEP_HOLD_REQ_B
* 0b0..Hold M7 platform in sleep mode. This bit is a software control bit to M7 platform.
* 0b1..Don't hold M7 platform in sleep mode.
*/
#define GPC_MISC_M7_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK)
#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U)
#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U)
/*! A53_SLEEP_HOLD_REQ_B
* 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
* 0b1..Don't hold A53 platform in sleep mode.
*/
#define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK)
#define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U)
#define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U)
/*! GPC_IRQ_MASK
* 0b0..Not masked
* 0b1..Interrupt / event is masked
*/
#define GPC_MISC_GPC_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK)
#define GPC_MISC_M7_PDN_REQ_MASK_MASK (0x100U)
#define GPC_MISC_M7_PDN_REQ_MASK_SHIFT (8U)
/*! M7_PDN_REQ_MASK
* 0b0..M7 power down request to virtual M7 PGC will be masked.
* 0b1..M7 power down request to virtual M7 PGC will not be masked. Set this bit to 1'b1 when M7 virtual PGC is used.
*/
#define GPC_MISC_M7_PDN_REQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M7_PDN_REQ_MASK_MASK)
#define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U)
#define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U)
#define GPC_MISC_A53_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK)
#define GPC_MISC_M7_BYPASS_PUP_MASK_MASK (0x2000000U)
#define GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT (25U)
#define GPC_MISC_M7_BYPASS_PUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M7_BYPASS_PUP_MASK_MASK)
#define GPC_MISC_MIPI_LDO_EN_CTRL_MASK (0x80000000U)
#define GPC_MISC_MIPI_LDO_EN_CTRL_SHIFT (31U)
#define GPC_MISC_MIPI_LDO_EN_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GPC_MISC_MIPI_LDO_EN_CTRL_SHIFT)) & GPC_MISC_MIPI_LDO_EN_CTRL_MASK)
/*! @} */
/*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 5 of A53 core0 */
/*! @{ */
#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U)
/*! IMR1_CORE0_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK)
#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U)
/*! IMR2_CORE0_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK)
#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U)
/*! IMR3_CORE0_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK)
#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U)
/*! IMR4_CORE0_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK)
#define GPC_IMR_CORE0_A53_IMR5_CORE0_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE0_A53_IMR5_CORE0_A53_SHIFT (0U)
/*! IMR5_CORE0_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE0_A53_IMR5_CORE0_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR5_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR5_CORE0_A53_MASK)
/*! @} */
/* The count of GPC_IMR_CORE0_A53 */
#define GPC_IMR_CORE0_A53_COUNT (5U)
/*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 5 of A53 core1 */
/*! @{ */
#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U)
/*! IMR1_CORE1_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK)
#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U)
/*! IMR2_CORE1_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK)
#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U)
/*! IMR3_CORE1_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK)
#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U)
/*! IMR4_CORE1_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK)
#define GPC_IMR_CORE1_A53_IMR5_CORE1_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE1_A53_IMR5_CORE1_A53_SHIFT (0U)
/*! IMR5_CORE1_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE1_A53_IMR5_CORE1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR5_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR5_CORE1_A53_MASK)
/*! @} */
/* The count of GPC_IMR_CORE1_A53 */
#define GPC_IMR_CORE1_A53_COUNT (5U)
/*! @name IMR_M7 - IRQ masking register 1 of M7..IRQ masking register 5 of M7 */
/*! @{ */
#define GPC_IMR_M7_IMR1_M7_MASK (0xFFFFFFFFU)
#define GPC_IMR_M7_IMR1_M7_SHIFT (0U)
/*! IMR1_M7
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_M7_IMR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR1_M7_SHIFT)) & GPC_IMR_M7_IMR1_M7_MASK)
#define GPC_IMR_M7_IMR2_M7_MASK (0xFFFFFFFFU)
#define GPC_IMR_M7_IMR2_M7_SHIFT (0U)
/*! IMR2_M7
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_M7_IMR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR2_M7_SHIFT)) & GPC_IMR_M7_IMR2_M7_MASK)
#define GPC_IMR_M7_IMR3_M7_MASK (0xFFFFFFFFU)
#define GPC_IMR_M7_IMR3_M7_SHIFT (0U)
/*! IMR3_M7
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_M7_IMR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR3_M7_SHIFT)) & GPC_IMR_M7_IMR3_M7_MASK)
#define GPC_IMR_M7_IMR4_M7_MASK (0xFFFFFFFFU)
#define GPC_IMR_M7_IMR4_M7_SHIFT (0U)
/*! IMR4_M7
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_M7_IMR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR4_M7_SHIFT)) & GPC_IMR_M7_IMR4_M7_MASK)
#define GPC_IMR_M7_IMR5_M7_MASK (0xFFFFFFFFU)
#define GPC_IMR_M7_IMR5_M7_SHIFT (0U)
/*! IMR5_M7
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_M7_IMR5_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR5_M7_SHIFT)) & GPC_IMR_M7_IMR5_M7_MASK)
/*! @} */
/* The count of GPC_IMR_M7 */
#define GPC_IMR_M7_COUNT (5U)
/*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 5 of A53 */
/*! @{ */
#define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU)
#define GPC_ISR_A53_ISR1_A53_SHIFT (0U)
#define GPC_ISR_A53_ISR1_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK)
#define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU)
#define GPC_ISR_A53_ISR2_A53_SHIFT (0U)
#define GPC_ISR_A53_ISR2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK)
#define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU)
#define GPC_ISR_A53_ISR3_A53_SHIFT (0U)
#define GPC_ISR_A53_ISR3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK)
#define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU)
#define GPC_ISR_A53_ISR4_A53_SHIFT (0U)
#define GPC_ISR_A53_ISR4_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK)
#define GPC_ISR_A53_ISR5_A53_MASK (0xFFFFFFFFU)
#define GPC_ISR_A53_ISR5_A53_SHIFT (0U)
#define GPC_ISR_A53_ISR5_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR5_A53_SHIFT)) & GPC_ISR_A53_ISR5_A53_MASK)
/*! @} */
/* The count of GPC_ISR_A53 */
#define GPC_ISR_A53_COUNT (5U)
/*! @name ISR_M7 - IRQ status register 1 of M7..IRQ status register 5 of M7 */
/*! @{ */
#define GPC_ISR_M7_ISR1_M7_MASK (0xFFFFFFFFU)
#define GPC_ISR_M7_ISR1_M7_SHIFT (0U)
#define GPC_ISR_M7_ISR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR1_M7_SHIFT)) & GPC_ISR_M7_ISR1_M7_MASK)
#define GPC_ISR_M7_ISR2_M7_MASK (0xFFFFFFFFU)
#define GPC_ISR_M7_ISR2_M7_SHIFT (0U)
#define GPC_ISR_M7_ISR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR2_M7_SHIFT)) & GPC_ISR_M7_ISR2_M7_MASK)
#define GPC_ISR_M7_ISR3_M7_MASK (0xFFFFFFFFU)
#define GPC_ISR_M7_ISR3_M7_SHIFT (0U)
#define GPC_ISR_M7_ISR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR3_M7_SHIFT)) & GPC_ISR_M7_ISR3_M7_MASK)
#define GPC_ISR_M7_ISR4_M7_MASK (0xFFFFFFFFU)
#define GPC_ISR_M7_ISR4_M7_SHIFT (0U)
#define GPC_ISR_M7_ISR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR4_M7_SHIFT)) & GPC_ISR_M7_ISR4_M7_MASK)
#define GPC_ISR_M7_ISR5_M7_MASK (0xFFFFFFFFU)
#define GPC_ISR_M7_ISR5_M7_SHIFT (0U)
#define GPC_ISR_M7_ISR5_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR5_M7_SHIFT)) & GPC_ISR_M7_ISR5_M7_MASK)
/*! @} */
/* The count of GPC_ISR_M7 */
#define GPC_ISR_M7_COUNT (5U)
/*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */
/*! @{ */
#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x4U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (2U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK)
#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK)
/*! @} */
/*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */
/*! @{ */
#define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_MASK (0x1U)
#define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_SHIFT (0U)
#define GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_MF_SW_PUP_REQ_MASK)
#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK (0x2U)
#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT (1U)
#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT)) & GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK)
/*! @} */
/*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */
/*! @{ */
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_MASK (0x1U)
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_SHIFT (0U)
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY1_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK (0x2U)
#define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT (1U)
#define GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_PCIE_PHY_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_MASK (0x4U)
#define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_SHIFT (2U)
#define GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB1_PHY_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_MASK (0x8U)
#define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_SHIFT (3U)
#define GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_USB2_PHY_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_MASK (0x10U)
#define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_SHIFT (4U)
#define GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MLMIX_PHY_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_MASK (0x20U)
#define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT (5U)
#define GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_AUDIOMIX_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_MASK (0x40U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_SHIFT (6U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_2D_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_MASK (0x80U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_SHIFT (7U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_SHARE_LOGIC_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_MASK (0x100U)
#define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_SHIFT (8U)
#define GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPUMIX_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_MASK (0x200U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_SHIFT (9U)
#define GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_GPU_3D_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_MASK (0x400U)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_SHIFT (10U)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MEDIMIX_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_MASK (0x800U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_SHIFT (11U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_G1_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_MASK (0x1000U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_SHIFT (12U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_G2_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_MASK (0x2000U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_SHIFT (13U)
#define GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_VPU_VC8K_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_MASK (0x4000U)
#define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_SHIFT (14U)
#define GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMIMIX_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_MASK (0x8000U)
#define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_SHIFT (15U)
#define GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HDMI_PHY_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_MASK (0x10000U)
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_SHIFT (16U)
#define GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MIPI_PHY2_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_MASK (0x20000U)
#define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_SHIFT (17U)
#define GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_HSIOMIX_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_MASK (0x40000U)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_SHIFT (18U)
#define GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_MEDIA_ISP_DWP_SW_PUP_REQ_MASK)
#define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_MASK (0x80000U)
#define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_SHIFT (19U)
#define GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_SHIFT)) & GPC_PU_PGC_SW_PUP_REQ_DDRMIX_SW_PUP_REQ_MASK)
/*! @} */
/*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */
/*! @{ */
#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK (0x4U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT (2U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK)
#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK)
/*! @} */
/*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */
/*! @{ */
#define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_MASK (0x1U)
#define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_SHIFT (0U)
#define GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_MF_SW_PDN_REQ_MASK)
#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK (0x2U)
#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT (1U)
#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT)) & GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK)
/*! @} */
/*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */
/*! @{ */
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_MASK (0x1U)
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_SHIFT (0U)
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY1_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK (0x2U)
#define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT (1U)
#define GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_PCIE_PHY_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_MASK (0x4U)
#define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_SHIFT (2U)
#define GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB1_PHY_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_MASK (0x8U)
#define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_SHIFT (3U)
#define GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_USB2_PHY_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_MASK (0x10U)
#define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_SHIFT (4U)
#define GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MLMIX_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_MASK (0x20U)
#define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_SHIFT (5U)
#define GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_AUDIOMIX_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_MASK (0x40U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_SHIFT (6U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_2D_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_MASK (0x80U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_SHIFT (7U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_SHARE_LOGIC_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_MASK (0x100U)
#define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_SHIFT (8U)
#define GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPUMIX_SHARE_LOGIC_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_MASK (0x200U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_SHIFT (9U)
#define GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_GPU_3D_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_MASK (0x400U)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_SHIFT (10U)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MEDIMIX_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_MASK (0x800U)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_SHIFT (11U)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_G1_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_MASK (0x1000U)
#define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_SHIFT (12U)
#define GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ__SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_MASK (0x2000U)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_SHIFT (13U)
#define GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_VPU_VC8K_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_MASK (0x4000U)
#define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_SHIFT (14U)
#define GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMIMIX_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_MASK (0x8000U)
#define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_SHIFT (15U)
#define GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HDMI_PHY_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_MASK (0x10000U)
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_SHIFT (16U)
#define GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MIPI_PHY2_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_MASK (0x20000U)
#define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_SHIFT (17U)
#define GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_HSIOMIX_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_MASK (0x40000U)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_SHIFT (18U)
#define GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_MEDIA_ISP_DWP_SW_PDN_REQ_MASK)
#define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_MASK (0x80000U)
#define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_SHIFT (19U)
#define GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_SHIFT)) & GPC_PU_PGC_SW_PDN_REQ_DDRMIX_SW_PDN_REQ_MASK)
/*! @} */
/*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */
/*! @{ */
#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK)
#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK)
#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x4U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (2U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK)
#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK (0x8U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT (3U)
#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK)
#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK (0x10U)
#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT (4U)
#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT)) & GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK)
/*! @} */
/*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */
/*! @{ */
#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U)
#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U)
#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK)
/*! @} */
/* The count of GPC_A53_MIX_PGC_PUP_STATUS */
#define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U)
/*! @name M7_MIX_PGC_PUP_STATUS - M7 MIX PGC software up trigger status register */
/*! @{ */
#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK (0x1U)
#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT (0U)
#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT)) & GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK)
/*! @} */
/* The count of GPC_M7_MIX_PGC_PUP_STATUS */
#define GPC_M7_MIX_PGC_PUP_STATUS_COUNT (3U)
/*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */
/*! @{ */
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_MASK (0x1U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_SHIFT (0U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY1_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_MASK (0x2U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_SHIFT (1U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_PCIE_PHY_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_MASK (0x4U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_SHIFT (2U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_USB1_PHY_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_MASK (0x8U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_SHIFT (3U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_USB2_PHY_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_MASK (0x10U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_SHIFT (4U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MLMIX_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_MASK (0x20U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_SHIFT (5U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_AUDIOMIX_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_MASK (0x40U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_SHIFT (6U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_2D_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_MASK (0x80U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT (7U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_SHARE_LOGIC_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK (0x100U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT (8U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_MASK (0x200U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_SHIFT (9U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_GPU_3D_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_MASK (0x400U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_SHIFT (10U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIMIX_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_MASK (0x800U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_SHIFT (11U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G1_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_MASK (0x1000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_SHIFT (12U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_G2_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_MASK (0x2000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_SHIFT (13U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_VPU_VC8K_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_MASK (0x4000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_SHIFT (14U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMIMIX_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_MASK (0x8000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_SHIFT (15U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HDMI_PHY_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_MASK (0x10000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_SHIFT (16U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY2_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_MASK (0x20000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_SHIFT (17U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_HSIOMIX_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_MASK (0x40000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_SHIFT (18U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_MEDIA_ISP_DWP_PUP_STATUS_MASK)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_MASK (0x80000U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_SHIFT (19U)
#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_SHIFT)) & GPC_A53_PU_PGC_PUP_STATUS_A53_DDRMIX_PUP_STATUS_MASK)
/*! @} */
/* The count of GPC_A53_PU_PGC_PUP_STATUS */
#define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U)
/*! @name M7_PU_PGC_PUP_STATUS - M7 PU PGC software up trigger status register */
/*! @{ */
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_MASK (0x1U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_SHIFT (0U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY1_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_MASK (0x2U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_SHIFT (1U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_PCIE_PHY_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_MASK (0x4U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_SHIFT (2U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_USB1_PHY_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_MASK (0x8U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_SHIFT (3U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_USB2_PHY_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_MASK (0x10U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_SHIFT (4U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MLMIX_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_MASK (0x20U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_SHIFT (5U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_AUDIOMIX_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_MASK (0x40U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_SHIFT (6U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU2D_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_MASK (0x80U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT (7U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU_SHARE_LOGIC_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK (0x100U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT (8U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPUMIX_SHARE_LOGIC_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_MASK (0x200U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_SHIFT (9U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_GPU3D_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_MASK (0x400U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_SHIFT (10U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIMIX_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_MASK (0x800U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_SHIFT (11U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G1_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_MASK (0x1000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_SHIFT (12U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_G2_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_MASK (0x2000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_SHIFT (13U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_VPU_VC8K_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_MASK (0x4000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_SHIFT (14U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HDMIMIX_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_MASK (0x8000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_SHIFT (15U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HDMI_PHY_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_MASK (0x10000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_SHIFT (16U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY2_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_MASK (0x20000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_SHIFT (17U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_HSIOMIX_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_MASK (0x40000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_SHIFT (18U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_MEDIA_ISP_DWP_PUP_STATUS_MASK)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_MASK (0x80000U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_SHIFT (19U)
#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_SHIFT)) & GPC_M7_PU_PGC_PUP_STATUS_M7_DDRMIX_PUP_STATUS_MASK)
/*! @} */
/* The count of GPC_M7_PU_PGC_PUP_STATUS */
#define GPC_M7_PU_PGC_PUP_STATUS_COUNT (3U)
/*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */
/*! @{ */
#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK)
#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK)
#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x4U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (2U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK)
#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK (0x8U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT (3U)
#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK)
#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK (0x10U)
#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT (4U)
#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT)) & GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK)
/*! @} */
/*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */
/*! @{ */
#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U)
#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U)
#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK)
/*! @} */
/* The count of GPC_A53_MIX_PGC_PDN_STATUS */
#define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U)
/*! @name M7_MIX_PGC_PDN_STATUS - M7 MIX PGC software power down trigger status register */
/*! @{ */
#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK (0x1U)
#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT (0U)
#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT)) & GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK)
/*! @} */
/* The count of GPC_M7_MIX_PGC_PDN_STATUS */
#define GPC_M7_MIX_PGC_PDN_STATUS_COUNT (3U)
/*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */
/*! @{ */
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_MASK (0x1U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_SHIFT (0U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY1_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_MASK (0x2U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_SHIFT (1U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_PCIEPHY_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_MASK (0x4U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_SHIFT (2U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_USB1_PHY_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_MASK (0x8U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_SHIFT (3U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_USB2_PHY_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_MASK (0x10U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_SHIFT (4U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MLMIX_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_MASK (0x20U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_SHIFT (5U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_AUDIOMIX_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_MASK (0x40U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_SHIFT (6U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_2D_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_MASK (0x80U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT (7U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_SHARE_LOGIC_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK (0x100U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT (8U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_MASK (0x200U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_SHIFT (9U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_GPU_3D_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_MASK (0x400U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_SHIFT (10U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIMIX_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_MASK (0x800U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_SHIFT (11U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G1_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_MASK (0x1000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_SHIFT (12U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_G2_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_MASK (0x2000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_SHIFT (13U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_VPU_VC8K_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_MASK (0x4000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_SHIFT (14U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMIMIX_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_MASK (0x8000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_SHIFT (15U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HDMI_PHY_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_MASK (0x10000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_SHIFT (16U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY2_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_MASK (0x20000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_SHIFT (17U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_HSIOMIX_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_MASK (0x40000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_SHIFT (18U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_MEDIA_ISP_DWP_PDN_STATUS_MASK)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_MASK (0x80000U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_SHIFT (19U)
#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_SHIFT)) & GPC_A53_PU_PGC_PDN_STATUS_A53_DDRMIX_PDN_STATUS_MASK)
/*! @} */
/* The count of GPC_A53_PU_PGC_PDN_STATUS */
#define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U)
/*! @name M7_PU_PGC_PDN_STATUS - M7 PU PGC software down trigger status */
/*! @{ */
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_MASK (0x1U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_SHIFT (0U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY1_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_MASK (0x2U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_SHIFT (1U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_PCIE_PHY_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_MASK (0x4U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_SHIFT (2U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_USB1_PHY_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_MASK (0x8U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_SHIFT (3U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_USB2_PHY_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_MASK (0x10U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_SHIFT (4U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MLMIX_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_MASK (0x20U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_SHIFT (5U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_AUDIOMIX_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_MASK (0x40U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_SHIFT (6U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_2D_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_MASK (0x80U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT (7U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU_SHARE_LOGIC_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK (0x100U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT (8U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPUMIX_SHARE_LOGIC_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_MASK (0x200U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_SHIFT (9U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_GPU3D_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_MASK (0x400U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_SHIFT (10U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIMIX_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_MASK (0x800U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_SHIFT (11U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G1_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_MASK (0x1000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_SHIFT (12U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_G2_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_MASK (0x2000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_SHIFT (13U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_VPU_VC8K_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_MASK (0x4000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_SHIFT (14U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HDMIMIX_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_MASK (0x8000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_SHIFT (15U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HDMI_PHY_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_MASK (0x10000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_SHIFT (16U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY2_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_MASK (0x20000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_SHIFT (17U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_HSIOMIX_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_MASK (0x40000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_SHIFT (18U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_MEDIA_ISP_DWP_PDN_STATUS_MASK)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_MASK (0x80000U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_SHIFT (19U)
#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_SHIFT)) & GPC_M7_PU_PGC_PDN_STATUS_M7_DDRMIX_PDN_STATUS_MASK)
/*! @} */
/* The count of GPC_M7_PU_PGC_PDN_STATUS */
#define GPC_M7_PU_PGC_PDN_STATUS_COUNT (3U)
/*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */
/*! @{ */
#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U)
#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U)
#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK)
/*! @} */
/*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */
/*! @{ */
#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0xFFFFFU)
#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U)
#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK)
/*! @} */
/*! @name M7_MIX_PDN_FLG - M7 MIX PDN FLG */
/*! @{ */
#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK (0x1U)
#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT (0U)
#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT)) & GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK)
/*! @} */
/*! @name M7_PU_PDN_FLG - M7 PU PDN FLG */
/*! @{ */
#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK (0xFFFFFU)
#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT (0U)
#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG(x) (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT)) & GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK)
/*! @} */
/*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */
/*! @{ */
#define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U)
#define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U)
/*! LPM2
* 0b00..Remain in RUN mode
* 0b01..Transfer to WAIT mode
* 0b10..Transfer to STOP mode
* 0b11..Reserved
*/
#define GPC_LPCR_A53_BSC2_LPM2(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK)
#define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU)
#define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U)
/*! LPM3
* 0b00..Remain in RUN mode
* 0b01..Transfer to WAIT mode
* 0b10..Transfer to STOP mode
* 0b11..Reserved
*/
#define GPC_LPCR_A53_BSC2_LPM3(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK)
/*! @} */
/*! @name PU_PWRHSK - Power handshake register */
/*! @{ */
#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U)
#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U)
#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK)
#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U)
#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U)
#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_MASK (0x10U)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_SHIFT (4U)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK (0x20U)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT (5U)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK (0x40U)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT (6U)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_MASK (0x80U)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_SHIFT (7U)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_MASK (0x100U)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_SHIFT (8U)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_MASK (0x200U)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_SHIFT (9U)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_MASK (0x400U)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_SHIFT (10U)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_NOC_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_MASK (0x800U)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_SHIFT (11U)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_MASK (0x1000U)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_SHIFT (12U)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_MASK (0x2000U)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_SHIFT (13U)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_MASK (0x4000U)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_SHIFT (14U)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_MASK (0x8000U)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_SHIFT (15U)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_SHIFT)) & GPC_PU_PWRHSK_GPC_AUDIOMIX_NOC_PWRDNREQN_MASK)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_MASK (0x10000U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_SHIFT (16U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_LWPWACKN_MASK)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_MASK (0x20000U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_SHIFT (17U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_CLKACTIVE_MASK)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_MASK (0x40000U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_SHIFT (18U)
#define GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CTRL_REQACK_MASK)
#define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_MASK (0x80000U)
#define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_SHIFT (19U)
#define GPC_PU_PWRHSK_GPC_DDR1_CACTIVE(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_SHIFT)) & GPC_PU_PWRHSK_GPC_DDR1_CACTIVE_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_MASK (0x100000U)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_SHIFT (20U)
#define GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2AUDIOMIX_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_MASK (0x200000U)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_SHIFT (21U)
#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_ADBS_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_MASK (0x400000U)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_SHIFT (22U)
#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_ADBS_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_MASK (0x800000U)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_SHIFT (23U)
#define GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_MLMIX_ADBS_PWRDNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_MASK (0x1000000U)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_SHIFT (24U)
#define GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2MLMIX_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_MASK (0x2000000U)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_SHIFT (25U)
#define GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_GPUMIX_NOC_ADBS_PWRDNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_MASK (0x4000000U)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_SHIFT (26U)
#define GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_VPUMIX_NOX_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_MASK (0x8000000U)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_SHIFT (27U)
#define GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2DDRMIX_PWRDNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_MASK (0x10000000U)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_SHIFT (28U)
#define GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_NOC2HSIO_ADBS_PWDWNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_MASK (0x20000000U)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_SHIFT (29U)
#define GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_HDMIMIX_NOC_PWRDNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_MASK (0x40000000U)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_SHIFT (30U)
#define GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN_MASK)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_MASK (0x80000000U)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_SHIFT (31U)
#define GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_SHIFT)) & GPC_PU_PWRHSK_GPC_AUDIOMIX_PWRDNACKN_MASK)
/*! @} */
/*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 5 of A53 core2 */
/*! @{ */
#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U)
/*! IMR1_CORE2_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK)
#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U)
/*! IMR2_CORE2_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK)
#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U)
/*! IMR3_CORE2_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK)
#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U)
/*! IMR4_CORE2_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK)
#define GPC_IMR_CORE2_A53_IMR5_CORE2_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE2_A53_IMR5_CORE2_A53_SHIFT (0U)
/*! IMR5_CORE2_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE2_A53_IMR5_CORE2_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR5_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR5_CORE2_A53_MASK)
/*! @} */
/* The count of GPC_IMR_CORE2_A53 */
#define GPC_IMR_CORE2_A53_COUNT (5U)
/*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 5 of A53 core3 */
/*! @{ */
#define GPC_IMR_CORE3_A53_IM5_CORE3_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE3_A53_IM5_CORE3_A53_SHIFT (0U)
/*! IM5_CORE3_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE3_A53_IM5_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IM5_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IM5_CORE3_A53_MASK)
#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U)
/*! IMR1_CORE3_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK)
#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U)
/*! IMR2_CORE3_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK)
#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U)
/*! IMR3_CORE3_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK)
#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU)
#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U)
/*! IMR4_CORE3_A53
* 0b00000000000000000000000000000000..IRQ not masked
* 0b00000000000000000000000000000001..IRQ masked
*/
#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK)
/*! @} */
/* The count of GPC_IMR_CORE3_A53 */
#define GPC_IMR_CORE3_A53_COUNT (5U)
/*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */
/*! @{ */
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_MASK (0x1U)
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT (0U)
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_MASK (0x2U)
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT (1U)
#define GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MIPI_PHY1_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_MASK (0x4U)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT (2U)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_MASK (0x8U)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT (3U)
#define GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_PCIE_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_MASK (0x10U)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_SHIFT (4U)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_MASK (0x20U)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_SHIFT (5U)
#define GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB1_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_MASK (0x40U)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_SHIFT (6U)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_MASK (0x80U)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_SHIFT (7U)
#define GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_USB2_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_MASK (0x100U)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_SHIFT (8U)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MLMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_MASK (0x200U)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_SHIFT (9U)
#define GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MLMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_MASK (0x400U)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT (10U)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_MASK (0x800U)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT (11U)
#define GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_AUDIOMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_MASK (0x1000U)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_SHIFT (12U)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_MASK (0x2000U)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_SHIFT (13U)
#define GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_2D_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x4000U)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (14U)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x8000U)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (15U)
#define GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x10000U)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (16U)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x20000U)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (17U)
#define GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_MASK (0x40000U)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_SHIFT (18U)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU3D_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_MASK (0x80000U)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_SHIFT (19U)
#define GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_GPU3D_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_MASK (0x100000U)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_SHIFT (20U)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_MASK (0x200000U)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_SHIFT (21U)
#define GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_MEDIMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_MASK (0x400000U)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_SHIFT (22U)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_MASK (0x800000U)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_SHIFT (23U)
#define GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G1_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_MASK (0x1000000U)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_SHIFT (24U)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_MASK (0x2000000U)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_SHIFT (25U)
#define GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_G2_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_MASK (0x4000000U)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT (26U)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_MASK (0x8000000U)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT (27U)
#define GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_VPU_VC8K_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_MASK (0x10000000U)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_SHIFT (28U)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_MASK (0x20000000U)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_SHIFT (29U)
#define GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMIMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_MASK (0x40000000U)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT (30U)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_MASK (0x80000000U)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT (31U)
#define GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU_HDMI_PHY_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name ACK_SEL_A53_PU1 - PGC acknowledge signal selection of A53 platform for PUs */
/*! @{ */
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK (0x1U)
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT (0U)
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK (0x2U)
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT (1U)
#define GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_MASK (0x4U)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT (2U)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_MASK (0x8U)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT (3U)
#define GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_HSIOMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK (0x10U)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT (4U)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK (0x20U)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT (5U)
#define GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_MASK (0x40U)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_SHIFT (6U)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_MASK (0x80U)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_SHIFT (7U)
#define GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_A53_PU1_DDRMIX_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name ACK_SEL_M7_PU - PGC acknowledge signal selection of M7 platform for PUs */
/*! @{ */
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_MASK (0x1U)
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT (0U)
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_MASK (0x2U)
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT (1U)
#define GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MIPI_PHY1_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_MASK (0x4U)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT (2U)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_MASK (0x8U)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT (3U)
#define GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_PCIE_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_MASK (0x10U)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_SHIFT (4U)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_MASK (0x20U)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_SHIFT (5U)
#define GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB1_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_MASK (0x40U)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_SHIFT (6U)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_MASK (0x80U)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_SHIFT (7U)
#define GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_USB2_PHY_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_MASK (0x100U)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_SHIFT (8U)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MLMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_MASK (0x200U)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_SHIFT (9U)
#define GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MLMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_MASK (0x400U)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT (10U)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_MASK (0x800U)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT (11U)
#define GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_AUDIOMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_MASK (0x1000U)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_SHIFT (12U)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_MASK (0x2000U)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_SHIFT (13U)
#define GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_2D_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x4000U)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (14U)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x8000U)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (15U)
#define GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU_SHARE_LOGIC_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK (0x10000U)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT (16U)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK (0x20000U)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT (17U)
#define GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPUMIX_SHARE_LOGIC_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_MASK (0x40000U)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_SHIFT (18U)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU3D_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_MASK (0x80000U)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_SHIFT (19U)
#define GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_GPU3D_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_MASK (0x100000U)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_SHIFT (20U)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_MASK (0x200000U)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_SHIFT (21U)
#define GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_MEDIMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_MASK (0x400000U)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_SHIFT (22U)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_MASK (0x800000U)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_SHIFT (23U)
#define GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G1_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_MASK (0x1000000U)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_SHIFT (24U)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_MASK (0x2000000U)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_SHIFT (25U)
#define GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_G2_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_MASK (0x4000000U)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT (26U)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_MASK (0x8000000U)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT (27U)
#define GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_VPU_VC8K_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_MASK (0x10000000U)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_SHIFT (28U)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_MASK (0x20000000U)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_SHIFT (29U)
#define GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMIMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_MASK (0x40000000U)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT (30U)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_MASK (0x80000000U)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT (31U)
#define GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU_HDMI_PHY_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name ACK_SEL_M7_PU1 - PGC acknowledge signal selection of M7 platform for PUs */
/*! @{ */
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK (0x1U)
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT (0U)
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK (0x2U)
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT (1U)
#define GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MIPI_PHY2_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_MASK (0x4U)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT (2U)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_MASK (0x8U)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT (3U)
#define GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_HSIOMIX_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK (0x10U)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT (4U)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK (0x20U)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT (5U)
#define GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_MEDIA_ISP_DWP_PGC_PUP_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_MASK (0x40U)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_SHIFT (6U)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PDN_ACK_MASK)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_MASK (0x80U)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_SHIFT (7U)
#define GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK(x) (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_SHIFT)) & GPC_ACK_SEL_M7_PU1_DDRMIX_PGC_PUP_ACK_MASK)
/*! @} */
/*! @name PGC_CPU_A53_MAPPING - PGC CPU A53 mapping */
/*! @{ */
#define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK (0x1U)
#define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT (0U)
/*! MIX0_SUPERMIXM7_DOMAIN
* 0b0..Don't map M7 to A53 domain
* 0b1..Map M7 to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_MASK (0x2U)
#define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_SHIFT (1U)
/*! MIX1_NOC_DOMAIN
* 0b0..Don't map NOC to A53 domain
* 0b1..Map NOC to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIX1_NOC_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_MASK (0x4U)
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_SHIFT (2U)
/*! MIPI_PHY1_DOMAIN
* 0b0..Don't map MIPI_PHY1 to A53 domain
* 0b1..Map MIPI_PHY1 to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIPI_PHY1_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_MASK (0x8U)
#define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_SHIFT (3U)
/*! PCIE_PHY_DOMAIN
* 0b0..Don't map PCIE_PHY to A53 domain
* 0b1..Map PCIE_PHY to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_PCIE_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_MASK (0x10U)
#define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_SHIFT (4U)
/*! USB1_PHY_DOMAIN
* 0b0..Don't map USB1_PHY to A53 domain
* 0b1..Map USB1_PHY to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_USB1_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_MASK (0x20U)
#define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_SHIFT (5U)
/*! USB2_PHY_DOMAIN
* 0b0..Don't map USB2_PHY to A53 domain
* 0b1..Map USB2_PHY to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_USB2_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_MASK (0x40U)
#define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_SHIFT (6U)
/*! MLMIX_DOMAIN
* 0b0..Don't map MLMIX to A53 domain
* 0b1..Map MLMIX to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MLMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_MASK (0x80U)
#define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_SHIFT (7U)
/*! AUDIOMIX_DOMAIN
* 0b0..Don't map AUDIOMIX to A53 domain
* 0b1..Map AUDIOMIX to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_AUDIOMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_MASK (0x100U)
#define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_SHIFT (8U)
/*! GPU_2D_DOMAIN
* 0b0..Don't map GPU2D to A53 domain
* 0b1..Map GPU2D to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU_2D_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK (0x200U)
#define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT (9U)
/*! GPU_SHARE_LOGIC_DOMAIN
* 0b0..Don't map GPU Share Logic to A53 domain
* 0b1..Map GPU Share Logic to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK (0x400U)
#define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT (10U)
/*! VPUMIX_SHARE_LOGIC_DOMAIN
* 0b0..Don't map VPUMIX Share Logic to A53 domain
* 0b1..Map VPUMIX Share Logic to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_MASK (0x800U)
#define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_SHIFT (11U)
/*! GPU3D_DOMAIN
* 0b0..Don't map GPU2D to A53 domain
* 0b1..Map GPU2D to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_GPU3D_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_MASK (0x1000U)
#define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_SHIFT (12U)
/*! MEDIMIX_DOMAIN
* 0b0..Don't map MEDIMIX to A53 domain
* 0b1..Map MEDIMIX to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MEDIMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_MASK (0x2000U)
#define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_SHIFT (13U)
/*! VPU_G1_DOMAIN
* 0b0..Don't map VPU_G1 to A53 domain
* 0b1..Map VPU_G1 to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_G1_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_MASK (0x4000U)
#define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_SHIFT (14U)
/*! VPU_G2_DOMAIN
* 0b0..Don't map VPU_G1 to A53 domain
* 0b1..Map VPU_G1 to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_G2_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_MASK (0x8000U)
#define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_SHIFT (15U)
/*! VPU_VC8K_DOMAIN
* 0b0..Don't map VPU_VC8K to A53 domain
* 0b1..Map VPU_VC8K to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_VPU_VC8K_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_MASK (0x10000U)
#define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_SHIFT (16U)
/*! HDMIMIX_DOMAIN
* 0b0..Don't map HDMI to A53 domain
* 0b1..Map HDMI to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HDMIMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_MASK (0x20000U)
#define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_SHIFT (17U)
/*! HDMI_PHY_DOMAIN
* 0b0..Don't map HDMI PHY to A53 domain
* 0b1..Map HDMI PHY to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HDMI_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_MASK (0x40000U)
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_SHIFT (18U)
/*! MIPI_PHY2_DOMAIN
* 0b0..Don't map MIPI PHY2 to A53 domain
* 0b1..Map MIPI PHY2 to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MIPI_PHY2_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_MASK (0x80000U)
#define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_SHIFT (19U)
/*! HSIOMIX_DOMAIN
* 0b0..Don't map HSIOMIX to A53 domain
* 0b1..Map HSIOMIX to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_HSIOMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK (0x100000U)
#define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT (20U)
/*! MEDIA_ISP_DWP_DOMAIN
* 0b0..Don't map MEDIA_ISP_DWP_DOMAIN to A53 domain
* 0b1..Map DDR to MEDIA_ISP_DWP_DOMAIN domain
*/
#define GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK)
#define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_MASK (0x200000U)
#define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_SHIFT (21U)
/*! DDRMIX_DOMAIN
* 0b0..Don't map DDR to A53 domain
* 0b1..Map DDR to A53 domain
*/
#define GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_A53_MAPPING_DDRMIX_DOMAIN_MASK)
/*! @} */
/*! @name PGC_CPU_M7_MAPPING - PGC CPU M7 mapping */
/*! @{ */
#define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK (0x1U)
#define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT (0U)
/*! MIX0_SUPERMIXM7_DOMAIN
* 0b0..Don't map MIX0_SUPERMIXM7 to M7 domain
* 0b1..Map MIX0_SUPERMIXM7 to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_MASK (0x2U)
#define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_SHIFT (1U)
/*! MIX1_NOC_DOMAIN
* 0b0..Don't map MIX1_NOC to M7 domain
* 0b1..Map MIX1_NOC to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIX1_NOC_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_MASK (0x4U)
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_SHIFT (2U)
/*! MIPI_PHY1_DOMAIN
* 0b0..Don't map MIPI_PHY1 to M7 domain
* 0b1..Map MIPI_PHY1 to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIPI_PHY1_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_MASK (0x8U)
#define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_SHIFT (3U)
/*! PCIE_PHY_DOMAIN
* 0b0..Don't map PCIE_PHY to M7 domain
* 0b1..Map PCIE_PHY to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_PCIE_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_MASK (0x10U)
#define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_SHIFT (4U)
/*! USB1_PHY_DOMAIN
* 0b0..Don't map USB1_PHY to M7 domain
* 0b1..Map USB1_PHY to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_USB1_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_MASK (0x20U)
#define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_SHIFT (5U)
/*! USB2_PHY_DOMAIN
* 0b0..Don't map USB2_PHY to M7 domain
* 0b1..Map USB2_PHY to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_USB2_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_MASK (0x40U)
#define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_SHIFT (6U)
/*! MLMIX_DOMAIN
* 0b0..Don't map MLMIX to M7 domain
* 0b1..Map MLMIX to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MLMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_MASK (0x80U)
#define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_SHIFT (7U)
/*! AUDIOMIX_DOMAIN
* 0b0..Don't map AUDIOMIX to M7 domain
* 0b1..Map AUDIOMIX to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_AUDIOMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_MASK (0x100U)
#define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_SHIFT (8U)
/*! GPU_2D_DOMAIN
* 0b0..Don't map GPU2D to M7 domain
* 0b1..Map GPU2D to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU_2D_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK (0x200U)
#define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT (9U)
/*! GPU_SHARE_LOGIC_DOMAIN
* 0b0..Don't map GPU Share Logic to M7 domain
* 0b1..Map GPU Share Logic to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU_SHARE_LOGIC_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK (0x400U)
#define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT (10U)
/*! VPUMIX_SHARE_LOGIC_DOMAIN
* 0b0..Don't map VPUMIX Share Logic to M7 domain
* 0b1..Map VPUMIX Share Logic to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPUMIX_SHARE_LOGIC_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_MASK (0x800U)
#define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_SHIFT (11U)
/*! GPU3D_DOMAIN
* 0b0..Don't map GPU2D to M7 domain
* 0b1..Map GPU2D to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_GPU3D_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_MASK (0x1000U)
#define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_SHIFT (12U)
/*! MEDIMIX_DOMAIN
* 0b0..Don't map MEDIMIX to M7 domain
* 0b1..Map MEDIMIX to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MEDIMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_MASK (0x2000U)
#define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_SHIFT (13U)
/*! VPU_G1_DOMAIN
* 0b0..Don't map VPU_G1 to M7 domain
* 0b1..Map VPU_G1 to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_G1_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_MASK (0x4000U)
#define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_SHIFT (14U)
/*! VPU_G2_DOMAIN
* 0b0..Don't map VPU_G1 to M7 domain
* 0b1..Map VPU_G1 to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_G2_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_MASK (0x8000U)
#define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_SHIFT (15U)
/*! VPU_VC8K_DOMAIN
* 0b0..Don't map VPU_VC8K to M7 domain
* 0b1..Map VPU_VC8K to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_VPU_VC8K_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_MASK (0x10000U)
#define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_SHIFT (16U)
/*! HDMIMIX_DOMAIN
* 0b0..Don't map HDMI to M7 domain
* 0b1..Map HDMI to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HDMIMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_MASK (0x20000U)
#define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_SHIFT (17U)
/*! HDMI_PHY_DOMAIN
* 0b0..Don't map HDMI PHY to M7 domain
* 0b1..Map HDMI PHY to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HDMI_PHY_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_MASK (0x40000U)
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_SHIFT (18U)
/*! MIPI_PHY2_DOMAIN
* 0b0..Don't map MIPI PHY2 to M7 domain
* 0b1..Map MIPI PHY2 to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MIPI_PHY2_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_MASK (0x80000U)
#define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_SHIFT (19U)
/*! HSIOMIX_DOMAIN
* 0b0..Don't map HSIOMIX to M7 domain
* 0b1..Map HSIOMIX to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_HSIOMIX_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK (0x100000U)
#define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT (20U)
/*! MEDIA_ISP_DWP_DOMAIN
* 0b0..Don't map MEDIA_ISP_DWP_DOMAIN to M7 domain
* 0b1..Map MEDIA_ISP_DWP_DOMAIN to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_MEDIA_ISP_DWP_DOMAIN_MASK)
#define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_MASK (0x200000U)
#define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_SHIFT (21U)
/*! DDRMIX_DOMAIN
* 0b0..Don't map DDR to M7 domain
* 0b1..Map DDR to M7 domain
*/
#define GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_SHIFT)) & GPC_PGC_CPU_M7_MAPPING_DDRMIX_DOMAIN_MASK)
/*! @} */
/*! @name SLT_CFG - Slot configure register for CPUs */
/*! @{ */
#define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
#define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
#define GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
#define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
#define GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
#define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
#define GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
#define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
#define GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
#define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
#define GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
#define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
#define GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
#define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
#define GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
#define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
#define GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
#define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
#define GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_SCU_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
#define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
#define GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_SCU_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x1000U)
#define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (12U)
#define GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_NOC_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x2000U)
#define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (13U)
#define GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_NOC_PUP_SLOT_CONTROL_MASK)
/*! @} */
/* The count of GPC_SLT_CFG */
#define GPC_SLT_CFG_COUNT (27U)
/*! @name SLT_CFG_PU - Slot configure register for PGC PUs */
/*! @{ */
#define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_MASK (0x1U)
#define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_SHIFT (0U)
#define GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PHY1_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_MASK (0x2U)
#define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_SHIFT (1U)
#define GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MIPI_PHY1_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_MASK (0x4U)
#define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT (2U)
#define GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PHY_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_MASK (0x8U)
#define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT (3U)
#define GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_PCIE_PHY_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_MASK (0x10U)
#define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_SHIFT (4U)
#define GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB1_PHY_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_MASK (0x20U)
#define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_SHIFT (5U)
#define GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB1_PHY_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_MASK (0x40U)
#define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_SHIFT (6U)
#define GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB2_PHY_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_MASK (0x80U)
#define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_SHIFT (7U)
#define GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_USB2_PHY_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_MASK (0x100U)
#define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_SHIFT (8U)
#define GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MLMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_MASK (0x200U)
#define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_SHIFT (9U)
#define GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MLMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_MASK (0x400U)
#define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_SHIFT (10U)
#define GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_AUDIOMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_MASK (0x800U)
#define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_SHIFT (11U)
#define GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_AUDIOMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_MASK (0x1000U)
#define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_SHIFT (12U)
#define GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_2D_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_MASK (0x2000U)
#define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_SHIFT (13U)
#define GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_2D_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK (0x4000U)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT (14U)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK (0x8000U)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT (15U)
#define GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK (0x10000U)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT (16U)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK (0x20000U)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT (17U)
#define GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPUMIX_SHARE_LOGIC_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_MASK (0x40000U)
#define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_SHIFT (18U)
#define GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU3D_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_MASK (0x80000U)
#define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_SHIFT (19U)
#define GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_GPU3D_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_MASK (0x100000U)
#define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_SHIFT (20U)
#define GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MEDIMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_MASK (0x200000U)
#define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_SHIFT (21U)
#define GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_MEDIMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_MASK (0x400000U)
#define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_SHIFT (22U)
#define GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G1_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_MASK (0x800000U)
#define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_SHIFT (23U)
#define GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G1_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_MASK (0x1000000U)
#define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_SHIFT (24U)
#define GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G2_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_MASK (0x2000000U)
#define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_SHIFT (25U)
#define GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_G2_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_MASK (0x4000000U)
#define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_SHIFT (26U)
#define GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_VC8K_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_MASK (0x8000000U)
#define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_SHIFT (27U)
#define GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_VPU_VC8K_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_MASK (0x10000000U)
#define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_SHIFT (28U)
#define GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMIMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_MASK (0x20000000U)
#define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_SHIFT (29U)
#define GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMIMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_MASK (0x40000000U)
#define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_SHIFT (30U)
#define GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PHY_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_MASK (0x80000000U)
#define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_SHIFT (31U)
#define GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU_HDMI_PHY_PUP_SLOT_CONTROL_MASK)
/*! @} */
/* The count of GPC_SLT_CFG_PU */
#define GPC_SLT_CFG_PU_COUNT (27U)
/*! @name SLT_CFG_PU1 - Extended slot configure register for PGC PUs */
/*! @{ */
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_MASK (0x1U)
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_SHIFT (0U)
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MIPI_PHY2_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_MASK (0x2U)
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_SHIFT (1U)
#define GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MIPI_PHY2_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_MASK (0x4U)
#define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_SHIFT (2U)
#define GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_HSIOMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_MASK (0x8U)
#define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_SHIFT (3U)
#define GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_HSIOMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_MASK (0x10U)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_SHIFT (4U)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_MASK (0x20U)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_SHIFT (5U)
#define GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_MEDIA_ISP_DWP_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_MASK (0x40U)
#define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_SHIFT (6U)
#define GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_DDRMIX_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_MASK (0x80U)
#define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_SHIFT (7U)
#define GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_DDRMIX_PUP_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_MASK (0x100U)
#define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_SHIFT (8U)
#define GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_MASK)
#define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_MASK (0x200U)
#define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_SHIFT (9U)
#define GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_MASK)
/*! @} */
/* The count of GPC_SLT_CFG_PU1 */
#define GPC_SLT_CFG_PU1_COUNT (27U)
/*!
* @}
*/ /* end of group GPC_Register_Masks */
/* GPC - Peripheral instance base addresses */
/** Peripheral GPC base address */
#define GPC_BASE (0x303A0000u)
/** Peripheral GPC base pointer */
#define GPC ((GPC_Type *)GPC_BASE)
/** Array initializer of GPC peripheral base addresses */
#define GPC_BASE_ADDRS { GPC_BASE }
/** Array initializer of GPC peripheral base pointers */
#define GPC_BASE_PTRS { GPC }
/*!
* @}
*/ /* end of group GPC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC_PGC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer
* @{
*/
/** GPC_PGC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[2048];
struct { /* offset: 0x800, array step: 0x40 */
__IO uint32_t PGC_CTRL; /**< GPC PGC Control Register for PGC CPUs, array offset: 0x800, array step: 0x40 */
__IO uint32_t PGC_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0x804, array step: 0x40 */
__IO uint32_t PGC_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0x808, array step: 0x40 */
__IO uint32_t PGC_SR; /**< GPC PGC Status Register, array offset: 0x80C, array step: 0x40 */
uint8_t RESERVED_0[48];
} GPC_PGC_A53COREnCTRL[4];
__IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register for PGC CPUs, offset: 0x900 */
__IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x904 */
__IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x908 */
__IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x90C */
uint8_t RESERVED_1[304];
__IO uint32_t NOC_MIX_CTRL; /**< GPC PGC Control Register for PGC MIX., offset: 0xA40 */
__IO uint32_t NOC_MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xA44 */
__IO uint32_t NOC_MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xA48 */
__IO uint32_t NOC_MIX_SR; /**< GPC PGC Status Register, offset: 0xA4C */
uint8_t RESERVED_2[176];
struct { /* offset: 0xB00, array step: 0x40 */
__IO uint32_t PU_CTRL; /**< GPC PGC Control Register for PGC PUs, array offset: 0xB00, array step: 0x40 */
__IO uint32_t PU_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0xB04, array step: 0x40 */
__IO uint32_t PU_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0xB08, array step: 0x40 */
__IO uint32_t PU_SR; /**< GPC PGC Status Register, array offset: 0xB0C, array step: 0x40 */
uint8_t RESERVED_0[48];
} GPC_PGC_CTRL[20];
} GPC_PGC_Type;
/* ----------------------------------------------------------------------------
-- GPC_PGC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks
* @{
*/
/*! @name PGC_CTRL - GPC PGC Control Register for PGC CPUs */
/*! @{ */
#define GPC_PGC_PGC_CTRL_PCR_MASK (0x1U)
#define GPC_PGC_PGC_CTRL_PCR_SHIFT (0U)
/*! PCR
* 0b0..Do not switch off power even if pdn_req is asserted.
* 0b1..Switch off power when pdn_req is asserted.
*/
#define GPC_PGC_PGC_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_PCR_SHIFT)) & GPC_PGC_PGC_CTRL_PCR_MASK)
#define GPC_PGC_PGC_CTRL_L2RSTDIS_MASK (0x7EU)
#define GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT (1U)
#define GPC_PGC_PGC_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PGC_CTRL_L2RSTDIS_MASK)
#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT (8U)
#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK)
#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK)
#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
/*! @} */
/* The count of GPC_PGC_PGC_CTRL */
#define GPC_PGC_PGC_CTRL_COUNT (4U)
/*! @name PGC_PUPSCR - GPC PGC Up Sequence Control Register */
/*! @{ */
#define GPC_PGC_PGC_PUPSCR_SW_MASK (0x3FU)
#define GPC_PGC_PGC_PUPSCR_SW_SHIFT (0U)
#define GPC_PGC_PGC_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW_MASK)
#define GPC_PGC_PGC_PUPSCR_SW2ISO_MASK (0x7FFF80U)
#define GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT (7U)
#define GPC_PGC_PGC_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW2ISO_MASK)
/*! @} */
/* The count of GPC_PGC_PGC_PUPSCR */
#define GPC_PGC_PGC_PUPSCR_COUNT (4U)
/*! @name PGC_PDNSCR - GPC PGC Down Sequence Control Register */
/*! @{ */
#define GPC_PGC_PGC_PDNSCR_ISO_MASK (0x3FU)
#define GPC_PGC_PGC_PDNSCR_ISO_SHIFT (0U)
#define GPC_PGC_PGC_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO_MASK)
#define GPC_PGC_PGC_PDNSCR_ISO2SW_MASK (0x3F00U)
#define GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT (8U)
#define GPC_PGC_PGC_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO2SW_MASK)
/*! @} */
/* The count of GPC_PGC_PGC_PDNSCR */
#define GPC_PGC_PGC_PDNSCR_COUNT (4U)
/*! @name PGC_SR - GPC PGC Status Register */
/*! @{ */
#define GPC_PGC_PGC_SR_PSR_MASK (0x1U)
#define GPC_PGC_PGC_SR_PSR_SHIFT (0U)
/*! PSR
* 0b0..The target subsystem was not powered down for the previous power-down request.
* 0b1..The target subsystem was powered down for the previous power-down request.
*/
#define GPC_PGC_PGC_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PSR_SHIFT)) & GPC_PGC_PGC_SR_PSR_MASK)
#define GPC_PGC_PGC_SR_L2RETN_FLAG_MASK (0x2U)
#define GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT (1U)
/*! L2RETN_FLAG
* 0b0..A53 is not wakeup from L2 retention mode.
* 0b1..A53 is wakeup from L2 retention mode.
*/
#define GPC_PGC_PGC_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PGC_SR_L2RETN_FLAG_MASK)
#define GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK (0x4U)
#define GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT (2U)
/*! ALLOFF_FLAG
* 0b0..A53 is not wakeup from ALL_OFF mode.
* 0b1..A53 is wakeup from ALL_OFF mode.
*/
#define GPC_PGC_PGC_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK)
#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
/*! PUP_CLK_DIV_SEL
* 0b0000..1
* 0b0001..1/2 count_clk
* 0b0010..1/4 count_clk
* 0b0011..1/8 count_clk
* 0b0100..1/16 count_clk
* 0b0101..1/32 count_clk
* 0b0110..1/64 count_clk
* 0b0111..1/128 count_clk
* 0b1000..1/256 count_clk
* 0b1001..1/512 count_clk
* 0b1010..1/1024 count_clk
* 0b1011..1/2056 count_clk
* 0b1100..1/4096 count_clk
* 0b1101..1/8192 count_clk
* 0b1110..1/16384 count_clk
* 0b1111..1/32768 count_clk
*/
#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK)
#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK)
/*! @} */
/* The count of GPC_PGC_PGC_SR */
#define GPC_PGC_PGC_SR_COUNT (4U)
/*! @name A53SCU_CTRL - GPC PGC Control Register for PGC CPUs */
/*! @{ */
#define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U)
#define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U)
/*! PCR
* 0b0..Do not switch off power even if pdn_req is asserted.
* 0b1..Switch off power when pdn_req is asserted.
*/
#define GPC_PGC_A53SCU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK)
#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU)
#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U)
#define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK)
#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U)
#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK)
#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK)
#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
/*! @} */
/*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */
/*! @{ */
#define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU)
#define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U)
#define GPC_PGC_A53SCU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK)
#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U)
#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U)
#define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK)
/*! @} */
/*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */
/*! @{ */
#define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU)
#define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U)
#define GPC_PGC_A53SCU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK)
#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U)
#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U)
#define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK)
/*! @} */
/*! @name A53SCU_SR - GPC PGC Status Register */
/*! @{ */
#define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U)
#define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U)
/*! PSR
* 0b0..The target subsystem was not powered down for the previous power-down request.
* 0b1..The target subsystem was powered down for the previous power-down request.
*/
#define GPC_PGC_A53SCU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK)
#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U)
#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U)
/*! L2RETN_FLAG
* 0b0..A53 is not wakeup from L2 retention mode.
* 0b1..A53 is wakeup from L2 retention mode.
*/
#define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK)
#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U)
#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U)
/*! ALLOFF_FLAG
* 0b0..A53 is not wakeup from ALL_OFF mode.
* 0b1..A53 is wakeup from ALL_OFF mode.
*/
#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK)
#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
/*! PUP_CLK_DIV_SEL
* 0b0000..1
* 0b0001..1/2 count_clk
* 0b0010..1/4 count_clk
* 0b0011..1/8 count_clk
* 0b0100..1/16 count_clk
* 0b0101..1/32 count_clk
* 0b0110..1/64 count_clk
* 0b0111..1/128 count_clk
* 0b1000..1/256 count_clk
* 0b1001..1/512 count_clk
* 0b1010..1/1024 count_clk
* 0b1011..1/2056 count_clk
* 0b1100..1/4096 count_clk
* 0b1101..1/8192 count_clk
* 0b1110..1/16384 count_clk
* 0b1111..1/32768 count_clk
*/
#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK)
#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
/*! @} */
/*! @name NOC_MIX_CTRL - GPC PGC Control Register for PGC MIX. */
/*! @{ */
#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK (0x1U)
#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT (0U)
/*! MIX_PCR
* 0b0..Do not switch off power even if pdn_req is asserted.
* 0b1..Switch off power when pdn_req is asserted.
*/
#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK)
#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK (0x7EU)
#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT (1U)
#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK)
#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U)
#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK)
#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK)
#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
/*! @} */
/*! @name NOC_MIX_PUPSCR - GPC PGC Up Sequence Control Register */
/*! @{ */
#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U)
#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT (7U)
#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK)
/*! @} */
/*! @name NOC_MIX_PDNSCR - GPC PGC Down Sequence Control Register */
/*! @{ */
#define GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK (0x3FU)
#define GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT (0U)
#define GPC_PGC_NOC_MIX_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK)
#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U)
#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT (8U)
#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK)
/*! @} */
/*! @name NOC_MIX_SR - GPC PGC Status Register */
/*! @{ */
#define GPC_PGC_NOC_MIX_SR_PSR_MASK (0x1U)
#define GPC_PGC_NOC_MIX_SR_PSR_SHIFT (0U)
/*! PSR
* 0b0..The target subsystem was not powered down for the previous power-down request.
* 0b1..The target subsystem was powered down for the previous power-down request.
*/
#define GPC_PGC_NOC_MIX_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PSR_SHIFT)) & GPC_PGC_NOC_MIX_SR_PSR_MASK)
#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK (0x2U)
#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT (1U)
/*! L2RETN_FLAG
* 0b0..A53 is not wakeup from L2 retention mode.
* 0b1..A53 is wakeup from L2 retention mode.
*/
#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK)
#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK (0x4U)
#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT (2U)
/*! ALLOFF_FLAG
* 0b0..A53 is not wakeup from ALL_OFF mode.
* 0b1..A53 is wakeup from ALL_OFF mode.
*/
#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK)
#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
/*! PUP_CLK_DIV_SEL
* 0b0000..1
* 0b0001..1/2 count_clk
* 0b0010..1/4 count_clk
* 0b0011..1/8 count_clk
* 0b0100..1/16 count_clk
* 0b0101..1/32 count_clk
* 0b0110..1/64 count_clk
* 0b0111..1/128 count_clk
* 0b1000..1/256 count_clk
* 0b1001..1/512 count_clk
* 0b1010..1/1024 count_clk
* 0b1011..1/2056 count_clk
* 0b1100..1/4096 count_clk
* 0b1101..1/8192 count_clk
* 0b1110..1/16384 count_clk
* 0b1111..1/32768 count_clk
*/
#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK)
#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK)
/*! @} */
/*! @name PU_CTRL - GPC PGC Control Register for PGC PUs */
/*! @{ */
#define GPC_PGC_PU_CTRL_PCR_MASK (0x1U)
#define GPC_PGC_PU_CTRL_PCR_SHIFT (0U)
/*! PCR
* 0b0..Do not switch off power even if pdn_req is asserted.
* 0b1..Switch off power when pdn_req is asserted.
*/
#define GPC_PGC_PU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_PCR_SHIFT)) & GPC_PGC_PU_CTRL_PCR_MASK)
#define GPC_PGC_PU_CTRL_L2RSTDIS_MASK (0x7EU)
#define GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT (1U)
#define GPC_PGC_PU_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU_CTRL_L2RSTDIS_MASK)
#define GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
#define GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT (8U)
#define GPC_PGC_PU_CTRL_DFTRAM_TCD1(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK)
#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK)
#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
/*! @} */
/* The count of GPC_PGC_PU_CTRL */
#define GPC_PGC_PU_CTRL_COUNT (20U)
/*! @name PU_PUPSCR - GPC PGC Up Sequence Control Register */
/*! @{ */
#define GPC_PGC_PU_PUPSCR_SW_MASK (0x3FU)
#define GPC_PGC_PU_PUPSCR_SW_SHIFT (0U)
#define GPC_PGC_PU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW_SHIFT)) & GPC_PGC_PU_PUPSCR_SW_MASK)
#define GPC_PGC_PU_PUPSCR_SW2ISO_MASK (0x7FFF80U)
#define GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT (7U)
#define GPC_PGC_PU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU_PUPSCR_SW2ISO_MASK)
/*! @} */
/* The count of GPC_PGC_PU_PUPSCR */
#define GPC_PGC_PU_PUPSCR_COUNT (20U)
/*! @name PU_PDNSCR - GPC PGC Down Sequence Control Register */
/*! @{ */
#define GPC_PGC_PU_PDNSCR_ISO_MASK (0x3FU)
#define GPC_PGC_PU_PDNSCR_ISO_SHIFT (0U)
#define GPC_PGC_PU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO_MASK)
#define GPC_PGC_PU_PDNSCR_ISO2SW_MASK (0x3F00U)
#define GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT (8U)
#define GPC_PGC_PU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO2SW_MASK)
/*! @} */
/* The count of GPC_PGC_PU_PDNSCR */
#define GPC_PGC_PU_PDNSCR_COUNT (20U)
/*! @name PU_SR - GPC PGC Status Register */
/*! @{ */
#define GPC_PGC_PU_SR_PSR_MASK (0x1U)
#define GPC_PGC_PU_SR_PSR_SHIFT (0U)
/*! PSR
* 0b0..The target subsystem was not powered down for the previous power-down request.
* 0b1..The target subsystem was powered down for the previous power-down request.
*/
#define GPC_PGC_PU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PSR_SHIFT)) & GPC_PGC_PU_SR_PSR_MASK)
#define GPC_PGC_PU_SR_L2RETN_FLAG_MASK (0x2U)
#define GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT (1U)
/*! L2RETN_FLAG
* 0b0..A53 is not wakeup from L2 retention mode.
* 0b1..A53 is wakeup from L2 retention mode.
*/
#define GPC_PGC_PU_SR_L2RETN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU_SR_L2RETN_FLAG_MASK)
#define GPC_PGC_PU_SR_ALLOFF_FLAG_MASK (0x4U)
#define GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT (2U)
/*! ALLOFF_FLAG
* 0b0..A53 is not wakeup from ALL_OFF mode.
* 0b1..A53 is wakeup from ALL_OFF mode.
*/
#define GPC_PGC_PU_SR_ALLOFF_FLAG(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU_SR_ALLOFF_FLAG_MASK)
#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
/*! PUP_CLK_DIV_SEL
* 0b0000..1
* 0b0001..1/2 count_clk
* 0b0010..1/4 count_clk
* 0b0011..1/8 count_clk
* 0b0100..1/16 count_clk
* 0b0101..1/32 count_clk
* 0b0110..1/64 count_clk
* 0b0111..1/128 count_clk
* 0b1000..1/256 count_clk
* 0b1001..1/512 count_clk
* 0b1010..1/1024 count_clk
* 0b1011..1/2056 count_clk
* 0b1100..1/4096 count_clk
* 0b1101..1/8192 count_clk
* 0b1110..1/16384 count_clk
* 0b1111..1/32768 count_clk
*/
#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK)
#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
/*! @} */
/* The count of GPC_PGC_PU_SR */
#define GPC_PGC_PU_SR_COUNT (20U)
/*!
* @}
*/ /* end of group GPC_PGC_Register_Masks */
/* GPC_PGC - Peripheral instance base addresses */
/** Peripheral GPC_PGC base address */
#define GPC_PGC_BASE (0x303A0000u)
/** Peripheral GPC_PGC base pointer */
#define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE)
/** Array initializer of GPC_PGC peripheral base addresses */
#define GPC_PGC_BASE_ADDRS { GPC_PGC_BASE }
/** Array initializer of GPC_PGC peripheral base pointers */
#define GPC_PGC_BASE_PTRS { GPC_PGC }
/*!
* @}
*/ /* end of group GPC_PGC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
__IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
__I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
__IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
__IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
__IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
__IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name DR - GPIO data register */
/*! @{ */
#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
#define GPIO_DR_DR_SHIFT (0U)
#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
/*! @} */
/*! @name GDIR - GPIO direction register */
/*! @{ */
#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
#define GPIO_GDIR_GDIR_SHIFT (0U)
/*! GDIR
* 0b00000000000000000000000000000000..GPIO is configured as input.
* 0b00000000000000000000000000000001..GPIO is configured as output.
*/
#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
/*! @} */
/*! @name PSR - GPIO pad status register */
/*! @{ */
#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
#define GPIO_PSR_PSR_SHIFT (0U)
#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
/*! @} */
/*! @name ICR1 - GPIO interrupt configuration register1 */
/*! @{ */
#define GPIO_ICR1_ICR0_MASK (0x3U)
#define GPIO_ICR1_ICR0_SHIFT (0U)
/*! ICR0
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
#define GPIO_ICR1_ICR1_MASK (0xCU)
#define GPIO_ICR1_ICR1_SHIFT (2U)
/*! ICR1
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
#define GPIO_ICR1_ICR2_MASK (0x30U)
#define GPIO_ICR1_ICR2_SHIFT (4U)
/*! ICR2
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
#define GPIO_ICR1_ICR3_MASK (0xC0U)
#define GPIO_ICR1_ICR3_SHIFT (6U)
/*! ICR3
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
#define GPIO_ICR1_ICR4_MASK (0x300U)
#define GPIO_ICR1_ICR4_SHIFT (8U)
/*! ICR4
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
#define GPIO_ICR1_ICR5_MASK (0xC00U)
#define GPIO_ICR1_ICR5_SHIFT (10U)
/*! ICR5
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
#define GPIO_ICR1_ICR6_MASK (0x3000U)
#define GPIO_ICR1_ICR6_SHIFT (12U)
/*! ICR6
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
#define GPIO_ICR1_ICR7_MASK (0xC000U)
#define GPIO_ICR1_ICR7_SHIFT (14U)
/*! ICR7
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
#define GPIO_ICR1_ICR8_MASK (0x30000U)
#define GPIO_ICR1_ICR8_SHIFT (16U)
/*! ICR8
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
#define GPIO_ICR1_ICR9_MASK (0xC0000U)
#define GPIO_ICR1_ICR9_SHIFT (18U)
/*! ICR9
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
#define GPIO_ICR1_ICR10_MASK (0x300000U)
#define GPIO_ICR1_ICR10_SHIFT (20U)
/*! ICR10
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
#define GPIO_ICR1_ICR11_MASK (0xC00000U)
#define GPIO_ICR1_ICR11_SHIFT (22U)
/*! ICR11
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
#define GPIO_ICR1_ICR12_MASK (0x3000000U)
#define GPIO_ICR1_ICR12_SHIFT (24U)
/*! ICR12
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
#define GPIO_ICR1_ICR13_MASK (0xC000000U)
#define GPIO_ICR1_ICR13_SHIFT (26U)
/*! ICR13
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
#define GPIO_ICR1_ICR14_MASK (0x30000000U)
#define GPIO_ICR1_ICR14_SHIFT (28U)
/*! ICR14
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
#define GPIO_ICR1_ICR15_SHIFT (30U)
/*! ICR15
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
/*! @} */
/*! @name ICR2 - GPIO interrupt configuration register2 */
/*! @{ */
#define GPIO_ICR2_ICR16_MASK (0x3U)
#define GPIO_ICR2_ICR16_SHIFT (0U)
/*! ICR16
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
#define GPIO_ICR2_ICR17_MASK (0xCU)
#define GPIO_ICR2_ICR17_SHIFT (2U)
/*! ICR17
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
#define GPIO_ICR2_ICR18_MASK (0x30U)
#define GPIO_ICR2_ICR18_SHIFT (4U)
/*! ICR18
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
#define GPIO_ICR2_ICR19_MASK (0xC0U)
#define GPIO_ICR2_ICR19_SHIFT (6U)
/*! ICR19
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
#define GPIO_ICR2_ICR20_MASK (0x300U)
#define GPIO_ICR2_ICR20_SHIFT (8U)
/*! ICR20
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
#define GPIO_ICR2_ICR21_MASK (0xC00U)
#define GPIO_ICR2_ICR21_SHIFT (10U)
/*! ICR21
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
#define GPIO_ICR2_ICR22_MASK (0x3000U)
#define GPIO_ICR2_ICR22_SHIFT (12U)
/*! ICR22
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
#define GPIO_ICR2_ICR23_MASK (0xC000U)
#define GPIO_ICR2_ICR23_SHIFT (14U)
/*! ICR23
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
#define GPIO_ICR2_ICR24_MASK (0x30000U)
#define GPIO_ICR2_ICR24_SHIFT (16U)
/*! ICR24
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
#define GPIO_ICR2_ICR25_MASK (0xC0000U)
#define GPIO_ICR2_ICR25_SHIFT (18U)
/*! ICR25
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
#define GPIO_ICR2_ICR26_MASK (0x300000U)
#define GPIO_ICR2_ICR26_SHIFT (20U)
/*! ICR26
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
#define GPIO_ICR2_ICR27_MASK (0xC00000U)
#define GPIO_ICR2_ICR27_SHIFT (22U)
/*! ICR27
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
#define GPIO_ICR2_ICR28_MASK (0x3000000U)
#define GPIO_ICR2_ICR28_SHIFT (24U)
/*! ICR28
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
#define GPIO_ICR2_ICR29_MASK (0xC000000U)
#define GPIO_ICR2_ICR29_SHIFT (26U)
/*! ICR29
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
#define GPIO_ICR2_ICR30_MASK (0x30000000U)
#define GPIO_ICR2_ICR30_SHIFT (28U)
/*! ICR30
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
#define GPIO_ICR2_ICR31_SHIFT (30U)
/*! ICR31
* 0b00..Interrupt n is low-level sensitive.
* 0b01..Interrupt n is high-level sensitive.
* 0b10..Interrupt n is rising-edge sensitive.
* 0b11..Interrupt n is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
/*! @} */
/*! @name IMR - GPIO interrupt mask register */
/*! @{ */
#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
#define GPIO_IMR_IMR_SHIFT (0U)
/*! IMR
* 0b00000000000000000000000000000000..Interrupt n is disabled.
* 0b00000000000000000000000000000001..Interrupt n is enabled.
*/
#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
/*! @} */
/*! @name ISR - GPIO interrupt status register */
/*! @{ */
#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
#define GPIO_ISR_ISR_SHIFT (0U)
#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
/*! @} */
/*! @name EDGE_SEL - GPIO edge select register */
/*! @{ */
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIO1 base address */
#define GPIO1_BASE (0x30200000u)
/** Peripheral GPIO1 base pointer */
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
/** Peripheral GPIO2 base address */
#define GPIO2_BASE (0x30210000u)
/** Peripheral GPIO2 base pointer */
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
/** Peripheral GPIO3 base address */
#define GPIO3_BASE (0x30220000u)
/** Peripheral GPIO3 base pointer */
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
/** Peripheral GPIO4 base address */
#define GPIO4_BASE (0x30230000u)
/** Peripheral GPIO4 base pointer */
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
/** Peripheral GPIO5 base address */
#define GPIO5_BASE (0x30240000u)
/** Peripheral GPIO5 base pointer */
#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 }
/** Interrupt vectors for the GPIO peripheral type */
#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn }
#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPMI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
* @{
*/
/** GPMI - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */
__IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */
__IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */
__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */
__IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
__IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
__IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
__IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
__IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
uint8_t RESERVED_1[12];
__IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */
uint8_t RESERVED_2[12];
__IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
uint8_t RESERVED_3[12];
__IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */
__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */
__IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */
__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */
__IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */
uint8_t RESERVED_4[12];
__IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */
uint8_t RESERVED_5[12];
__IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */
uint8_t RESERVED_6[12];
__IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
uint8_t RESERVED_7[12];
__I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */
uint8_t RESERVED_8[12];
__I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
uint8_t RESERVED_9[12];
__I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */
uint8_t RESERVED_10[12];
__IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
uint8_t RESERVED_11[12];
__I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
uint8_t RESERVED_12[12];
__IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
uint8_t RESERVED_13[12];
__IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
uint8_t RESERVED_14[12];
__I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
uint8_t RESERVED_15[12];
__I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
} GPMI_Type;
/* ----------------------------------------------------------------------------
-- GPMI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPMI_Register_Masks GPMI Register Masks
* @{
*/
/*! @name CTRL0 - GPMI Control Register 0 Description */
/*! @{ */
#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU)
#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U)
#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U)
#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U)
/*! ADDRESS_INCREMENT
* 0b0..Address does not increment.
* 0b1..Increment address.
*/
#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U)
#define GPMI_CTRL0_ADDRESS_SHIFT (17U)
#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
#define GPMI_CTRL0_CS_MASK (0x700000U)
#define GPMI_CTRL0_CS_SHIFT (20U)
#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U)
#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U)
/*! WORD_LENGTH
* 0b0..Reserved.
* 0b1..8-bit Data Bus mode.
*/
#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U)
#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U)
/*! COMMAND_MODE
* 0b00..Write mode.
* 0b01..Read Mode.
* 0b10..Read and Compare Mode (setting sense flop).
* 0b11..Wait for Ready.
*/
#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
#define GPMI_CTRL0_UDMA_MASK (0x4000000U)
#define GPMI_CTRL0_UDMA_SHIFT (26U)
/*! UDMA
* 0b0..Use ATA-PIO mode on the external bus.
* 0b1..Use ATA-Ultra DMA mode on the external bus.
*/
#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U)
#define GPMI_CTRL0_LOCK_CS_SHIFT (27U)
#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U)
#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U)
#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK)
#define GPMI_CTRL0_RUN_MASK (0x20000000U)
#define GPMI_CTRL0_RUN_SHIFT (29U)
#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U)
#define GPMI_CTRL0_CLKGATE_SHIFT (30U)
#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
#define GPMI_CTRL0_SFTRST_MASK (0x80000000U)
#define GPMI_CTRL0_SFTRST_SHIFT (31U)
#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_SET - GPMI Control Register 0 Description */
/*! @{ */
#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU)
#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U)
#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK)
#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U)
#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U)
/*! ADDRESS_INCREMENT
* 0b0..Address does not increment.
* 0b1..Increment address.
*/
#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK)
#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U)
#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U)
#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK)
#define GPMI_CTRL0_SET_CS_MASK (0x700000U)
#define GPMI_CTRL0_SET_CS_SHIFT (20U)
#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK)
#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U)
#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U)
/*! WORD_LENGTH
* 0b0..Reserved.
* 0b1..8-bit Data Bus mode.
*/
#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK)
#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U)
#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U)
/*! COMMAND_MODE
* 0b00..Write mode.
* 0b01..Read Mode.
* 0b10..Read and Compare Mode (setting sense flop).
* 0b11..Wait for Ready.
*/
#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK)
#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U)
#define GPMI_CTRL0_SET_UDMA_SHIFT (26U)
/*! UDMA
* 0b0..Use ATA-PIO mode on the external bus.
* 0b1..Use ATA-Ultra DMA mode on the external bus.
*/
#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK)
#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U)
#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U)
#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK)
#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U)
#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U)
#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK)
#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U)
#define GPMI_CTRL0_SET_RUN_SHIFT (29U)
#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK)
#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U)
#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U)
#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK)
#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U)
#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U)
#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_CLR - GPMI Control Register 0 Description */
/*! @{ */
#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU)
#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U)
#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK)
#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U)
#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U)
/*! ADDRESS_INCREMENT
* 0b0..Address does not increment.
* 0b1..Increment address.
*/
#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK)
#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U)
#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U)
#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK)
#define GPMI_CTRL0_CLR_CS_MASK (0x700000U)
#define GPMI_CTRL0_CLR_CS_SHIFT (20U)
#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK)
#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U)
#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U)
/*! WORD_LENGTH
* 0b0..Reserved.
* 0b1..8-bit Data Bus mode.
*/
#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK)
#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U)
#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U)
/*! COMMAND_MODE
* 0b00..Write mode.
* 0b01..Read Mode.
* 0b10..Read and Compare Mode (setting sense flop).
* 0b11..Wait for Ready.
*/
#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U)
#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U)
/*! UDMA
* 0b0..Use ATA-PIO mode on the external bus.
* 0b1..Use ATA-Ultra DMA mode on the external bus.
*/
#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK)
#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U)
#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U)
#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK)
#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U)
#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U)
#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK)
#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U)
#define GPMI_CTRL0_CLR_RUN_SHIFT (29U)
#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK)
#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U)
#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK)
#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U)
#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U)
#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL0_TOG - GPMI Control Register 0 Description */
/*! @{ */
#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU)
#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U)
#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK)
#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U)
#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U)
/*! ADDRESS_INCREMENT
* 0b0..Address does not increment.
* 0b1..Increment address.
*/
#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK)
#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U)
#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U)
#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK)
#define GPMI_CTRL0_TOG_CS_MASK (0x700000U)
#define GPMI_CTRL0_TOG_CS_SHIFT (20U)
#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK)
#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U)
#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U)
/*! WORD_LENGTH
* 0b0..Reserved.
* 0b1..8-bit Data Bus mode.
*/
#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK)
#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U)
#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U)
/*! COMMAND_MODE
* 0b00..Write mode.
* 0b01..Read Mode.
* 0b10..Read and Compare Mode (setting sense flop).
* 0b11..Wait for Ready.
*/
#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U)
#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U)
/*! UDMA
* 0b0..Use ATA-PIO mode on the external bus.
* 0b1..Use ATA-Ultra DMA mode on the external bus.
*/
#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK)
#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U)
#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U)
#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK)
#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U)
#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U)
#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK)
#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U)
#define GPMI_CTRL0_TOG_RUN_SHIFT (29U)
#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK)
#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U)
#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK)
#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U)
#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U)
#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK)
/*! @} */
/*! @name COMPARE - GPMI Compare Register Description */
/*! @{ */
#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU)
#define GPMI_COMPARE_REFERENCE_SHIFT (0U)
#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U)
#define GPMI_COMPARE_MASK_SHIFT (16U)
#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
/*! @} */
/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
/*! @{ */
#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU)
#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U)
#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
#define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U)
#define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U)
/*! RANDOMIZER_TYPE
* 0b00..Type 0
* 0b01..Type 1
*/
#define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U)
#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U)
/*! RANDOMIZER_ENABLE
* 0b0..disable
* 0b1..enable
*/
#define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U)
#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U)
#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U)
#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U)
#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U)
#define GPMI_ECCCTRL_RSVD2_SHIFT (15U)
#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U)
#define GPMI_ECCCTRL_HANDLE_SHIFT (16U)
#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
/*! @} */
/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */
/*! @{ */
#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU)
#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U)
#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U)
#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U)
/*! RANDOMIZER_TYPE
* 0b00..Type 0
* 0b01..Type 1
*/
#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK)
#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U)
#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U)
/*! RANDOMIZER_ENABLE
* 0b0..disable
* 0b1..enable
*/
#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK)
#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U)
#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U)
#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK)
#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U)
#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U)
#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK)
#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U)
#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U)
#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK)
#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U)
#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U)
#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK)
/*! @} */
/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */
/*! @{ */
#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU)
#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U)
#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U)
#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U)
/*! RANDOMIZER_TYPE
* 0b00..Type 0
* 0b01..Type 1
*/
#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK)
#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U)
#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U)
/*! RANDOMIZER_ENABLE
* 0b0..disable
* 0b1..enable
*/
#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK)
#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U)
#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U)
#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK)
#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U)
#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U)
#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U)
#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U)
#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK)
#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U)
#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U)
#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK)
/*! @} */
/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */
/*! @{ */
#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU)
#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U)
#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U)
#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U)
/*! RANDOMIZER_TYPE
* 0b00..Type 0
* 0b01..Type 1
*/
#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK)
#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U)
#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U)
/*! RANDOMIZER_ENABLE
* 0b0..disable
* 0b1..enable
*/
#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK)
#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U)
#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U)
#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK)
#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U)
#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U)
#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U)
#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U)
#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK)
#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U)
#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U)
#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK)
/*! @} */
/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
/*! @{ */
#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU)
#define GPMI_ECCCOUNT_COUNT_SHIFT (0U)
#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U)
#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U)
#define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
/*! @} */
/*! @name PAYLOAD - GPMI Payload Address Register Description */
/*! @{ */
#define GPMI_PAYLOAD_RSVD0_MASK (0x3U)
#define GPMI_PAYLOAD_RSVD0_SHIFT (0U)
#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU)
#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U)
#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
/*! @} */
/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
/*! @{ */
#define GPMI_AUXILIARY_RSVD0_MASK (0x3U)
#define GPMI_AUXILIARY_RSVD0_SHIFT (0U)
#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU)
#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U)
#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
/*! @} */
/*! @name CTRL1 - GPMI Control Register 1 Description */
/*! @{ */
#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U)
#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U)
/*! GPMI_MODE
* 0b0..NAND mode.
* 0b1..ATA mode.
*/
#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U)
#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U)
#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U)
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U)
/*! ATA_IRQRDY_POLARITY
* 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
* 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
*/
#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
#define GPMI_CTRL1_DEV_RESET_MASK (0x8U)
#define GPMI_CTRL1_DEV_RESET_SHIFT (3U)
/*! DEV_RESET
* 0b0..NANDF_WP_B pin is held low (asserted).
* 0b1..NANDF_WP_B pin is held high (de-asserted).
*/
#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U)
#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
#define GPMI_CTRL1_BURST_EN_MASK (0x100U)
#define GPMI_CTRL1_BURST_EN_SHIFT (8U)
#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U)
#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U)
#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U)
#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U)
#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U)
#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U)
#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U)
#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U)
#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U)
#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U)
#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U)
#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U)
#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U)
#define GPMI_CTRL1_BCH_MODE_SHIFT (18U)
#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U)
#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U)
#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U)
#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U)
#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U)
/*! TEST_TRIGGER
* 0b0..Disable
* 0b1..Enable
*/
#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK)
#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U)
#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U)
#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U)
#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U)
#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U)
#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U)
#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U)
#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U)
#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U)
/*! GPMI_CLK_DIV2_EN
* 0b0..internal factor-2 clock divider is disabled
* 0b1..internal factor-2 clock divider is enabled.
*/
#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U)
#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U)
#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U)
#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U)
#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U)
#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U)
#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U)
#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U)
#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
/*! @} */
/*! @name CTRL1_SET - GPMI Control Register 1 Description */
/*! @{ */
#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U)
#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U)
/*! GPMI_MODE
* 0b0..NAND mode.
* 0b1..ATA mode.
*/
#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK)
#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U)
#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U)
#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK)
#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U)
#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U)
/*! ATA_IRQRDY_POLARITY
* 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
* 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
*/
#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK)
#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U)
#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U)
/*! DEV_RESET
* 0b0..NANDF_WP_B pin is held low (asserted).
* 0b1..NANDF_WP_B pin is held high (de-asserted).
*/
#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK)
#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U)
#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U)
#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK)
#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U)
#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U)
#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK)
#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U)
#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U)
#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK)
#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U)
#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U)
#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK)
#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U)
#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U)
#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK)
#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U)
#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U)
#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK)
#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U)
#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U)
#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK)
#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U)
#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U)
#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK)
#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U)
#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U)
#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U)
#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK)
#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U)
#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U)
/*! TEST_TRIGGER
* 0b0..Disable
* 0b1..Enable
*/
#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK)
#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U)
#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U)
#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U)
#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U)
#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK)
#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U)
#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U)
#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK)
#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U)
#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U)
#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK)
#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U)
/*! GPMI_CLK_DIV2_EN
* 0b0..internal factor-2 clock divider is disabled
* 0b1..internal factor-2 clock divider is enabled.
*/
#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK)
#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U)
#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U)
#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK)
#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U)
#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U)
#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK)
#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U)
#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U)
#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK)
#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U)
#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U)
#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK)
/*! @} */
/*! @name CTRL1_CLR - GPMI Control Register 1 Description */
/*! @{ */
#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U)
#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U)
/*! GPMI_MODE
* 0b0..NAND mode.
* 0b1..ATA mode.
*/
#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK)
#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U)
#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U)
#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK)
#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U)
#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U)
/*! ATA_IRQRDY_POLARITY
* 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
* 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
*/
#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK)
#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U)
#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U)
/*! DEV_RESET
* 0b0..NANDF_WP_B pin is held low (asserted).
* 0b1..NANDF_WP_B pin is held high (de-asserted).
*/
#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK)
#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U)
#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U)
#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK)
#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U)
#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U)
#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK)
#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U)
#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U)
#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK)
#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U)
#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U)
#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK)
#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U)
#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U)
#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK)
#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U)
#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U)
#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK)
#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U)
#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U)
#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK)
#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U)
#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U)
#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK)
#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U)
#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U)
#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U)
#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK)
#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U)
#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U)
/*! TEST_TRIGGER
* 0b0..Disable
* 0b1..Enable
*/
#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK)
#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U)
#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U)
#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U)
#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U)
#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK)
#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U)
#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U)
#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK)
#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U)
#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U)
#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK)
#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U)
/*! GPMI_CLK_DIV2_EN
* 0b0..internal factor-2 clock divider is disabled
* 0b1..internal factor-2 clock divider is enabled.
*/
#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK)
#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U)
#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U)
#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK)
#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U)
#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U)
#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK)
#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U)
#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U)
#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK)
#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U)
#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U)
#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK)
/*! @} */
/*! @name CTRL1_TOG - GPMI Control Register 1 Description */
/*! @{ */
#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U)
#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U)
/*! GPMI_MODE
* 0b0..NAND mode.
* 0b1..ATA mode.
*/
#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK)
#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U)
#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U)
#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK)
#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U)
#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U)
/*! ATA_IRQRDY_POLARITY
* 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
* 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
*/
#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK)
#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U)
#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U)
/*! DEV_RESET
* 0b0..NANDF_WP_B pin is held low (asserted).
* 0b1..NANDF_WP_B pin is held high (de-asserted).
*/
#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK)
#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U)
#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U)
#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK)
#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U)
#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U)
#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK)
#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U)
#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U)
#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK)
#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U)
#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U)
#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK)
#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U)
#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U)
#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK)
#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U)
#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U)
#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK)
#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U)
#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U)
#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK)
#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U)
#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U)
#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK)
#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U)
#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U)
#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U)
#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK)
#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U)
#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U)
/*! TEST_TRIGGER
* 0b0..Disable
* 0b1..Enable
*/
#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK)
#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U)
#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U)
#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U)
#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U)
#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK)
#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U)
#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U)
#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK)
#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U)
#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U)
#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK)
#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U)
/*! GPMI_CLK_DIV2_EN
* 0b0..internal factor-2 clock divider is disabled
* 0b1..internal factor-2 clock divider is enabled.
*/
#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK)
#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U)
#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U)
#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK)
#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U)
#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U)
#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK)
#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U)
#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U)
#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK)
#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U)
#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U)
#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK)
/*! @} */
/*! @name TIMING0 - GPMI Timing Register 0 Description */
/*! @{ */
#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU)
#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U)
#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U)
#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U)
#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U)
#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U)
#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U)
#define GPMI_TIMING0_RSVD1_SHIFT (24U)
#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
/*! @} */
/*! @name TIMING1 - GPMI Timing Register 1 Description */
/*! @{ */
#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU)
#define GPMI_TIMING1_RSVD1_SHIFT (0U)
#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U)
#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
/*! @} */
/*! @name TIMING2 - GPMI Timing Register 2 Description */
/*! @{ */
#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU)
#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U)
#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U)
#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U)
#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U)
#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U)
#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U)
#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U)
#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U)
#define GPMI_TIMING2_CE_DELAY_SHIFT (16U)
#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
#define GPMI_TIMING2_RSVD0_MASK (0xE00000U)
#define GPMI_TIMING2_RSVD0_SHIFT (21U)
#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U)
#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U)
/*! READ_LATENCY
* 0b000..READ LATENCY is 0
* 0b001..READ LATENCY is 1
* 0b010..READ LATENCY is 2
* 0b011..READ LATENCY is 3
* 0b100..READ LATENCY is 4
* 0b101..READ LATENCY is 5
*/
#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
#define GPMI_TIMING2_TCR_MASK (0x18000000U)
#define GPMI_TIMING2_TCR_SHIFT (27U)
#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U)
#define GPMI_TIMING2_TRPSTH_SHIFT (29U)
#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
/*! @} */
/*! @name DATA - GPMI DMA Data Transfer Register Description */
/*! @{ */
#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU)
#define GPMI_DATA_DATA_SHIFT (0U)
#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
/*! @} */
/*! @name STAT - GPMI Status Register Description */
/*! @{ */
#define GPMI_STAT_PRESENT_MASK (0x1U)
#define GPMI_STAT_PRESENT_SHIFT (0U)
/*! PRESENT
* 0b0..GPMI is not present in this product.
* 0b1..GPMI is present is in this product.
*/
#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
#define GPMI_STAT_FIFO_FULL_MASK (0x2U)
#define GPMI_STAT_FIFO_FULL_SHIFT (1U)
/*! FIFO_FULL
* 0b0..FIFO is not full.
* 0b1..FIFO is full.
*/
#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U)
#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U)
/*! FIFO_EMPTY
* 0b0..FIFO is not empty.
* 0b1..FIFO is empty.
*/
#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U)
#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U)
/*! INVALID_BUFFER_MASK
* 0b0..ECC Buffer Mask is not invalid.
* 0b1..ECC Buffer Mask is invalid.
*/
#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
#define GPMI_STAT_ATA_IRQ_MASK (0x10U)
#define GPMI_STAT_ATA_IRQ_SHIFT (4U)
#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
#define GPMI_STAT_RSVD1_MASK (0xE0U)
#define GPMI_STAT_RSVD1_SHIFT (5U)
#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
#define GPMI_STAT_DEV0_ERROR_MASK (0x100U)
#define GPMI_STAT_DEV0_ERROR_SHIFT (8U)
/*! DEV0_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
#define GPMI_STAT_DEV1_ERROR_MASK (0x200U)
#define GPMI_STAT_DEV1_ERROR_SHIFT (9U)
/*! DEV1_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
#define GPMI_STAT_DEV2_ERROR_MASK (0x400U)
#define GPMI_STAT_DEV2_ERROR_SHIFT (10U)
/*! DEV2_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
#define GPMI_STAT_DEV3_ERROR_MASK (0x800U)
#define GPMI_STAT_DEV3_ERROR_SHIFT (11U)
/*! DEV3_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U)
#define GPMI_STAT_DEV4_ERROR_SHIFT (12U)
/*! DEV4_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U)
#define GPMI_STAT_DEV5_ERROR_SHIFT (13U)
/*! DEV5_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U)
#define GPMI_STAT_DEV6_ERROR_SHIFT (14U)
/*! DEV6_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U)
#define GPMI_STAT_DEV7_ERROR_SHIFT (15U)
/*! DEV7_ERROR
* 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
* 0b1..An Error has occurred on ATA/NAND Device accessed by
*/
#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U)
#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U)
#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U)
#define GPMI_STAT_READY_BUSY_SHIFT (24U)
#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
/*! @} */
/*! @name DEBUG - GPMI Debug Information Register Description */
/*! @{ */
#define GPMI_DEBUG_CMD_END_MASK (0xFFU)
#define GPMI_DEBUG_CMD_END_SHIFT (0U)
#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U)
#define GPMI_DEBUG_DMAREQ_SHIFT (8U)
#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U)
#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U)
#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U)
#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U)
#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
/*! @} */
/*! @name VERSION - GPMI Version Register Description */
/*! @{ */
#define GPMI_VERSION_STEP_MASK (0xFFFFU)
#define GPMI_VERSION_STEP_SHIFT (0U)
#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
#define GPMI_VERSION_MINOR_MASK (0xFF0000U)
#define GPMI_VERSION_MINOR_SHIFT (16U)
#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
#define GPMI_VERSION_MAJOR_MASK (0xFF000000U)
#define GPMI_VERSION_MAJOR_SHIFT (24U)
#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
/*! @} */
/*! @name DEBUG2 - GPMI Debug2 Information Register Description */
/*! @{ */
#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU)
#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U)
#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U)
#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U)
#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U)
#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U)
#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U)
#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U)
#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U)
#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U)
#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U)
#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U)
#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U)
#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U)
#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U)
#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U)
#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U)
#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U)
#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U)
#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
#define GPMI_DEBUG2_BUSY_MASK (0x800000U)
#define GPMI_DEBUG2_BUSY_SHIFT (23U)
#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U)
#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U)
#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U)
#define GPMI_DEBUG2_RSVD1_SHIFT (28U)
#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
/*! @} */
/*! @name DEBUG3 - GPMI Debug3 Information Register Description */
/*! @{ */
#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU)
#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U)
#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U)
#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U)
#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
/*! @} */
/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
/*! @{ */
#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U)
#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U)
#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
/*! @{ */
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U)
#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
/*! @{ */
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U)
#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U)
#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U)
#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
/*! @} */
/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
/*! @{ */
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U)
#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U)
#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPMI_Register_Masks */
/* GPMI - Peripheral instance base addresses */
/** Peripheral GPMI base address */
#define GPMI_BASE (0x33002000u)
/** Peripheral GPMI base pointer */
#define GPMI ((GPMI_Type *)GPMI_BASE)
/** Array initializer of GPMI peripheral base addresses */
#define GPMI_BASE_ADDRS { GPMI_BASE }
/** Array initializer of GPMI peripheral base pointers */
#define GPMI_BASE_PTRS { GPMI }
/*!
* @}
*/ /* end of group GPMI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
* @{
*/
/** GPT - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
__IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
__IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
__IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
__IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
__I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
__I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
} GPT_Type;
/* ----------------------------------------------------------------------------
-- GPT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Register_Masks GPT Register Masks
* @{
*/
/*! @name CR - GPT Control Register */
/*! @{ */
#define GPT_CR_EN_MASK (0x1U)
#define GPT_CR_EN_SHIFT (0U)
/*! EN
* 0b0..GPT is disabled.
* 0b1..GPT is enabled.
*/
#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define GPT_CR_ENMOD_MASK (0x2U)
#define GPT_CR_ENMOD_SHIFT (1U)
/*! ENMOD
* 0b0..GPT counter will retain its value when it is disabled.
* 0b1..GPT counter value is reset to 0 when it is disabled.
*/
#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define GPT_CR_DBGEN_MASK (0x4U)
#define GPT_CR_DBGEN_SHIFT (2U)
/*! DBGEN
* 0b0..GPT is disabled in debug mode.
* 0b1..GPT is enabled in debug mode.
*/
#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define GPT_CR_WAITEN_MASK (0x8U)
#define GPT_CR_WAITEN_SHIFT (3U)
/*! WAITEN
* 0b0..GPT is disabled in wait mode.
* 0b1..GPT is enabled in wait mode.
*/
#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define GPT_CR_DOZEEN_MASK (0x10U)
#define GPT_CR_DOZEEN_SHIFT (4U)
/*! DOZEEN
* 0b0..GPT is disabled in doze mode.
* 0b1..GPT is enabled in doze mode.
*/
#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define GPT_CR_STOPEN_MASK (0x20U)
#define GPT_CR_STOPEN_SHIFT (5U)
/*! STOPEN
* 0b0..GPT is disabled in Stop mode.
* 0b1..GPT is enabled in Stop mode.
*/
#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define GPT_CR_CLKSRC_MASK (0x1C0U)
#define GPT_CR_CLKSRC_SHIFT (6U)
/*! CLKSRC
* 0b000..No clock
* 0b001..Peripheral Clock (ipg_clk)
* 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
* 0b011..External Clock
* 0b100..Low Frequency Reference Clock (ipg_clk_32k)
* 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
*/
#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define GPT_CR_FRR_MASK (0x200U)
#define GPT_CR_FRR_SHIFT (9U)
/*! FRR
* 0b0..Restart mode
* 0b1..Free-Run mode
*/
#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define GPT_CR_EN_24M_MASK (0x400U)
#define GPT_CR_EN_24M_SHIFT (10U)
/*! EN_24M
* 0b0..24M clock disabled
* 0b1..24M clock enabled
*/
#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define GPT_CR_SWR_MASK (0x8000U)
#define GPT_CR_SWR_SHIFT (15U)
/*! SWR
* 0b0..GPT is not in reset state
* 0b1..GPT is in reset state
*/
#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define GPT_CR_IM1_MASK (0x30000U)
#define GPT_CR_IM1_SHIFT (16U)
#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define GPT_CR_IM2_MASK (0xC0000U)
#define GPT_CR_IM2_SHIFT (18U)
/*! IM2
* 0b00..capture disabled
* 0b01..capture on rising edge only
* 0b10..capture on falling edge only
* 0b11..capture on both edges
*/
#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define GPT_CR_OM1_MASK (0x700000U)
#define GPT_CR_OM1_SHIFT (20U)
#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define GPT_CR_OM2_MASK (0x3800000U)
#define GPT_CR_OM2_SHIFT (23U)
#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define GPT_CR_OM3_MASK (0x1C000000U)
#define GPT_CR_OM3_SHIFT (26U)
/*! OM3
* 0b000..Output disconnected. No response on pin.
* 0b001..Toggle output pin
* 0b010..Clear output pin
* 0b011..Set output pin
* 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
*/
#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define GPT_CR_FO1_MASK (0x20000000U)
#define GPT_CR_FO1_SHIFT (29U)
#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define GPT_CR_FO2_MASK (0x40000000U)
#define GPT_CR_FO2_SHIFT (30U)
#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define GPT_CR_FO3_MASK (0x80000000U)
#define GPT_CR_FO3_SHIFT (31U)
/*! FO3
* 0b0..Writing a 0 has no effect.
* 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
*/
#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
/*! @} */
/*! @name PR - GPT Prescaler Register */
/*! @{ */
#define GPT_PR_PRESCALER_MASK (0xFFFU)
#define GPT_PR_PRESCALER_SHIFT (0U)
/*! PRESCALER
* 0b000000000000..Divide by 1
* 0b000000000001..Divide by 2
* 0b111111111111..Divide by 4096
*/
#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define GPT_PR_PRESCALER24M_MASK (0xF000U)
#define GPT_PR_PRESCALER24M_SHIFT (12U)
/*! PRESCALER24M
* 0b0000..Divide by 1
* 0b0001..Divide by 2
* 0b1111..Divide by 16
*/
#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
/*! @} */
/*! @name SR - GPT Status Register */
/*! @{ */
#define GPT_SR_OF1_MASK (0x1U)
#define GPT_SR_OF1_SHIFT (0U)
#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define GPT_SR_OF2_MASK (0x2U)
#define GPT_SR_OF2_SHIFT (1U)
#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define GPT_SR_OF3_MASK (0x4U)
#define GPT_SR_OF3_SHIFT (2U)
/*! OF3
* 0b0..Compare event has not occurred.
* 0b1..Compare event has occurred.
*/
#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define GPT_SR_IF1_MASK (0x8U)
#define GPT_SR_IF1_SHIFT (3U)
#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define GPT_SR_IF2_MASK (0x10U)
#define GPT_SR_IF2_SHIFT (4U)
/*! IF2
* 0b0..Capture event has not occurred.
* 0b1..Capture event has occurred.
*/
#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define GPT_SR_ROV_MASK (0x20U)
#define GPT_SR_ROV_SHIFT (5U)
/*! ROV
* 0b0..Rollover has not occurred.
* 0b1..Rollover has occurred.
*/
#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
/*! @} */
/*! @name IR - GPT Interrupt Register */
/*! @{ */
#define GPT_IR_OF1IE_MASK (0x1U)
#define GPT_IR_OF1IE_SHIFT (0U)
#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define GPT_IR_OF2IE_MASK (0x2U)
#define GPT_IR_OF2IE_SHIFT (1U)
#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define GPT_IR_OF3IE_MASK (0x4U)
#define GPT_IR_OF3IE_SHIFT (2U)
/*! OF3IE
* 0b0..Output Compare Channel n interrupt is disabled.
* 0b1..Output Compare Channel n interrupt is enabled.
*/
#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define GPT_IR_IF1IE_MASK (0x8U)
#define GPT_IR_IF1IE_SHIFT (3U)
#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define GPT_IR_IF2IE_MASK (0x10U)
#define GPT_IR_IF2IE_SHIFT (4U)
/*! IF2IE
* 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
* 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
*/
#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define GPT_IR_ROVIE_MASK (0x20U)
#define GPT_IR_ROVIE_SHIFT (5U)
/*! ROVIE
* 0b0..Rollover interrupt is disabled.
* 0b1..Rollover interrupt enabled.
*/
#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
/*! @} */
/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
/*! @{ */
#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
#define GPT_OCR_COMP_SHIFT (0U)
#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
/*! @} */
/* The count of GPT_OCR */
#define GPT_OCR_COUNT (3U)
/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
/*! @{ */
#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
#define GPT_ICR_CAPT_SHIFT (0U)
#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
/*! @} */
/* The count of GPT_ICR */
#define GPT_ICR_COUNT (2U)
/*! @name CNT - GPT Counter Register */
/*! @{ */
#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
#define GPT_CNT_COUNT_SHIFT (0U)
#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPT_Register_Masks */
/* GPT - Peripheral instance base addresses */
/** Peripheral GPT1 base address */
#define GPT1_BASE (0x302D0000u)
/** Peripheral GPT1 base pointer */
#define GPT1 ((GPT_Type *)GPT1_BASE)
/** Peripheral GPT2 base address */
#define GPT2_BASE (0x302E0000u)
/** Peripheral GPT2 base pointer */
#define GPT2 ((GPT_Type *)GPT2_BASE)
/** Peripheral GPT3 base address */
#define GPT3_BASE (0x302F0000u)
/** Peripheral GPT3 base pointer */
#define GPT3 ((GPT_Type *)GPT3_BASE)
/** Peripheral GPT4 base address */
#define GPT4_BASE (0x30700000u)
/** Peripheral GPT4 base pointer */
#define GPT4 ((GPT_Type *)GPT4_BASE)
/** Peripheral GPT5 base address */
#define GPT5_BASE (0x306F0000u)
/** Peripheral GPT5 base pointer */
#define GPT5 ((GPT_Type *)GPT5_BASE)
/** Peripheral GPT6 base address */
#define GPT6_BASE (0x306E0000u)
/** Peripheral GPT6 base pointer */
#define GPT6 ((GPT_Type *)GPT6_BASE)
/** Array initializer of GPT peripheral base addresses */
#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
/** Array initializer of GPT peripheral base pointers */
#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
/** Interrupt vectors for the GPT peripheral type */
#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
/*!
* @}
*/ /* end of group GPT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HDCP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDCP_Peripheral_Access_Layer HDCP Peripheral Access Layer
* @{
*/
/** HDCP - Register Layout Typedef */
typedef struct {
__IO uint8_t A_HDCPCFG0; /**< HDCP Enable and Functional Control Configuration Register 0, offset: 0x0 */
__IO uint8_t A_HDCPCFG1; /**< HDCP Software Reset and Functional Control Configuration Register 1, offset: 0x1 */
__I uint8_t A_HDCPOBS0; /**< HDCP Observation Register 0, offset: 0x2 */
__I uint8_t A_HDCPOBS1; /**< HDCP Observation Register 1, offset: 0x3 */
__I uint8_t A_HDCPOBS2; /**< HDCP Observation Register 2, offset: 0x4 */
__I uint8_t A_HDCPOBS3; /**< HDCP Observation Register 3, offset: 0x5 */
__O uint8_t A_APIINTCLR; /**< HDCP Interrupt Clear Register Write only register, active high and auto cleared, cleans the respective interruption in the interrupt status register., offset: 0x6 */
__I uint8_t A_APIINTSTAT; /**< HDCP Interrupt Status Register Read only register, reports the interruption which caused the activation of the interruption output pin., offset: 0x7 */
__IO uint8_t A_APIINTMSK; /**< HDCP Interrupt Mask Register The configuration of this register mask a given setup of interruption, disabling them from generating interruption pulses in the interruption output pin., offset: 0x8 */
__IO uint8_t A_VIDPOLCFG; /**< HDCP Video Polarity Configuration Register, offset: 0x9 */
__IO uint8_t A_OESSWCFG; /**< HDCP OESS WOO Configuration Register Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode., offset: 0xA */
uint8_t RESERVED_0[9];
__I uint8_t A_COREVERLSB; /**< HDCP Controller Version Register LSB Design ID number., offset: 0x14 */
__I uint8_t A_COREVERMSB; /**< HDCP Controller Version Register MSB Revision ID number., offset: 0x15 */
__IO uint8_t A_KSVMEMCTRL; /**< HDCP KSV Memory Control Register The KSVCTRLupd bit is a notification flag., offset: 0x16 */
uint8_t RESERVED_1[674];
__IO uint8_t HDCP_REVOC_SIZE_0; /**< HDCP Revocation KSV List Size Register 0, offset: 0x2B9 */
__IO uint8_t HDCP_REVOC_SIZE_1; /**< HDCP Revocation KSV List Size Register 1, offset: 0x2BA */
uint8_t RESERVED_2[9541];
__I uint8_t HDCPREG_BKSV0; /**< HDCP KSV Status Register 0, offset: 0x2800 */
__I uint8_t HDCPREG_BKSV1; /**< HDCP KSV Status Register 1, offset: 0x2801 */
__I uint8_t HDCPREG_BKSV2; /**< HDCP KSV Status Register 2, offset: 0x2802 */
__I uint8_t HDCPREG_BKSV3; /**< HDCP KSV Status Register 3, offset: 0x2803 */
__I uint8_t HDCPREG_BKSV4; /**< HDCP KSV Status Register 4, offset: 0x2804 */
__IO uint8_t HDCPREG_ANCONF; /**< HDCP AN Bypass Control Register, offset: 0x2805 */
__IO uint8_t HDCPREG_AN0; /**< HDCP Forced AN Register 0, offset: 0x2806 */
__IO uint8_t HDCPREG_AN1; /**< HDCP Forced AN Register 1, offset: 0x2807 */
__IO uint8_t HDCPREG_AN2; /**< HDCP forced AN Register 2, offset: 0x2808 */
__IO uint8_t HDCPREG_AN3; /**< HDCP Forced AN Register 3, offset: 0x2809 */
__IO uint8_t HDCPREG_AN4; /**< HDCP Forced AN Register 4, offset: 0x280A */
__IO uint8_t HDCPREG_AN5; /**< HDCP Forced AN Register 5, offset: 0x280B */
__IO uint8_t HDCPREG_AN6; /**< HDCP Forced AN Register 6, offset: 0x280C */
__IO uint8_t HDCPREG_AN7; /**< HDCP Forced AN Register 7, offset: 0x280D */
__IO uint8_t HDCPREG_RMLCTL; /**< HDCP Encrypted Device Private Keys Control Register This register is the control register for the software programmable encrypted DPK embedded storage feature., offset: 0x280E */
__I uint8_t HDCPREG_RMLSTS; /**< HDCP Encrypted DPK Status Register The required software configuration sequence is documented in the DesignWare Cores HDMI Transmitter User Guide in the "Programming" chapter, Section 3., offset: 0x280F */
__O uint8_t HDCPREG_SEED0; /**< HDCP Encrypted DPK Seed Register 0 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys., offset: 0x2810 */
__O uint8_t HDCPREG_SEED1; /**< HDCP Encrypted DPK Seed Register 1 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys., offset: 0x2811 */
__O uint8_t HDCPREG_DPK0; /**< HDCP Encrypted DPK Data Register 0 This register contains an HDCP DPK byte., offset: 0x2812 */
__O uint8_t HDCPREG_DPK1; /**< HDCP Encrypted DPK Data Register 1 This register contains an HDCP DPK byte., offset: 0x2813 */
__O uint8_t HDCPREG_DPK2; /**< HDCP Encrypted DPK Data Register 2 This register contains an HDCP DPK byte., offset: 0x2814 */
__O uint8_t HDCPREG_DPK3; /**< HDCP Encrypted DPK Data Register 3 This register contains an HDCP DPK byte., offset: 0x2815 */
__O uint8_t HDCPREG_DPK4; /**< HDCP Encrypted DPK Data Register 4 This register contains an HDCP DPK byte., offset: 0x2816 */
__O uint8_t HDCPREG_DPK5; /**< HDCP Encrypted DPK Data Register 5 This register contains an HDCP DPK byte., offset: 0x2817 */
__O uint8_t HDCPREG_DPK6; /**< HDCP Encrypted DPK Data Register 6 This register contains an HDCP DPK byte., offset: 0x2818 */
} HDCP_Type;
/* ----------------------------------------------------------------------------
-- HDCP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDCP_Register_Masks HDCP Register Masks
* @{
*/
/*! @name A_HDCPCFG0 - HDCP Enable and Functional Control Configuration Register 0 */
/*! @{ */
#define HDCP_A_HDCPCFG0_HDMIDVI_MASK (0x1U)
#define HDCP_A_HDCPCFG0_HDMIDVI_SHIFT (0U)
/*! hdmidvi - Configures the transmitter to operate with a HDMI capable device or with a DVI device.
*/
#define HDCP_A_HDCPCFG0_HDMIDVI(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_HDMIDVI_SHIFT)) & HDCP_A_HDCPCFG0_HDMIDVI_MASK)
#define HDCP_A_HDCPCFG0_EN11FEATURE_MASK (0x2U)
#define HDCP_A_HDCPCFG0_EN11FEATURE_SHIFT (1U)
/*! en11feature - Enable the use of features 1.
*/
#define HDCP_A_HDCPCFG0_EN11FEATURE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_EN11FEATURE_SHIFT)) & HDCP_A_HDCPCFG0_EN11FEATURE_MASK)
#define HDCP_A_HDCPCFG0_RXDETECT_MASK (0x4U)
#define HDCP_A_HDCPCFG0_RXDETECT_SHIFT (2U)
/*! rxdetect - Information that a sink device was detected connected to the HDMI port
*/
#define HDCP_A_HDCPCFG0_RXDETECT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_RXDETECT_SHIFT)) & HDCP_A_HDCPCFG0_RXDETECT_MASK)
#define HDCP_A_HDCPCFG0_AVMUTE_MASK (0x8U)
#define HDCP_A_HDCPCFG0_AVMUTE_SHIFT (3U)
/*! avmute - This register holds the current AVMUTE state of the DWC_hdmi_tx controller, as expected
* to be perceived by the connected HDMI/HDCP sink device.
*/
#define HDCP_A_HDCPCFG0_AVMUTE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_AVMUTE_SHIFT)) & HDCP_A_HDCPCFG0_AVMUTE_MASK)
#define HDCP_A_HDCPCFG0_SYNCRICHECK_MASK (0x10U)
#define HDCP_A_HDCPCFG0_SYNCRICHECK_SHIFT (4U)
/*! syncricheck - Configures if the Ri check should be done at every 2s even or synchronously to every 128 encrypted frame.
*/
#define HDCP_A_HDCPCFG0_SYNCRICHECK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_SYNCRICHECK_SHIFT)) & HDCP_A_HDCPCFG0_SYNCRICHECK_MASK)
#define HDCP_A_HDCPCFG0_BYPENCRYPTION_MASK (0x20U)
#define HDCP_A_HDCPCFG0_BYPENCRYPTION_SHIFT (5U)
/*! bypencryption - Bypasses all the data encryption stages
*/
#define HDCP_A_HDCPCFG0_BYPENCRYPTION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_BYPENCRYPTION_SHIFT)) & HDCP_A_HDCPCFG0_BYPENCRYPTION_MASK)
#define HDCP_A_HDCPCFG0_I2CFASTMODE_MASK (0x40U)
#define HDCP_A_HDCPCFG0_I2CFASTMODE_SHIFT (6U)
/*! I2Cfastmode - Enable the I2C fast mode option from the transmitter's side.
*/
#define HDCP_A_HDCPCFG0_I2CFASTMODE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_I2CFASTMODE_SHIFT)) & HDCP_A_HDCPCFG0_I2CFASTMODE_MASK)
#define HDCP_A_HDCPCFG0_ELVENA_MASK (0x80U)
#define HDCP_A_HDCPCFG0_ELVENA_SHIFT (7U)
/*! ELVena - Enables the Enhanced Link Verification from the transmitter's side
*/
#define HDCP_A_HDCPCFG0_ELVENA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG0_ELVENA_SHIFT)) & HDCP_A_HDCPCFG0_ELVENA_MASK)
/*! @} */
/*! @name A_HDCPCFG1 - HDCP Software Reset and Functional Control Configuration Register 1 */
/*! @{ */
#define HDCP_A_HDCPCFG1_SWRESET_MASK (0x1U)
#define HDCP_A_HDCPCFG1_SWRESET_SHIFT (0U)
/*! swreset - Software reset signal, active by writing a zero and auto cleared to 1 in the following cycle.
*/
#define HDCP_A_HDCPCFG1_SWRESET(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_SWRESET_SHIFT)) & HDCP_A_HDCPCFG1_SWRESET_MASK)
#define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK (0x2U)
#define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_SHIFT (1U)
/*! encryptiondisable - Disable encryption without losing authentication
*/
#define HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_SHIFT)) & HDCP_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK)
#define HDCP_A_HDCPCFG1_PH2UPSHFTENC_MASK (0x4U)
#define HDCP_A_HDCPCFG1_PH2UPSHFTENC_SHIFT (2U)
/*! ph2upshftenc - Enables the encoding of packet header in the tmdsch0 bit[0] with cipher[2]
* instead of the tmdsch0 bit[2] Note: This bit must always be set to 1 for all PHYs (PHY GEN1, PHY
* GEN2, and non-Synopsys PHY).
*/
#define HDCP_A_HDCPCFG1_PH2UPSHFTENC(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_PH2UPSHFTENC_SHIFT)) & HDCP_A_HDCPCFG1_PH2UPSHFTENC_MASK)
#define HDCP_A_HDCPCFG1_DISSHA1CHECK_MASK (0x8U)
#define HDCP_A_HDCPCFG1_DISSHA1CHECK_SHIFT (3U)
/*! dissha1check - Disables the request to the API processor to verify the SHA1 message digest of a received KSV List
*/
#define HDCP_A_HDCPCFG1_DISSHA1CHECK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_DISSHA1CHECK_SHIFT)) & HDCP_A_HDCPCFG1_DISSHA1CHECK_MASK)
#define HDCP_A_HDCPCFG1_HDCP_LOCK_MASK (0x10U)
#define HDCP_A_HDCPCFG1_HDCP_LOCK_SHIFT (4U)
/*! hdcp_lock - Lock the HDCP bypass and encryption disable mechanisms: - 1'b0: The default 1'b0
* value enables you to bypass HDCP through bit 5 (bypencryption) of the A_HDCPCFG0 register or to
* disable the encryption through bit 1 (encryptiondisable) of A_HDCPCFG1.
*/
#define HDCP_A_HDCPCFG1_HDCP_LOCK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_HDCP_LOCK_SHIFT)) & HDCP_A_HDCPCFG1_HDCP_LOCK_MASK)
#define HDCP_A_HDCPCFG1_SPARE_MASK (0xE0U)
#define HDCP_A_HDCPCFG1_SPARE_SHIFT (5U)
/*! spare - Reserved as "spare" register with no associated functionality.
*/
#define HDCP_A_HDCPCFG1_SPARE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPCFG1_SPARE_SHIFT)) & HDCP_A_HDCPCFG1_SPARE_MASK)
/*! @} */
/*! @name A_HDCPOBS0 - HDCP Observation Register 0 */
/*! @{ */
#define HDCP_A_HDCPOBS0_HDCPENGAGED_MASK (0x1U)
#define HDCP_A_HDCPOBS0_HDCPENGAGED_SHIFT (0U)
/*! hdcpengaged - Informs that the current HDMI link has the HDCP protocol fully engaged.
*/
#define HDCP_A_HDCPOBS0_HDCPENGAGED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_HDCPENGAGED_SHIFT)) & HDCP_A_HDCPOBS0_HDCPENGAGED_MASK)
#define HDCP_A_HDCPOBS0_SUBSTATEA_MASK (0xEU)
#define HDCP_A_HDCPOBS0_SUBSTATEA_SHIFT (1U)
/*! SUBSTATEA - Observability register informs in which sub-state the authentication is on.
*/
#define HDCP_A_HDCPOBS0_SUBSTATEA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_SUBSTATEA_SHIFT)) & HDCP_A_HDCPOBS0_SUBSTATEA_MASK)
#define HDCP_A_HDCPOBS0_STATEA_MASK (0xF0U)
#define HDCP_A_HDCPOBS0_STATEA_SHIFT (4U)
/*! STATEA - Observability register informs in which state the authentication machine is on.
*/
#define HDCP_A_HDCPOBS0_STATEA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS0_STATEA_SHIFT)) & HDCP_A_HDCPOBS0_STATEA_MASK)
/*! @} */
/*! @name A_HDCPOBS1 - HDCP Observation Register 1 */
/*! @{ */
#define HDCP_A_HDCPOBS1_STATER_MASK (0xFU)
#define HDCP_A_HDCPOBS1_STATER_SHIFT (0U)
/*! STATER - Observability register informs in which state the revocation machine is on.
*/
#define HDCP_A_HDCPOBS1_STATER(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS1_STATER_SHIFT)) & HDCP_A_HDCPOBS1_STATER_MASK)
#define HDCP_A_HDCPOBS1_STATEOEG_MASK (0x70U)
#define HDCP_A_HDCPOBS1_STATEOEG_SHIFT (4U)
/*! STATEOEG - Observability register informs in which state the OESS machine is on.
*/
#define HDCP_A_HDCPOBS1_STATEOEG(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS1_STATEOEG_SHIFT)) & HDCP_A_HDCPOBS1_STATEOEG_MASK)
/*! @} */
/*! @name A_HDCPOBS2 - HDCP Observation Register 2 */
/*! @{ */
#define HDCP_A_HDCPOBS2_STATEEEG_MASK (0x7U)
#define HDCP_A_HDCPOBS2_STATEEEG_SHIFT (0U)
/*! STATEEEG - Observability register informs in which state the EESS machine is on.
*/
#define HDCP_A_HDCPOBS2_STATEEEG(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS2_STATEEEG_SHIFT)) & HDCP_A_HDCPOBS2_STATEEEG_MASK)
#define HDCP_A_HDCPOBS2_STATEE_MASK (0x38U)
#define HDCP_A_HDCPOBS2_STATEE_SHIFT (3U)
/*! STATEE - Observability register informs in which state the cipher machine is on.
*/
#define HDCP_A_HDCPOBS2_STATEE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS2_STATEE_SHIFT)) & HDCP_A_HDCPOBS2_STATEE_MASK)
/*! @} */
/*! @name A_HDCPOBS3 - HDCP Observation Register 3 */
/*! @{ */
#define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_MASK (0x1U)
#define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_SHIFT (0U)
/*! FAST_REAUTHENTICATION - Register read from attached sink device: Bcap(0x40) bit 0.
*/
#define HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_SHIFT)) & HDCP_A_HDCPOBS3_FAST_REAUTHENTICATION_MASK)
#define HDCP_A_HDCPOBS3_FEATURES_1_1_MASK (0x2U)
#define HDCP_A_HDCPOBS3_FEATURES_1_1_SHIFT (1U)
/*! FEATURES_1_1 - Register read from attached sink device: Bcap(0x40) bit 1.
*/
#define HDCP_A_HDCPOBS3_FEATURES_1_1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FEATURES_1_1_SHIFT)) & HDCP_A_HDCPOBS3_FEATURES_1_1_MASK)
#define HDCP_A_HDCPOBS3_HDMI_MODE_MASK (0x4U)
#define HDCP_A_HDCPOBS3_HDMI_MODE_SHIFT (2U)
/*! HDMI_MODE - Register read from attached sink device: Bstatus(0x41) bit 12.
*/
#define HDCP_A_HDCPOBS3_HDMI_MODE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_MODE_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_MODE_MASK)
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_2_MASK (0x8U)
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_2_SHIFT (3U)
/*! HDMI_RESERVED_2 - Register read from attached sink device: Bstatus(0x41) bit 13.
*/
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_2(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_RESERVED_2_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_RESERVED_2_MASK)
#define HDCP_A_HDCPOBS3_FAST_I2C_MASK (0x10U)
#define HDCP_A_HDCPOBS3_FAST_I2C_SHIFT (4U)
/*! FAST_I2C - Register read from attached sink device: Bcap(0x40) bit 4.
*/
#define HDCP_A_HDCPOBS3_FAST_I2C(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_FAST_I2C_SHIFT)) & HDCP_A_HDCPOBS3_FAST_I2C_MASK)
#define HDCP_A_HDCPOBS3_KSV_FIFO_READY_MASK (0x20U)
#define HDCP_A_HDCPOBS3_KSV_FIFO_READY_SHIFT (5U)
/*! KSV_FIFO_READY - Register read from attached sink device: Bcap(0x40) bit 5.
*/
#define HDCP_A_HDCPOBS3_KSV_FIFO_READY(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_KSV_FIFO_READY_SHIFT)) & HDCP_A_HDCPOBS3_KSV_FIFO_READY_MASK)
#define HDCP_A_HDCPOBS3_REPEATER_MASK (0x40U)
#define HDCP_A_HDCPOBS3_REPEATER_SHIFT (6U)
/*! REPEATER - Register read from attached sink device: Bcap(0x40) bit 6.
*/
#define HDCP_A_HDCPOBS3_REPEATER(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_REPEATER_SHIFT)) & HDCP_A_HDCPOBS3_REPEATER_MASK)
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_1_MASK (0x80U)
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_1_SHIFT (7U)
/*! HDMI_RESERVED_1 - Register read from attached sink device: Bcap(0x40) bit 7.
*/
#define HDCP_A_HDCPOBS3_HDMI_RESERVED_1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_HDCPOBS3_HDMI_RESERVED_1_SHIFT)) & HDCP_A_HDCPOBS3_HDMI_RESERVED_1_MASK)
/*! @} */
/*! @name A_APIINTCLR - HDCP Interrupt Clear Register Write only register, active high and auto cleared, cleans the respective interruption in the interrupt status register. */
/*! @{ */
#define HDCP_A_APIINTCLR_KSVACCESSINT_MASK (0x1U)
#define HDCP_A_APIINTCLR_KSVACCESSINT_SHIFT (0U)
/*! KSVaccessint - Clears the interruption related to KSV memory access grant for Read-Write access.
*/
#define HDCP_A_APIINTCLR_KSVACCESSINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTCLR_KSVACCESSINT_MASK)
#define HDCP_A_APIINTCLR_KEEPOUTERRORINT_MASK (0x4U)
#define HDCP_A_APIINTCLR_KEEPOUTERRORINT_SHIFT (2U)
/*! Keepouterrorint - Clears the interruption related to keep out window error.
*/
#define HDCP_A_APIINTCLR_KEEPOUTERRORINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTCLR_KEEPOUTERRORINT_MASK)
#define HDCP_A_APIINTCLR_LOSTARBITRATION_MASK (0x8U)
#define HDCP_A_APIINTCLR_LOSTARBITRATION_SHIFT (3U)
/*! Lostarbitration - Clears the interruption related to I2C arbitration lost.
*/
#define HDCP_A_APIINTCLR_LOSTARBITRATION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTCLR_LOSTARBITRATION_MASK)
#define HDCP_A_APIINTCLR_I2CNACK_MASK (0x10U)
#define HDCP_A_APIINTCLR_I2CNACK_SHIFT (4U)
/*! I2Cnack - Clears the interruption related to I2C NACK reception.
*/
#define HDCP_A_APIINTCLR_I2CNACK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_I2CNACK_SHIFT)) & HDCP_A_APIINTCLR_I2CNACK_MASK)
#define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_MASK (0x20U)
#define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_SHIFT (5U)
/*! KSVsha1calcdoneint - Clears the interruption related to SHA1 verification has been done
*/
#define HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTCLR_KSVSHA1CALCDONEINT_MASK)
#define HDCP_A_APIINTCLR_HDCP_FAILED_MASK (0x40U)
#define HDCP_A_APIINTCLR_HDCP_FAILED_SHIFT (6U)
/*! HDCP_failed - Clears the interruption related to HDCP authentication process failed.
*/
#define HDCP_A_APIINTCLR_HDCP_FAILED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTCLR_HDCP_FAILED_MASK)
#define HDCP_A_APIINTCLR_HDCP_ENGAGED_MASK (0x80U)
#define HDCP_A_APIINTCLR_HDCP_ENGAGED_SHIFT (7U)
/*! HDCP_engaged - Clears the interruption related to HDCP authentication process successful.
*/
#define HDCP_A_APIINTCLR_HDCP_ENGAGED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTCLR_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTCLR_HDCP_ENGAGED_MASK)
/*! @} */
/*! @name A_APIINTSTAT - HDCP Interrupt Status Register Read only register, reports the interruption which caused the activation of the interruption output pin. */
/*! @{ */
#define HDCP_A_APIINTSTAT_KSVACCESSINT_MASK (0x1U)
#define HDCP_A_APIINTSTAT_KSVACCESSINT_SHIFT (0U)
/*! KSVaccessint - Notifies that the KSV memory access as been guaranteed for Read-Write access.
*/
#define HDCP_A_APIINTSTAT_KSVACCESSINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTSTAT_KSVACCESSINT_MASK)
#define HDCP_A_APIINTSTAT_KEEPOUTERRORINT_MASK (0x4U)
#define HDCP_A_APIINTSTAT_KEEPOUTERRORINT_SHIFT (2U)
/*! Keepouterrorint - Notifies that during the keep out window, the ctlout[3:0] bus was used besides control period.
*/
#define HDCP_A_APIINTSTAT_KEEPOUTERRORINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTSTAT_KEEPOUTERRORINT_MASK)
#define HDCP_A_APIINTSTAT_LOSTARBITRATION_MASK (0x8U)
#define HDCP_A_APIINTSTAT_LOSTARBITRATION_SHIFT (3U)
/*! Lostarbitration - Notifies that the I2C lost the arbitration to communicate.
*/
#define HDCP_A_APIINTSTAT_LOSTARBITRATION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTSTAT_LOSTARBITRATION_MASK)
#define HDCP_A_APIINTSTAT_I2CNACK_MASK (0x10U)
#define HDCP_A_APIINTSTAT_I2CNACK_SHIFT (4U)
/*! I2Cnack - Notifies that the I2C received a NACK from slave device.
*/
#define HDCP_A_APIINTSTAT_I2CNACK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_I2CNACK_SHIFT)) & HDCP_A_APIINTSTAT_I2CNACK_MASK)
#define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_MASK (0x20U)
#define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_SHIFT (5U)
/*! KSVsha1calcdoneint - Notifies that the HDCP13TCTRL block SHA1 verification has been done.
*/
#define HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTSTAT_KSVSHA1CALCDONEINT_MASK)
#define HDCP_A_APIINTSTAT_HDCP_FAILED_MASK (0x40U)
#define HDCP_A_APIINTSTAT_HDCP_FAILED_SHIFT (6U)
/*! HDCP_failed - Notifies that the HDCP authentication process was failed.
*/
#define HDCP_A_APIINTSTAT_HDCP_FAILED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTSTAT_HDCP_FAILED_MASK)
#define HDCP_A_APIINTSTAT_HDCP_ENGAGED_MASK (0x80U)
#define HDCP_A_APIINTSTAT_HDCP_ENGAGED_SHIFT (7U)
/*! HDCP_engaged - Notifies that the HDCP authentication process was successful
*/
#define HDCP_A_APIINTSTAT_HDCP_ENGAGED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTSTAT_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTSTAT_HDCP_ENGAGED_MASK)
/*! @} */
/*! @name A_APIINTMSK - HDCP Interrupt Mask Register The configuration of this register mask a given setup of interruption, disabling them from generating interruption pulses in the interruption output pin. */
/*! @{ */
#define HDCP_A_APIINTMSK_KSVACCESSINT_MASK (0x1U)
#define HDCP_A_APIINTMSK_KSVACCESSINT_SHIFT (0U)
/*! KSVaccessint - Masks the interruption related to KSV memory access grant for Read-Write access.
*/
#define HDCP_A_APIINTMSK_KSVACCESSINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KSVACCESSINT_SHIFT)) & HDCP_A_APIINTMSK_KSVACCESSINT_MASK)
#define HDCP_A_APIINTMSK_SPARE_MASK (0x2U)
#define HDCP_A_APIINTMSK_SPARE_SHIFT (1U)
/*! spare - Reserved as "spare" register with no associated functionality.
*/
#define HDCP_A_APIINTMSK_SPARE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_SPARE_SHIFT)) & HDCP_A_APIINTMSK_SPARE_MASK)
#define HDCP_A_APIINTMSK_KEEPOUTERRORINT_MASK (0x4U)
#define HDCP_A_APIINTMSK_KEEPOUTERRORINT_SHIFT (2U)
/*! Keepouterrorint - Masks the interruption related to keep out window error.
*/
#define HDCP_A_APIINTMSK_KEEPOUTERRORINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KEEPOUTERRORINT_SHIFT)) & HDCP_A_APIINTMSK_KEEPOUTERRORINT_MASK)
#define HDCP_A_APIINTMSK_LOSTARBITRATION_MASK (0x8U)
#define HDCP_A_APIINTMSK_LOSTARBITRATION_SHIFT (3U)
/*! Lostarbitration - Masks the interruption related to I2C arbitration lost.
*/
#define HDCP_A_APIINTMSK_LOSTARBITRATION(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_LOSTARBITRATION_SHIFT)) & HDCP_A_APIINTMSK_LOSTARBITRATION_MASK)
#define HDCP_A_APIINTMSK_I2CNACK_MASK (0x10U)
#define HDCP_A_APIINTMSK_I2CNACK_SHIFT (4U)
/*! I2Cnack - Masks the interruption related to I2C NACK reception.
*/
#define HDCP_A_APIINTMSK_I2CNACK(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_I2CNACK_SHIFT)) & HDCP_A_APIINTMSK_I2CNACK_MASK)
#define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_MASK (0x20U)
#define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_SHIFT (5U)
/*! KSVsha1calcdoneint - Masks the interruption related to SHA1 verification has been done
*/
#define HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_SHIFT)) & HDCP_A_APIINTMSK_KSVSHA1CALCDONEINT_MASK)
#define HDCP_A_APIINTMSK_HDCP_FAILED_MASK (0x40U)
#define HDCP_A_APIINTMSK_HDCP_FAILED_SHIFT (6U)
/*! HDCP_failed - Masks the interruption related to HDCP authentication process failed.
*/
#define HDCP_A_APIINTMSK_HDCP_FAILED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_HDCP_FAILED_SHIFT)) & HDCP_A_APIINTMSK_HDCP_FAILED_MASK)
#define HDCP_A_APIINTMSK_HDCP_ENGAGED_MASK (0x80U)
#define HDCP_A_APIINTMSK_HDCP_ENGAGED_SHIFT (7U)
/*! HDCP_engaged - Masks the interruption related to HDCP authentication process successful.
*/
#define HDCP_A_APIINTMSK_HDCP_ENGAGED(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_APIINTMSK_HDCP_ENGAGED_SHIFT)) & HDCP_A_APIINTMSK_HDCP_ENGAGED_MASK)
/*! @} */
/*! @name A_VIDPOLCFG - HDCP Video Polarity Configuration Register */
/*! @{ */
#define HDCP_A_VIDPOLCFG_SPARE_1_MASK (0x1U)
#define HDCP_A_VIDPOLCFG_SPARE_1_SHIFT (0U)
/*! spare_1 - Reserved as "spare" bit with no associated functionality.
*/
#define HDCP_A_VIDPOLCFG_SPARE_1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_SPARE_1_SHIFT)) & HDCP_A_VIDPOLCFG_SPARE_1_MASK)
#define HDCP_A_VIDPOLCFG_HSYNCPOL_MASK (0x2U)
#define HDCP_A_VIDPOLCFG_HSYNCPOL_SHIFT (1U)
/*! hsyncpol - Configuration of the video Horizontal synchronism polarity.
*/
#define HDCP_A_VIDPOLCFG_HSYNCPOL(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_HSYNCPOL_SHIFT)) & HDCP_A_VIDPOLCFG_HSYNCPOL_MASK)
#define HDCP_A_VIDPOLCFG_SPARE_2_MASK (0x4U)
#define HDCP_A_VIDPOLCFG_SPARE_2_SHIFT (2U)
/*! spare_2 - Reserved as "spare" bit with no associated functionality.
*/
#define HDCP_A_VIDPOLCFG_SPARE_2(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_SPARE_2_SHIFT)) & HDCP_A_VIDPOLCFG_SPARE_2_MASK)
#define HDCP_A_VIDPOLCFG_VSYNCPOL_MASK (0x8U)
#define HDCP_A_VIDPOLCFG_VSYNCPOL_SHIFT (3U)
/*! vsyncpol - Configuration of the video Vertical synchronism polarity
*/
#define HDCP_A_VIDPOLCFG_VSYNCPOL(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_VSYNCPOL_SHIFT)) & HDCP_A_VIDPOLCFG_VSYNCPOL_MASK)
#define HDCP_A_VIDPOLCFG_DATAENPOL_MASK (0x10U)
#define HDCP_A_VIDPOLCFG_DATAENPOL_SHIFT (4U)
/*! dataenpol - Configuration of the video data enable polarity
*/
#define HDCP_A_VIDPOLCFG_DATAENPOL(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_DATAENPOL_SHIFT)) & HDCP_A_VIDPOLCFG_DATAENPOL_MASK)
#define HDCP_A_VIDPOLCFG_UNENCRYPTCONF_MASK (0x60U)
#define HDCP_A_VIDPOLCFG_UNENCRYPTCONF_SHIFT (5U)
/*! unencryptconf - Configuration of the color sent when sending unencrypted video data For a
* complete table showing the color results (RGB), refer to the "Color Configuration When Sending
* Unencrypted Video Data" figure in Chapter 2, "Functional Description.
*/
#define HDCP_A_VIDPOLCFG_UNENCRYPTCONF(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_VIDPOLCFG_UNENCRYPTCONF_SHIFT)) & HDCP_A_VIDPOLCFG_UNENCRYPTCONF_MASK)
/*! @} */
/*! @name A_OESSWCFG - HDCP OESS WOO Configuration Register Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode. */
/*! @{ */
#define HDCP_A_OESSWCFG_A_OESSWCFG_MASK (0xFFU)
#define HDCP_A_OESSWCFG_A_OESSWCFG_SHIFT (0U)
/*! a_oesswcfg - HDCP OESS WOO Configuration Register
*/
#define HDCP_A_OESSWCFG_A_OESSWCFG(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_OESSWCFG_A_OESSWCFG_SHIFT)) & HDCP_A_OESSWCFG_A_OESSWCFG_MASK)
/*! @} */
/*! @name A_COREVERLSB - HDCP Controller Version Register LSB Design ID number. */
/*! @{ */
#define HDCP_A_COREVERLSB_A_COREVERLSB_MASK (0xFFU)
#define HDCP_A_COREVERLSB_A_COREVERLSB_SHIFT (0U)
/*! a_coreverlsb - HDCP Controller Version Register LSB
*/
#define HDCP_A_COREVERLSB_A_COREVERLSB(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_COREVERLSB_A_COREVERLSB_SHIFT)) & HDCP_A_COREVERLSB_A_COREVERLSB_MASK)
/*! @} */
/*! @name A_COREVERMSB - HDCP Controller Version Register MSB Revision ID number. */
/*! @{ */
#define HDCP_A_COREVERMSB_A_COREVERMSB_MASK (0xFFU)
#define HDCP_A_COREVERMSB_A_COREVERMSB_SHIFT (0U)
/*! a_corevermsb - HDCP Controller Version Register MSB
*/
#define HDCP_A_COREVERMSB_A_COREVERMSB(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_COREVERMSB_A_COREVERMSB_SHIFT)) & HDCP_A_COREVERMSB_A_COREVERMSB_MASK)
/*! @} */
/*! @name A_KSVMEMCTRL - HDCP KSV Memory Control Register The KSVCTRLupd bit is a notification flag. */
/*! @{ */
#define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_MASK (0x1U)
#define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_SHIFT (0U)
/*! KSVMEMrequest - Request access to the KSV memory; must be de-asserted after the access is completed by the system.
*/
#define HDCP_A_KSVMEMCTRL_KSVMEMREQUEST(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVMEMREQUEST_MASK)
#define HDCP_A_KSVMEMCTRL_KSVMEMACCESS_MASK (0x2U)
#define HDCP_A_KSVMEMCTRL_KSVMEMACCESS_SHIFT (1U)
/*! KSVMEMaccess - Notification that the KSV memory access as been guaranteed.
*/
#define HDCP_A_KSVMEMCTRL_KSVMEMACCESS(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVMEMACCESS_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVMEMACCESS_MASK)
#define HDCP_A_KSVMEMCTRL_KSVCTRLUPD_MASK (0x4U)
#define HDCP_A_KSVMEMCTRL_KSVCTRLUPD_SHIFT (2U)
/*! KSVCTRLupd - Set to inform that the KSV list in memory has been analyzed and the response to the
* Message Digest has been updated if on configurations on software SHA-1 calculation.
*/
#define HDCP_A_KSVMEMCTRL_KSVCTRLUPD(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVCTRLUPD_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVCTRLUPD_MASK)
#define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_MASK (0x10U)
#define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_SHIFT (4U)
/*! KSVsha1status - Notification whether the KSV list message digest is correct from the controller:
* 1'b1 if digest message verification failed 1'b0 if digest message verification succeeded
*/
#define HDCP_A_KSVMEMCTRL_KSVSHA1STATUS(x) (((uint8_t)(((uint8_t)(x)) << HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_SHIFT)) & HDCP_A_KSVMEMCTRL_KSVSHA1STATUS_MASK)
/*! @} */
/*! @name HDCP_REVOC_SIZE_0 - HDCP Revocation KSV List Size Register 0 */
/*! @{ */
#define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_MASK (0xFFU)
#define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_SHIFT (0U)
/*! hdcp_revoc_size_0 - Register containing the LSB of KSV list size (ksv_list_size[7:0]).
*/
#define HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_SHIFT)) & HDCP_HDCP_REVOC_SIZE_0_HDCP_REVOC_SIZE_0_MASK)
/*! @} */
/*! @name HDCP_REVOC_SIZE_1 - HDCP Revocation KSV List Size Register 1 */
/*! @{ */
#define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_MASK (0xFFU)
#define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_SHIFT (0U)
/*! hdcp_revoc_size_1 - Register containing the MSB of KSV list size (ksv_list_size[15:8]).
*/
#define HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_SHIFT)) & HDCP_HDCP_REVOC_SIZE_1_HDCP_REVOC_SIZE_1_MASK)
/*! @} */
/*! @name HDCPREG_BKSV0 - HDCP KSV Status Register 0 */
/*! @{ */
#define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_MASK (0xFFU)
#define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_SHIFT (0U)
/*! hdcpreg_bksv0 - Contains the value of BKSV[7:0].
*/
#define HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_SHIFT)) & HDCP_HDCPREG_BKSV0_HDCPREG_BKSV0_MASK)
/*! @} */
/*! @name HDCPREG_BKSV1 - HDCP KSV Status Register 1 */
/*! @{ */
#define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_MASK (0xFFU)
#define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_SHIFT (0U)
/*! hdcpreg_bksv1 - Contains the value of BKSV[15:8].
*/
#define HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_SHIFT)) & HDCP_HDCPREG_BKSV1_HDCPREG_BKSV1_MASK)
/*! @} */
/*! @name HDCPREG_BKSV2 - HDCP KSV Status Register 2 */
/*! @{ */
#define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_MASK (0xFFU)
#define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_SHIFT (0U)
/*! hdcpreg_bksv2 - Contains the value of BKSV[23:16].
*/
#define HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_SHIFT)) & HDCP_HDCPREG_BKSV2_HDCPREG_BKSV2_MASK)
/*! @} */
/*! @name HDCPREG_BKSV3 - HDCP KSV Status Register 3 */
/*! @{ */
#define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_MASK (0xFFU)
#define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_SHIFT (0U)
/*! hdcpreg_bksv3 - Contains the value of BKSV[31:24].
*/
#define HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_SHIFT)) & HDCP_HDCPREG_BKSV3_HDCPREG_BKSV3_MASK)
/*! @} */
/*! @name HDCPREG_BKSV4 - HDCP KSV Status Register 4 */
/*! @{ */
#define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_MASK (0xFFU)
#define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_SHIFT (0U)
/*! hdcpreg_bksv4 - Contains the value of BKSV[39:32].
*/
#define HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_SHIFT)) & HDCP_HDCPREG_BKSV4_HDCPREG_BKSV4_MASK)
/*! @} */
/*! @name HDCPREG_ANCONF - HDCP AN Bypass Control Register */
/*! @{ */
#define HDCP_HDCPREG_ANCONF_OANBYPASS_MASK (0x1U)
#define HDCP_HDCPREG_ANCONF_OANBYPASS_SHIFT (0U)
/*! oanbypass - - When oanbypass=1, the value of AN used in the HDCP engine comes from the hdcpreg_an0 to hdcpreg_an7 registers.
*/
#define HDCP_HDCPREG_ANCONF_OANBYPASS(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_ANCONF_OANBYPASS_SHIFT)) & HDCP_HDCPREG_ANCONF_OANBYPASS_MASK)
/*! @} */
/*! @name HDCPREG_AN0 - HDCP Forced AN Register 0 */
/*! @{ */
#define HDCP_HDCPREG_AN0_HDCPREG_AN0_MASK (0xFFU)
#define HDCP_HDCPREG_AN0_HDCPREG_AN0_SHIFT (0U)
/*! hdcpreg_an0 - Contains the value of AN[7:0]
*/
#define HDCP_HDCPREG_AN0_HDCPREG_AN0(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN0_HDCPREG_AN0_SHIFT)) & HDCP_HDCPREG_AN0_HDCPREG_AN0_MASK)
/*! @} */
/*! @name HDCPREG_AN1 - HDCP Forced AN Register 1 */
/*! @{ */
#define HDCP_HDCPREG_AN1_HDCPREG_AN1_MASK (0xFFU)
#define HDCP_HDCPREG_AN1_HDCPREG_AN1_SHIFT (0U)
/*! hdcpreg_an1 - Contains the value of AN[15:8]
*/
#define HDCP_HDCPREG_AN1_HDCPREG_AN1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN1_HDCPREG_AN1_SHIFT)) & HDCP_HDCPREG_AN1_HDCPREG_AN1_MASK)
/*! @} */
/*! @name HDCPREG_AN2 - HDCP forced AN Register 2 */
/*! @{ */
#define HDCP_HDCPREG_AN2_HDCPREG_AN2_MASK (0xFFU)
#define HDCP_HDCPREG_AN2_HDCPREG_AN2_SHIFT (0U)
/*! hdcpreg_an2 - Contains the value of AN[23:16]
*/
#define HDCP_HDCPREG_AN2_HDCPREG_AN2(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN2_HDCPREG_AN2_SHIFT)) & HDCP_HDCPREG_AN2_HDCPREG_AN2_MASK)
/*! @} */
/*! @name HDCPREG_AN3 - HDCP Forced AN Register 3 */
/*! @{ */
#define HDCP_HDCPREG_AN3_HDCPREG_AN3_MASK (0xFFU)
#define HDCP_HDCPREG_AN3_HDCPREG_AN3_SHIFT (0U)
/*! hdcpreg_an3 - Contains the value of AN[31:24]
*/
#define HDCP_HDCPREG_AN3_HDCPREG_AN3(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN3_HDCPREG_AN3_SHIFT)) & HDCP_HDCPREG_AN3_HDCPREG_AN3_MASK)
/*! @} */
/*! @name HDCPREG_AN4 - HDCP Forced AN Register 4 */
/*! @{ */
#define HDCP_HDCPREG_AN4_HDCPREG_AN4_MASK (0xFFU)
#define HDCP_HDCPREG_AN4_HDCPREG_AN4_SHIFT (0U)
/*! hdcpreg_an4 - Contains the value of AN[39:32]
*/
#define HDCP_HDCPREG_AN4_HDCPREG_AN4(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN4_HDCPREG_AN4_SHIFT)) & HDCP_HDCPREG_AN4_HDCPREG_AN4_MASK)
/*! @} */
/*! @name HDCPREG_AN5 - HDCP Forced AN Register 5 */
/*! @{ */
#define HDCP_HDCPREG_AN5_HDCPREG_AN5_MASK (0xFFU)
#define HDCP_HDCPREG_AN5_HDCPREG_AN5_SHIFT (0U)
/*! hdcpreg_an5 - Contains the value of AN[47:40]
*/
#define HDCP_HDCPREG_AN5_HDCPREG_AN5(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN5_HDCPREG_AN5_SHIFT)) & HDCP_HDCPREG_AN5_HDCPREG_AN5_MASK)
/*! @} */
/*! @name HDCPREG_AN6 - HDCP Forced AN Register 6 */
/*! @{ */
#define HDCP_HDCPREG_AN6_HDCPREG_AN6_MASK (0xFFU)
#define HDCP_HDCPREG_AN6_HDCPREG_AN6_SHIFT (0U)
/*! hdcpreg_an6 - Contains the value of AN[55:48]
*/
#define HDCP_HDCPREG_AN6_HDCPREG_AN6(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN6_HDCPREG_AN6_SHIFT)) & HDCP_HDCPREG_AN6_HDCPREG_AN6_MASK)
/*! @} */
/*! @name HDCPREG_AN7 - HDCP Forced AN Register 7 */
/*! @{ */
#define HDCP_HDCPREG_AN7_HDCPREG_AN7_MASK (0xFFU)
#define HDCP_HDCPREG_AN7_HDCPREG_AN7_SHIFT (0U)
/*! hdcpreg_an7 - Contains the value of BKSV[63:56]
*/
#define HDCP_HDCPREG_AN7_HDCPREG_AN7(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_AN7_HDCPREG_AN7_SHIFT)) & HDCP_HDCPREG_AN7_HDCPREG_AN7_MASK)
/*! @} */
/*! @name HDCPREG_RMLCTL - HDCP Encrypted Device Private Keys Control Register This register is the control register for the software programmable encrypted DPK embedded storage feature. */
/*! @{ */
#define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_MASK (0x1U)
#define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_SHIFT (0U)
/*! odpk_decrypt_enable - When set (1'b1), this bit activates the decryption of the Device Private keys.
*/
#define HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_SHIFT)) & HDCP_HDCPREG_RMLCTL_ODPK_DECRYPT_ENABLE_MASK)
/*! @} */
/*! @name HDCPREG_RMLSTS - HDCP Encrypted DPK Status Register The required software configuration sequence is documented in the DesignWare Cores HDMI Transmitter User Guide in the "Programming" chapter, Section 3. */
/*! @{ */
#define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_MASK (0x3FU)
#define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_SHIFT (0U)
/*! idpk_data_index - Current Device Private Key being written plus one.
*/
#define HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_SHIFT)) & HDCP_HDCPREG_RMLSTS_IDPK_DATA_INDEX_MASK)
#define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_MASK (0x40U)
#define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_SHIFT (6U)
/*! idpk_wr_ok_sts - When high (1'b1), it indicates that a DPK write is allowed.
*/
#define HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_SHIFT)) & HDCP_HDCPREG_RMLSTS_IDPK_WR_OK_STS_MASK)
/*! @} */
/*! @name HDCPREG_SEED0 - HDCP Encrypted DPK Seed Register 0 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys. */
/*! @{ */
#define HDCP_HDCPREG_SEED0_HDCPREG_SEED0_MASK (0xFFU)
#define HDCP_HDCPREG_SEED0_HDCPREG_SEED0_SHIFT (0U)
/*! hdcpreg_seed0 - Least significant byte of the decryption seed value (dpk_decrypt_seed[7:0]).
*/
#define HDCP_HDCPREG_SEED0_HDCPREG_SEED0(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_SEED0_HDCPREG_SEED0_SHIFT)) & HDCP_HDCPREG_SEED0_HDCPREG_SEED0_MASK)
/*! @} */
/*! @name HDCPREG_SEED1 - HDCP Encrypted DPK Seed Register 1 This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device Private Keys. */
/*! @{ */
#define HDCP_HDCPREG_SEED1_HDCPREG_SEED1_MASK (0xFFU)
#define HDCP_HDCPREG_SEED1_HDCPREG_SEED1_SHIFT (0U)
/*! hdcpreg_seed1 - Most significant byte of the decryption seed value (dpk_decrypt_seed[15:8]).
*/
#define HDCP_HDCPREG_SEED1_HDCPREG_SEED1(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_SEED1_HDCPREG_SEED1_SHIFT)) & HDCP_HDCPREG_SEED1_HDCPREG_SEED1_MASK)
/*! @} */
/*! @name HDCPREG_DPK0 - HDCP Encrypted DPK Data Register 0 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK0_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK0_DPK_DATA_SHIFT (0U)
/*! dpk_data - Byte of the encrypted DPK value.
*/
#define HDCP_HDCPREG_DPK0_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK0_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK0_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK1 - HDCP Encrypted DPK Data Register 1 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK1_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK1_DPK_DATA_SHIFT (0U)
/*! dpk_data - Byte of the encrypted DPK value.
*/
#define HDCP_HDCPREG_DPK1_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK1_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK1_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK2 - HDCP Encrypted DPK Data Register 2 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK2_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK2_DPK_DATA_SHIFT (0U)
/*! dpk_data - Byte of the encrypted DPK value.
*/
#define HDCP_HDCPREG_DPK2_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK2_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK2_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK3 - HDCP Encrypted DPK Data Register 3 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK3_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK3_DPK_DATA_SHIFT (0U)
/*! dpk_data - Byte of the encrypted DPK value.
*/
#define HDCP_HDCPREG_DPK3_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK3_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK3_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK4 - HDCP Encrypted DPK Data Register 4 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK4_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK4_DPK_DATA_SHIFT (0U)
/*! dpk_data - Byte of the encrypted DPK value.
*/
#define HDCP_HDCPREG_DPK4_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK4_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK4_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK5 - HDCP Encrypted DPK Data Register 5 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK5_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK5_DPK_DATA_SHIFT (0U)
/*! dpk_data - Contains the value of DPK[x][47:40]
*/
#define HDCP_HDCPREG_DPK5_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK5_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK5_DPK_DATA_MASK)
/*! @} */
/*! @name HDCPREG_DPK6 - HDCP Encrypted DPK Data Register 6 This register contains an HDCP DPK byte. */
/*! @{ */
#define HDCP_HDCPREG_DPK6_DPK_DATA_MASK (0xFFU)
#define HDCP_HDCPREG_DPK6_DPK_DATA_SHIFT (0U)
/*! dpk_data - Contains the value of DPK[x][55:48]
*/
#define HDCP_HDCPREG_DPK6_DPK_DATA(x) (((uint8_t)(((uint8_t)(x)) << HDCP_HDCPREG_DPK6_DPK_DATA_SHIFT)) & HDCP_HDCPREG_DPK6_DPK_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HDCP_Register_Masks */
/* HDCP - Peripheral instance base addresses */
/** Peripheral HDCP base address */
#define HDCP_BASE (0x32FDD000u)
/** Peripheral HDCP base pointer */
#define HDCP ((HDCP_Type *)HDCP_BASE)
/** Array initializer of HDCP peripheral base addresses */
#define HDCP_BASE_ADDRS { HDCP_BASE }
/** Array initializer of HDCP peripheral base pointers */
#define HDCP_BASE_PTRS { HDCP }
/*!
* @}
*/ /* end of group HDCP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HDCP22 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDCP22_Peripheral_Access_Layer HDCP22 Peripheral Access Layer
* @{
*/
/** HDCP22 - Register Layout Typedef */
typedef struct {
__I uint8_t HDCP22REG_ID; /**< HDCP 2., offset: 0x0 */
uint8_t RESERVED_0[3];
__IO uint8_t HDCP22REG_CTRL; /**< HDCP 2., offset: 0x4 */
__IO uint8_t HDCP22REG_CTRL1; /**< HDCP 2., offset: 0x5 */
uint8_t RESERVED_1[2];
__I uint8_t HDCP22REG_STS; /**< HDCP 2., offset: 0x8 */
uint8_t RESERVED_2[3];
__IO uint8_t HDCP22REG_MASK; /**< HDCP 2., offset: 0xC */
uint8_t RESERVED_3[2];
__IO uint8_t HDCP22REG_STAT; /**< HDCP 2., offset: 0xF */
uint8_t RESERVED_4[2];
__IO uint8_t HDCP22REG_MUTE; /**< HDCP 2., offset: 0x12 */
} HDCP22_Type;
/* ----------------------------------------------------------------------------
-- HDCP22 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDCP22_Register_Masks HDCP22 Register Masks
* @{
*/
/*! @name HDCP22REG_ID - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_MASK (0x2U)
#define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_SHIFT (1U)
/*! hdcp22_externalif - Indicates that External HDCP 2.
*/
#define HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_SHIFT)) & HDCP22_HDCP22REG_ID_HDCP22_EXTERNALIF_MASK)
#define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_MASK (0x4U)
#define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_SHIFT (2U)
/*! hdcp22_3rdparty - Indicates that External HDCP 2.
*/
#define HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_SHIFT)) & HDCP22_HDCP22REG_ID_HDCP22_3RDPARTY_MASK)
/*! @} */
/*! @name HDCP22REG_CTRL - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_MASK (0x1U)
#define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_SHIFT (0U)
/*! hdcp22_switch_lck - HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_SWITCH_LCK_MASK)
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_MASK (0x2U)
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_SHIFT (1U)
/*! hdcp22_ovr_en - HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_OVR_EN_MASK)
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_MASK (0x4U)
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_SHIFT (2U)
/*! hdcp22_ovr_val - HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL_HDCP22_OVR_VAL_MASK)
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_MASK (0x10U)
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_SHIFT (4U)
/*! hpd_ovr_en - HPD Override enable - 1'b0: The HPD value to the HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL_HPD_OVR_EN_MASK)
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_MASK (0x20U)
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_SHIFT (5U)
/*! hpd_ovr_val - HPD Override Value - 1'b0: If hpd_ovr_en is 1'b1 the HPD value to the HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL_HPD_OVR_VAL_MASK)
/*! @} */
/*! @name HDCP22REG_CTRL1 - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_MASK (0x1U)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_SHIFT (0U)
/*! hdcp22_avmute_ovr_en - HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_EN_MASK)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_MASK (0x2U)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_SHIFT (1U)
/*! hdcp22_avmute_ovr_val - HDCP AV_MUTE override value, which is sent through the HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_AVMUTE_OVR_VAL_MASK)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_MASK (0x8U)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_SHIFT (3U)
/*! hdcp22_cd_ovr_en - HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_EN_MASK)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_MASK (0xF0U)
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_SHIFT (4U)
/*! hdcp22_cd_ovr_val - HDCP color depth override value, which is sent through the HDCP 2.
*/
#define HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_SHIFT)) & HDCP22_HDCP22REG_CTRL1_HDCP22_CD_OVR_VAL_MASK)
/*! @} */
/*! @name HDCP22REG_STS - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_STS_HDMI_HPD_STS_MASK (0x1U)
#define HDCP22_HDCP22REG_STS_HDMI_HPD_STS_SHIFT (0U)
/*! hdmi_hpd_sts - HDCP 2.
*/
#define HDCP22_HDCP22REG_STS_HDMI_HPD_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDMI_HPD_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDMI_HPD_STS_MASK)
#define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_MASK (0x2U)
#define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_SHIFT (1U)
/*! hdcp_avmute_sts - HDCP 2.
*/
#define HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP_AVMUTE_STS_MASK)
#define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_MASK (0x4U)
#define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_SHIFT (2U)
/*! hdcp22_switch_sts - HDCP 2.
*/
#define HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP22_SWITCH_STS_MASK)
#define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_MASK (0x8U)
#define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_SHIFT (3U)
/*! hdcp_decrypted_sts - Value of HDCP 2.
*/
#define HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_SHIFT)) & HDCP22_HDCP22REG_STS_HDCP_DECRYPTED_STS_MASK)
/*! @} */
/*! @name HDCP22REG_MASK - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_MASK (0x1U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_SHIFT (0U)
/*! mask_hdcp2_capable - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP2_CAPABLE_MASK)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_MASK (0x2U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_SHIFT (1U)
/*! mask_hdcp2_not_capable - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP2_NOT_CAPABLE_MASK)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
/*! mask_hdcp_authentication_lost - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_LOST_MASK)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_MASK (0x8U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_SHIFT (3U)
/*! mask_hdcp_authenticated - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATED_MASK)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
/*! mask_hdcp_authentication_fail - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_AUTHENTICATION_FAIL_MASK)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_MASK (0x20U)
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_SHIFT (5U)
/*! mask_hdcp_decrypted_chg - Active high interrupt mask to HDCP 2.
*/
#define HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_MASK_MASK_HDCP_DECRYPTED_CHG_MASK)
/*! @} */
/*! @name HDCP22REG_STAT - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_MASK (0x1U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_SHIFT (0U)
/*! st_hdcp2_capable - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP2_CAPABLE_MASK)
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_MASK (0x2U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_SHIFT (1U)
/*! st_hdcp2_not_capable - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP2_NOT_CAPABLE_MASK)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
/*! st_hdcp_authentication_lost - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_LOST_MASK)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_MASK (0x8U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_SHIFT (3U)
/*! st_hdcp_authenticated - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATED_MASK)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
/*! st_hdcp_authentication_fail - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_AUTHENTICATION_FAIL_MASK)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_MASK (0x20U)
#define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_SHIFT (5U)
/*! st_hdcp_decrypted_chg - HDCP 2.
*/
#define HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_STAT_ST_HDCP_DECRYPTED_CHG_MASK)
/*! @} */
/*! @name HDCP22REG_MUTE - HDCP 2. */
/*! @{ */
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_MASK (0x1U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_SHIFT (0U)
/*! mute_hdcp2_capable - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_CAPABLE_MASK)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_MASK (0x2U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_SHIFT (1U)
/*! mute_hdcp2_not_capable - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP2_NOT_CAPABLE_MASK)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_MASK (0x4U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_SHIFT (2U)
/*! mute_hdcp_authentication_lost - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_LOST_MASK)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_MASK (0x8U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_SHIFT (3U)
/*! mute_hdcp_authenticated - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATED_MASK)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_MASK (0x10U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_SHIFT (4U)
/*! mute_hdcp_authentication_fail - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_AUTHENTICATION_FAIL_MASK)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_MASK (0x20U)
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_SHIFT (5U)
/*! mute_hdcp_decrypted_chg - Active high interrupt mute to HDCP 2.
*/
#define HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG(x) (((uint8_t)(((uint8_t)(x)) << HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_SHIFT)) & HDCP22_HDCP22REG_MUTE_MUTE_HDCP_DECRYPTED_CHG_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HDCP22_Register_Masks */
/* HDCP22 - Peripheral instance base addresses */
/** Peripheral HDCP22 base address */
#define HDCP22_BASE (0x32FDF900u)
/** Peripheral HDCP22 base pointer */
#define HDCP22 ((HDCP22_Type *)HDCP22_BASE)
/** Array initializer of HDCP22 peripheral base addresses */
#define HDCP22_BASE_ADDRS { HDCP22_BASE }
/** Array initializer of HDCP22 peripheral base pointers */
#define HDCP22_BASE_PTRS { HDCP22 }
/*!
* @}
*/ /* end of group HDCP22_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HDMI_TRNG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDMI_TRNG_Peripheral_Access_Layer HDMI_TRNG Peripheral Access Layer
* @{
*/
/** HDMI_TRNG - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< This register causes the DWC_trng to execute one of a number of actions., offset: 0x0 */
__I uint32_t STAT; /**< The NONCE_MODE field indicates that the engine is currently waiting for the host to load a nonce through the SEEDx registers., offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t SMODE; /**< This register is used to enable or disable certain mission-mode run-time features within the core., offset: 0xC */
__IO uint32_t IE; /**< This register is used to enable or disable interrupts within the DWC_trng., offset: 0x10 */
__IO uint32_t ISTAT; /**< This register allows the user to monitor the interrupt and/or status contributions of the DWC_trng., offset: 0x14 */
__I uint32_t COREKIT_REL; /**< Contains the coreKit release information., offset: 0x18 */
__I uint32_t FEATURES; /**< Contains the build-time parameter enumerations., offset: 0x1C */
__I uint32_t RAND0; /**< The RAND0 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x20 */
__I uint32_t RAND1; /**< The RAND1 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x24 */
__I uint32_t RAND2; /**< The RAND2 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x28 */
__I uint32_t RAND3; /**< The RAND3 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x2C */
__I uint32_t RAND4; /**< The RAND4 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x30 */
__I uint32_t RAND5; /**< The RAND5 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x34 */
__I uint32_t RAND6; /**< The RAND6 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x38 */
__I uint32_t RAND7; /**< The RAND7 register is part of the RANDx register set which are used by the host to read the newly generated random number., offset: 0x3C */
__I uint32_t SEED0; /**< The SEED0 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x40 */
__I uint32_t SEED1; /**< The SEED1 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x44 */
__I uint32_t SEED2; /**< The SEED2 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x48 */
__I uint32_t SEED3; /**< The SEED3 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x4C */
__I uint32_t SEED4; /**< The SEED4 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x50 */
__I uint32_t SEED5; /**< The SEED5 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x54 */
__I uint32_t SEED6; /**< The SEED6 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x58 */
__I uint32_t SEED7; /**< The SEED7 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng., offset: 0x5C */
__IO uint32_t AUTO_RQSTS; /**< This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host., offset: 0x60 */
__IO uint32_t AUTO_AGE; /**< This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host., offset: 0x64 */
__I uint32_t BUILD_CONFIG; /**< Contains the build-time parameter enumerations., offset: 0x68 */
} HDMI_TRNG_Type;
/* ----------------------------------------------------------------------------
-- HDMI_TRNG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDMI_TRNG_Register_Masks HDMI_TRNG Register Masks
* @{
*/
/*! @name CTRL - This register causes the DWC_trng to execute one of a number of actions. */
/*! @{ */
#define HDMI_TRNG_CTRL_CMD_MASK (0x7U)
#define HDMI_TRNG_CTRL_CMD_SHIFT (0U)
/*! CMD - Execute a command.
* 0b001..Generate a random number
* 0b011..Execute a nonce reseed
* 0b000..Execute a NOP
* 0b010..Execute a random reseed
*/
#define HDMI_TRNG_CTRL_CMD(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_CTRL_CMD_SHIFT)) & HDMI_TRNG_CTRL_CMD_MASK)
/*! @} */
/*! @name STAT - The NONCE_MODE field indicates that the engine is currently waiting for the host to load a nonce through the SEEDx registers. */
/*! @{ */
#define HDMI_TRNG_STAT_NONCE_MODE_MASK (0x4U)
#define HDMI_TRNG_STAT_NONCE_MODE_SHIFT (2U)
/*! NONCE_MODE - Current state of NONCE mode.
* 0b0..Nonce mode disabled
* 0b1..Nonce mode enabled
*/
#define HDMI_TRNG_STAT_NONCE_MODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_NONCE_MODE_SHIFT)) & HDMI_TRNG_STAT_NONCE_MODE_MASK)
#define HDMI_TRNG_STAT_R256_MASK (0x8U)
#define HDMI_TRNG_STAT_R256_SHIFT (3U)
/*! R256 - Reflects state of MODE.
*/
#define HDMI_TRNG_STAT_R256(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_R256_SHIFT)) & HDMI_TRNG_STAT_R256_MASK)
#define HDMI_TRNG_STAT_MISSION_MODE_MASK (0x100U)
#define HDMI_TRNG_STAT_MISSION_MODE_SHIFT (8U)
/*! MISSION_MODE - Reflects state of SMODE.
*/
#define HDMI_TRNG_STAT_MISSION_MODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_MISSION_MODE_SHIFT)) & HDMI_TRNG_STAT_MISSION_MODE_MASK)
#define HDMI_TRNG_STAT_SEEDED_MASK (0x200U)
#define HDMI_TRNG_STAT_SEEDED_SHIFT (9U)
/*! SEEDED - Current SEEDED state.
* 0b0..PRNG core is not seeded
* 0b1..PRNG core is seeded
*/
#define HDMI_TRNG_STAT_SEEDED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_SEEDED_SHIFT)) & HDMI_TRNG_STAT_SEEDED_MASK)
#define HDMI_TRNG_STAT_LAST_RESEED_MASK (0x70000U)
#define HDMI_TRNG_STAT_LAST_RESEED_SHIFT (16U)
/*! LAST_RESEED - Action which loaded current seed.
* 0b000..Reseeded by host random reseed command
* 0b011..Reseeded by nonce
* 0b100..Reseeded by I_reseed driven to 1 or internal auto-reseed
* 0b111..Unseeded (zeroized state)
*/
#define HDMI_TRNG_STAT_LAST_RESEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_LAST_RESEED_SHIFT)) & HDMI_TRNG_STAT_LAST_RESEED_MASK)
#define HDMI_TRNG_STAT_SRVC_RQST_MASK (0x8000000U)
#define HDMI_TRNG_STAT_SRVC_RQST_SHIFT (27U)
/*! SRVC_RQST - Current state of unacknowledged request indicator.
* 0b0..No unacknowledged service request
* 0b1..Unacknowledged service request
*/
#define HDMI_TRNG_STAT_SRVC_RQST(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_SRVC_RQST_SHIFT)) & HDMI_TRNG_STAT_SRVC_RQST_MASK)
#define HDMI_TRNG_STAT_RAND_GENERATING_MASK (0x40000000U)
#define HDMI_TRNG_STAT_RAND_GENERATING_SHIFT (30U)
/*! RAND_GENERATING - Current state of random number generation operations.
* 0b0..No random number generation process in progress
* 0b1..Random number generation process in progress
*/
#define HDMI_TRNG_STAT_RAND_GENERATING(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_RAND_GENERATING_SHIFT)) & HDMI_TRNG_STAT_RAND_GENERATING_MASK)
#define HDMI_TRNG_STAT_RAND_RESEEDING_MASK (0x80000000U)
#define HDMI_TRNG_STAT_RAND_RESEEDING_SHIFT (31U)
/*! RAND_RESEEDING - Current state of random seed generation operations.
* 0b0..No random reseed generation process in progress
* 0b1..Random reseed generation process in progress
*/
#define HDMI_TRNG_STAT_RAND_RESEEDING(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_STAT_RAND_RESEEDING_SHIFT)) & HDMI_TRNG_STAT_RAND_RESEEDING_MASK)
/*! @} */
/*! @name SMODE - This register is used to enable or disable certain mission-mode run-time features within the core. */
/*! @{ */
#define HDMI_TRNG_SMODE_NONCE_MODE_MASK (0x4U)
#define HDMI_TRNG_SMODE_NONCE_MODE_SHIFT (2U)
/*! NONCE_MODE - Sets the reseed mode to nonce or random.
* 0b0..Disable nonce mode
* 0b1..Enable nonce mode
*/
#define HDMI_TRNG_SMODE_NONCE_MODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_NONCE_MODE_SHIFT)) & HDMI_TRNG_SMODE_NONCE_MODE_MASK)
#define HDMI_TRNG_SMODE_MISSION_MODE_MASK (0x100U)
#define HDMI_TRNG_SMODE_MISSION_MODE_SHIFT (8U)
/*! MISSION_MODE - Sets the operating mode to TEST or MISSION.
* 0b1..Mission mode (no access to internal state)
* 0b0..Test mode (access to internal state and test fields)
*/
#define HDMI_TRNG_SMODE_MISSION_MODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_MISSION_MODE_SHIFT)) & HDMI_TRNG_SMODE_MISSION_MODE_MASK)
#define HDMI_TRNG_SMODE_MAX_REJECTS_MASK (0xFF0000U)
#define HDMI_TRNG_SMODE_MAX_REJECTS_SHIFT (16U)
/*! MAX_REJECTS - Maximum number of consecutive bit rejections before issuing ring tweak.
*/
#define HDMI_TRNG_SMODE_MAX_REJECTS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SMODE_MAX_REJECTS_SHIFT)) & HDMI_TRNG_SMODE_MAX_REJECTS_MASK)
/*! @} */
/*! @name IE - This register is used to enable or disable interrupts within the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_IE_RAND_RDY_EN_MASK (0x1U)
#define HDMI_TRNG_IE_RAND_RDY_EN_SHIFT (0U)
/*! RAND_RDY_EN - Include or exclude RAND_RDY interrupt contribution.
* 0b0..Disable RAND_RDY interrupt contribution
* 0b1..Enable RAND_RDY interrupt contribution
*/
#define HDMI_TRNG_IE_RAND_RDY_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_RAND_RDY_EN_SHIFT)) & HDMI_TRNG_IE_RAND_RDY_EN_MASK)
#define HDMI_TRNG_IE_SEED_DONE_EN_MASK (0x2U)
#define HDMI_TRNG_IE_SEED_DONE_EN_SHIFT (1U)
/*! SEED_DONE_EN - Include or exclude SEED_DONE interrupt contribution.
* 0b0..Disable SEED_DONE interrupt contribution
* 0b1..Enable SEED_DONE interrupt contribution
*/
#define HDMI_TRNG_IE_SEED_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_SEED_DONE_EN_SHIFT)) & HDMI_TRNG_IE_SEED_DONE_EN_MASK)
#define HDMI_TRNG_IE_AGE_ALARM_EN_MASK (0x4U)
#define HDMI_TRNG_IE_AGE_ALARM_EN_SHIFT (2U)
/*! AGE_ALARM_EN - Include or exclude AGE_ALARM interrupt contribution.
* 0b0..Disable AGE_ALARM interrupt contribution
* 0b1..Enable AGE_ALARM interrupt contribution
*/
#define HDMI_TRNG_IE_AGE_ALARM_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_AGE_ALARM_EN_SHIFT)) & HDMI_TRNG_IE_AGE_ALARM_EN_MASK)
#define HDMI_TRNG_IE_RQST_ALARM_EN_MASK (0x8U)
#define HDMI_TRNG_IE_RQST_ALARM_EN_SHIFT (3U)
/*! RQST_ALARM_EN - Include or exclude RQST_ALARM interrupt contribution.
* 0b0..Disable RQST_ALARM interrupt contribution
* 0b1..Enable RQST_ALARM interrupt contribution
*/
#define HDMI_TRNG_IE_RQST_ALARM_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_RQST_ALARM_EN_SHIFT)) & HDMI_TRNG_IE_RQST_ALARM_EN_MASK)
#define HDMI_TRNG_IE_LFSR_LOCKUP_EN_MASK (0x10U)
#define HDMI_TRNG_IE_LFSR_LOCKUP_EN_SHIFT (4U)
/*! LFSR_LOCKUP_EN - Include or exclude LFSR_LOCKUP interrupt contribution.
* 0b0..Disable LFSR_LOCKUP interrupt contribution
* 0b1..Enable LFSR_LOCKUP interrupt contribution
*/
#define HDMI_TRNG_IE_LFSR_LOCKUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_LFSR_LOCKUP_EN_SHIFT)) & HDMI_TRNG_IE_LFSR_LOCKUP_EN_MASK)
#define HDMI_TRNG_IE_GLBL_EN_MASK (0x80000000U)
#define HDMI_TRNG_IE_GLBL_EN_SHIFT (31U)
/*! GLBL_EN - Global interrupt enable.
* 0b0..Globally disable interrupts
* 0b1..Globally enable interrupts
*/
#define HDMI_TRNG_IE_GLBL_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_IE_GLBL_EN_SHIFT)) & HDMI_TRNG_IE_GLBL_EN_MASK)
/*! @} */
/*! @name ISTAT - This register allows the user to monitor the interrupt and/or status contributions of the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_ISTAT_RAND_RDY_MASK (0x1U)
#define HDMI_TRNG_ISTAT_RAND_RDY_SHIFT (0U)
/*! RAND_RDY - Status and acknowledgment (clearing) of RAND_RDY indicator.
* 0b0..No unacknowledged RAND_RDY indicator
* 0b1..Unacknowledged RAND_RDY indicator
* 0b0..NOP
* 0b1..Acknowledge RAND_RDY indicator
*/
#define HDMI_TRNG_ISTAT_RAND_RDY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_RAND_RDY_SHIFT)) & HDMI_TRNG_ISTAT_RAND_RDY_MASK)
#define HDMI_TRNG_ISTAT_SEED_DONE_MASK (0x2U)
#define HDMI_TRNG_ISTAT_SEED_DONE_SHIFT (1U)
/*! SEED_DONE - Status and acknowledgment (clearing) of SEED_DONE indicator.
* 0b0..No unacknowledged SEED_DONE indicator
* 0b1..Unacknowledged SEED_DONE indicator
* 0b0..NOP
* 0b1..Acknowledge SEED_DONE indicator
*/
#define HDMI_TRNG_ISTAT_SEED_DONE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_SEED_DONE_SHIFT)) & HDMI_TRNG_ISTAT_SEED_DONE_MASK)
#define HDMI_TRNG_ISTAT_AGE_ALARM_MASK (0x4U)
#define HDMI_TRNG_ISTAT_AGE_ALARM_SHIFT (2U)
/*! AGE_ALARM - Status and acknowledgment (clearing) of AGE_ALARM indicator.
* 0b0..No unacknowledged AGE_ALARM indicator
* 0b1..Unacknowledged AGE_ALARM indicator
* 0b0..NOP
* 0b1..Acknowledge AGE_ALARM indicator
*/
#define HDMI_TRNG_ISTAT_AGE_ALARM(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_AGE_ALARM_SHIFT)) & HDMI_TRNG_ISTAT_AGE_ALARM_MASK)
#define HDMI_TRNG_ISTAT_RQST_ALARM_MASK (0x8U)
#define HDMI_TRNG_ISTAT_RQST_ALARM_SHIFT (3U)
/*! RQST_ALARM - Status and acknowledgment (clearing) of RQST_ALARM indicator.
* 0b0..No unacknowledged RQST_ALARM indicator
* 0b1..Unacknowledged RQST_ALARM indicator
* 0b0..NOP
* 0b1..Acknowledge RQST_ALARM indicator
*/
#define HDMI_TRNG_ISTAT_RQST_ALARM(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_RQST_ALARM_SHIFT)) & HDMI_TRNG_ISTAT_RQST_ALARM_MASK)
#define HDMI_TRNG_ISTAT_LFSR_LOCKUP_MASK (0x10U)
#define HDMI_TRNG_ISTAT_LFSR_LOCKUP_SHIFT (4U)
/*! LFSR_LOCKUP - Status and acknowledgment (clearing) of LFSR_LOCKUP indicator.
* 0b0..No unacknowledged LFSR_LOCKUP indicator
* 0b1..Unacknowledged LFSR_LOCKUP indicator
* 0b0..NOP
* 0b1..Acknowledge LFSR_LOCKUP indicator
*/
#define HDMI_TRNG_ISTAT_LFSR_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_ISTAT_LFSR_LOCKUP_SHIFT)) & HDMI_TRNG_ISTAT_LFSR_LOCKUP_MASK)
/*! @} */
/*! @name COREKIT_REL - Contains the coreKit release information. */
/*! @{ */
#define HDMI_TRNG_COREKIT_REL_REL_NUM_MASK (0xFFFFU)
#define HDMI_TRNG_COREKIT_REL_REL_NUM_SHIFT (0U)
/*! REL_NUM - Indicates the coreKit release version in pseudo-BCD.
*/
#define HDMI_TRNG_COREKIT_REL_REL_NUM(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_REL_NUM_SHIFT)) & HDMI_TRNG_COREKIT_REL_REL_NUM_MASK)
#define HDMI_TRNG_COREKIT_REL_EXT_VER_MASK (0xFF0000U)
#define HDMI_TRNG_COREKIT_REL_EXT_VER_SHIFT (16U)
/*! EXT_VER - Indicates the coreKit release extension version number.
*/
#define HDMI_TRNG_COREKIT_REL_EXT_VER(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_EXT_VER_SHIFT)) & HDMI_TRNG_COREKIT_REL_EXT_VER_MASK)
#define HDMI_TRNG_COREKIT_REL_EXT_ENUM_MASK (0xF0000000U)
#define HDMI_TRNG_COREKIT_REL_EXT_ENUM_SHIFT (28U)
/*! EXT_ENUM - Indicates the coreKit release extension type.
* 0b0010..EA release
* 0b0000..GA release
* 0b0001..LCA release
* 0b0011..LP release
* 0b0100..LPC release
* 0b0101..SOW release
*/
#define HDMI_TRNG_COREKIT_REL_EXT_ENUM(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_COREKIT_REL_EXT_ENUM_SHIFT)) & HDMI_TRNG_COREKIT_REL_EXT_ENUM_MASK)
/*! @} */
/*! @name FEATURES - Contains the build-time parameter enumerations. */
/*! @{ */
#define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_MASK (0x3U)
#define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_SHIFT (0U)
/*! MAX_RAND_LENGTH - Maximum length of the PRNG RANDx register set.
* 0b00..PRNG set up for 128-bit maximum
* 0b01..PRNG set up for 256-bit maximum
*/
#define HDMI_TRNG_FEATURES_MAX_RAND_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_SHIFT)) & HDMI_TRNG_FEATURES_MAX_RAND_LENGTH_MASK)
#define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_MASK (0x4U)
#define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_SHIFT (2U)
/*! RAND_SEED_AVAIL - Indicates the ring-oscillator sub-section is present.
* 0b0..No ring-oscillator seed generator present
* 0b1..Ring-oscillator seed generator present
*/
#define HDMI_TRNG_FEATURES_RAND_SEED_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_SHIFT)) & HDMI_TRNG_FEATURES_RAND_SEED_AVAIL_MASK)
#define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_MASK (0x8U)
#define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_SHIFT (3U)
/*! MISSION_MODE_RESET_STATE - Indicates state of SMODE.
* 0b1..Resets to MISSION_MODE
* 0b0..Resets to TEST_MODE
*/
#define HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_SHIFT)) & HDMI_TRNG_FEATURES_MISSION_MODE_RESET_STATE_MASK)
#define HDMI_TRNG_FEATURES_DIAG_LEVEL_MASK (0x70U)
#define HDMI_TRNG_FEATURES_DIAG_LEVEL_SHIFT (4U)
/*! DIAG_LEVEL - Level of diagnostic support provided.
*/
#define HDMI_TRNG_FEATURES_DIAG_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_FEATURES_DIAG_LEVEL_SHIFT)) & HDMI_TRNG_FEATURES_DIAG_LEVEL_MASK)
/*! @} */
/*! @name RAND0 - The RAND0 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND0_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND0_RAND_SHIFT (0U)
/*! RAND - Random data word 0.
*/
#define HDMI_TRNG_RAND0_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND0_RAND_SHIFT)) & HDMI_TRNG_RAND0_RAND_MASK)
/*! @} */
/*! @name RAND1 - The RAND1 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND1_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND1_RAND_SHIFT (0U)
/*! RAND - Random data word 1.
*/
#define HDMI_TRNG_RAND1_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND1_RAND_SHIFT)) & HDMI_TRNG_RAND1_RAND_MASK)
/*! @} */
/*! @name RAND2 - The RAND2 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND2_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND2_RAND_SHIFT (0U)
/*! RAND - Random data word 2.
*/
#define HDMI_TRNG_RAND2_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND2_RAND_SHIFT)) & HDMI_TRNG_RAND2_RAND_MASK)
/*! @} */
/*! @name RAND3 - The RAND3 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND3_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND3_RAND_SHIFT (0U)
/*! RAND - Random data word 3.
*/
#define HDMI_TRNG_RAND3_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND3_RAND_SHIFT)) & HDMI_TRNG_RAND3_RAND_MASK)
/*! @} */
/*! @name RAND4 - The RAND4 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND4_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND4_RAND_SHIFT (0U)
/*! RAND - Random data word 4.
*/
#define HDMI_TRNG_RAND4_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND4_RAND_SHIFT)) & HDMI_TRNG_RAND4_RAND_MASK)
/*! @} */
/*! @name RAND5 - The RAND5 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND5_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND5_RAND_SHIFT (0U)
/*! RAND - Random data word 5.
*/
#define HDMI_TRNG_RAND5_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND5_RAND_SHIFT)) & HDMI_TRNG_RAND5_RAND_MASK)
/*! @} */
/*! @name RAND6 - The RAND6 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND6_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND6_RAND_SHIFT (0U)
/*! RAND - Random data word 6.
*/
#define HDMI_TRNG_RAND6_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND6_RAND_SHIFT)) & HDMI_TRNG_RAND6_RAND_MASK)
/*! @} */
/*! @name RAND7 - The RAND7 register is part of the RANDx register set which are used by the host to read the newly generated random number. */
/*! @{ */
#define HDMI_TRNG_RAND7_RAND_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_RAND7_RAND_SHIFT (0U)
/*! RAND - Random data word 7.
*/
#define HDMI_TRNG_RAND7_RAND(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_RAND7_RAND_SHIFT)) & HDMI_TRNG_RAND7_RAND_MASK)
/*! @} */
/*! @name SEED0 - The SEED0 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED0_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED0_SEED_SHIFT (0U)
/*! SEED - Seed data word 0.
*/
#define HDMI_TRNG_SEED0_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED0_SEED_SHIFT)) & HDMI_TRNG_SEED0_SEED_MASK)
/*! @} */
/*! @name SEED1 - The SEED1 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED1_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED1_SEED_SHIFT (0U)
/*! SEED - Seed data word 1.
*/
#define HDMI_TRNG_SEED1_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED1_SEED_SHIFT)) & HDMI_TRNG_SEED1_SEED_MASK)
/*! @} */
/*! @name SEED2 - The SEED2 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED2_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED2_SEED_SHIFT (0U)
/*! SEED - Seed data word 2.
*/
#define HDMI_TRNG_SEED2_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED2_SEED_SHIFT)) & HDMI_TRNG_SEED2_SEED_MASK)
/*! @} */
/*! @name SEED3 - The SEED3 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED3_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED3_SEED_SHIFT (0U)
/*! SEED - Seed data word 3.
*/
#define HDMI_TRNG_SEED3_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED3_SEED_SHIFT)) & HDMI_TRNG_SEED3_SEED_MASK)
/*! @} */
/*! @name SEED4 - The SEED4 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED4_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED4_SEED_SHIFT (0U)
/*! SEED - Seed data word 4.
*/
#define HDMI_TRNG_SEED4_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED4_SEED_SHIFT)) & HDMI_TRNG_SEED4_SEED_MASK)
/*! @} */
/*! @name SEED5 - The SEED5 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED5_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED5_SEED_SHIFT (0U)
/*! SEED - Seed data word 5.
*/
#define HDMI_TRNG_SEED5_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED5_SEED_SHIFT)) & HDMI_TRNG_SEED5_SEED_MASK)
/*! @} */
/*! @name SEED6 - The SEED6 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED6_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED6_SEED_SHIFT (0U)
/*! SEED - Seed data word 6.
*/
#define HDMI_TRNG_SEED6_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED6_SEED_SHIFT)) & HDMI_TRNG_SEED6_SEED_MASK)
/*! @} */
/*! @name SEED7 - The SEED7 register is part of the SEEDx register set which are used to load a host generated nonce seed into the DWC_trng. */
/*! @{ */
#define HDMI_TRNG_SEED7_SEED_MASK (0xFFFFFFFFU)
#define HDMI_TRNG_SEED7_SEED_SHIFT (0U)
/*! SEED - Seed data word 7.
*/
#define HDMI_TRNG_SEED7_SEED(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_SEED7_SEED_SHIFT)) & HDMI_TRNG_SEED7_SEED_MASK)
/*! @} */
/*! @name AUTO_RQSTS - This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host. */
/*! @{ */
#define HDMI_TRNG_AUTO_RQSTS_RQSTS_MASK (0xFFFFU)
#define HDMI_TRNG_AUTO_RQSTS_RQSTS_SHIFT (0U)
/*! RQSTS - 0 = disable the AUTO_RQSTS alarm feature other = reload value for internal AUTO_RQSTS counter
*/
#define HDMI_TRNG_AUTO_RQSTS_RQSTS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_AUTO_RQSTS_RQSTS_SHIFT)) & HDMI_TRNG_AUTO_RQSTS_RQSTS_MASK)
/*! @} */
/*! @name AUTO_AGE - This register allows the DWC_trng to generate a reseed reminder alarm after a specified number of random numbers have been requested by the host. */
/*! @{ */
#define HDMI_TRNG_AUTO_AGE_AGE_MASK (0xFFFFU)
#define HDMI_TRNG_AUTO_AGE_AGE_SHIFT (0U)
/*! AGE - 0 = disable the AUTO_AGE alarm feature other = reload value for internal AUTO_AGE counter
*/
#define HDMI_TRNG_AUTO_AGE_AGE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_AUTO_AGE_AGE_SHIFT)) & HDMI_TRNG_AUTO_AGE_AGE_MASK)
/*! @} */
/*! @name BUILD_CONFIG - Contains the build-time parameter enumerations. */
/*! @{ */
#define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_MASK (0x3U)
#define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_SHIFT (0U)
/*! CORE_TYPE - Configured I/O style (license controlled).
* 0b01..ESM nonce I/O
* 0b10..ESM nonce I/O with multi-ESM support
* 0b00..5-Wire control/status I/O
*/
#define HDMI_TRNG_BUILD_CONFIG_CORE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_CORE_TYPE_MASK)
#define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_MASK (0x4U)
#define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_SHIFT (2U)
/*! MAX_PRNG_LEN - Maximum length of the PRNG RANDx register set.
* 0b0..PRNG set up for 128-bit maximum
* 0b1..PRNG set up for 256-bit maximum
*/
#define HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_MAX_PRNG_LEN_MASK)
#define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_MASK (0x8U)
#define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_SHIFT (3U)
/*! PRNG_LEN_AFTER_RST - State of MODE.
* 0b0..PRNG length set to 128-bit after reset
* 0b1..PRNG length set to 256-bit after reset
*/
#define HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_PRNG_LEN_AFTER_RST_MASK)
#define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_MASK (0x10U)
#define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_SHIFT (4U)
/*! MODE_AFTER_RST - Indicates state of SMODE.
* 0b1..Resets to MISSION_MODE
* 0b0..Resets to TEST_MODE
*/
#define HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_MODE_AFTER_RST_MASK)
#define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_MASK (0x20U)
#define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_SHIFT (5U)
/*! AUTO_RESEED_LOOPBACK - Indicates auto-reseed configuration setting.
* 0b1..Auto-reseed loopback present
* 0b0..No auto-reseed loopback
*/
#define HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_AUTO_RESEED_LOOPBACK_MASK)
#define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_MASK (0x700U)
#define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_SHIFT (8U)
/*! DIAGNOSTIC_LEVEL - Level of diagnostic support provided.
*/
#define HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_DIAGNOSTIC_LEVEL_MASK)
#define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_MASK (0xF000U)
#define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_SHIFT (12U)
/*! ESM_PORTS - Indicates number of ESM arbitration ports available minus 1.
*/
#define HDMI_TRNG_BUILD_CONFIG_ESM_PORTS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_SHIFT)) & HDMI_TRNG_BUILD_CONFIG_ESM_PORTS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HDMI_TRNG_Register_Masks */
/* HDMI_TRNG - Peripheral instance base addresses */
/** Peripheral HDMI_TRNG base address */
#define HDMI_TRNG_BASE (0x32FD3000u)
/** Peripheral HDMI_TRNG base pointer */
#define HDMI_TRNG ((HDMI_TRNG_Type *)HDMI_TRNG_BASE)
/** Array initializer of HDMI_TRNG peripheral base addresses */
#define HDMI_TRNG_BASE_ADDRS { HDMI_TRNG_BASE }
/** Array initializer of HDMI_TRNG peripheral base pointers */
#define HDMI_TRNG_BASE_PTRS { HDMI_TRNG }
/*!
* @}
*/ /* end of group HDMI_TRNG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HDMI_TX_BLK_CTL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDMI_TX_BLK_CTL_Peripheral_Access_Layer HDMI_TX_BLK_CTL Peripheral Access Layer
* @{
*/
/** HDMI_TX_BLK_CTL - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x0 */
__IO uint32_t SET; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x4 */
__IO uint32_t CLR; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x8 */
__IO uint32_t TOG; /**< HDMI_RTX_GENERAL CONFIG, offset: 0xC */
} RTX_GENERAL;
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x10 */
__IO uint32_t SET; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x14 */
__IO uint32_t CLR; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x18 */
__IO uint32_t TOG; /**< HDMI_RTX_GENERAL CONFIG, offset: 0x1C */
} RTX_GENERAL_1;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< HDMI_RTX_RESET_CTL0, offset: 0x20 */
__IO uint32_t SET; /**< HDMI_RTX_RESET_CTL0, offset: 0x24 */
__IO uint32_t CLR; /**< HDMI_RTX_RESET_CTL0, offset: 0x28 */
__IO uint32_t TOG; /**< HDMI_RTX_RESET_CTL0, offset: 0x2C */
} RTX_RESET_CTL0;
uint8_t RESERVED_0[16];
struct { /* offset: 0x40 */
__IO uint32_t RW; /**< HDMI_RTX_CLK_CTL0, offset: 0x40 */
__IO uint32_t SET; /**< HDMI_RTX_CLK_CTL0, offset: 0x44 */
__IO uint32_t CLR; /**< HDMI_RTX_CLK_CTL0, offset: 0x48 */
__IO uint32_t TOG; /**< HDMI_RTX_CLK_CTL0, offset: 0x4C */
} RTX_CLK_CTL0;
struct { /* offset: 0x50 */
__IO uint32_t RW; /**< HDMI_RTX_CLK_CTL1, offset: 0x50 */
__IO uint32_t SET; /**< HDMI_RTX_CLK_CTL1, offset: 0x54 */
__IO uint32_t CLR; /**< HDMI_RTX_CLK_CTL1, offset: 0x58 */
__IO uint32_t TOG; /**< HDMI_RTX_CLK_CTL1, offset: 0x5C */
} RTX_CLK_CTL1;
struct { /* offset: 0x60 */
__IO uint32_t RW; /**< RTX_CLK_CTL2, offset: 0x60 */
__IO uint32_t SET; /**< RTX_CLK_CTL2, offset: 0x64 */
__IO uint32_t CLR; /**< RTX_CLK_CTL2, offset: 0x68 */
__IO uint32_t TOG; /**< RTX_CLK_CTL2, offset: 0x6C */
} RTX_CLK_CTL2;
struct { /* offset: 0x70 */
__IO uint32_t RW; /**< RTX_CLK_CTL3, offset: 0x70 */
__IO uint32_t SET; /**< RTX_CLK_CTL3, offset: 0x74 */
__IO uint32_t CLR; /**< RTX_CLK_CTL3, offset: 0x78 */
__IO uint32_t TOG; /**< RTX_CLK_CTL3, offset: 0x7C */
} RTX_CLK_CTL3;
struct { /* offset: 0x80 */
__IO uint32_t RW; /**< RTX_CLK_CTL4, offset: 0x80 */
__IO uint32_t SET; /**< RTX_CLK_CTL4, offset: 0x84 */
__IO uint32_t CLR; /**< RTX_CLK_CTL4, offset: 0x88 */
__IO uint32_t TOG; /**< RTX_CLK_CTL4, offset: 0x8C */
} RTX_CLK_CTL4;
struct { /* offset: 0x90 */
__IO uint32_t RW; /**< HDMI_RX_Control, offset: 0x90 */
__IO uint32_t SET; /**< HDMI_RX_Control, offset: 0x94 */
__IO uint32_t CLR; /**< HDMI_RX_Control, offset: 0x98 */
__IO uint32_t TOG; /**< HDMI_RX_Control, offset: 0x9C */
} RTX_IRQ_MASK;
struct { /* offset: 0xA0 */
__I uint32_t RW; /**< HDMI_TX Masked Interrupt status, offset: 0xA0 */
__I uint32_t SET; /**< HDMI_TX Masked Interrupt status, offset: 0xA4 */
__I uint32_t CLR; /**< HDMI_TX Masked Interrupt status, offset: 0xA8 */
__I uint32_t TOG; /**< HDMI_TX Masked Interrupt status, offset: 0xAC */
} RTX_IRQ_MASKED_STATUS;
struct { /* offset: 0xB0 */
__IO uint32_t RW; /**< HDMI_RX_Control, offset: 0xB0 */
__IO uint32_t SET; /**< HDMI_RX_Control, offset: 0xB4 */
__IO uint32_t CLR; /**< HDMI_RX_Control, offset: 0xB8 */
__IO uint32_t TOG; /**< HDMI_RX_Control, offset: 0xBC */
} RTX_IRQ_NONMASK_STATUS;
uint8_t RESERVED_1[320];
struct { /* offset: 0x200 */
__IO uint32_t RW; /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x200 */
__IO uint32_t SET; /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x204 */
__IO uint32_t CLR; /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x208 */
__IO uint32_t TOG; /**< Miscellaneous Controls for the HDMI TX Controller, offset: 0x20C */
} TX_CONTROL0;
uint8_t RESERVED_2[16];
struct { /* offset: 0x220 */
__IO uint32_t RW; /**< TX Control, offset: 0x220 */
__IO uint32_t SET; /**< TX Control, offset: 0x224 */
__IO uint32_t CLR; /**< TX Control, offset: 0x228 */
__IO uint32_t TOG; /**< TX Control, offset: 0x22C */
} TX_CONTROL2;
struct { /* offset: 0x230 */
__I uint32_t RW; /**< Status, offset: 0x230 */
__I uint32_t SET; /**< Status, offset: 0x234 */
__I uint32_t CLR; /**< Status, offset: 0x238 */
__I uint32_t TOG; /**< Status, offset: 0x23C */
} TX_STATUS0;
uint8_t RESERVED_3[3456];
struct { /* offset: 0xFC0 */
__IO uint32_t RW; /**< Spare Config, offset: 0xFC0 */
__IO uint32_t SET; /**< Spare Config, offset: 0xFC4 */
__IO uint32_t CLR; /**< Spare Config, offset: 0xFC8 */
__IO uint32_t TOG; /**< Spare Config, offset: 0xFCC */
} SPARE_CONFIG0;
uint8_t RESERVED_4[32];
struct { /* offset: 0xFF0 */
__I uint32_t RW; /**< Spare Status0, offset: 0xFF0 */
__I uint32_t SET; /**< Spare Status0, offset: 0xFF4 */
__I uint32_t CLR; /**< Spare Status0, offset: 0xFF8 */
__I uint32_t TOG; /**< Spare Status0, offset: 0xFFC */
} SPARE_STATUS0;
} HDMI_TX_BLK_CTL_Type;
/* ----------------------------------------------------------------------------
-- HDMI_TX_BLK_CTL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HDMI_TX_BLK_CTL_Register_Masks HDMI_TX_BLK_CTL Register Masks
* @{
*/
/*! @name RTX_GENERAL - HDMI_RTX_GENERAL CONFIG */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_MASK (0x1U)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_SHIFT (0U)
/*! DEBUG_LOCKOUT_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_DEBUG_LOCKOUT_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_MASK (0x30U)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_SHIFT (4U)
/*! HDCP_AXI_ADDR_EXTN - HDCP_AXI_ADDR_EXTN control
*/
#define HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_HDCP_AXI_ADDR_EXTN_MASK)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_MASK (0x100U)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_SHIFT (8U)
/*! LCDIF_AXI_LIMIT_EN - Enables the AXI Read Beat count limiter; the beat limit value is given by the 16b value LCDIF_AXI_BEAT_LIMIT
*/
#define HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_LCDIF_AXI_LIMIT_EN_MASK)
/*! @} */
/*! @name RTX_GENERAL_1 - HDMI_RTX_GENERAL CONFIG */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_MASK (0xFFFFU)
#define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_SHIFT (0U)
/*! LCDIF_AXI_BEAT_LIMIT - LCDIF_AXI_BEAT_LIMIT
*/
#define HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_SHIFT)) & HDMI_TX_BLK_CTL_RTX_GENERAL_1_LCDIF_AXI_BEAT_LIMIT_MASK)
/*! @} */
/*! @name RTX_RESET_CTL0 - HDMI_RTX_RESET_CTL0 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_MASK (0x1U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_SHIFT (0U)
/*! NOC_RESET_N - NOC_RESET_N control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_NOC_RESET_N_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_MASK (0x10U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_SHIFT (4U)
/*! LCDIF_ASYNC_RESET_N - LCDIF_ASYNC_RESET_N control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_ASYNC_RESET_N_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_MASK (0x20U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_SHIFT (5U)
/*! LCDIF_APB_RESET_N - LCDIF_APB_RESET_N control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_LCDIF_APB_RESET_N_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_MASK (0x40U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_SHIFT (6U)
/*! FDCC_RESETN - FDCC_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_MASK (0x80U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_SHIFT (7U)
/*! FDCC_HDMI_RESETN - FDCC_HDMI_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_FDCC_HDMI_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_MASK (0x400U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_SHIFT (10U)
/*! TX_RSTZ - TX_RSTZ control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_RSTZ_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_MASK (0x800U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_SHIFT (11U)
/*! TX_APBRSTZ - TX_APBRSTZ control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_APBRSTZ_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_MASK (0x1000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_SHIFT (12U)
/*! TX_PHY_PRESETN - TX_PHY_PRESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_PHY_PRESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_MASK (0x2000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_SHIFT (13U)
/*! TX_KSV_MEM_RESETN - KSV Mem reset control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_KSV_MEM_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_MASK (0x4000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_SHIFT (14U)
/*! TX_SEC_MEM_RESETN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_SEC_MEM_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_MASK (0x8000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_SHIFT (15U)
/*! HRV_MWR_RESETN - HRV_MWR_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_HRV_MWR_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_MASK (0x10000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_SHIFT (16U)
/*! IRQ_RESETN - IRQ_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_IRQ_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_MASK (0x40000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_SHIFT (18U)
/*! PAI_RESETN - PAI_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_PAI_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_MASK (0x100000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_SHIFT (20U)
/*! TX_TRNG_RESETN - TX_TRNG_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_TX_TRNG_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_MASK (0x400000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_SHIFT (22U)
/*! VID_LINK_SLV_RESETN - VID_LINK_SLV_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VID_LINK_SLV_RESETN_MASK)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_MASK (0x800000U)
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_SHIFT (23U)
/*! VSFD_RESETN - VSFD_RESETN control
*/
#define HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_RESET_CTL0_VSFD_RESETN_MASK)
/*! @} */
/*! @name RTX_CLK_CTL0 - HDMI_RTX_CLK_CTL0 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_MASK (0x1U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_SHIFT (0U)
/*! GLOBAL_APB_CLK_EN - GLOBAL_APB_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_APB_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_MASK (0x2U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_SHIFT (1U)
/*! GLOBAL_B_CLK_EN - GLOBAL_B_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_B_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_MASK (0x4U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_SHIFT (2U)
/*! GLOBAL_REF266M_CLK_EN - GLOBAL_REF266M_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_REF266M_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_MASK (0x8U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_SHIFT (3U)
/*! GLOBAL_XTAL27M_CLK_EN - GLOBAL_XTAL27M_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL27M_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_MASK (0x10U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_SHIFT (4U)
/*! GLOBAL_XTAL24M_CLK_EN - GLOBAL_XTAL24M_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL24M_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_MASK (0x20U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_SHIFT (5U)
/*! GLOBAL_XTAL32K_CLK_EN - GLOBAL_XTAL32K_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_XTAL32K_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_MASK (0x40U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_SHIFT (6U)
/*! GLOBAL_AUD_PLL_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_AUD_PLL_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_MASK (0x80U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_SHIFT (7U)
/*! GLOBAL_TX_PIX_CLK_EN - TX pix clk control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_GLOBAL_TX_PIX_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_MASK (0x100U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_SHIFT (8U)
/*! PD1_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_PD1_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_MASK (0x200U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_SHIFT (9U)
/*! IRQS_CLK_EN - clock control for the irq_steer block
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_IRQS_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_MASK (0x400U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_SHIFT (10U)
/*! NOC_HDMI_CLK_EN - clock enable for the NOC bus_clk enable
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDMI_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_MASK (0x800U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_SHIFT (11U)
/*! NOC_HDCP_CLK_EN - clock enable for the NOC hdcp_clk
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_NOC_HDCP_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_MASK (0x10000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_SHIFT (16U)
/*! LCDIF_APB_CLK_EN - clock enable for lcdif apb_clk input
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_APB_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_MASK (0x20000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_SHIFT (17U)
/*! LCDIF_B_CLK_EN - clock enable for lcdif bus_clk input
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_B_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_MASK (0x40000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_SHIFT (18U)
/*! LCDIF_PDI_CLK_EN - clock enable for lcdif pdi_clk input
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PDI_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_MASK (0x80000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_SHIFT (19U)
/*! LCDIF_PIX_CLK_EN - clock enable for lcdif pix_clk input
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_PIX_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_MASK (0x100000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_SHIFT (20U)
/*! LCDIF_SPU_CLK_EN - clock enable for lcdif spu_clk input
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL0_LCDIF_SPU_CLK_EN_MASK)
/*! @} */
/*! @name RTX_CLK_CTL1 - HDMI_RTX_CLK_CTL1 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_MASK (0x2U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_SHIFT (1U)
/*! FDCC_IHDMI_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_IHDMI_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_MASK (0x4U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_SHIFT (2U)
/*! FDCC_REF_CLK_EN - FDCC_REF_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_FDCC_REF_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_MASK (0x8U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_SHIFT (3U)
/*! HRV_MWR_APB_CLK_EN - HRV_MWR_APB_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_APB_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_MASK (0x10U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_SHIFT (4U)
/*! HRV_MWR_B_CLK_EN - HRV_MWR_B_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_B_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_MASK (0x20U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_SHIFT (5U)
/*! HRV_MWR_CEA_CLK_EN - HRV_MWR_CEA_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HRV_MWR_CEA_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_MASK (0x40U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_SHIFT (6U)
/*! VSFD_CEA_CLK_EN - VSFD_CEA_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_VSFD_CEA_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_MASK (0x100U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_SHIFT (8U)
/*! vpll_clk_sel - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_vpll_clk_sel_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_MASK (0x200U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_SHIFT (9U)
/*! fdcc_clk_sel - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_fdcc_clk_sel_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_MASK (0x400U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_SHIFT (10U)
/*! htxphy_clk_sel - htxphy_clk_sel control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_htxphy_clk_sel_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_MASK (0x800U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_SHIFT (11U)
/*! lcdif_clk_sel - lcdif_clk_sel control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_lcdif_clk_sel_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_MASK (0x1000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_SHIFT (12U)
/*! HTX_PIPE_CLK_SEL - HTX_PIPE_CLK_SEL control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_HTX_PIPE_CLK_SEL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_MASK (0x2000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_SHIFT (13U)
/*! TX_HPI_CLK_EN - TX_HPI_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_HPI_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_MASK (0x4000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_SHIFT (14U)
/*! TX_APB_CLK_EN - TX_APB_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_APB_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_MASK (0x8000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_SHIFT (15U)
/*! TX_CEC_CLK_EN - TX_CEC_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_CEC_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_MASK (0x10000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_SHIFT (16U)
/*! TX_ESM_CLK_EN - TX_ESM_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_ESM_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_MASK (0x20000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_SHIFT (17U)
/*! TX_GPA_CLK_EN - TX_GPA_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_GPA_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_MASK (0x40000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_SHIFT (18U)
/*! TX_PIXEL_CLK_EN - TX_PIXEL_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PIXEL_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_MASK (0x80000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_SHIFT (19U)
/*! TX_SFR_CLK_EN - TX_SFR_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SFR_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_MASK (0x100000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_SHIFT (20U)
/*! TX_SKP_CLK_EN - TX_SKP_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SKP_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_MASK (0x200000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_SHIFT (21U)
/*! TX_PREP_CLK_EN - TX_PREP_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PREP_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_MASK (0x400000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_SHIFT (22U)
/*! TX_PHY_APB_CLK_EN - TX_PHY_APB_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_APB_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_MASK (0x800000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_SHIFT (23U)
/*! TX_PHY_PIXEL_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_PIXEL_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_MASK (0x1000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_SHIFT (24U)
/*! TX_PHY_INT_CLK_EN - TX_PHY_INT_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_PHY_INT_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_MASK (0x2000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_SHIFT (25U)
/*! TX_SEC_MEM_CLK_EN - TX_SEC_MEM_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_SEC_MEM_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_MASK (0x4000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_SHIFT (26U)
/*! PAI_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_PAI_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_MASK (0x8000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_SHIFT (27U)
/*! TX_TRNG_SKP_CLK_EN - TX_TRNG_SKP_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_SKP_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_MASK (0x10000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_SHIFT (28U)
/*! TX_VID_LINK_PIX_CLK_EN - TX_VID_LINK_PIX_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_VID_LINK_PIX_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_MASK (0x20000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_SHIFT (29U)
/*! TX_MEM_266M_CLK_EN - RESERVED
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_MEM_266M_CLK_EN_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_MASK (0x40000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_SHIFT (30U)
/*! TX_TRNG_APB_CLK_EN - TX_TRNG_APB_CLK_EN control
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL1_TX_TRNG_APB_CLK_EN_MASK)
/*! @} */
/*! @name RTX_CLK_CTL2 - RTX_CLK_CTL2 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_MASK (0x3U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_SHIFT (0U)
/*! IRQS_CLK_CTL - Used to bypass the programmable clock controls for IRQ_STEER
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_IRQS_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_MASK (0xCU)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_SHIFT (2U)
/*! FDCC_APB_CLK_CTL - Used to bypass the programmable clock controls for FDCC apb clock
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_MASK (0x30U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_SHIFT (4U)
/*! FDCC_REF_CLK_CTL - Used to bypass the programmable clock controls for FDCC ref clock
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_FDCC_REF_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_MASK (0xC0U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_SHIFT (6U)
/*! HDMI_TX_HPI_CLK_CTL - Used to bypass the programmable clock controls for hpi_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_HPI_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_MASK (0x300U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_SHIFT (8U)
/*! HDMI_TX_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_MASK (0xC00U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_SHIFT (10U)
/*! HDMI_TX_CEC_CLK_CTL - Used to bypass the programmable clock controls for cec_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_CEC_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_MASK (0x3000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_SHIFT (12U)
/*! HDMI_TX_ESM_CLK_CTL - Used to bypass the programmable clock controls for esm_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_ESM_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_MASK (0xC000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_SHIFT (14U)
/*! HDMI_TX_GPA_CLK_CTL - Used to bypass the programmable clock controls for gpa_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_GPA_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_MASK (0x30000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_SHIFT (16U)
/*! HDMI_TX_PIX_CLK_CTL - Used to bypass the programmable clock controls for ipixel_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PIX_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_MASK (0xC0000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_SHIFT (18U)
/*! HDMI_TX_SFR_CLK_CTL - Used to bypass the programmable clock controls for sfr_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SFR_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_MASK (0x300000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_SHIFT (20U)
/*! HDMI_TX_SKP_CLK_CTL - Used to bypass the programmable clock controls for skp_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_SKP_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_MASK (0xC00000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_SHIFT (22U)
/*! HDMI_TX_PREP_CLK_CTL - Used to bypass the programmable clock controls for prep_clk input of HDMI TX
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_HDMI_TX_PREP_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_MASK (0x3000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_SHIFT (24U)
/*! TX_PHY_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of the HDMI TX PHY
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_MASK (0xC000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_SHIFT (26U)
/*! TX_PHY_INT_CLK_CTL - Used to bypass the programmable clock controls for int_clk input of the HDMI TX PHY
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_TX_PHY_INT_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_MASK (0x30000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_SHIFT (28U)
/*! PAI_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of HTX_PAI
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_MASK (0xC0000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_SHIFT (30U)
/*! PAI_AUD_CLK_CTL - Used to bypass the programmable clock controls for aud_clk input of HTX_PAI
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL2_PAI_AUD_CLK_CTL_MASK)
/*! @} */
/*! @name RTX_CLK_CTL3 - RTX_CLK_CTL3 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_MASK (0x3U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_SHIFT (0U)
/*! TRNG_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of TRNG
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_MASK (0xCU)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_SHIFT (2U)
/*! TRNG_SKP_CLK_CTL - Used to bypass the programmable clock controls for skp_clk input of TRNG
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_TRNG_SKP_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_MASK (0x30U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_SHIFT (4U)
/*! VID_SLV_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of video link slave
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_MASK (0xC0U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_SHIFT (6U)
/*! VID_SLV_PIX_CLK_CTL - Used to bypass the programmable clock controls for pix_clk input of video link slave
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VID_SLV_PIX_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_MASK (0x300U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_SHIFT (8U)
/*! HRV_MWR_B_CLK_CTL - Used to bypass the programmable clock controls for b_clk input of HRV_MWR
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_B_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_MASK (0xC00U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_SHIFT (10U)
/*! HRV_MWR_CEA_CLK_CTL - Used to bypass the programmable clock controls for cea_clk input of HRV_MWR
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_HRV_MWR_CEA_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_MASK (0x3000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_SHIFT (12U)
/*! VSFD_HTX_APB_CLK_CTL - Used to bypass the programmable clock controls for the apb clk input of VSFD (including portions of HRV_MWR logic)
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_MASK (0xC000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_SHIFT (14U)
/*! VSFD_HTX_P_CLK_CTL - Used to bypass the programmable clock controls for the htx_p_clk input used
* in VSFD (including portions of HRV_MWR logic)
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_HTX_P_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_MASK (0x30000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_SHIFT (16U)
/*! VSFD_CEA_CLK_CTL - Used to bypass the programmable clock controls for cea_clk input of vsfd
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_VSFD_CEA_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_MASK (0xC0000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_SHIFT (18U)
/*! LCDIF_APB_CLK_CTL - Used to bypass the programmable clock controls for apb_clk input of LCDIF
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_APB_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_MASK (0x300000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_SHIFT (20U)
/*! LCDIF_B_CLK_CTL - Used to bypass the programmable clock controls for b_clk input of LCDIF
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_B_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_MASK (0xC00000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_SHIFT (22U)
/*! LCDIF_PDI_CLK_CTL - Used to bypass the programmable clock controls for pdi_clk input of LCDIF
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PDI_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_MASK (0x3000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_SHIFT (24U)
/*! LCDIF_PIX_CLK_CTL - Used to bypass the programmable clock controls for pix_clk input of LCDIF
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_PIX_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_MASK (0xC000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_SHIFT (26U)
/*! LCDIF_SPU_CLK_CTL - Used to bypass the programmable clock controls for spu_clk input of LCDIF
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_LCDIF_SPU_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_MASK (0x30000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_SHIFT (28U)
/*! NOC_HDCP_CLK_CTL - Used to bypass the programmable clock controls for hdcp clock input of the HDMI NOC
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_HDCP_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_MASK (0xC0000000U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_SHIFT (30U)
/*! NOC_B_CLK_CTL - Used to bypass the programmable clock controls for bus clock input of the HDMI NOC
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL3_NOC_B_CLK_CTL_MASK)
/*! @} */
/*! @name RTX_CLK_CTL4 - RTX_CLK_CTL4 */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_MASK (0x3U)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_SHIFT (0U)
/*! REVOCMEM_CLK_CTL - Used to bypass the request based clock gating on revocmem
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL4_REVOCMEM_CLK_CTL_MASK)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_MASK (0xCU)
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_SHIFT (2U)
/*! TX_SEC_MEM_CLK_CTL - Used to bypass the request based clock gating on tx_sec_mem
*/
#define HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_SHIFT)) & HDMI_TX_BLK_CTL_RTX_CLK_CTL4_TX_SEC_MEM_CLK_CTL_MASK)
/*! @} */
/*! @name RTX_IRQ_MASK - HDMI_RX_Control */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_MASK (0x1000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_SHIFT (12U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_MASK (0x2000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_SHIFT (13U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_HPD_LOW2HIGH_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_MASK (0x4000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_SHIFT (14U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_MASK (0x8000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_SHIFT (15U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASK_TX_READY_LOW2HIGH_MASK)
/*! @} */
/*! @name RTX_IRQ_MASKED_STATUS - HDMI_TX Masked Interrupt status */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_MASK (0x1000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_SHIFT (12U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_MASK (0x2000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_SHIFT (13U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_HPD_LOW2HIGH_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_MASK (0x4000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_SHIFT (14U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_MASK (0x8000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_SHIFT (15U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_MASKED_STATUS_TX_READY_LOW2HIGH_MASK)
/*! @} */
/*! @name RTX_IRQ_NONMASK_STATUS - HDMI_RX_Control */
/*! @{ */
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_MASK (0x1000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_SHIFT (12U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_MASK (0x2000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_SHIFT (13U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_HPD_LOW2HIGH_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_MASK (0x4000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_SHIFT (14U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_HIGH2LOW_MASK)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_MASK (0x8000U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_SHIFT (15U)
#define HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_SHIFT)) & HDMI_TX_BLK_CTL_RTX_IRQ_NONMASK_STATUS_TX_READY_LOW2HIGH_MASK)
/*! @} */
/*! @name TX_CONTROL0 - Miscellaneous Controls for the HDMI TX Controller */
/*! @{ */
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_MASK (0x1U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_SHIFT (0U)
/*! TX_KEY_MEM_WR_LOCK - TX_KEY_MEM_WR_LOCK control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_KEY_MEM_WR_LOCK_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_MASK (0x2U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_SHIFT (1U)
/*! TX_CEC_EN - TX_CEC_EN control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CEC_EN_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_MASK (0x4U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_SHIFT (2U)
/*! TX_SKP_KEYS_VALID - RESERVED
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_SKP_KEYS_VALID_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_MASK (0x8U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_SHIFT (3U)
/*! TX_PHY_PDOWN - TX_PHY_PDOWN control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_PHY_PDOWN_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_MASK (0x1F0U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_SHIFT (4U)
/*! TX_CTL_CLK_DIV_CNT - RESERVED
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TX_CTL_CLK_DIV_CNT_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_MASK (0x7000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_SHIFT (12U)
/*! LCDIF_NOC_HURRY - LCDIF_NOC_HURRY
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_LCDIF_NOC_HURRY_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_MASK (0x70000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_SHIFT (16U)
/*! HRV_MWR_NOC_HURRY - HRV_MWR_NOC_HURRY
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_HRV_MWR_NOC_HURRY_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_MASK (0x100000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_SHIFT (20U)
/*! HPD_FILT_BYP - HPD_FILT_BYP
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_HPD_FILT_BYP_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_MASK (0x200000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_SHIFT (21U)
/*! CECIN_FILT_BYP - CECIN_FILT_BYP
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_CECIN_FILT_BYP_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_MASK (0x400000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_SHIFT (22U)
/*! DDC_SCLIN_FILT_BYP - DDC_SCLIN_FILT_BYP
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SCLIN_FILT_BYP_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_MASK (0x800000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_SHIFT (23U)
/*! DDC_SDAIN_FILT_BYP - DDC_SDAIN_FILT_BYP
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_DDC_SDAIN_FILT_BYP_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_MASK (0x1000000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_SHIFT (24U)
/*! TRNG_LOCK - TRNG_LOCK control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL0_TRNG_LOCK_MASK)
/*! @} */
/*! @name TX_CONTROL2 - TX Control */
/*! @{ */
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_MASK (0x3FF0U)
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_SHIFT (4U)
/*! TX_PREPCLK_TOT_COUNT - TX_PREPCLK_TOT_COUNT control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_TOT_COUNT_MASK)
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_MASK (0x3FF0000U)
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_SHIFT (16U)
/*! TX_PREPCLK_ACTCYC_COUNT - TX_PREPCLK_ACTCYC_COUNT control
*/
#define HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_SHIFT)) & HDMI_TX_BLK_CTL_TX_CONTROL2_TX_PREPCLK_ACTCYC_COUNT_MASK)
/*! @} */
/*! @name TX_STATUS0 - Status */
/*! @{ */
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_MASK (0x1FU)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_SHIFT (0U)
/*! TX_PHY_AFC_CODE - TX_PHY_AFC_CODE status
*/
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_AFC_CODE_MASK)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_MASK (0x20U)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_SHIFT (5U)
/*! TX_PHY_CLK_RDY - TX_PHY_CLK_RDY status
*/
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_CLK_RDY_MASK)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_MASK (0x40U)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_SHIFT (6U)
/*! TX_PHY_RDY - TX_PHY_RDY status
*/
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_RDY_MASK)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_MASK (0x80U)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_SHIFT (7U)
/*! TX_PHY_PLL_LOCK - TX_PHY_PLL_LOCK status
*/
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_PHY_PLL_LOCK_MASK)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_MASK (0x100U)
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_SHIFT (8U)
/*! TX_HPD_STATUS - TX_HPD_STATUS status
*/
#define HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_SHIFT)) & HDMI_TX_BLK_CTL_TX_STATUS0_TX_HPD_STATUS_MASK)
/*! @} */
/*! @name SPARE_CONFIG0 - Spare Config */
/*! @{ */
#define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_MASK (0xFFFFFFFFU)
#define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_SHIFT (0U)
#define HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_SHIFT)) & HDMI_TX_BLK_CTL_SPARE_CONFIG0_SPARE_CONFIG_MASK)
/*! @} */
/*! @name SPARE_STATUS0 - Spare Status0 */
/*! @{ */
#define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK (0xFFFFFFFFU)
#define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT (0U)
/*! SPARE_STATUS - SPARE Control
*/
#define HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_SHIFT)) & HDMI_TX_BLK_CTL_SPARE_STATUS0_SPARE_STATUS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HDMI_TX_BLK_CTL_Register_Masks */
/* HDMI_TX_BLK_CTL - Peripheral instance base addresses */
/** Peripheral HDMI_TX_BLK_CTRL base address */
#define HDMI_TX_BLK_CTRL_BASE (0x32FC0000u)
/** Peripheral HDMI_TX_BLK_CTRL base pointer */
#define HDMI_TX_BLK_CTRL ((HDMI_TX_BLK_CTL_Type *)HDMI_TX_BLK_CTRL_BASE)
/** Array initializer of HDMI_TX_BLK_CTL peripheral base addresses */
#define HDMI_TX_BLK_CTL_BASE_ADDRS { HDMI_TX_BLK_CTRL_BASE }
/** Array initializer of HDMI_TX_BLK_CTL peripheral base pointers */
#define HDMI_TX_BLK_CTL_BASE_PTRS { HDMI_TX_BLK_CTRL }
/*!
* @}
*/ /* end of group HDMI_TX_BLK_CTL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HSIO_BLK_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HSIO_BLK_CTRL_Peripheral_Access_Layer HSIO_BLK_CTRL Peripheral Access Layer
* @{
*/
/** HSIO_BLK_CTRL - Register Layout Typedef */
typedef struct {
__IO uint32_t GPR_REG0; /**< Clock select reset and debug info select, offset: 0x0 */
__I uint32_t GPR_REG1; /**< PCIE controller status, offset: 0x4 */
__IO uint32_t GPR_REG2; /**< PLL configuration 0, offset: 0x8 */
__IO uint32_t GPR_REG3; /**< PLL configuration 1, offset: 0xC */
__IO uint32_t GPR_REG4; /**< PCIE PME message and error detect register, offset: 0x10 */
__IO uint32_t GPR_REG5; /**< PCIE PME message and error detect interrupt enable register, offset: 0x14 */
__IO uint32_t GPR_REG6; /**< PCIE PME message and error detect interrupt detect disable register, offset: 0x18 */
__IO uint32_t GPR_REG7; /**< USB1 beat limit and enable, offset: 0x1C */
__IO uint32_t GPR_REG8; /**< USB2 beat limit and enable, offset: 0x20 */
__IO uint32_t GPR_REG9; /**< PCIE beat limit and enable, offset: 0x24 */
uint8_t RESERVED_0[216];
__IO uint32_t USB1_WAKEUP_CTRL; /**< Register for USB1 wakeup, offset: 0x100 */
__I uint32_t USB1_WAKEUP_STATUS; /**< Status of USB1 wakeup, offset: 0x104 */
__IO uint32_t USB2_WAKEUP_CTRL; /**< Register for USB2 wakeup, offset: 0x108 */
__I uint32_t USB2_WAKEUP_STATUS; /**< Status of USB2 wakeup, offset: 0x10C */
} HSIO_BLK_CTRL_Type;
/* ----------------------------------------------------------------------------
-- HSIO_BLK_CTRL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HSIO_BLK_CTRL_Register_Masks HSIO_BLK_CTRL Register Masks
* @{
*/
/*! @name GPR_REG0 - Clock select reset and debug info select */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_MASK (0x1U)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_SHIFT (0U)
/*! PCIE_CLOCK_MODULE_EN - PCIE related clock enable
*/
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_CLOCK_MODULE_EN_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_MASK (0x2U)
#define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_SHIFT (1U)
/*! USB_CLOCK_MODULE_EN - USB related clock enable
*/
#define HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_USB_CLOCK_MODULE_EN_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_MASK (0xCU)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_SHIFT (2U)
/*! PCIE_USB_DEBUG_INFO_SEL - PCIE USB debug information selection
*/
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_USB_DEBUG_INFO_SEL_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_MASK (0x10U)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_SHIFT (4U)
/*! PCIE_PHY_APB_RESETN_INTERNAL - PCIE PHY APB interface reset
*/
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_APB_RESETN_INTERNAL_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_MASK (0x20U)
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_SHIFT (5U)
/*! PCIE_PHY_INIT_RESETN_INTERNAL - PCIE PHY init reset
*/
#define HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_PCIE_PHY_INIT_RESETN_INTERNAL_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK (0x40U)
#define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT (6U)
/*! USB_PHY_REF_CLK_SEL - USB PHY ref clock selection
* 0b0..24Mhz exteral osc
* 0b1..100Mhz high performace PLL
*/
#define HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_USB_PHY_REF_CLK_SEL_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_CFG_READY_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG0_CFG_READY_SHIFT (7U)
/*! CFG_READY - Configuration ready
*/
#define HSIO_BLK_CTRL_GPR_REG0_CFG_READY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_CFG_READY_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_CFG_READY_MASK)
#define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_MASK (0x100U)
#define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_SHIFT (8U)
/*! CRS_CLEAR - Clear CSR interrupt
*/
#define HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_SHIFT)) & HSIO_BLK_CTRL_GPR_REG0_CRS_CLEAR_MASK)
/*! @} */
/*! @name GPR_REG1 - PCIE controller status */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_MASK (0x1U)
#define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_SHIFT (0U)
/*! PM_EN_CORE_CLK - pm_en_core_clk pin status of pcie ctrl
*/
#define HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PM_EN_CORE_CLK_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_MASK (0x7EU)
#define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_SHIFT (1U)
/*! SMLH_LTSSM_STATE - PCIE link state
*/
#define HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_SMLH_LTSSM_STATE_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_SHIFT (7U)
/*! PCIE_CTRL_PM_LINKST_IN_L1SUB - PCIE ctrl link in l1sub state
*/
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1SUB_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_MASK (0x100U)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_SHIFT (8U)
/*! PCIE_CTRL_PM_LINKST_IN_L1 - PCIE ctrl link in l1 state
*/
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L1_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_MASK (0x200U)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_SHIFT (9U)
/*! PCIE_CTRL_PM_LINKST_IN_L0S - PCIE ctrl link in l0s state
*/
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_LINKST_IN_L0S_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_MASK (0x1C00U)
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_SHIFT (10U)
/*! PCIE_CTRL_PM_DSTATE - PCIE ctrl's pm dstate
*/
#define HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PCIE_CTRL_PM_DSTATE_MASK)
#define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_MASK (0x2000U)
#define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_SHIFT (13U)
/*! PLL_LOCK - High performance PLL lock status
*/
#define HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_SHIFT)) & HSIO_BLK_CTRL_GPR_REG1_PLL_LOCK_MASK)
/*! @} */
/*! @name GPR_REG2 - PLL configuration 0 */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG2_P_PLL_MASK (0x3FU)
#define HSIO_BLK_CTRL_GPR_REG2_P_PLL_SHIFT (0U)
/*! P_PLL - P pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_P_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_P_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_P_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_M_PLL_MASK (0xFFC0U)
#define HSIO_BLK_CTRL_GPR_REG2_M_PLL_SHIFT (6U)
/*! M_PLL - M pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_M_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_M_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_M_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_S_PLL_MASK (0x70000U)
#define HSIO_BLK_CTRL_GPR_REG2_S_PLL_SHIFT (16U)
/*! S_PLL - S pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_S_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_S_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_S_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_MASK (0x180000U)
#define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_SHIFT (19U)
/*! ICP_PLL - ICP pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_ICP_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_ICP_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_MASK (0x200000U)
#define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_SHIFT (21U)
/*! BYPASS_PLL - Bypass pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_BYPASS_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_MASK (0x400000U)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_SHIFT (22U)
/*! LOCK_EN_PLL - locken pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_EN_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_MASK (0x1800000U)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_SHIFT (23U)
/*! LOCK_CON_IN_PLL - Lock con in pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_IN_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_MASK (0x6000000U)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_SHIFT (25U)
/*! LOCK_CON_OUT_PLL - Lock con input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_OUT_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_MASK (0x18000000U)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_SHIFT (27U)
/*! LOCK_CON_DLY_PLL - Lock con delay input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_DLY_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_MASK (0x60000000U)
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_SHIFT (29U)
/*! LOCK_CON_REV_PLL - Lock con rev pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_LOCK_CON_REV_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_MASK (0x80000000U)
#define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_SHIFT (31U)
/*! AFC_ENB_PLL - AFC_ENB input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG2_AFC_ENB_PLL_MASK)
/*! @} */
/*! @name GPR_REG3 - PLL configuration 1 */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_MASK (0x1FU)
#define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_SHIFT (0U)
/*! EXTAFC_PLL - Extafc pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_EXTAFC_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_MASK (0x20U)
#define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_SHIFT (5U)
/*! FEED_EN_PLL - Feed en pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FEED_EN_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_MASK (0x40U)
#define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_SHIFT (6U)
/*! FSEL_PLL - FSEL pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FSEL_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_SHIFT (7U)
/*! AFCINIT_SEL_PLL - AFCINT SEL input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_AFCINIT_SEL_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_MASK (0x100U)
#define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_SHIFT (8U)
/*! FOUT_MASK_PLL - FOUT MASK pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_FOUT_MASK_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_MASK (0x200U)
#define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_SHIFT (9U)
/*! VCO_BOOST_PLL - VCO BOOST pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_VCO_BOOST_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_MASK (0x400U)
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_SHIFT (10U)
/*! PBIAS_CTRL_EN_PLL - PBIAS CTRL EN pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_EN_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_MASK (0x800U)
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_SHIFT (11U)
/*! PBIAS_CTRL_PLL - PBIAS CTRL pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PBIAS_CTRL_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_MASK (0x1000U)
#define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_SHIFT (12U)
/*! LRD_EN_PLL - LRD EN pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_LRD_EN_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_MASK (0x1E000U)
#define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_SHIFT (13U)
/*! RSEL_PLL - RSEL pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_RSEL_PLL_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_MASK (0x20000U)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_SHIFT (17U)
/*! PLL_CKE - PLL cke pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_PLL_CKE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_CKE_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_MASK (0x40000U)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_SHIFT (18U)
/*! PLL_EXT_BYPASS - PLL ext bypass pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_EXT_BYPASS_MASK)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_MASK (0x80000000U)
#define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_SHIFT (31U)
/*! PLL_RESETB - reset pin input of high performance PLL
*/
#define HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_SHIFT)) & HSIO_BLK_CTRL_GPR_REG3_PLL_RESETB_MASK)
/*! @} */
/*! @name GPR_REG4 - PCIE PME message and error detect register */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG4_LUD_MASK (0x1U)
#define HSIO_BLK_CTRL_GPR_REG4_LUD_SHIFT (0U)
/*! LUD - Indicates a link up was detected
*/
#define HSIO_BLK_CTRL_GPR_REG4_LUD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_LUD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_LUD_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_LDD_MASK (0x2U)
#define HSIO_BLK_CTRL_GPR_REG4_LDD_SHIFT (1U)
/*! LDD - Indicates a link down was detected
*/
#define HSIO_BLK_CTRL_GPR_REG4_LDD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_LDD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_LDD_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_HRD_MASK (0x4U)
#define HSIO_BLK_CTRL_GPR_REG4_HRD_SHIFT (2U)
/*! HRD - Indicates a hot reset was detected
*/
#define HSIO_BLK_CTRL_GPR_REG4_HRD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_HRD_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_HRD_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_PTO_MASK (0x8U)
#define HSIO_BLK_CTRL_GPR_REG4_PTO_SHIFT (3U)
/*! PTO - Indicates that PME turn off was detected
*/
#define HSIO_BLK_CTRL_GPR_REG4_PTO(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PTO_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PTO_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_UREP_MASK (0x10U)
#define HSIO_BLK_CTRL_GPR_REG4_UREP_SHIFT (4U)
/*! UREP - Indicates an unsupported request completion was detected
*/
#define HSIO_BLK_CTRL_GPR_REG4_UREP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_UREP_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_UREP_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_CDNSC_MASK (0x20U)
#define HSIO_BLK_CTRL_GPR_REG4_CDNSC_SHIFT (5U)
/*! CDNSC - Completion with data not succsessful was detected.
*/
#define HSIO_BLK_CTRL_GPR_REG4_CDNSC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_CDNSC_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_CDNSC_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_PCAC_MASK (0x40U)
#define HSIO_BLK_CTRL_GPR_REG4_PCAC_SHIFT (6U)
/*! PCAC - Completer abort was detected.
*/
#define HSIO_BLK_CTRL_GPR_REG4_PCAC(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PCAC_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PCAC_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_PCT_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG4_PCT_SHIFT (7U)
/*! PCT - Indicates completion timeout
*/
#define HSIO_BLK_CTRL_GPR_REG4_PCT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_PCT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_PCT_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_ME_MASK (0x100U)
#define HSIO_BLK_CTRL_GPR_REG4_ME_SHIFT (8U)
/*! ME - Indicates Multiple errors of same type. If any of the detectable errors in PEX_ERR_DET
* register is detected more than one time the ME bit will be set
*/
#define HSIO_BLK_CTRL_GPR_REG4_ME(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_ME_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_ME_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_INTE_MASK (0x40000000U)
#define HSIO_BLK_CTRL_GPR_REG4_INTE_SHIFT (30U)
/*! INTE - Per PF dependent error interrupt is pending.
*/
#define HSIO_BLK_CTRL_GPR_REG4_INTE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_INTE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_INTE_MASK)
#define HSIO_BLK_CTRL_GPR_REG4_INTM_MASK (0x80000000U)
#define HSIO_BLK_CTRL_GPR_REG4_INTM_SHIFT (31U)
/*! INTM - Per PF dependent message interrupt is pending
*/
#define HSIO_BLK_CTRL_GPR_REG4_INTM(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG4_INTM_SHIFT)) & HSIO_BLK_CTRL_GPR_REG4_INTM_MASK)
/*! @} */
/*! @name GPR_REG5 - PCIE PME message and error detect interrupt enable register */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG5_LUD_IE_MASK (0x1U)
#define HSIO_BLK_CTRL_GPR_REG5_LUD_IE_SHIFT (0U)
/*! LUD_IE - Link up detect interrupt enable
*/
#define HSIO_BLK_CTRL_GPR_REG5_LUD_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_LUD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_LUD_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_LDD_IE_MASK (0x2U)
#define HSIO_BLK_CTRL_GPR_REG5_LDD_IE_SHIFT (1U)
/*! LDD_IE - Link down detect interrupt enable
*/
#define HSIO_BLK_CTRL_GPR_REG5_LDD_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_LDD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_LDD_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_HRD_IE_MASK (0x4U)
#define HSIO_BLK_CTRL_GPR_REG5_HRD_IE_SHIFT (2U)
/*! HRD_IE - Hot reset detect interrupt enable.
*/
#define HSIO_BLK_CTRL_GPR_REG5_HRD_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_HRD_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_HRD_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_PTO_IE_MASK (0x8U)
#define HSIO_BLK_CTRL_GPR_REG5_PTO_IE_SHIFT (3U)
/*! PTO_IE - PME turn off detect interrupt enable
*/
#define HSIO_BLK_CTRL_GPR_REG5_PTO_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PTO_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PTO_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_UREP_IE_MASK (0x10U)
#define HSIO_BLK_CTRL_GPR_REG5_UREP_IE_SHIFT (4U)
/*! UREP_IE - Unsupported request in EP mode interrupt enable.
*/
#define HSIO_BLK_CTRL_GPR_REG5_UREP_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_UREP_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_UREP_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_MASK (0x20U)
#define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_SHIFT (5U)
/*! CDNSC_IE - Completion with data not succsessful interrupt enable
*/
#define HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_CDNSC_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_MASK (0x40U)
#define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_SHIFT (6U)
/*! PCAC_IE - Completer abort interrupt enable.
*/
#define HSIO_BLK_CTRL_GPR_REG5_PCAC_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PCAC_IE_MASK)
#define HSIO_BLK_CTRL_GPR_REG5_PCT_IE_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG5_PCT_IE_SHIFT (7U)
/*! PCT_IE - completion timeout interrupt enable
*/
#define HSIO_BLK_CTRL_GPR_REG5_PCT_IE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG5_PCT_IE_SHIFT)) & HSIO_BLK_CTRL_GPR_REG5_PCT_IE_MASK)
/*! @} */
/*! @name GPR_REG6 - PCIE PME message and error detect interrupt detect disable register */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_MASK (0x1U)
#define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_SHIFT (0U)
/*! LUD_DIS - Link up detect disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_LUD_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_LUD_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_MASK (0x2U)
#define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_SHIFT (1U)
/*! LDD_DIS - Link down detect disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_LDD_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_LDD_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_MASK (0x4U)
#define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_SHIFT (2U)
/*! HRD_DIS - Hot reset detect disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_HRD_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_HRD_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_MASK (0x8U)
#define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_SHIFT (3U)
/*! PTO_DIS - PME turn off detect disabled.
*/
#define HSIO_BLK_CTRL_GPR_REG6_PTO_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PTO_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_MASK (0x10U)
#define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_SHIFT (4U)
/*! UREP_DIS - Unsupported request in EP mode detection disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_UREP_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_UREP_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_MASK (0x20U)
#define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_SHIFT (5U)
/*! CDNSC_DIS - Completion with data not succsessful detection disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_CDNSC_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_MASK (0x40U)
#define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_SHIFT (6U)
/*! PCAC_DIS - Completer abort detection disable.
*/
#define HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PCAC_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_MASK (0x80U)
#define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_SHIFT (7U)
/*! PCT_DIS - completion detection disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_PCT_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_PCT_DIS_MASK)
#define HSIO_BLK_CTRL_GPR_REG6_ME_DIS_MASK (0x100U)
#define HSIO_BLK_CTRL_GPR_REG6_ME_DIS_SHIFT (8U)
/*! ME_DIS - Multiple errors of same type detection disable
*/
#define HSIO_BLK_CTRL_GPR_REG6_ME_DIS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG6_ME_DIS_SHIFT)) & HSIO_BLK_CTRL_GPR_REG6_ME_DIS_MASK)
/*! @} */
/*! @name GPR_REG7 - USB1 beat limit and enable */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_MASK (0xFFFFU)
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_SHIFT (0U)
/*! USB1_BEAT_LIMIT - USB1 beat limit number
*/
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_MASK)
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_MASK (0x10000U)
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_SHIFT (16U)
/*! USB1_BEAT_LIMIT_EN - USB1 beat limit enable
*/
#define HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG7_USB1_BEAT_LIMIT_EN_MASK)
/*! @} */
/*! @name GPR_REG8 - USB2 beat limit and enable */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_MASK (0xFFFFU)
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_SHIFT (0U)
/*! USB2_BEAT_LIMIT - USB2 beat limit number
*/
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_MASK)
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_MASK (0x10000U)
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_SHIFT (16U)
/*! USB2_BEAT_LIMIT_EN - USB2 beat limit enable
*/
#define HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG8_USB2_BEAT_LIMIT_EN_MASK)
/*! @} */
/*! @name GPR_REG9 - PCIE beat limit and enable */
/*! @{ */
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_MASK (0xFFFFU)
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_SHIFT (0U)
/*! PCIE_BEAT_LIMIT - PCIE beat limit number
*/
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_SHIFT)) & HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_MASK)
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_MASK (0x10000U)
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_SHIFT (16U)
/*! PCIE_BEAT_LIMIT_EN - PCIE beat limit enable
*/
#define HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_SHIFT)) & HSIO_BLK_CTRL_GPR_REG9_PCIE_BEAT_LIMIT_EN_MASK)
/*! @} */
/*! @name USB1_WAKEUP_CTRL - Register for USB1 wakeup */
/*! @{ */
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U)
/*! OTG_WKDPDMCHG_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U)
/*! OTG_VBUS_WAKE_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U)
/*! OTG_ID_WAKEUP_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U)
/*! OTG_U3_WAKE_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U)
/*! OTG_VBUS_SOURCE_SEL
* 0b0..select vbus_valid
* 0b1..select sessvld
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U)
/*! AUTORESUME_EN
* 0b1..enable.
* 0b0..disable.
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U)
/*! LOWSPEED_EN
* 0b1..lowspeed
* 0b0..full/high speed
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_LOWSPEED_EN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_PHY_BYPASSSEL_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK)
/*! @} */
/*! @name USB1_WAKEUP_STATUS - Status of USB1 wakeup */
/*! @{ */
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U)
/*! OTG_HOST_MODE
* 0b1..host mode
* 0b0..device mode
*/
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_HOST_MODE_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U)
#define HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB1_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK)
/*! @} */
/*! @name USB2_WAKEUP_CTRL - Register for USB2 wakeup */
/*! @{ */
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK (0x1U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT (0U)
/*! OTG_WKDPDMCHG_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WKDPDMCHG_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK (0x2U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT (1U)
/*! OTG_VBUS_WAKE_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_WAKE_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK (0x4U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT (2U)
/*! OTG_ID_WAKEUP_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_ID_WAKEUP_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK (0x8U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT (3U)
/*! OTG_U3_WAKE_EN
* 0b1..enable
* 0b0..disable
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_U3_WAKE_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK (0x10U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT (4U)
/*! OTG_VBUS_SOURCE_SEL
* 0b0..select vbus_valid
* 0b1..select sessvld
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_VBUS_SOURCE_SEL_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK (0x20U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT (5U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_CONN_WAKEUP_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK (0x100U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT (8U)
/*! AUTORESUME_EN
* 0b1..enable.
* 0b0..disable.
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK (0x200U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT (9U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_DATADLY_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK (0x400U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT (10U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_AUTORESUME_ENDLY_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK (0x800U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT (11U)
/*! LOWSPEED_EN
* 0b1..lowspeed
* 0b0..full/high speed
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_LOWSPEED_EN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK (0x1000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT (12U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMDATA_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK (0x2000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT (13U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDMEN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK (0x4000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT (14U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPDATA_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK (0x8000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT (15U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSDPEN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK (0x10000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT (16U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_PHY_BYPASSSEL_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK (0x80000000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT (31U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_CTRL_OTG_WAKE_ENABLE_MASK)
/*! @} */
/*! @name USB2_WAKEUP_STATUS - Status of USB2 wakeup */
/*! @{ */
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK (0x1U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT (0U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_DP_DM_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK (0x2U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT (1U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_VBUS_SESSVLD_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK (0x4U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT (2U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_ID_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK (0x8U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT (3U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_U3_WAKEUP_INTERRUP_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK (0x10U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT (4U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_0_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK (0x20U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT (5U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_LINESTATE0_1_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK (0x40U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT (6U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_IDDIG0_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK (0x80U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT (7U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_VBUSVALID0_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK (0x100U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT (8U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_PHY_OTGSESSVLD0_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK (0x200U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT (9U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE_RXELECIDLE_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK (0x400U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT (10U)
/*! OTG_HOST_MODE
* 0b1..host mode
* 0b0..device mode
*/
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_HOST_MODE_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK (0x1800U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT (11U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_PIPE3_POWERDOWN_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK (0x2000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT (13U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_CONN_WAKEUP_INTERRUPT_MASK)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK (0x80000000U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT (31U)
#define HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_SHIFT)) & HSIO_BLK_CTRL_USB2_WAKEUP_STATUS_OTG_WAKEUP_INTERRUPT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HSIO_BLK_CTRL_Register_Masks */
/* HSIO_BLK_CTRL - Peripheral instance base addresses */
/** Peripheral HSIO_BLK_CTRL base address */
#define HSIO_BLK_CTRL_BASE (0x32F10000u)
/** Peripheral HSIO_BLK_CTRL base pointer */
#define HSIO_BLK_CTRL ((HSIO_BLK_CTRL_Type *)HSIO_BLK_CTRL_BASE)
/** Array initializer of HSIO_BLK_CTRL peripheral base addresses */
#define HSIO_BLK_CTRL_BASE_ADDRS { HSIO_BLK_CTRL_BASE }
/** Array initializer of HSIO_BLK_CTRL peripheral base pointers */
#define HSIO_BLK_CTRL_BASE_PTRS { HSIO_BLK_CTRL }
/*!
* @}
*/ /* end of group HSIO_BLK_CTRL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HTX_PAI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HTX_PAI_Peripheral_Access_Layer HTX_PAI Peripheral Access Layer
* @{
*/
/** HTX_PAI - Register Layout Typedef */
typedef struct {
__IO uint32_t HTX_PAI_CTRL; /**< HTX PAI Control, offset: 0x0 */
__IO uint32_t HTX_PAI_CTRL_EXT; /**< HTX PAI Control Extended, offset: 0x4 */
__IO uint32_t HTX_PAI_FIELD_CTRL; /**< HTX PAI Field Control, offset: 0x8 */
__I uint32_t HTX_PAI_STAT; /**< HTX PAI Status, offset: 0xC */
__IO uint32_t HTX_PAI_IRQ_NOMASK; /**< HTX PAI Nonmasked Interrupt Flags, offset: 0x10 */
__IO uint32_t HTX_PAI_IRQ_MASKED; /**< HTX PAI Masked Interrupt Flags, offset: 0x14 */
__IO uint32_t HTX_PAI_IRQ_MASK; /**< HTX PAI IRQ Masks, offset: 0x18 */
} HTX_PAI_Type;
/* ----------------------------------------------------------------------------
-- HTX_PAI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HTX_PAI_Register_Masks HTX_PAI Register Masks
* @{
*/
/*! @name HTX_PAI_CTRL - HTX PAI Control */
/*! @{ */
#define HTX_PAI_HTX_PAI_CTRL_ENABLE_MASK (0x1U)
#define HTX_PAI_HTX_PAI_CTRL_ENABLE_SHIFT (0U)
/*! ENABLE - HTX PAI Enable
*/
#define HTX_PAI_HTX_PAI_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_ENABLE_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_ENABLE_MASK)
/*! @} */
/*! @name HTX_PAI_CTRL_EXT - HTX PAI Control Extended */
/*! @{ */
#define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_MASK (0x1U)
#define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_SHIFT (0U)
/*! SOURCE - HTX PAI Source Select
* 0b0..Normal operation. Data input from the audio subsystem.
* 0b1..Low latency bypass mode. Data input from RASFD.
*/
#define HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_SOURCE_MASK)
#define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_MASK (0x700U)
#define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_SHIFT (8U)
/*! NUM_CH - Number of Channels Per Packet
* 0b000..There is 1 channel per packet.
* 0b001..There are 2 channels per packet.
* 0b010..There are 3 channels per packet.
* 0b011..There are 4 channels per packet.
* 0b100..There are 5 channels per packet.
* 0b101..There are 6 channels per packet.
* 0b110..There are 7 channels per packet.
* 0b111..There are 8 channels per packet.
*/
#define HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_NUM_CH_MASK)
#define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_MASK (0x800U)
#define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_SHIFT (11U)
/*! B_EXT - B-Field Extension
* 0b0..Use default B-Preamble timing (from selected input source).
* 0b1..Extend B-Preamble timing to ensure it is set for at least 2 cycles.
*/
#define HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_B_EXT_MASK)
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_MASK (0xFF0000U)
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_SHIFT (16U)
/*! WTMK_LOW - HTX PAI Watermark Low
*/
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_LOW_MASK)
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_MASK (0xFF000000U)
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_SHIFT (24U)
/*! WTMK_HIGH - HTX PAI Watermark High
*/
#define HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_SHIFT)) & HTX_PAI_HTX_PAI_CTRL_EXT_WTMK_HIGH_MASK)
/*! @} */
/*! @name HTX_PAI_FIELD_CTRL - HTX PAI Field Control */
/*! @{ */
#define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_MASK (0x1FU)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_SHIFT (0U)
/*! P_SEL - IEC60958 P Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_P_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_MASK (0x3E0U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_SHIFT (5U)
/*! C_SEL - IEC60958 C Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_C_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_MASK (0x7C00U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_SHIFT (10U)
/*! U_SEL - IEC60958 U Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_U_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_MASK (0xF8000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_SHIFT (15U)
/*! V_SEL - IEC60958 V Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_V_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_MASK (0xF00000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_SHIFT (20U)
/*! D_SEL - IEC60958 Data Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_D_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_MASK (0x1F000000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_SHIFT (24U)
/*! PRE_SEL - IEC60958 Preamble Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_PRE_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_MASK (0x20000000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_SHIFT (29U)
/*! END_SEL - Endianness Select
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_END_SEL_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_MASK (0x40000000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_SHIFT (30U)
/*! PARITY_EN - Parity Enable
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_PARITY_EN_MASK)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_MASK (0x80000000U)
#define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_SHIFT (31U)
/*! B_FILT - B-Detect Filter
*/
#define HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_SHIFT)) & HTX_PAI_HTX_PAI_FIELD_CTRL_B_FILT_MASK)
/*! @} */
/*! @name HTX_PAI_STAT - HTX PAI Status */
/*! @{ */
#define HTX_PAI_HTX_PAI_STAT_WM_LOW_MASK (0x1U)
#define HTX_PAI_HTX_PAI_STAT_WM_LOW_SHIFT (0U)
/*! WM_LOW - Watermark Low Flag
*/
#define HTX_PAI_HTX_PAI_STAT_WM_LOW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_STAT_WM_LOW_SHIFT)) & HTX_PAI_HTX_PAI_STAT_WM_LOW_MASK)
#define HTX_PAI_HTX_PAI_STAT_WM_HIGH_MASK (0x2U)
#define HTX_PAI_HTX_PAI_STAT_WM_HIGH_SHIFT (1U)
/*! WM_HIGH - Watermark High Flag
*/
#define HTX_PAI_HTX_PAI_STAT_WM_HIGH(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_STAT_WM_HIGH_SHIFT)) & HTX_PAI_HTX_PAI_STAT_WM_HIGH_MASK)
/*! @} */
/*! @name HTX_PAI_IRQ_NOMASK - HTX PAI Nonmasked Interrupt Flags */
/*! @{ */
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_MASK (0x1U)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_SHIFT (0U)
/*! OVF - HTX PAI Buffer Overflow
*/
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_OVF_MASK)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_MASK (0x2U)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_SHIFT (1U)
/*! UND - HTX PAI Buffer Underflow
*/
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_UND(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_UND_MASK)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_MASK (0x4U)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_SHIFT (2U)
/*! WM_LOW_IRQ - Watermark Low IRQ
*/
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_LOW_IRQ_MASK)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_MASK (0x8U)
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_SHIFT (3U)
/*! WM_HIGH_IRQ - Watermark High IRQ
*/
#define HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_NOMASK_WM_HIGH_IRQ_MASK)
/*! @} */
/*! @name HTX_PAI_IRQ_MASKED - HTX PAI Masked Interrupt Flags */
/*! @{ */
#define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_MASK (0x1U)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_SHIFT (0U)
/*! OVF - HTX PAI Buffer Overflow
*/
#define HTX_PAI_HTX_PAI_IRQ_MASKED_OVF(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_OVF_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_UND_MASK (0x2U)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_UND_SHIFT (1U)
/*! UND - HTX PAI Buffer Underflow
*/
#define HTX_PAI_HTX_PAI_IRQ_MASKED_UND(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_UND_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_UND_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_MASK (0x4U)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_SHIFT (2U)
/*! WM_LOW_IRQ - Watermark Low IRQ Masked
*/
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_WM_LOW_IRQ_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_MASK (0x8U)
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_SHIFT (3U)
/*! WM_HIGH_IRQ - Watermark High IRQ Masked
*/
#define HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASKED_WM_HIGH_IRQ_MASK)
/*! @} */
/*! @name HTX_PAI_IRQ_MASK - HTX PAI IRQ Masks */
/*! @{ */
#define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_MASK (0x1U)
#define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_SHIFT (0U)
/*! OVF_MASK - HTX PAI Buffer Overflow Mask
*/
#define HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_OVF_MASK_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_MASK (0x2U)
#define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_SHIFT (1U)
/*! UND_MASK - HTX PAI Buffer Underflow Mask
*/
#define HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_UND_MASK_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_MASK (0x4U)
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_SHIFT (2U)
/*! WM_LOW_IRQ_MASK - Watermark Low IRQ Mask
*/
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_WM_LOW_IRQ_MASK_MASK)
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_MASK (0x8U)
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_SHIFT (3U)
/*! WM_HIGH_IRQ_MASK - Watermark High IRQ Mask
*/
#define HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_SHIFT)) & HTX_PAI_HTX_PAI_IRQ_MASK_WM_HIGH_IRQ_MASK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HTX_PAI_Register_Masks */
/* HTX_PAI - Peripheral instance base addresses */
/** Peripheral HTX_PAI base address */
#define HTX_PAI_BASE (0x32FC4800u)
/** Peripheral HTX_PAI base pointer */
#define HTX_PAI ((HTX_PAI_Type *)HTX_PAI_BASE)
/** Array initializer of HTX_PAI peripheral base addresses */
#define HTX_PAI_BASE_ADDRS { HTX_PAI_BASE }
/** Array initializer of HTX_PAI peripheral base pointers */
#define HTX_PAI_BASE_PTRS { HTX_PAI }
/*!
* @}
*/ /* end of group HTX_PAI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- HTX_PVI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup HTX_PVI_Peripheral_Access_Layer HTX_PVI Peripheral Access Layer
* @{
*/
/** HTX_PVI - Register Layout Typedef */
typedef struct {
__IO uint32_t HTX_PVI_CTRL; /**< HTX_PVI Control Reg, offset: 0x0 */
__IO uint32_t HTX_PVI_IRQ_MASK; /**< Masks off the Interrupts, offset: 0x4 */
__I uint32_t HTX_PVI_IRQ_STATUS; /**< Interrupt Status, offset: 0x8 */
__IO uint32_t HTX_PVI_IRQ_CLR; /**< Interrupts, offset: 0xC */
__IO uint32_t HTX_TMG_GEN_DISP_LRC; /**< Display Coordinates, offset: 0x10 */
__IO uint32_t HTX_TMG_GEN_DE_ULC; /**< Data Enable Coordinates, offset: 0x14 */
__IO uint32_t HTX_TMG_GEN_DE_LRC; /**< Data Enable Coordinates, offset: 0x18 */
__IO uint32_t HTX_TMG_GEN_HSYNC; /**< Hsync Start and End, offset: 0x1C */
__IO uint32_t HTX_TMG_GEN_VSYNC; /**< Vsync Start and End, offset: 0x20 */
__IO uint32_t HTX_TMG_GEN_IRQ0; /**< Controls the Position of first IRQ from Timing Generator, offset: 0x24 */
__IO uint32_t HTX_TMG_GEN_IRQ1; /**< Controls the Position of Second IRQ from Timing Generator, offset: 0x28 */
__IO uint32_t HTX_TMG_GEN_IRQ2; /**< Controls the Position of Third IRQ from Timing Generator, offset: 0x2C */
__IO uint32_t HTX_TMG_GEN_IRQ3; /**< Controls the Position of Fourth IRQ from Timing Generator, offset: 0x30 */
__IO uint32_t HTX_TMG_GEN_BG0; /**< Background Color insertion for R or Y, offset: 0x34 */
__IO uint32_t HTX_TMG_GEN_BG1; /**< Background Color insertion for G or Cb, offset: 0x38 */
__IO uint32_t HTX_TMG_GEN_BG2; /**< Background Color insertion for B or Cr, offset: 0x3C */
__IO uint32_t HTX_TMG_GEN_CFG; /**< HStart and Vstart Delay Configuration, offset: 0x40 */
} HTX_PVI_Type;
/* ----------------------------------------------------------------------------
-- HTX_PVI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup HTX_PVI_Register_Masks HTX_PVI Register Masks
* @{
*/
/*! @name HTX_PVI_CTRL - HTX_PVI Control Reg */
/*! @{ */
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_MASK (0x1U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_SHIFT (0U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_EN_MASK)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_MASK (0x6U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_SHIFT (1U)
/*! HTX_PVI_MODE - Selects the mode of operation in HTX PVI
* 0b00..Select the DCSS Path
* 0b01..Select the Bypass path from HDMI Rx
* 0b10..Select the LCDIF Path
* 0b11..Reserved
*/
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_MODE_MASK)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_MASK (0x8U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_SHIFT (3U)
/*! HTX_PVI_UPSMPL - Select the mode of upsample in case of 16bit output and 12bit input
* 0b0..Fill LSB with 4'b0
* 0b1..Fill LSB with MSB 4 bits, i.e. [11:8]
*/
#define HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PVI_UPSMPL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_MASK (0x10U)
#define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_SHIFT (4U)
#define HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_DCSS_YUV420_MODE_MASK)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_MASK (0x20U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_SHIFT (5U)
#define HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_HTX_PLB_EN_MASK)
#define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_MASK (0xC0U)
#define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_SHIFT (6U)
/*! PIPE_MODE - Sets the Timing Generator mode.
* 0b00..bypass
* 0b01..422 subsample
* 0b10..420 subsample
* 0b11..bypass
*/
#define HTX_PVI_HTX_PVI_CTRL_PIPE_MODE(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_PIPE_MODE_MASK)
#define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_MASK (0x100U)
#define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_SHIFT (8U)
/*! VSYNC_SHIFT - VSYNC shift
* 0b0..Run in general interlaced mode. Every other field the vsync is shifted forward 1/2 scan lines. In
* addition, the horizontal back porch is extended 1 scan line.
* 0b1..Run in special interlaced format. This shifts vsync backwards 1/2 scan line every other field. Remaining timing won't change.
*/
#define HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_VSYNC_SHIFT_MASK)
#define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_MASK (0x200U)
#define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_SHIFT (9U)
/*! TMG_GEN_EN - Enable Timing Generator to insert the hsync and vsync.
* 0b0..Disable
* 0b1..Enable
*/
#define HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_TMG_GEN_EN_MASK)
#define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_MASK (0x400U)
#define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_SHIFT (10U)
/*! INTRLC_EN - Enable interlaced HDMI timing
* 0b0..Disable
* 0b1..Enable
*/
#define HTX_PVI_HTX_PVI_CTRL_INTRLC_EN(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INTRLC_EN_MASK)
#define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_MASK (0x1000U)
#define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_SHIFT (12U)
/*! INP_DE_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_INP_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_DE_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_MASK (0x2000U)
#define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_SHIFT (13U)
/*! INP_HSYNC_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_HSYNC_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_MASK (0x4000U)
#define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_SHIFT (14U)
/*! INP_VSYNC_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_INP_VSYNC_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_MASK (0x10000U)
#define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_SHIFT (16U)
/*! OP_DE_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_OP_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_DE_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_MASK (0x20000U)
#define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_SHIFT (17U)
/*! OP_HSYNC_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_HSYNC_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_MASK (0x40000U)
#define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_SHIFT (18U)
/*! OP_VSYNC_POL
* 0b0..Active Low
* 0b1..Active High
*/
#define HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_OP_VSYNC_POL_MASK)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_MASK (0x100000U)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_SHIFT (20U)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_FDCC_MASK)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_MASK (0x200000U)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_SHIFT (21U)
#define HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_CTRL_EN_BG_INS_UNDRFLW_MASK)
/*! @} */
/*! @name HTX_PVI_IRQ_MASK - Masks off the Interrupts */
/*! @{ */
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_MASK (0x1U)
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_SHIFT (0U)
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_OVRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
#define HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_ASYNC_FIFO_UNDRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_MASK (0x3CU)
#define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_SHIFT (2U)
#define HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_MASK_TMG_GEN_IRQ_MASK)
/*! @} */
/*! @name HTX_PVI_IRQ_STATUS - Interrupt Status */
/*! @{ */
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_MASK (0x1U)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_SHIFT (0U)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_OVRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_ASYNC_FIFO_UNDRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_MASK (0x3CU)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_SHIFT (2U)
#define HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_STATUS_TMG_GEN_IRQ_MASK)
/*! @} */
/*! @name HTX_PVI_IRQ_CLR - Interrupts */
/*! @{ */
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_MASK (0x1U)
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_SHIFT (0U)
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_OVRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_MASK (0x2U)
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_SHIFT (1U)
#define HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_ASYNC_FIFO_UNDRFLW_MASK)
#define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_MASK (0x3CU)
#define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_SHIFT (2U)
#define HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_SHIFT)) & HTX_PVI_HTX_PVI_IRQ_CLR_TMG_GEN_IRQ_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_DISP_LRC - Display Coordinates */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSY_MASK)
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DISP_LRC_POSX_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_DE_ULC - Data Enable Coordinates */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_ULC_POSY_MASK)
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_ULC_POSX_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_DE_LRC - Data Enable Coordinates */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_LRC_POSY_MASK)
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_SHIFT)) & HTX_PVI_HTX_TMG_GEN_DE_LRC_POSX_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_HSYNC - Hsync Start and End */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_HSYNC_END_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_HSYNC_END_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_HSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_HSYNC_END_SHIFT)) & HTX_PVI_HTX_TMG_GEN_HSYNC_END_MASK)
#define HTX_PVI_HTX_TMG_GEN_HSYNC_START_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_HSYNC_START_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_HSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_HSYNC_START_SHIFT)) & HTX_PVI_HTX_TMG_GEN_HSYNC_START_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_VSYNC - Vsync Start and End */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_VSYNC_END_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_VSYNC_END_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_VSYNC_END(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_VSYNC_END_SHIFT)) & HTX_PVI_HTX_TMG_GEN_VSYNC_END_MASK)
#define HTX_PVI_HTX_TMG_GEN_VSYNC_START_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_VSYNC_START_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_VSYNC_START(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_VSYNC_START_SHIFT)) & HTX_PVI_HTX_TMG_GEN_VSYNC_START_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_IRQ0 - Controls the Position of first IRQ from Timing Generator */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ0_POS_Y_MASK)
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ0_POS_X_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_IRQ1 - Controls the Position of Second IRQ from Timing Generator */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ1_POS_Y_MASK)
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ1_POS_X_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_IRQ2 - Controls the Position of Third IRQ from Timing Generator */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ2_POS_Y_MASK)
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ2_POS_X_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_IRQ3 - Controls the Position of Fourth IRQ from Timing Generator */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_MASK (0xFFFFU)
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ3_POS_Y_MASK)
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_MASK (0xFFFF0000U)
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_SHIFT)) & HTX_PVI_HTX_TMG_GEN_IRQ3_POS_X_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_BG0 - Background Color insertion for R or Y */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_MASK (0xFFFU)
#define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG0_DEF_VAL_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_BG1 - Background Color insertion for G or Cb */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_MASK (0xFFFU)
#define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG1_DEF_VAL_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_BG2 - Background Color insertion for B or Cr */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_MASK (0xFFFU)
#define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_SHIFT)) & HTX_PVI_HTX_TMG_GEN_BG2_DEF_VAL_MASK)
/*! @} */
/*! @name HTX_TMG_GEN_CFG - HStart and Vstart Delay Configuration */
/*! @{ */
#define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_MASK (0x1FFFU)
#define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_SHIFT (0U)
#define HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_H_STRT_DLY_MASK)
#define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_MASK (0x1FFF0000U)
#define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_SHIFT (16U)
#define HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_V_STRT_DLY_MASK)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_MASK (0x40000000U)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_SHIFT (30U)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_EN_HS_DLY_STRT_MASK)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_MASK (0x80000000U)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_SHIFT (31U)
#define HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT(x) (((uint32_t)(((uint32_t)(x)) << HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_SHIFT)) & HTX_PVI_HTX_TMG_GEN_CFG_EN_VS_DLY_STRT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group HTX_PVI_Register_Masks */
/* HTX_PVI - Peripheral instance base addresses */
/** Peripheral HTX_PVI base address */
#define HTX_PVI_BASE (0x32FC4000u)
/** Peripheral HTX_PVI base pointer */
#define HTX_PVI ((HTX_PVI_Type *)HTX_PVI_BASE)
/** Array initializer of HTX_PVI peripheral base addresses */
#define HTX_PVI_BASE_ADDRS { HTX_PVI_BASE }
/** Array initializer of HTX_PVI peripheral base pointers */
#define HTX_PVI_BASE_PTRS { HTX_PVI }
/*!
* @}
*/ /* end of group HTX_PVI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
* @{
*/
/** I2C - Register Layout Typedef */
typedef struct {
__IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */
uint8_t RESERVED_0[2];
__IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */
uint8_t RESERVED_1[2];
__IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */
uint8_t RESERVED_2[2];
__IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */
uint8_t RESERVED_3[2];
__IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */
} I2C_Type;
/* ----------------------------------------------------------------------------
-- I2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2C_Register_Masks I2C Register Masks
* @{
*/
/*! @name IADR - I2C Address Register */
/*! @{ */
#define I2C_IADR_ADR_MASK (0xFEU)
#define I2C_IADR_ADR_SHIFT (1U)
#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK)
/*! @} */
/*! @name IFDR - I2C Frequency Divider Register */
/*! @{ */
#define I2C_IFDR_IC_MASK (0x3FU)
#define I2C_IFDR_IC_SHIFT (0U)
#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK)
/*! @} */
/*! @name I2CR - I2C Control Register */
/*! @{ */
#define I2C_I2CR_RSTA_MASK (0x4U)
#define I2C_I2CR_RSTA_SHIFT (2U)
/*! RSTA
* 0b0..No repeat start
* 0b1..Generates a Repeated Start condition
*/
#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK)
#define I2C_I2CR_TXAK_MASK (0x8U)
#define I2C_I2CR_TXAK_SHIFT (3U)
/*! TXAK
* 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
* 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1).
*/
#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK)
#define I2C_I2CR_MTX_MASK (0x10U)
#define I2C_I2CR_MTX_SHIFT (4U)
/*! MTX
* 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in
* the I2C status register (I2C_I2SR[SRW]).
* 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address cycles, MTX is always 1.
*/
#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK)
#define I2C_I2CR_MSTA_MASK (0x20U)
#define I2C_I2CR_MSTA_SHIFT (5U)
/*! MSTA
* 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.
* 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.
*/
#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK)
#define I2C_I2CR_IIEN_MASK (0x40U)
#define I2C_I2CR_IIEN_SHIFT (6U)
/*! IIEN
* 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition occurs.
* 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
*/
#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK)
#define I2C_I2CR_IEN_MASK (0x80U)
#define I2C_I2CR_IEN_SHIFT (7U)
/*! IEN
* 0b0..The block is disabled, but registers can still be accessed.
* 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.
*/
#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK)
/*! @} */
/*! @name I2SR - I2C Status Register */
/*! @{ */
#define I2C_I2SR_RXAK_MASK (0x1U)
#define I2C_I2SR_RXAK_SHIFT (0U)
/*! RXAK
* 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
* 0b1..A "No acknowledge" signal was detected at the ninth clock.
*/
#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK)
#define I2C_I2SR_IIF_MASK (0x2U)
#define I2C_I2SR_IIF_SHIFT (1U)
/*! IIF
* 0b0..No I2C interrupt pending.
* 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted
* [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the
* interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific
* address in Slave Receive mode. Arbitration is lost.
*/
#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK)
#define I2C_I2SR_SRW_MASK (0x4U)
#define I2C_I2SR_SRW_SHIFT (2U)
/*! SRW
* 0b0..Slave receive, master writing to slave
* 0b1..Slave transmit, master reading from slave
*/
#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK)
#define I2C_I2SR_IAL_MASK (0x10U)
#define I2C_I2SR_IAL_SHIFT (4U)
/*! IAL
* 0b0..No arbitration lost.
* 0b1..Arbitration is lost.
*/
#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK)
#define I2C_I2SR_IBB_MASK (0x20U)
#define I2C_I2SR_IBB_SHIFT (5U)
/*! IBB
* 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared.
* 0b1..Bus is busy. When Start is detected, IBB is set.
*/
#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK)
#define I2C_I2SR_IAAS_MASK (0x40U)
#define I2C_I2SR_IAAS_SHIFT (6U)
/*! IAAS
* 0b0..Not addressed
* 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
*/
#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK)
#define I2C_I2SR_ICF_MASK (0x80U)
#define I2C_I2SR_ICF_SHIFT (7U)
/*! ICF
* 0b0..Transfer is in progress.
* 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.
*/
#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK)
/*! @} */
/*! @name I2DR - I2C Data I/O Register */
/*! @{ */
#define I2C_I2DR_DATA_MASK (0xFFU)
#define I2C_I2DR_DATA_SHIFT (0U)
#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group I2C_Register_Masks */
/* I2C - Peripheral instance base addresses */
/** Peripheral I2C1 base address */
#define I2C1_BASE (0x30A20000u)
/** Peripheral I2C1 base pointer */
#define I2C1 ((I2C_Type *)I2C1_BASE)
/** Peripheral I2C2 base address */
#define I2C2_BASE (0x30A30000u)
/** Peripheral I2C2 base pointer */
#define I2C2 ((I2C_Type *)I2C2_BASE)
/** Peripheral I2C3 base address */
#define I2C3_BASE (0x30A40000u)
/** Peripheral I2C3 base pointer */
#define I2C3 ((I2C_Type *)I2C3_BASE)
/** Peripheral I2C4 base address */
#define I2C4_BASE (0x30A50000u)
/** Peripheral I2C4 base pointer */
#define I2C4 ((I2C_Type *)I2C4_BASE)
/** Peripheral I2C5 base address */
#define I2C5_BASE (0x30AD0000u)
/** Peripheral I2C5 base pointer */
#define I2C5 ((I2C_Type *)I2C5_BASE)
/** Peripheral I2C6 base address */
#define I2C6_BASE (0x30AE0000u)
/** Peripheral I2C6 base pointer */
#define I2C6 ((I2C_Type *)I2C6_BASE)
/** Array initializer of I2C peripheral base addresses */
#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE }
/** Array initializer of I2C peripheral base pointers */
#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6 }
/** Interrupt vectors for the I2C peripheral type */
#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn, I2C5_IRQn, I2C6_IRQn }
/*!
* @}
*/ /* end of group I2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
__IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
__IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
__IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
__IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
__IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
__O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
__I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
__IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
uint8_t RESERVED_0[12];
__IO uint32_t TTCR; /**< SAI Transmit Timestamp Control Register, offset: 0x70 */
__I uint32_t TTSR; /**< SAI Transmit Timestamp Register, offset: 0x74 */
__I uint32_t TBCR; /**< SAI Transmit Bit Count Register, offset: 0x78 */
__I uint32_t TBCTR; /**< SAI Transmit Bit Count Timestamp Register, offset: 0x7C */
uint8_t RESERVED_1[8];
__IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
__IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
__IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
__IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
__IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
__IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
__I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
__I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
__IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
uint8_t RESERVED_2[12];
__IO uint32_t RTCR; /**< SAI Receive Timestamp Control Register, offset: 0xF0 */
__I uint32_t RTSR; /**< SAI Receive Timestamp Register, offset: 0xF4 */
__I uint32_t RBCR; /**< SAI Receive Bit Count Register, offset: 0xF8 */
__I uint32_t RBCTR; /**< SAI Receive Bit Count Timestamp Register, offset: 0xFC */
__IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define I2S_VERID_FEATURE_MASK (0xFFFFU)
#define I2S_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Specification Number
* 0b0000000000000000..Standard feature set.
* 0b0000000000000010..Standard feature set with Timestamp Registers.
*/
#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define I2S_VERID_MINOR_MASK (0xFF0000U)
#define I2S_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define I2S_VERID_MAJOR_MASK (0xFF000000U)
#define I2S_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define I2S_PARAM_DATALINE_MASK (0xFU)
#define I2S_PARAM_DATALINE_SHIFT (0U)
/*! DATALINE - Number of Datalines
*/
#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define I2S_PARAM_FIFO_MASK (0xF00U)
#define I2S_PARAM_FIFO_SHIFT (8U)
/*! FIFO - FIFO Size
*/
#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define I2S_PARAM_FRAME_MASK (0xF0000U)
#define I2S_PARAM_FRAME_SHIFT (16U)
/*! FRAME - Frame Size
*/
#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
/*! @} */
/*! @name TCSR - SAI Transmit Control Register */
/*! @{ */
#define I2S_TCSR_FRDE_MASK (0x1U)
#define I2S_TCSR_FRDE_SHIFT (0U)
/*! FRDE - FIFO Request DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK (0x2U)
#define I2S_TCSR_FWDE_SHIFT (1U)
/*! FWDE - FIFO Warning DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK (0x100U)
#define I2S_TCSR_FRIE_SHIFT (8U)
/*! FRIE - FIFO Request Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK (0x200U)
#define I2S_TCSR_FWIE_SHIFT (9U)
/*! FWIE - FIFO Warning Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK (0x400U)
#define I2S_TCSR_FEIE_SHIFT (10U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK (0x800U)
#define I2S_TCSR_SEIE_SHIFT (11U)
/*! SEIE - Sync Error Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK (0x1000U)
#define I2S_TCSR_WSIE_SHIFT (12U)
/*! WSIE - Word Start Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK (0x10000U)
#define I2S_TCSR_FRF_SHIFT (16U)
/*! FRF - FIFO Request Flag
* 0b0..Transmit FIFO watermark has not been reached.
* 0b1..Transmit FIFO watermark has been reached.
*/
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK (0x20000U)
#define I2S_TCSR_FWF_SHIFT (17U)
/*! FWF - FIFO Warning Flag
* 0b0..No enabled transmit FIFO is empty.
* 0b1..Enabled transmit FIFO is empty.
*/
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK (0x40000U)
#define I2S_TCSR_FEF_SHIFT (18U)
/*! FEF - FIFO Error Flag
* 0b0..Transmit underrun not detected.
* 0b1..Transmit underrun detected.
*/
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK (0x80000U)
#define I2S_TCSR_SEF_SHIFT (19U)
/*! SEF - Sync Error Flag
* 0b0..Sync error not detected.
* 0b1..Frame sync error detected.
*/
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK (0x100000U)
#define I2S_TCSR_WSF_SHIFT (20U)
/*! WSF - Word Start Flag
* 0b0..Start of word not detected.
* 0b1..Start of word detected.
*/
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK (0x1000000U)
#define I2S_TCSR_SR_SHIFT (24U)
/*! SR - Software Reset
* 0b0..No effect.
* 0b1..Software reset.
*/
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK (0x2000000U)
#define I2S_TCSR_FR_SHIFT (25U)
/*! FR - FIFO Reset
* 0b0..No effect.
* 0b1..FIFO reset.
*/
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK (0x10000000U)
#define I2S_TCSR_BCE_SHIFT (28U)
/*! BCE - Bit Clock Enable
* 0b0..Transmit bit clock is disabled.
* 0b1..Transmit bit clock is enabled.
*/
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT (29U)
/*! DBGE - Debug Enable
* 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
* 0b1..Transmitter is enabled in Debug mode.
*/
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT (30U)
/*! STOPE - Stop Enable
* 0b0..Transmitter disabled in Stop mode.
* 0b1..Transmitter enabled in Stop mode.
*/
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK (0x80000000U)
#define I2S_TCSR_TE_SHIFT (31U)
/*! TE - Transmitter Enable
* 0b0..Transmitter is disabled.
* 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
*/
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */
/*! @name TCR1 - SAI Transmit Configuration 1 Register */
/*! @{ */
#define I2S_TCR1_TFW_MASK (0x7FU)
#define I2S_TCR1_TFW_SHIFT (0U)
/*! TFW - Transmit FIFO Watermark
*/
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */
/*! @name TCR2 - SAI Transmit Configuration 2 Register */
/*! @{ */
#define I2S_TCR2_DIV_MASK (0xFFU)
#define I2S_TCR2_DIV_SHIFT (0U)
/*! DIV - Bit Clock Divide
*/
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BYP_MASK (0x800000U)
#define I2S_TCR2_BYP_SHIFT (23U)
/*! BYP - Bit Clock Bypass
* 0b0..Internal bit clock is generated from bit clock divider.
* 0b1..Internal bit clock is divide by one of the audio master clock.
*/
#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
#define I2S_TCR2_BCD_MASK (0x1000000U)
#define I2S_TCR2_BCD_SHIFT (24U)
/*! BCD - Bit Clock Direction
* 0b0..Bit clock is generated externally in Slave mode.
* 0b1..Bit clock is generated internally in Master mode.
*/
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK (0x2000000U)
#define I2S_TCR2_BCP_SHIFT (25U)
/*! BCP - Bit Clock Polarity
* 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
* 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
*/
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT (26U)
/*! MSEL - MCLK Select
* 0b00..Bus Clock selected.
* 0b01..Master Clock (MCLK) 1 option selected.
* 0b10..Master Clock (MCLK) 2 option selected.
* 0b11..Master Clock (MCLK) 3 option selected.
*/
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK (0x10000000U)
#define I2S_TCR2_BCI_SHIFT (28U)
/*! BCI - Bit Clock Input
* 0b0..No effect.
* 0b1..Internal logic is clocked as if bit clock was externally generated.
*/
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK (0x20000000U)
#define I2S_TCR2_BCS_SHIFT (29U)
/*! BCS - Bit Clock Swap
* 0b0..Use the normal bit clock source.
* 0b1..Swap the bit clock source.
*/
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK (0xC0000000U)
#define I2S_TCR2_SYNC_SHIFT (30U)
/*! SYNC - Synchronous Mode
* 0b00..Asynchronous mode.
* 0b01..Synchronous with receiver.
* 0b10..Reserved.
* 0b11..Reserved.
*/
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @} */
/*! @name TCR3 - SAI Transmit Configuration 3 Register */
/*! @{ */
#define I2S_TCR3_WDFL_MASK (0x1FU)
#define I2S_TCR3_WDFL_SHIFT (0U)
/*! WDFL - Word Flag Configuration
*/
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK (0xFF0000U)
#define I2S_TCR3_TCE_SHIFT (16U)
/*! TCE - Transmit Channel Enable
*/
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
#define I2S_TCR3_CFR_MASK (0xFF000000U)
#define I2S_TCR3_CFR_SHIFT (24U)
/*! CFR - Channel FIFO Reset
*/
#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
/*! @} */
/*! @name TCR4 - SAI Transmit Configuration 4 Register */
/*! @{ */
#define I2S_TCR4_FSD_MASK (0x1U)
#define I2S_TCR4_FSD_SHIFT (0U)
/*! FSD - Frame Sync Direction
* 0b0..Frame sync is generated externally in Slave mode.
* 0b1..Frame sync is generated internally in Master mode.
*/
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK (0x2U)
#define I2S_TCR4_FSP_SHIFT (1U)
/*! FSP - Frame Sync Polarity
* 0b0..Frame sync is active high.
* 0b1..Frame sync is active low.
*/
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK (0x4U)
#define I2S_TCR4_ONDEM_SHIFT (2U)
/*! ONDEM - On Demand Mode
* 0b0..Internal frame sync is generated continuously.
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
*/
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK (0x8U)
#define I2S_TCR4_FSE_SHIFT (3U)
/*! FSE - Frame Sync Early
* 0b0..Frame sync asserts with the first bit of the frame.
* 0b1..Frame sync asserts one bit before the first bit of the frame.
*/
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK (0x10U)
#define I2S_TCR4_MF_SHIFT (4U)
/*! MF - MSB First
* 0b0..LSB is transmitted first.
* 0b1..MSB is transmitted first.
*/
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define I2S_TCR4_CHMOD_MASK (0x20U)
#define I2S_TCR4_CHMOD_SHIFT (5U)
/*! CHMOD - Channel Mode
* 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
* 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
*/
#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define I2S_TCR4_SYWD_MASK (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT (8U)
/*! SYWD - Sync Width
*/
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
#define I2S_TCR4_FRSZ_SHIFT (16U)
/*! FRSZ - Frame size
*/
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT (24U)
/*! FPACK - FIFO Packing Mode
* 0b00..FIFO packing is disabled
* 0b01..Reserved
* 0b10..8-bit FIFO packing is enabled
* 0b11..16-bit FIFO packing is enabled
*/
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCOMB_MASK (0xC000000U)
#define I2S_TCR4_FCOMB_SHIFT (26U)
/*! FCOMB - FIFO Combine Mode
* 0b00..FIFO combine mode disabled.
* 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
* 0b10..FIFO combine mode enabled on FIFO writes (by software).
* 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
*/
#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define I2S_TCR4_FCONT_MASK (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT (28U)
/*! FCONT - FIFO Continue on Error
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
*/
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */
/*! @name TCR5 - SAI Transmit Configuration 5 Register */
/*! @{ */
#define I2S_TCR5_FBT_MASK (0x1F00U)
#define I2S_TCR5_FBT_SHIFT (8U)
/*! FBT - First Bit Shifted
*/
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT (16U)
/*! W0W - Word 0 Width
*/
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT (24U)
/*! WNW - Word N Width
*/
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */
/*! @name TDR - SAI Transmit Data Register */
/*! @{ */
#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT (0U)
/*! TDR - Transmit Data Register
*/
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */
/* The count of I2S_TDR */
#define I2S_TDR_COUNT (8U)
/*! @name TFR - SAI Transmit FIFO Register */
/*! @{ */
#define I2S_TFR_RFP_MASK (0xFFU)
#define I2S_TFR_RFP_SHIFT (0U)
/*! RFP - Read FIFO Pointer
*/
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK (0xFF0000U)
#define I2S_TFR_WFP_SHIFT (16U)
/*! WFP - Write FIFO Pointer
*/
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define I2S_TFR_WCP_MASK (0x80000000U)
#define I2S_TFR_WCP_SHIFT (31U)
/*! WCP - Write Channel Pointer
* 0b0..No effect.
* 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
*/
#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
/*! @} */
/* The count of I2S_TFR */
#define I2S_TFR_COUNT (8U)
/*! @name TMR - SAI Transmit Mask Register */
/*! @{ */
#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
#define I2S_TMR_TWM_SHIFT (0U)
/*! TWM - Transmit Word Mask
* 0b00000000000000000000000000000000..Word N is enabled.
* 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
*/
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @} */
/*! @name TTCR - SAI Transmit Timestamp Control Register */
/*! @{ */
#define I2S_TTCR_TSEN_MASK (0x1U)
#define I2S_TTCR_TSEN_SHIFT (0U)
/*! TSEN - Timestamp Enable
* 0b0..Timestamp counter is disabled.
* 0b1..Timestamp counter is enabled.
*/
#define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK)
#define I2S_TTCR_TSINC_MASK (0x2U)
#define I2S_TTCR_TSINC_SHIFT (1U)
/*! TSINC - Timestamp Increment
* 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
* 0b1..Timestamp counter starts to increment when enabled.
*/
#define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK)
#define I2S_TTCR_RTSC_MASK (0x100U)
#define I2S_TTCR_RTSC_SHIFT (8U)
/*! RTSC - Reset Timestamp Counter
* 0b0..Timestamp counter is not reset.
* 0b1..Timestamp counter is reset.
*/
#define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK)
#define I2S_TTCR_RBC_MASK (0x200U)
#define I2S_TTCR_RBC_SHIFT (9U)
/*! RBC - Reset Bit Counter
* 0b0..Bit counter is not reset.
* 0b1..Bit counter is reset.
*/
#define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK)
/*! @} */
/*! @name TTSR - SAI Transmit Timestamp Register */
/*! @{ */
#define I2S_TTSR_TSC_MASK (0xFFFFFFFFU)
#define I2S_TTSR_TSC_SHIFT (0U)
/*! TSC - Timestamp Counter
*/
#define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK)
/*! @} */
/*! @name TBCR - SAI Transmit Bit Count Register */
/*! @{ */
#define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU)
#define I2S_TBCR_BCNT_SHIFT (0U)
/*! BCNT - Bit Counter
*/
#define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK)
/*! @} */
/*! @name TBCTR - SAI Transmit Bit Count Timestamp Register */
/*! @{ */
#define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU)
#define I2S_TBCTR_BCTS_SHIFT (0U)
/*! BCTS - Bit Timestamp
*/
#define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK)
/*! @} */
/*! @name RCSR - SAI Receive Control Register */
/*! @{ */
#define I2S_RCSR_FRDE_MASK (0x1U)
#define I2S_RCSR_FRDE_SHIFT (0U)
/*! FRDE - FIFO Request DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK (0x2U)
#define I2S_RCSR_FWDE_SHIFT (1U)
/*! FWDE - FIFO Warning DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK (0x100U)
#define I2S_RCSR_FRIE_SHIFT (8U)
/*! FRIE - FIFO Request Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK (0x200U)
#define I2S_RCSR_FWIE_SHIFT (9U)
/*! FWIE - FIFO Warning Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK (0x400U)
#define I2S_RCSR_FEIE_SHIFT (10U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK (0x800U)
#define I2S_RCSR_SEIE_SHIFT (11U)
/*! SEIE - Sync Error Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK (0x1000U)
#define I2S_RCSR_WSIE_SHIFT (12U)
/*! WSIE - Word Start Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK (0x10000U)
#define I2S_RCSR_FRF_SHIFT (16U)
/*! FRF - FIFO Request Flag
* 0b0..Receive FIFO watermark not reached.
* 0b1..Receive FIFO watermark has been reached.
*/
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK (0x20000U)
#define I2S_RCSR_FWF_SHIFT (17U)
/*! FWF - FIFO Warning Flag
* 0b0..No enabled receive FIFO is full.
* 0b1..Enabled receive FIFO is full.
*/
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK (0x40000U)
#define I2S_RCSR_FEF_SHIFT (18U)
/*! FEF - FIFO Error Flag
* 0b0..Receive overflow not detected.
* 0b1..Receive overflow detected.
*/
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK (0x80000U)
#define I2S_RCSR_SEF_SHIFT (19U)
/*! SEF - Sync Error Flag
* 0b0..Sync error not detected.
* 0b1..Frame sync error detected.
*/
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK (0x100000U)
#define I2S_RCSR_WSF_SHIFT (20U)
/*! WSF - Word Start Flag
* 0b0..Start of word not detected.
* 0b1..Start of word detected.
*/
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK (0x1000000U)
#define I2S_RCSR_SR_SHIFT (24U)
/*! SR - Software Reset
* 0b0..No effect.
* 0b1..Software reset.
*/
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK (0x2000000U)
#define I2S_RCSR_FR_SHIFT (25U)
/*! FR - FIFO Reset
* 0b0..No effect.
* 0b1..FIFO reset.
*/
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK (0x10000000U)
#define I2S_RCSR_BCE_SHIFT (28U)
/*! BCE - Bit Clock Enable
* 0b0..Receive bit clock is disabled.
* 0b1..Receive bit clock is enabled.
*/
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT (29U)
/*! DBGE - Debug Enable
* 0b0..Receiver is disabled in Debug mode, after completing the current frame.
* 0b1..Receiver is enabled in Debug mode.
*/
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT (30U)
/*! STOPE - Stop Enable
* 0b0..Receiver disabled in Stop mode.
* 0b1..Receiver enabled in Stop mode.
*/
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK (0x80000000U)
#define I2S_RCSR_RE_SHIFT (31U)
/*! RE - Receiver Enable
* 0b0..Receiver is disabled.
* 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
*/
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */
/*! @name RCR1 - SAI Receive Configuration 1 Register */
/*! @{ */
#define I2S_RCR1_RFW_MASK (0x7FU)
#define I2S_RCR1_RFW_SHIFT (0U)
/*! RFW - Receive FIFO Watermark
*/
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */
/*! @name RCR2 - SAI Receive Configuration 2 Register */
/*! @{ */
#define I2S_RCR2_DIV_MASK (0xFFU)
#define I2S_RCR2_DIV_SHIFT (0U)
/*! DIV - Bit Clock Divide
*/
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BYP_MASK (0x800000U)
#define I2S_RCR2_BYP_SHIFT (23U)
/*! BYP - Bit Clock Bypass
* 0b0..Internal bit clock is generated from bit clock divider.
* 0b1..Internal bit clock is divide by one of the audio master clock.
*/
#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
#define I2S_RCR2_BCD_MASK (0x1000000U)
#define I2S_RCR2_BCD_SHIFT (24U)
/*! BCD - Bit Clock Direction
* 0b0..Bit clock is generated externally in Slave mode.
* 0b1..Bit clock is generated internally in Master mode.
*/
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK (0x2000000U)
#define I2S_RCR2_BCP_SHIFT (25U)
/*! BCP - Bit Clock Polarity
* 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
* 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
*/
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT (26U)
/*! MSEL - MCLK Select
* 0b00..Bus Clock selected.
* 0b01..Master Clock (MCLK) 1 option selected.
* 0b10..Master Clock (MCLK) 2 option selected.
* 0b11..Master Clock (MCLK) 3 option selected.
*/
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK (0x10000000U)
#define I2S_RCR2_BCI_SHIFT (28U)
/*! BCI - Bit Clock Input
* 0b0..No effect.
* 0b1..Internal logic is clocked as if bit clock was externally generated.
*/
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK (0x20000000U)
#define I2S_RCR2_BCS_SHIFT (29U)
/*! BCS - Bit Clock Swap
* 0b0..Use the normal bit clock source.
* 0b1..Swap the bit clock source.
*/
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK (0xC0000000U)
#define I2S_RCR2_SYNC_SHIFT (30U)
/*! SYNC - Synchronous Mode
* 0b00..Asynchronous mode.
* 0b01..Synchronous with transmitter.
* 0b10..Reserved.
* 0b11..Reserved.
*/
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @} */
/*! @name RCR3 - SAI Receive Configuration 3 Register */
/*! @{ */
#define I2S_RCR3_WDFL_MASK (0x1FU)
#define I2S_RCR3_WDFL_SHIFT (0U)
/*! WDFL - Word Flag Configuration
*/
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK (0xFF0000U)
#define I2S_RCR3_RCE_SHIFT (16U)
/*! RCE - Receive Channel Enable
*/
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
#define I2S_RCR3_CFR_MASK (0xFF000000U)
#define I2S_RCR3_CFR_SHIFT (24U)
/*! CFR - Channel FIFO Reset
*/
#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
/*! @} */
/*! @name RCR4 - SAI Receive Configuration 4 Register */
/*! @{ */
#define I2S_RCR4_FSD_MASK (0x1U)
#define I2S_RCR4_FSD_SHIFT (0U)
/*! FSD - Frame Sync Direction
* 0b0..Frame Sync is generated externally in Slave mode.
* 0b1..Frame Sync is generated internally in Master mode.
*/
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK (0x2U)
#define I2S_RCR4_FSP_SHIFT (1U)
/*! FSP - Frame Sync Polarity
* 0b0..Frame sync is active high.
* 0b1..Frame sync is active low.
*/
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK (0x4U)
#define I2S_RCR4_ONDEM_SHIFT (2U)
/*! ONDEM - On Demand Mode
* 0b0..Internal frame sync is generated continuously.
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
*/
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK (0x8U)
#define I2S_RCR4_FSE_SHIFT (3U)
/*! FSE - Frame Sync Early
* 0b0..Frame sync asserts with the first bit of the frame.
* 0b1..Frame sync asserts one bit before the first bit of the frame.
*/
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK (0x10U)
#define I2S_RCR4_MF_SHIFT (4U)
/*! MF - MSB First
* 0b0..LSB is received first.
* 0b1..MSB is received first.
*/
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT (8U)
/*! SYWD - Sync Width
*/
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
#define I2S_RCR4_FRSZ_SHIFT (16U)
/*! FRSZ - Frame Size
*/
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT (24U)
/*! FPACK - FIFO Packing Mode
* 0b00..FIFO packing is disabled
* 0b01..Reserved.
* 0b10..8-bit FIFO packing is enabled
* 0b11..16-bit FIFO packing is enabled
*/
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCOMB_MASK (0xC000000U)
#define I2S_RCR4_FCOMB_SHIFT (26U)
/*! FCOMB - FIFO Combine Mode
* 0b00..FIFO combine mode disabled.
* 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
* 0b10..FIFO combine mode enabled on FIFO reads (by software).
* 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
*/
#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define I2S_RCR4_FCONT_MASK (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT (28U)
/*! FCONT - FIFO Continue on Error
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
*/
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */
/*! @name RCR5 - SAI Receive Configuration 5 Register */
/*! @{ */
#define I2S_RCR5_FBT_MASK (0x1F00U)
#define I2S_RCR5_FBT_SHIFT (8U)
/*! FBT - First Bit Shifted
*/
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT (16U)
/*! W0W - Word 0 Width
*/
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT (24U)
/*! WNW - Word N Width
*/
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */
/*! @name RDR - SAI Receive Data Register */
/*! @{ */
#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT (0U)
/*! RDR - Receive Data Register
*/
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */
/* The count of I2S_RDR */
#define I2S_RDR_COUNT (8U)
/*! @name RFR - SAI Receive FIFO Register */
/*! @{ */
#define I2S_RFR_RFP_MASK (0xFFU)
#define I2S_RFR_RFP_SHIFT (0U)
/*! RFP - Read FIFO Pointer
*/
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define I2S_RFR_RCP_MASK (0x8000U)
#define I2S_RFR_RCP_SHIFT (15U)
/*! RCP - Receive Channel Pointer
* 0b0..No effect.
* 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
*/
#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define I2S_RFR_WFP_MASK (0xFF0000U)
#define I2S_RFR_WFP_SHIFT (16U)
/*! WFP - Write FIFO Pointer
*/
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */
/* The count of I2S_RFR */
#define I2S_RFR_COUNT (8U)
/*! @name RMR - SAI Receive Mask Register */
/*! @{ */
#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
#define I2S_RMR_RWM_SHIFT (0U)
/*! RWM - Receive Word Mask
* 0b00000000000000000000000000000000..Word N is enabled.
* 0b00000000000000000000000000000001..Word N is masked.
*/
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*! @} */
/*! @name RTCR - SAI Receive Timestamp Control Register */
/*! @{ */
#define I2S_RTCR_TSEN_MASK (0x1U)
#define I2S_RTCR_TSEN_SHIFT (0U)
/*! TSEN - Timestamp Enable
* 0b0..Timestamp counter is disabled.
* 0b1..Timestamp counter is enabled.
*/
#define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK)
#define I2S_RTCR_TSINC_MASK (0x2U)
#define I2S_RTCR_TSINC_SHIFT (1U)
/*! TSINC - Timestamp Increment
* 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
* 0b1..Timestamp counter starts to increment when enabled.
*/
#define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK)
#define I2S_RTCR_RTSC_MASK (0x100U)
#define I2S_RTCR_RTSC_SHIFT (8U)
/*! RTSC - Reset Timestamp Counter
* 0b0..Timestamp counter is not reset.
* 0b1..Timestamp counter is reset.
*/
#define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK)
#define I2S_RTCR_RBC_MASK (0x200U)
#define I2S_RTCR_RBC_SHIFT (9U)
/*! RBC - Reset Bit Counter
* 0b0..Bit counter is not reset.
* 0b1..Bit counter is reset.
*/
#define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK)
/*! @} */
/*! @name RTSR - SAI Receive Timestamp Register */
/*! @{ */
#define I2S_RTSR_TSC_MASK (0xFFFFFFFFU)
#define I2S_RTSR_TSC_SHIFT (0U)
/*! TSC - Timestamp Counter
*/
#define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK)
/*! @} */
/*! @name RBCR - SAI Receive Bit Count Register */
/*! @{ */
#define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU)
#define I2S_RBCR_BCNT_SHIFT (0U)
/*! BCNT - Bit Counter
*/
#define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK)
/*! @} */
/*! @name RBCTR - SAI Receive Bit Count Timestamp Register */
/*! @{ */
#define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU)
#define I2S_RBCTR_BCTS_SHIFT (0U)
/*! BCTS - Bit Timestamp
*/
#define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK)
/*! @} */
/*! @name MCR - SAI MCLK Control Register */
/*! @{ */
#define I2S_MCR_DIV_MASK (0xFFU)
#define I2S_MCR_DIV_SHIFT (0U)
/*! DIV - MCLK Post Divide
*/
#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK)
#define I2S_MCR_DIVEN_MASK (0x800000U)
#define I2S_MCR_DIVEN_SHIFT (23U)
/*! DIVEN - MCLK Post Divide Enable
* 0b0..Output on MCLK signal pin is the audio master clock.
* 0b1..Output on MCLK signal pin is a post-divided version of audio master clock.
*/
#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK)
#define I2S_MCR_MOE_MASK (0x40000000U)
#define I2S_MCR_MOE_SHIFT (30U)
/*! MOE - MCLK Output Enable
* 0b0..MCLK signal pin is an input.
* 0b1..MCLK signal pin is an output.
*/
#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral I2S1 base address */
#define I2S1_BASE (0x30C10000u)
/** Peripheral I2S1 base pointer */
#define I2S1 ((I2S_Type *)I2S1_BASE)
/** Peripheral I2S2 base address */
#define I2S2_BASE (0x30C20000u)
/** Peripheral I2S2 base pointer */
#define I2S2 ((I2S_Type *)I2S2_BASE)
/** Peripheral I2S3 base address */
#define I2S3_BASE (0x30C30000u)
/** Peripheral I2S3 base pointer */
#define I2S3 ((I2S_Type *)I2S3_BASE)
/** Peripheral I2S5 base address */
#define I2S5_BASE (0x30C50000u)
/** Peripheral I2S5 base pointer */
#define I2S5 ((I2S_Type *)I2S5_BASE)
/** Peripheral I2S6 base address */
#define I2S6_BASE (0x30C60000u)
/** Peripheral I2S6 base pointer */
#define I2S6 ((I2S_Type *)I2S6_BASE)
/** Peripheral I2S7 base address */
#define I2S7_BASE (0x30C80000u)
/** Peripheral I2S7 base pointer */
#define I2S7 ((I2S_Type *)I2S7_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE, 0u, I2S5_BASE, I2S6_BASE, I2S7_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3, (I2S_Type *)0u, I2S5, I2S6, I2S7 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn }
#define I2S_TX_IRQS { NotAvail_IRQn, I2S1_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn }
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IDENTIFICATION Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IDENTIFICATION_Peripheral_Access_Layer IDENTIFICATION Peripheral Access Layer
* @{
*/
/** IDENTIFICATION - Register Layout Typedef */
typedef struct {
__I uint8_t DESIGN_ID; /**< Design Identification Register, offset: 0x0 */
__I uint8_t REVISION_ID; /**< Revision Identification Register, offset: 0x1 */
__I uint8_t PRODUCT_ID0; /**< Product Identification Register 0, offset: 0x2 */
__I uint8_t PRODUCT_ID1; /**< Product Identification Register 1, offset: 0x3 */
__I uint8_t CONFIG0_ID; /**< Configuration Identification Register 0, offset: 0x4 */
__I uint8_t CONFIG1_ID; /**< Configuration Identification Register 1, offset: 0x5 */
__I uint8_t CONFIG2_ID; /**< Configuration Identification Register 2, offset: 0x6 */
__I uint8_t CONFIG3_ID; /**< Configuration Identification Register 3, offset: 0x7 */
} IDENTIFICATION_Type;
/* ----------------------------------------------------------------------------
-- IDENTIFICATION Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IDENTIFICATION_Register_Masks IDENTIFICATION Register Masks
* @{
*/
/*! @name DESIGN_ID - Design Identification Register */
/*! @{ */
#define IDENTIFICATION_DESIGN_ID_design_id_MASK (0xFFU)
#define IDENTIFICATION_DESIGN_ID_design_id_SHIFT (0U)
/*! design_id - Design ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller.
*/
#define IDENTIFICATION_DESIGN_ID_design_id(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_DESIGN_ID_design_id_SHIFT)) & IDENTIFICATION_DESIGN_ID_design_id_MASK)
/*! @} */
/*! @name REVISION_ID - Revision Identification Register */
/*! @{ */
#define IDENTIFICATION_REVISION_ID_revision_id_MASK (0xFFU)
#define IDENTIFICATION_REVISION_ID_revision_id_SHIFT (0U)
/*! revision_id - Revision ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller.
*/
#define IDENTIFICATION_REVISION_ID_revision_id(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_REVISION_ID_revision_id_SHIFT)) & IDENTIFICATION_REVISION_ID_revision_id_MASK)
/*! @} */
/*! @name PRODUCT_ID0 - Product Identification Register 0 */
/*! @{ */
#define IDENTIFICATION_PRODUCT_ID0_product_id0_MASK (0xFFU)
#define IDENTIFICATION_PRODUCT_ID0_product_id0_SHIFT (0U)
/*! product_id0 - This one byte fixed code Identifies Synopsys's product line ("A0h" for DWC_hdmi_tx products).
*/
#define IDENTIFICATION_PRODUCT_ID0_product_id0(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID0_product_id0_SHIFT)) & IDENTIFICATION_PRODUCT_ID0_product_id0_MASK)
/*! @} */
/*! @name PRODUCT_ID1 - Product Identification Register 1 */
/*! @{ */
#define IDENTIFICATION_PRODUCT_ID1_product_id1_tx_MASK (0x1U)
#define IDENTIFICATION_PRODUCT_ID1_product_id1_tx_SHIFT (0U)
/*! product_id1_tx - This bit Identifies Synopsys's DWC_hdmi_tx Controller according to Synopsys product line.
*/
#define IDENTIFICATION_PRODUCT_ID1_product_id1_tx(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_tx_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_tx_MASK)
#define IDENTIFICATION_PRODUCT_ID1_product_id1_rx_MASK (0x2U)
#define IDENTIFICATION_PRODUCT_ID1_product_id1_rx_SHIFT (1U)
/*! product_id1_rx - This bit Identifies Synopsys's DWC_hdmi_rx Controller according to Synopsys product line.
*/
#define IDENTIFICATION_PRODUCT_ID1_product_id1_rx(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_rx_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_rx_MASK)
#define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_MASK (0xC0U)
#define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_SHIFT (6U)
/*! product_id1_hdcp - These bits identify a Synopsys's HDMI Controller with HDCP encryption according to Synopsys product line.
*/
#define IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_SHIFT)) & IDENTIFICATION_PRODUCT_ID1_product_id1_hdcp_MASK)
/*! @} */
/*! @name CONFIG0_ID - Configuration Identification Register 0 */
/*! @{ */
#define IDENTIFICATION_CONFIG0_ID_hdcp_MASK (0x1U)
#define IDENTIFICATION_CONFIG0_ID_hdcp_SHIFT (0U)
/*! hdcp - Indicates if HDCP is present
*/
#define IDENTIFICATION_CONFIG0_ID_hdcp(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_hdcp_SHIFT)) & IDENTIFICATION_CONFIG0_ID_hdcp_MASK)
#define IDENTIFICATION_CONFIG0_ID_cec_MASK (0x2U)
#define IDENTIFICATION_CONFIG0_ID_cec_SHIFT (1U)
/*! cec - Indicates if CEC is present
*/
#define IDENTIFICATION_CONFIG0_ID_cec(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_cec_SHIFT)) & IDENTIFICATION_CONFIG0_ID_cec_MASK)
#define IDENTIFICATION_CONFIG0_ID_csc_MASK (0x4U)
#define IDENTIFICATION_CONFIG0_ID_csc_SHIFT (2U)
/*! csc - Indicates if Color Space Conversion block is present
*/
#define IDENTIFICATION_CONFIG0_ID_csc(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_csc_SHIFT)) & IDENTIFICATION_CONFIG0_ID_csc_MASK)
#define IDENTIFICATION_CONFIG0_ID_hdmi14_MASK (0x8U)
#define IDENTIFICATION_CONFIG0_ID_hdmi14_SHIFT (3U)
/*! hdmi14 - Indicates if HDMI 1.
*/
#define IDENTIFICATION_CONFIG0_ID_hdmi14(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_hdmi14_SHIFT)) & IDENTIFICATION_CONFIG0_ID_hdmi14_MASK)
#define IDENTIFICATION_CONFIG0_ID_audi2s_MASK (0x10U)
#define IDENTIFICATION_CONFIG0_ID_audi2s_SHIFT (4U)
/*! audi2s - Indicates if I2S interface is present
*/
#define IDENTIFICATION_CONFIG0_ID_audi2s(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_audi2s_SHIFT)) & IDENTIFICATION_CONFIG0_ID_audi2s_MASK)
#define IDENTIFICATION_CONFIG0_ID_audspdif_MASK (0x20U)
#define IDENTIFICATION_CONFIG0_ID_audspdif_SHIFT (5U)
/*! audspdif - Indicates if the SPDIF audio interface is present
*/
#define IDENTIFICATION_CONFIG0_ID_audspdif(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_audspdif_SHIFT)) & IDENTIFICATION_CONFIG0_ID_audspdif_MASK)
#define IDENTIFICATION_CONFIG0_ID_prepen_MASK (0x80U)
#define IDENTIFICATION_CONFIG0_ID_prepen_SHIFT (7U)
/*! prepen - Indicates if it is possible to use internal pixel repetition
*/
#define IDENTIFICATION_CONFIG0_ID_prepen(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG0_ID_prepen_SHIFT)) & IDENTIFICATION_CONFIG0_ID_prepen_MASK)
/*! @} */
/*! @name CONFIG1_ID - Configuration Identification Register 1 */
/*! @{ */
#define IDENTIFICATION_CONFIG1_ID_confapb_MASK (0x2U)
#define IDENTIFICATION_CONFIG1_ID_confapb_SHIFT (1U)
/*! confapb - Indicates that configuration interface is APB interface
*/
#define IDENTIFICATION_CONFIG1_ID_confapb(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_confapb_SHIFT)) & IDENTIFICATION_CONFIG1_ID_confapb_MASK)
#define IDENTIFICATION_CONFIG1_ID_hdmi20_MASK (0x20U)
#define IDENTIFICATION_CONFIG1_ID_hdmi20_SHIFT (5U)
/*! hdmi20 - Indicates if HDMI 2.
*/
#define IDENTIFICATION_CONFIG1_ID_hdmi20(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_hdmi20_SHIFT)) & IDENTIFICATION_CONFIG1_ID_hdmi20_MASK)
#define IDENTIFICATION_CONFIG1_ID_hdcp22_ext_MASK (0x40U)
#define IDENTIFICATION_CONFIG1_ID_hdcp22_ext_SHIFT (6U)
/*! hdcp22_ext - Indicates if external HDCP 2.
*/
#define IDENTIFICATION_CONFIG1_ID_hdcp22_ext(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG1_ID_hdcp22_ext_SHIFT)) & IDENTIFICATION_CONFIG1_ID_hdcp22_ext_MASK)
/*! @} */
/*! @name CONFIG2_ID - Configuration Identification Register 2 */
/*! @{ */
#define IDENTIFICATION_CONFIG2_ID_phytype_MASK (0xFFU)
#define IDENTIFICATION_CONFIG2_ID_phytype_SHIFT (0U)
/*! phytype - Indicates the type of PHY interface selected: 0x00: Legacy PHY (HDMI TX PHY) 0xF2: PHY
* GEN2 (HDMI 3D TX PHY) 0xE2: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY 0xC2: PHY MHL COMBO
* (MHL+HDMI 2.
*/
#define IDENTIFICATION_CONFIG2_ID_phytype(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG2_ID_phytype_SHIFT)) & IDENTIFICATION_CONFIG2_ID_phytype_MASK)
/*! @} */
/*! @name CONFIG3_ID - Configuration Identification Register 3 */
/*! @{ */
#define IDENTIFICATION_CONFIG3_ID_confgpaud_MASK (0x1U)
#define IDENTIFICATION_CONFIG3_ID_confgpaud_SHIFT (0U)
/*! confgpaud - Indicates that the audio interface is Generic Parallel Audio (GPAUD)
*/
#define IDENTIFICATION_CONFIG3_ID_confgpaud(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG3_ID_confgpaud_SHIFT)) & IDENTIFICATION_CONFIG3_ID_confgpaud_MASK)
#define IDENTIFICATION_CONFIG3_ID_confahbauddma_MASK (0x2U)
#define IDENTIFICATION_CONFIG3_ID_confahbauddma_SHIFT (1U)
/*! confahbauddma - Indicates that the audio interface is AHB AUD DMA
*/
#define IDENTIFICATION_CONFIG3_ID_confahbauddma(x) (((uint8_t)(((uint8_t)(x)) << IDENTIFICATION_CONFIG3_ID_confahbauddma_SHIFT)) & IDENTIFICATION_CONFIG3_ID_confahbauddma_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IDENTIFICATION_Register_Masks */
/* IDENTIFICATION - Peripheral instance base addresses */
/** Peripheral IDENTIFICATION base address */
#define IDENTIFICATION_BASE (0x32FD8000u)
/** Peripheral IDENTIFICATION base pointer */
#define IDENTIFICATION ((IDENTIFICATION_Type *)IDENTIFICATION_BASE)
/** Array initializer of IDENTIFICATION peripheral base addresses */
#define IDENTIFICATION_BASE_ADDRS { IDENTIFICATION_BASE }
/** Array initializer of IDENTIFICATION peripheral base pointers */
#define IDENTIFICATION_BASE_PTRS { IDENTIFICATION }
/*!
* @}
*/ /* end of group IDENTIFICATION_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- INTERRUPT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTERRUPT_Peripheral_Access_Layer INTERRUPT Peripheral Access Layer
* @{
*/
/** INTERRUPT - Register Layout Typedef */
typedef struct {
__IO uint8_t IH_FC_STAT0; /**< Frame Composer Interrupt Status Register 0 (Packet Interrupts), offset: 0x0 */
__IO uint8_t IH_FC_STAT1; /**< Frame Composer Interrupt Status Register 1 (Packet Interrupts), offset: 0x1 */
__IO uint8_t IH_FC_STAT2; /**< Frame Composer Interrupt Status Register 2 (Packet Interrupts), offset: 0x2 */
__IO uint8_t IH_AS_STAT0; /**< Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and Overflow Interrupts), offset: 0x3 */
__IO uint8_t IH_PHY_STAT0; /**< PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD Interrupts), offset: 0x4 */
__IO uint8_t IH_I2CM_STAT0; /**< E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts), offset: 0x5 */
__IO uint8_t IH_CEC_STAT0; /**< CEC Interrupt Status Register (Functional Operation Interrupts), offset: 0x6 */
__IO uint8_t IH_VP_STAT0; /**< Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts), offset: 0x7 */
__IO uint8_t IH_I2CMPHY_STAT0; /**< PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts), offset: 0x8 */
uint8_t RESERVED_0[103];
__I uint8_t IH_DECODE; /**< Interruption Handler Decode Assist Register, offset: 0x70 */
uint8_t RESERVED_1[15];
__IO uint8_t IH_MUTE_FC_STAT0; /**< Frame Composer Interrupt Mute Control Register 0, offset: 0x80 */
__IO uint8_t IH_MUTE_FC_STAT1; /**< Frame Composer Interrupt Mute Control Register 1, offset: 0x81 */
__IO uint8_t IH_MUTE_FC_STAT2; /**< Frame Composer Interrupt Mute Control Register 2, offset: 0x82 */
__IO uint8_t IH_MUTE_AS_STAT0; /**< Audio Sampler Interrupt Mute Control Register, offset: 0x83 */
__IO uint8_t IH_MUTE_PHY_STAT0; /**< PHY Interface Interrupt Mute Control Register, offset: 0x84 */
__IO uint8_t IH_MUTE_I2CM_STAT0; /**< E-DDC I2C Master Interrupt Mute Control Register, offset: 0x85 */
__IO uint8_t IH_MUTE_CEC_STAT0; /**< CEC Interrupt Mute Control Register, offset: 0x86 */
__IO uint8_t IH_MUTE_VP_STAT0; /**< Video Packetizer Interrupt Mute Control Register, offset: 0x87 */
__IO uint8_t IH_MUTE_I2CMPHY_STAT0; /**< PHY GEN2 I2C Master Interrupt Mute Control Register, offset: 0x88 */
uint8_t RESERVED_2[118];
__IO uint8_t IH_MUTE; /**< Global Interrupt Mute Control Register, offset: 0xFF */
} INTERRUPT_Type;
/* ----------------------------------------------------------------------------
-- INTERRUPT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup INTERRUPT_Register_Masks INTERRUPT Register Masks
* @{
*/
/*! @name IH_FC_STAT0 - Frame Composer Interrupt Status Register 0 (Packet Interrupts) */
/*! @{ */
#define INTERRUPT_IH_FC_STAT0_NULL_MASK (0x1U)
#define INTERRUPT_IH_FC_STAT0_NULL_SHIFT (0U)
/*! NULL - Active after successful transmission of an Null packet.
*/
#define INTERRUPT_IH_FC_STAT0_NULL(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_NULL_SHIFT)) & INTERRUPT_IH_FC_STAT0_NULL_MASK)
#define INTERRUPT_IH_FC_STAT0_ACR_MASK (0x2U)
#define INTERRUPT_IH_FC_STAT0_ACR_SHIFT (1U)
/*! ACR - Active after successful transmission of an Audio Clock Regeneration (N/CTS transmission) packet.
*/
#define INTERRUPT_IH_FC_STAT0_ACR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_ACR_SHIFT)) & INTERRUPT_IH_FC_STAT0_ACR_MASK)
#define INTERRUPT_IH_FC_STAT0_AUDS_MASK (0x4U)
#define INTERRUPT_IH_FC_STAT0_AUDS_SHIFT (2U)
/*! AUDS - Active after successful transmission of an Audio Sample packet.
*/
#define INTERRUPT_IH_FC_STAT0_AUDS(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_AUDS_SHIFT)) & INTERRUPT_IH_FC_STAT0_AUDS_MASK)
#define INTERRUPT_IH_FC_STAT0_NVBI_MASK (0x8U)
#define INTERRUPT_IH_FC_STAT0_NVBI_SHIFT (3U)
/*! NVBI - Active after successful transmission of an NTSC VBI packet
*/
#define INTERRUPT_IH_FC_STAT0_NVBI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_NVBI_SHIFT)) & INTERRUPT_IH_FC_STAT0_NVBI_MASK)
#define INTERRUPT_IH_FC_STAT0_MAS_MASK (0x10U)
#define INTERRUPT_IH_FC_STAT0_MAS_SHIFT (4U)
/*! MAS - Active after successful transmission of an MultiStream Audio packet
*/
#define INTERRUPT_IH_FC_STAT0_MAS(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_MAS_SHIFT)) & INTERRUPT_IH_FC_STAT0_MAS_MASK)
#define INTERRUPT_IH_FC_STAT0_HBR_MASK (0x20U)
#define INTERRUPT_IH_FC_STAT0_HBR_SHIFT (5U)
/*! HBR - Active after successful transmission of an Audio HBR packet.
*/
#define INTERRUPT_IH_FC_STAT0_HBR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_HBR_SHIFT)) & INTERRUPT_IH_FC_STAT0_HBR_MASK)
#define INTERRUPT_IH_FC_STAT0_ACP_MASK (0x40U)
#define INTERRUPT_IH_FC_STAT0_ACP_SHIFT (6U)
/*! ACP - Active after successful transmission of an Audio Content Protection packet.
*/
#define INTERRUPT_IH_FC_STAT0_ACP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_ACP_SHIFT)) & INTERRUPT_IH_FC_STAT0_ACP_MASK)
#define INTERRUPT_IH_FC_STAT0_AUDI_MASK (0x80U)
#define INTERRUPT_IH_FC_STAT0_AUDI_SHIFT (7U)
/*! AUDI - Active after successful transmission of an Audio InfoFrame packet.
*/
#define INTERRUPT_IH_FC_STAT0_AUDI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT0_AUDI_SHIFT)) & INTERRUPT_IH_FC_STAT0_AUDI_MASK)
/*! @} */
/*! @name IH_FC_STAT1 - Frame Composer Interrupt Status Register 1 (Packet Interrupts) */
/*! @{ */
#define INTERRUPT_IH_FC_STAT1_GCP_MASK (0x1U)
#define INTERRUPT_IH_FC_STAT1_GCP_SHIFT (0U)
/*! GCP - Active after successful transmission of an General Control Packet.
*/
#define INTERRUPT_IH_FC_STAT1_GCP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_GCP_SHIFT)) & INTERRUPT_IH_FC_STAT1_GCP_MASK)
#define INTERRUPT_IH_FC_STAT1_AVI_MASK (0x2U)
#define INTERRUPT_IH_FC_STAT1_AVI_SHIFT (1U)
/*! AVI - Active after successful transmission of an AVI InfoFrame packet.
*/
#define INTERRUPT_IH_FC_STAT1_AVI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_AVI_SHIFT)) & INTERRUPT_IH_FC_STAT1_AVI_MASK)
#define INTERRUPT_IH_FC_STAT1_AMP_MASK (0x4U)
#define INTERRUPT_IH_FC_STAT1_AMP_SHIFT (2U)
/*! AMP - Active after successful transmission of an Audio Metadata packet
*/
#define INTERRUPT_IH_FC_STAT1_AMP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_AMP_SHIFT)) & INTERRUPT_IH_FC_STAT1_AMP_MASK)
#define INTERRUPT_IH_FC_STAT1_SPD_MASK (0x8U)
#define INTERRUPT_IH_FC_STAT1_SPD_SHIFT (3U)
/*! SPD - Active after successful transmission of an Source Product Descriptor InfoFrame packet.
*/
#define INTERRUPT_IH_FC_STAT1_SPD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_SPD_SHIFT)) & INTERRUPT_IH_FC_STAT1_SPD_MASK)
#define INTERRUPT_IH_FC_STAT1_VSD_MASK (0x10U)
#define INTERRUPT_IH_FC_STAT1_VSD_SHIFT (4U)
/*! VSD - Active after successful transmission of an Vendor Specific Data InfoFrame packet.
*/
#define INTERRUPT_IH_FC_STAT1_VSD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_VSD_SHIFT)) & INTERRUPT_IH_FC_STAT1_VSD_MASK)
#define INTERRUPT_IH_FC_STAT1_ISCR2_MASK (0x20U)
#define INTERRUPT_IH_FC_STAT1_ISCR2_SHIFT (5U)
/*! ISCR2 - Active after successful transmission of an International Standard Recording Code 2 packet
*/
#define INTERRUPT_IH_FC_STAT1_ISCR2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_ISCR2_SHIFT)) & INTERRUPT_IH_FC_STAT1_ISCR2_MASK)
#define INTERRUPT_IH_FC_STAT1_ISCR1_MASK (0x40U)
#define INTERRUPT_IH_FC_STAT1_ISCR1_SHIFT (6U)
/*! ISCR1 - Active after successful transmission of an International Standard Recording Code 1 packet.
*/
#define INTERRUPT_IH_FC_STAT1_ISCR1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_ISCR1_SHIFT)) & INTERRUPT_IH_FC_STAT1_ISCR1_MASK)
#define INTERRUPT_IH_FC_STAT1_GMD_MASK (0x80U)
#define INTERRUPT_IH_FC_STAT1_GMD_SHIFT (7U)
/*! GMD - Active after successful transmission of an Gamut metadata packet.
*/
#define INTERRUPT_IH_FC_STAT1_GMD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT1_GMD_SHIFT)) & INTERRUPT_IH_FC_STAT1_GMD_MASK)
/*! @} */
/*! @name IH_FC_STAT2 - Frame Composer Interrupt Status Register 2 (Packet Interrupts) */
/*! @{ */
#define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
#define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
/*! HighPriority_overflow - Frame Composer high priority packet queue descriptor overflow indication
*/
#define INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK)
#define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
#define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
/*! LowPriority_overflow - Frame Composer low priority packet queue descriptor overflow indication
*/
#define INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK)
#define INTERRUPT_IH_FC_STAT2_DRM_MASK (0x10U)
#define INTERRUPT_IH_FC_STAT2_DRM_SHIFT (4U)
/*! DRM - Active after successful transmission of an DRM packet
*/
#define INTERRUPT_IH_FC_STAT2_DRM(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_FC_STAT2_DRM_SHIFT)) & INTERRUPT_IH_FC_STAT2_DRM_MASK)
/*! @} */
/*! @name IH_AS_STAT0 - Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and Overflow Interrupts) */
/*! @{ */
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_MASK (0x1U)
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT (0U)
/*! Aud_fifo_overflow - Audio Sampler audio FIFO full indication.
*/
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_OVERFLOW_MASK)
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK (0x2U)
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT (1U)
/*! Aud_fifo_underflow - Audio Sampler audio FIFO empty indication.
*/
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK)
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK (0x4U)
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT (2U)
/*! Aud_fifo_underflow_thr - Audio Sampler audio FIFO empty threshold (four samples) indication for the legacy HBR audio interface.
*/
#define INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT)) & INTERRUPT_IH_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK)
#define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_MASK (0x8U)
#define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_SHIFT (3U)
/*! fifo_overrun - Indicates an overrun on the audio FIFO.
*/
#define INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_SHIFT)) & INTERRUPT_IH_AS_STAT0_FIFO_OVERRUN_MASK)
/*! @} */
/*! @name IH_PHY_STAT0 - PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD Interrupts) */
/*! @{ */
#define INTERRUPT_IH_PHY_STAT0_HPD_MASK (0x1U)
#define INTERRUPT_IH_PHY_STAT0_HPD_SHIFT (0U)
/*! HPD - HDMI Hot Plug Detect indication.
*/
#define INTERRUPT_IH_PHY_STAT0_HPD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_HPD_SHIFT)) & INTERRUPT_IH_PHY_STAT0_HPD_MASK)
#define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_MASK (0x2U)
#define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_SHIFT (1U)
/*! TX_PHY_LOCK - TX PHY PLL lock indication.
*/
#define INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & INTERRUPT_IH_PHY_STAT0_TX_PHY_LOCK_MASK)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_MASK (0x4U)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_SHIFT (2U)
/*! RX_SENSE_0 - TX PHY RX_SENSE indication for driver 0.
*/
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_0_MASK)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_MASK (0x8U)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_SHIFT (3U)
/*! RX_SENSE_1 - TX PHY RX_SENSE indication for driver 1.
*/
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_1_MASK)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_MASK (0x10U)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_SHIFT (4U)
/*! RX_SENSE_2 - TX PHY RX_SENSE indication for driver 2.
*/
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_2_MASK)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_MASK (0x20U)
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_SHIFT (5U)
/*! RX_SENSE_3 - TX PHY RX_SENSE indication for driver 3.
*/
#define INTERRUPT_IH_PHY_STAT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_SHIFT)) & INTERRUPT_IH_PHY_STAT0_RX_SENSE_3_MASK)
/*! @} */
/*! @name IH_I2CM_STAT0 - E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts) */
/*! @{ */
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_MASK (0x1U)
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_SHIFT (0U)
/*! I2Cmastererror - I2C Master error indication
*/
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_I2CMASTERERROR_MASK)
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_MASK (0x2U)
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_SHIFT (1U)
/*! I2Cmasterdone - I2C Master done indication
*/
#define INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_I2CMASTERDONE_MASK)
#define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_MASK (0x4U)
#define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_SHIFT (2U)
/*! scdc_readreq - I2C Master SCDC read request indication.
*/
#define INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_SHIFT)) & INTERRUPT_IH_I2CM_STAT0_SCDC_READREQ_MASK)
/*! @} */
/*! @name IH_CEC_STAT0 - CEC Interrupt Status Register (Functional Operation Interrupts) */
/*! @{ */
#define INTERRUPT_IH_CEC_STAT0_DONE_MASK (0x1U)
#define INTERRUPT_IH_CEC_STAT0_DONE_SHIFT (0U)
/*! DONE - CEC Done Indication
*/
#define INTERRUPT_IH_CEC_STAT0_DONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_DONE_SHIFT)) & INTERRUPT_IH_CEC_STAT0_DONE_MASK)
#define INTERRUPT_IH_CEC_STAT0_EOM_MASK (0x2U)
#define INTERRUPT_IH_CEC_STAT0_EOM_SHIFT (1U)
/*! EOM - CEC End of Message Indication
*/
#define INTERRUPT_IH_CEC_STAT0_EOM(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_EOM_SHIFT)) & INTERRUPT_IH_CEC_STAT0_EOM_MASK)
#define INTERRUPT_IH_CEC_STAT0_NACK_MASK (0x4U)
#define INTERRUPT_IH_CEC_STAT0_NACK_SHIFT (2U)
/*! NACK - CEC Not Acknowledge indication
*/
#define INTERRUPT_IH_CEC_STAT0_NACK(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_NACK_SHIFT)) & INTERRUPT_IH_CEC_STAT0_NACK_MASK)
#define INTERRUPT_IH_CEC_STAT0_ARB_LOST_MASK (0x8U)
#define INTERRUPT_IH_CEC_STAT0_ARB_LOST_SHIFT (3U)
/*! ARB_LOST - CEC Arbitration Lost indication
*/
#define INTERRUPT_IH_CEC_STAT0_ARB_LOST(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ARB_LOST_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ARB_LOST_MASK)
#define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_MASK (0x10U)
#define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_SHIFT (4U)
/*! ERROR_INITIATOR - CEC Error Initiator indication
*/
#define INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ERROR_INITIATOR_MASK)
#define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_MASK (0x20U)
#define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_SHIFT (5U)
/*! ERROR_FOLLOW - CEC Error Follow indication
*/
#define INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_SHIFT)) & INTERRUPT_IH_CEC_STAT0_ERROR_FOLLOW_MASK)
#define INTERRUPT_IH_CEC_STAT0_WAKEUP_MASK (0x40U)
#define INTERRUPT_IH_CEC_STAT0_WAKEUP_SHIFT (6U)
/*! WAKEUP - CEC Wake-up indication
*/
#define INTERRUPT_IH_CEC_STAT0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_CEC_STAT0_WAKEUP_SHIFT)) & INTERRUPT_IH_CEC_STAT0_WAKEUP_MASK)
/*! @} */
/*! @name IH_VP_STAT0 - Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts) */
/*! @{ */
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_MASK (0x4U)
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_SHIFT (2U)
/*! fifoemptyremap - Video Packetizer pixel YCbCr 422 re-mapper FIFO empty interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYREMAP_MASK)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_MASK (0x8U)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_SHIFT (3U)
/*! fifofullremap - Video Packetizer pixel YCbCr 422 re-mapper FIFO full interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLREMAP_MASK)
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_MASK (0x10U)
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_SHIFT (4U)
/*! fifoemptypp - Video Packetizer pixel packing FIFO empty interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYPP_MASK)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLPP_MASK (0x20U)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLPP_SHIFT (5U)
/*! fifofullpp - Video Packetizer pixel packing FIFO full interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOFULLPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLPP_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLPP_MASK)
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_MASK (0x40U)
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_SHIFT (6U)
/*! fifoemptyrepet - Video Packetizer pixel repeater FIFO empty interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOEMPTYREPET_MASK)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_MASK (0x80U)
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_SHIFT (7U)
/*! fifofullrepet - Video Packetizer pixel repeater FIFO full interrupt
*/
#define INTERRUPT_IH_VP_STAT0_FIFOFULLREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_SHIFT)) & INTERRUPT_IH_VP_STAT0_FIFOFULLREPET_MASK)
/*! @} */
/*! @name IH_I2CMPHY_STAT0 - PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts) */
/*! @{ */
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_MASK (0x1U)
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT (0U)
/*! I2Cmphyerror - I2C Master PHY error indication
*/
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT)) & INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYERROR_MASK)
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_MASK (0x2U)
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT (1U)
/*! I2Cmphydone - I2C Master PHY done indication
*/
#define INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT)) & INTERRUPT_IH_I2CMPHY_STAT0_I2CMPHYDONE_MASK)
/*! @} */
/*! @name IH_DECODE - Interruption Handler Decode Assist Register */
/*! @{ */
#define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_MASK (0x1U)
#define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_SHIFT (0U)
/*! ih_ahbdmaaud_stat0 - Interruption active at the ih_ahbdmaaud_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_AHBDMAAUD_STAT0_MASK)
#define INTERRUPT_IH_DECODE_IH_CEC_STAT0_MASK (0x2U)
#define INTERRUPT_IH_DECODE_IH_CEC_STAT0_SHIFT (1U)
/*! ih_cec_stat0 - Interruption active at the ih_cec_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_CEC_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_CEC_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_CEC_STAT0_MASK)
#define INTERRUPT_IH_DECODE_IH_I2CM_STAT0_MASK (0x4U)
#define INTERRUPT_IH_DECODE_IH_I2CM_STAT0_SHIFT (2U)
/*! ih_i2cm_stat0 - Interruption active at the ih_i2cm_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_I2CM_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_I2CM_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_I2CM_STAT0_MASK)
#define INTERRUPT_IH_DECODE_IH_PHY_MASK (0x8U)
#define INTERRUPT_IH_DECODE_IH_PHY_SHIFT (3U)
/*! ih_phy - Interruption active at the ih_phy_stat0 or ih_i2cmphy_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_PHY(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_PHY_SHIFT)) & INTERRUPT_IH_DECODE_IH_PHY_MASK)
#define INTERRUPT_IH_DECODE_IH_AS_STAT0_MASK (0x10U)
#define INTERRUPT_IH_DECODE_IH_AS_STAT0_SHIFT (4U)
/*! ih_as_stat0 - Interruption active at the ih_as_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_AS_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_AS_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_AS_STAT0_MASK)
#define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_MASK (0x20U)
#define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_SHIFT (5U)
/*! ih_fc_stat2_vp - Interruption active at the ih_fc_stat2 or ih_vp_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_FC_STAT2_VP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT2_VP_MASK)
#define INTERRUPT_IH_DECODE_IH_FC_STAT1_MASK (0x40U)
#define INTERRUPT_IH_DECODE_IH_FC_STAT1_SHIFT (6U)
/*! ih_fc_stat1 - Interruption active at the ih_fc_stat1 register
*/
#define INTERRUPT_IH_DECODE_IH_FC_STAT1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT1_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT1_MASK)
#define INTERRUPT_IH_DECODE_IH_FC_STAT0_MASK (0x80U)
#define INTERRUPT_IH_DECODE_IH_FC_STAT0_SHIFT (7U)
/*! ih_fc_stat0 - Interruption active at the ih_fc_stat0 register
*/
#define INTERRUPT_IH_DECODE_IH_FC_STAT0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_DECODE_IH_FC_STAT0_SHIFT)) & INTERRUPT_IH_DECODE_IH_FC_STAT0_MASK)
/*! @} */
/*! @name IH_MUTE_FC_STAT0 - Frame Composer Interrupt Mute Control Register 0 */
/*! @{ */
#define INTERRUPT_IH_MUTE_FC_STAT0_NULL_MASK (0x1U)
#define INTERRUPT_IH_MUTE_FC_STAT0_NULL_SHIFT (0U)
/*! NULL - When set to 1, mutes ih_fc_stat0[0]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_NULL(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_NULL_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_NULL_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_ACR_MASK (0x2U)
#define INTERRUPT_IH_MUTE_FC_STAT0_ACR_SHIFT (1U)
/*! ACR - When set to 1, mutes ih_fc_stat0[1]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_ACR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_ACR_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_ACR_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDS_MASK (0x4U)
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDS_SHIFT (2U)
/*! AUDS - When set to 1, mutes ih_fc_stat0[2]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDS(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_AUDS_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_AUDS_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_NVBI_MASK (0x8U)
#define INTERRUPT_IH_MUTE_FC_STAT0_NVBI_SHIFT (3U)
/*! NVBI - When set to 1, mutes ih_fc_stat0[3].
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_NVBI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_NVBI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_NVBI_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_MAS_MASK (0x10U)
#define INTERRUPT_IH_MUTE_FC_STAT0_MAS_SHIFT (4U)
/*! MAS - When set to 1, mutes ih_fc_stat0[4].
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_MAS(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_MAS_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_MAS_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_HBR_MASK (0x20U)
#define INTERRUPT_IH_MUTE_FC_STAT0_HBR_SHIFT (5U)
/*! HBR - When set to 1, mutes ih_fc_stat0[5]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_HBR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_HBR_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_HBR_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_ACP_MASK (0x40U)
#define INTERRUPT_IH_MUTE_FC_STAT0_ACP_SHIFT (6U)
/*! ACP - When set to 1, mutes ih_fc_stat0[6]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_ACP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_ACP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_ACP_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDI_MASK (0x80U)
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDI_SHIFT (7U)
/*! AUDI - When set to 1, mutes ih_fc_stat0[7]
*/
#define INTERRUPT_IH_MUTE_FC_STAT0_AUDI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT0_AUDI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT0_AUDI_MASK)
/*! @} */
/*! @name IH_MUTE_FC_STAT1 - Frame Composer Interrupt Mute Control Register 1 */
/*! @{ */
#define INTERRUPT_IH_MUTE_FC_STAT1_GCP_MASK (0x1U)
#define INTERRUPT_IH_MUTE_FC_STAT1_GCP_SHIFT (0U)
/*! GCP - When set to 1, mutes ih_fc_stat1[0]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_GCP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_GCP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_GCP_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_AVI_MASK (0x2U)
#define INTERRUPT_IH_MUTE_FC_STAT1_AVI_SHIFT (1U)
/*! AVI - When set to 1, mutes ih_fc_stat1[1]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_AVI(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_AVI_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_AVI_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_AMP_MASK (0x4U)
#define INTERRUPT_IH_MUTE_FC_STAT1_AMP_SHIFT (2U)
/*! AMP - When set to 1, mutes ih_fc_stat1[2].
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_AMP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_AMP_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_AMP_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_SPD_MASK (0x8U)
#define INTERRUPT_IH_MUTE_FC_STAT1_SPD_SHIFT (3U)
/*! SPD - When set to 1, mutes ih_fc_stat1[3]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_SPD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_SPD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_SPD_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_VSD_MASK (0x10U)
#define INTERRUPT_IH_MUTE_FC_STAT1_VSD_SHIFT (4U)
/*! VSD - When set to 1, mutes ih_fc_stat1[4]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_VSD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_VSD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_VSD_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_MASK (0x20U)
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_SHIFT (5U)
/*! ISCR2 - When set to 1, mutes ih_fc_stat1[5]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_ISCR2_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_MASK (0x40U)
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_SHIFT (6U)
/*! ISCR1 - When set to 1, mutes ih_fc_stat1[6]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_ISCR1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_ISCR1_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT1_GMD_MASK (0x80U)
#define INTERRUPT_IH_MUTE_FC_STAT1_GMD_SHIFT (7U)
/*! GMD - When set to 1, mutes ih_fc_stat1[7]
*/
#define INTERRUPT_IH_MUTE_FC_STAT1_GMD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT1_GMD_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT1_GMD_MASK)
/*! @} */
/*! @name IH_MUTE_FC_STAT2 - Frame Composer Interrupt Mute Control Register 2 */
/*! @{ */
#define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK (0x1U)
#define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT (0U)
/*! HighPriority_overflow - When set to 1, mutes ih_fc_stat2[0]
*/
#define INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_HIGHPRIORITY_OVERFLOW_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK (0x2U)
#define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT (1U)
/*! LowPriority_overflow - When set to 1, mutes ih_fc_stat2[1]
*/
#define INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_LOWPRIORITY_OVERFLOW_MASK)
#define INTERRUPT_IH_MUTE_FC_STAT2_DRM_MASK (0x10U)
#define INTERRUPT_IH_MUTE_FC_STAT2_DRM_SHIFT (4U)
/*! DRM - When set to 1, mutes ih_fc_stat2[4].
*/
#define INTERRUPT_IH_MUTE_FC_STAT2_DRM(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_FC_STAT2_DRM_SHIFT)) & INTERRUPT_IH_MUTE_FC_STAT2_DRM_MASK)
/*! @} */
/*! @name IH_MUTE_AS_STAT0 - Audio Sampler Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_MASK (0x1U)
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT (0U)
/*! Aud_fifo_overflow - When set to 1, mutes ih_as_stat0[0]
*/
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_OVERFLOW_MASK)
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK (0x2U)
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT (1U)
/*! Aud_fifo_underflow - When set to 1, mutes ih_as_stat0[1]
*/
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_MASK)
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK (0x4U)
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT (2U)
/*! Aud_fifo_underflow_thr - When set to 1, mutes ih_as_stat0[2]
*/
#define INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_AUD_FIFO_UNDERFLOW_THR_MASK)
#define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_MASK (0x8U)
#define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_SHIFT (3U)
/*! fifo_overrun - When set to 1, mutes ih_as_stat0[3]
*/
#define INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_SHIFT)) & INTERRUPT_IH_MUTE_AS_STAT0_FIFO_OVERRUN_MASK)
/*! @} */
/*! @name IH_MUTE_PHY_STAT0 - PHY Interface Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_PHY_STAT0_HPD_MASK (0x1U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_HPD_SHIFT (0U)
/*! HPD - When set to 1, mutes ih_phy_stat0[0]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_HPD(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_HPD_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_HPD_MASK)
#define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_MASK (0x2U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_SHIFT (1U)
/*! TX_PHY_LOCK - When set to 1, mutes ih_phy_stat0[1]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_TX_PHY_LOCK_MASK)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_MASK (0x4U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_SHIFT (2U)
/*! RX_SENSE_0 - When set to 1, mutes ih_phy_stat0[2]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_0_MASK)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_MASK (0x8U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_SHIFT (3U)
/*! RX_SENSE_1 - When set to 1, mutes ih_phy_stat0[3]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_1_MASK)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_MASK (0x10U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_SHIFT (4U)
/*! RX_SENSE_2 - When set to 1, mutes ih_phy_stat0[4]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_2_MASK)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_MASK (0x20U)
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_SHIFT (5U)
/*! RX_SENSE_3 - When set to 1, mutes ih_phy_stat0[5]
*/
#define INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_SHIFT)) & INTERRUPT_IH_MUTE_PHY_STAT0_RX_SENSE_3_MASK)
/*! @} */
/*! @name IH_MUTE_I2CM_STAT0 - E-DDC I2C Master Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_MASK (0x1U)
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_SHIFT (0U)
/*! I2Cmastererror - When set to 1, mutes ih_i2cm_stat0[0]
*/
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERERROR_MASK)
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_MASK (0x2U)
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_SHIFT (1U)
/*! I2Cmasterdone - When set to 1, mutes ih_i2cm_stat0[1]
*/
#define INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_I2CMASTERDONE_MASK)
#define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_MASK (0x4U)
#define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_SHIFT (2U)
/*! scdc_readreq - When set to 1, mutes ih_i2cm_stat0[2]
*/
#define INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_SHIFT)) & INTERRUPT_IH_MUTE_I2CM_STAT0_SCDC_READREQ_MASK)
/*! @} */
/*! @name IH_MUTE_CEC_STAT0 - CEC Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_CEC_STAT0_DONE_MASK (0x1U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_DONE_SHIFT (0U)
/*! DONE - When set to 1, mutes ih_cec_stat0[0]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_DONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_DONE_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_DONE_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_EOM_MASK (0x2U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_EOM_SHIFT (1U)
/*! EOM - When set to 1, mutes ih_cec_stat0[1]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_EOM(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_EOM_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_EOM_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_NACK_MASK (0x4U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_NACK_SHIFT (2U)
/*! NACK - When set to 1, mutes ih_cec_stat0[2]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_NACK(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_NACK_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_NACK_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_MASK (0x8U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_SHIFT (3U)
/*! ARB_LOST - When set to 1, mutes ih_cec_stat0[3]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ARB_LOST_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_MASK (0x10U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_SHIFT (4U)
/*! ERROR_INITIATOR - When set to 1, mutes ih_cec_stat0[4]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_INITIATOR_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_MASK (0x20U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_SHIFT (5U)
/*! ERROR_FOLLOW - When set to 1, mutes ih_cec_stat0[5]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_ERROR_FOLLOW_MASK)
#define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_MASK (0x40U)
#define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_SHIFT (6U)
/*! WAKEUP - When set to 1, mutes ih_cec_stat0[6]
*/
#define INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_SHIFT)) & INTERRUPT_IH_MUTE_CEC_STAT0_WAKEUP_MASK)
/*! @} */
/*! @name IH_MUTE_VP_STAT0 - Video Packetizer Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_MASK (0x1U)
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_SHIFT (0U)
/*! spare_1 - Reserved as "spare" bit with no associated functionality.
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_SPARE_1_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_MASK (0x2U)
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_SHIFT (1U)
/*! spare_2 - Reserved as "spare" bit with no associated functionality.
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_SPARE_2_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_MASK (0x4U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_SHIFT (2U)
/*! fifoemptyremap - When set to 1, mutes ih_vp_stat0[2]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREMAP_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_MASK (0x8U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_SHIFT (3U)
/*! fifofullremap - When set to 1, mutes ih_vp_stat0[3]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREMAP_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_MASK (0x10U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_SHIFT (4U)
/*! fifoemptypp - When set to 1, mutes ih_vp_stat0[4]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYPP_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_MASK (0x20U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_SHIFT (5U)
/*! fifofullpp - When set to 1, mutes ih_vp_stat0[5]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLPP_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_MASK (0x40U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_SHIFT (6U)
/*! fifoemptyrepet - When set to 1, mutes ih_vp_stat0[6]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOEMPTYREPET_MASK)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_MASK (0x80U)
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_SHIFT (7U)
/*! fifofullrepet - When set to 1, mutes ih_vp_stat0[7]
*/
#define INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_SHIFT)) & INTERRUPT_IH_MUTE_VP_STAT0_FIFOFULLREPET_MASK)
/*! @} */
/*! @name IH_MUTE_I2CMPHY_STAT0 - PHY GEN2 I2C Master Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_MASK (0x1U)
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT (0U)
/*! I2Cmphyerror - When set to 1, mutes ih_i2cmphy_stat0[0]
*/
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_SHIFT)) & INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR_MASK)
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_MASK (0x2U)
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT (1U)
/*! I2Cmphydone - When set to 1, mutes ih_i2cmphy_stat0[1]
*/
#define INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_SHIFT)) & INTERRUPT_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE_MASK)
/*! @} */
/*! @name IH_MUTE - Global Interrupt Mute Control Register */
/*! @{ */
#define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_MASK (0x1U)
#define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_SHIFT (0U)
/*! mute_all_interrupt - When set to 1, mutes the main interrupt line (where all interrupts are ORed).
*/
#define INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_SHIFT)) & INTERRUPT_IH_MUTE_MUTE_ALL_INTERRUPT_MASK)
#define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_MASK (0x2U)
#define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_SHIFT (1U)
/*! mute_wakeup_interrupt - When set to 1, mutes the main interrupt output port.
*/
#define INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_SHIFT)) & INTERRUPT_IH_MUTE_MUTE_WAKEUP_INTERRUPT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group INTERRUPT_Register_Masks */
/* INTERRUPT - Peripheral instance base addresses */
/** Peripheral INTERRUPT base address */
#define INTERRUPT_BASE (0x32FD8100u)
/** Peripheral INTERRUPT base pointer */
#define INTERRUPT ((INTERRUPT_Type *)INTERRUPT_BASE)
/** Array initializer of INTERRUPT peripheral base addresses */
#define INTERRUPT_BASE_ADDRS { INTERRUPT_BASE }
/** Array initializer of INTERRUPT peripheral base pointers */
#define INTERRUPT_BASE_PTRS { INTERRUPT }
/*!
* @}
*/ /* end of group INTERRUPT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
* @{
*/
/** IOMUXC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[20];
__IO uint32_t SW_MUX_CTL_PAD[143]; /**< SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register, array offset: 0x14, array step: 0x4 */
__IO uint32_t SW_PAD_CTL_PAD[156]; /**< SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register..SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register, array offset: 0x250, array step: 0x4 */
__IO uint32_t SELECT_INPUT[94]; /**< AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register..USDHC3_WP_ON_SELECT_INPUT DAISY Register, array offset: 0x4C0, array step: 0x4 */
} IOMUXC_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register..SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register */
/*! @{ */
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: AUDIOMIX_SAI2_RX_DATA00 of instance: sai2
* 0b001..Select mux mode: ALT1 mux port: AUDIOMIX_SAI5_TX_DATA00 of instance: sai5
* 0b010..Select mux mode: ALT2 mux port: ENET_QOS_1588_EVENT2_OUT of instance: enet_qos
* 0b011..Select mux mode: ALT3 mux port: AUDIOMIX_SAI2_TX_DATA01 of instance: sai2
* 0b100..Select mux mode: ALT4 mux port: UART1_RTS_B of instance: uart1
* 0b101..Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4
* 0b110..Select mux mode: ALT6 mux port: AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
*/
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad SPDIF_EXT_CLK
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
/*! @} */
/* The count of IOMUXC_SW_MUX_CTL_PAD */
#define IOMUXC_SW_MUX_CTL_PAD_COUNT (143U)
/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control Register..SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register */
/*! @{ */
#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x6U)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b00..X1
* 0b10..X2
* 0b01..X4
* 0b11..X6
*/
#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK (0x10U)
#define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT (4U)
/*! FSEL - Slew Rate Field
* 0b0..Slow Slew Rate (SR=1)
* 0b1..Fast Slew Rate (SR=0)
*/
#define IOMUXC_SW_PAD_CTL_PAD_FSEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U)
/*! ODE - Open Drain Field
* 0b0..Open Drain Disable
* 0b1..Open Drain Enable
*/
#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U)
/*! PUE - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U)
#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U)
/*! HYS - Input Select Field
* 0b0..CMOS
* 0b1..Schmitt
*/
#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PE_MASK (0x100U)
#define IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT (8U)
/*! PE - Pull Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SW_PAD_CTL_PAD_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PE_MASK)
/*! @} */
/* The count of IOMUXC_SW_PAD_CTL_PAD */
#define IOMUXC_SW_PAD_CTL_PAD_COUNT (156U)
/*! @name SELECT_INPUT - AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY Register..USDHC3_WP_ON_SELECT_INPUT DAISY Register */
/*! @{ */
#define IOMUXC_SELECT_INPUT_DAISY_MASK (0xFU) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */
#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
/*! DAISY - Selecting Pads Involved in Daisy Chain.
* 0b0000..Selecting Pad: SD2_CLK for Mode: ALT3
* 0b0001..Selecting Pad: SD2_CMD for Mode: ALT3
* 0b0010..Selecting Pad: NAND_CLE for Mode: ALT4
* 0b0011..Selecting Pad: NAND_DATA00 for Mode: ALT4
* 0b0100..Selecting Pad: NAND_DATA01 for Mode: ALT4
* 0b0101..Selecting Pad: NAND_RE_B for Mode: ALT4
* 0b0110..Selecting Pad: ECSPI2_SCLK for Mode: ALT1
* 0b0111..Selecting Pad: ECSPI2_MOSI for Mode: ALT1
* 0b1000..Selecting Pad: UART4_RXD for Mode: ALT0
* 0b1001..Selecting Pad: UART4_TXD for Mode: ALT0
*/
#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */
/*! @} */
/* The count of IOMUXC_SELECT_INPUT */
#define IOMUXC_SELECT_INPUT_COUNT (94U)
/*!
* @}
*/ /* end of group IOMUXC_Register_Masks */
/* IOMUXC - Peripheral instance base addresses */
/** Peripheral IOMUXC base address */
#define IOMUXC_BASE (0x30330000u)
/** Peripheral IOMUXC base pointer */
#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
/** Array initializer of IOMUXC peripheral base addresses */
#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
/** Array initializer of IOMUXC peripheral base pointers */
#define IOMUXC_BASE_PTRS { IOMUXC }
/*!
* @}
*/ /* end of group IOMUXC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_GPR - Register Layout Typedef */
typedef struct {
uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */
__IO uint32_t GPR1; /**< General Purpose Register 1, offset: 0x4 */
__IO uint32_t GPR2; /**< General Purpose Register 2, offset: 0x8 */
uint32_t GPR3; /**< General Purpose Register 3, offset: 0xC */
__IO uint32_t GPR4; /**< General Purpose Register 4, offset: 0x10 */
__IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */
__IO uint32_t GPR6; /**< General Purpose Register 6, offset: 0x18 */
uint32_t GPR7; /**< General Purpose Register 7, offset: 0x1C */
uint32_t GPR8; /**< General Purpose Register 8, offset: 0x20 */
uint32_t GPR9; /**< General Purpose Register 9, offset: 0x24 */
__IO uint32_t GPR10; /**< General Purpose Register 10, offset: 0x28 */
__IO uint32_t GPR11; /**< General Purpose Register 11, offset: 0x2C */
__IO uint32_t GPR12; /**< General Purpose Register 12, offset: 0x30 */
__IO uint32_t GPR13; /**< General Purpose Register 13, offset: 0x34 */
__IO uint32_t GPR14; /**< General Purpose Register 14, offset: 0x38 */
__IO uint32_t GPR15; /**< General Purpose Register 15, offset: 0x3C */
__IO uint32_t GPR16; /**< General Purpose Register 16, offset: 0x40 */
uint32_t GPR17; /**< General Purpose Register 17, offset: 0x44 */
uint32_t GPR18; /**< General Purpose Register 18, offset: 0x48 */
__I uint32_t GPR19; /**< General Purpose Register 19, offset: 0x4C */
__IO uint32_t GPR20; /**< General Purpose Register 20, offset: 0x50 */
__IO uint32_t GPR21; /**< General Purpose Register 21, offset: 0x54 */
__IO uint32_t GPR22; /**< General Purpose Register 22, offset: 0x58 */
uint32_t GPR23; /**< General Purpose Register 23, offset: 0x5C */
__I uint32_t GPR24; /**< General Purpose Register 24, offset: 0x60 */
} IOMUXC_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
* @{
*/
/*! @name GPR1 - General Purpose Register 1 */
/*! @{ */
#define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_MASK (0x1U)
#define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_SHIFT (0U)
/*! GPR_ENET1_EVENT0IN_SEL
* 0b0..IOMUX
* 0b1..GPT1 CMPOUT2
*/
#define IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET1_EVENT0IN_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_MASK (0x2U)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_SHIFT (1U)
/*! GPR_ENET_QOS_EVENT0IN_SEL
* 0b0..IOMUX;
* 0b1..GPT1 CMPOUT2
*/
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_EVENT0IN_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_SHIFT (2U)
/*! GPR_GPT1_CAPIN1_SEL
* 0b0..IOMUX
* 0b1..ENET1 TIMIER1 EVENT
*/
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN1_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_MASK (0x8U)
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_SHIFT (3U)
/*! GPR_GPT1_CAPIN2_SEL
* 0b0..IOMUX
* 0b1..ENET QOS TIMIER1 EVENT
*/
#define IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_GPT1_CAPIN2_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_MASK (0x10U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_SHIFT (4U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON0_MASK)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_MASK (0x20U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_SHIFT (5U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON1_MASK)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_MASK (0x40U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_SHIFT (6U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON2_MASK)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_MASK (0x80U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_SHIFT (7U)
#define IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_SHIFT)) & IOMUXC_GPR_GPR1_GPR_LVDS_TEST_DO_ON3_MASK)
#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK (0x1000U)
#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT (12U)
#define IOMUXC_GPR_GPR1_GPR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR1_GPR_IRQ_MASK)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_SHIFT (13U)
/*! IOMUXC_GPR_ENET1_TX_CLK_SEL
* 0b1..ENET1 RMII clock comes from ccm->pad->loopback
* 0b0..ENET1 RMII clock comes from external PHY or OSC
*/
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_TX_CLK_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_MASK (0x4000U)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_SHIFT (14U)
/*! GPR_ENET_QOS_DIS_CRC_CHK
* 0b0..do not disable
* 0b1..disable
*/
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_DIS_CRC_CHK_MASK)
#define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_MASK (0x8000U)
#define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_SHIFT (15U)
/*! GPR_ANAMIX_IPT_MODE
* 0b0..masked to 0
* 0b1..unmasked
*/
#define IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ANAMIX_IPT_MODE_MASK)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK (0x70000U)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_SHIFT (16U)
/*! GPR_ENET_QOS_INTF_SEL
* 0b000..MII
* 0b001..RGMII
* 0b100..RMII
*/
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_MASK (0x80000U)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_SHIFT (19U)
/*! GPR_ENET_QOS_CLK_GEN_EN
* 0b0..disable
* 0b1..enable
*/
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_SHIFT)) & IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN_MASK)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_MASK (0x100000U)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_SHIFT (20U)
/*! IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL
* 0b1..ENET QOS RMII clock comes from ccm->pad->loopback
* 0b0..ENET QOS RMII clock comes from external PHY or OSC
*/
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_CLK_TX_CLK_SEL_MASK)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_MASK (0x200000U)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_SHIFT (21U)
/*! IOMUXC_GPR_ENET_QOS_RGMII_EN
* 0b0..MII(input)
* 0b1..RGMII(output)
*/
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET_QOS_RGMII_EN_MASK)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_MASK (0x400000U)
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_SHIFT (22U)
/*! IOMUXC_GPR_ENET1_RGMII_EN
* 0b0..MII(input)
* 0b1..RGMII(output)
*/
#define IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR1_IOMUXC_GPR_ENET1_RGMII_EN_MASK)
#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U)
#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U)
#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK)
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_MASK (0x8000000U)
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_SHIFT (27U)
/*! GPR_DBG_ACK_M7_MASK
* 0b0..unmasked
* 0b1..mask to 0
*/
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_M7_MASK_MASK)
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_MASK (0xF0000000U)
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_SHIFT (28U)
/*! GPR_DBG_ACK_A53_MASK
* 0b0000..unmasked
* 0b0001..mask to 0
*/
#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_A53_MASK_MASK)
/*! @} */
/*! @name GPR2 - General Purpose Register 2 */
/*! @{ */
#define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_MASK (0x3U)
#define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_SHIFT (0U)
#define IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_SHIFT)) & IOMUXC_GPR_GPR2_GPR_CORESIGHT_GPR_CTM_SEL_MASK)
/*! @} */
/*! @name GPR4 - General Purpose Register 4 */
/*! @{ */
#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK (0x1U)
#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT (0U)
#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_MASK (0x2U)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_SHIFT (1U)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_FLEXSPI_I_IPG_STOP_MASK)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK (0x8U)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT (3U)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK (0x10U)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT (4U)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK (0x20U)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT (5U)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK)
#define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_MASK (0x10000U)
#define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_SHIFT (16U)
#define IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_SDAM1_IPG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_MASK (0x20000U)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_SHIFT (17U)
#define IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_FLEXSPI_O_IPG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_MASK (0x80000U)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_SHIFT (19U)
#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_MASK (0x100000U)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_SHIFT (20U)
#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_MASK (0x200000U)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_SHIFT (21U)
#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK (0xF000000U)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT (24U)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR4_CPU_STANDBYWFI_MASK)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK (0xF0000000U)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT (28U)
#define IOMUXC_GPR_GPR4_CPU_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR4_CPU_STANDBYWFE_MASK)
/*! @} */
/*! @name GPR5 - General Purpose Register 5 */
/*! @{ */
#define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_SHIFT (0U)
#define IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_RMW_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_MASK (0x2U)
#define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_SHIFT (1U)
#define IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_RMW_S_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_MASK (0x4U)
#define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_SHIFT (2U)
#define IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_SHIFT)) & IOMUXC_GPR_GPR5_GPR_ENABLE_UPSIZER_MASK)
#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK (0x40U)
#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT (6U)
/*! GPR_WDOG1_MASK
* 0b0..wdog1 low will make the GPIO1_IO02.alt5_out low;
* 0b1..wdog1 low will NOT impact the GPIO1_IO02.alt5_out
*/
#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK)
#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK (0x80U)
#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT (7U)
/*! GPR_WDOG2_MASK
* 0b0..wdog2 low will make the GPIO1_IO02.alt5_out low;
* 0b1..wdog2 low will NOT impact the GPIO1_IO02.alt5_out
*/
#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK)
#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK (0x100000U)
#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT (20U)
/*! GPR_WDOG3_MASK
* 0b0..wdog3 low will make the GPIO1_IO02.alt5_out low;
* 0b1..wdog3 low will NOT impact the GPIO1_IO02.alt5_out
*/
#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK)
/*! @} */
/*! @name GPR6 - General Purpose Register 6 */
/*! @{ */
#define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_MASK (0xFFFFFF80U)
#define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_SHIFT (7U)
#define IOMUXC_GPR_GPR6_GPR_M7_INITVTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_SHIFT)) & IOMUXC_GPR_GPR6_GPR_M7_INITVTOR_MASK)
/*! @} */
/*! @name GPR10 - General Purpose Register 10 */
/*! @{ */
#define IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK (0x1U)
#define IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT (0U)
#define IOMUXC_GPR_GPR10_GPR_TZASC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK)
#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U)
#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U)
#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK)
#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK (0x4U)
#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT (2U)
#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK)
#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT (3U)
#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_MASK (0x10U)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_SHIFT (4U)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_EN_MASK)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_MASK (0x7E0U)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_SHIFT (5U)
#define IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_GPR_OCRAM_A_TZ_START_ADDR_MASK)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK (0x10000U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT (16U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x20000U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (17U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK)
#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK (0x40000U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT (18U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK)
#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK (0x80000U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT (19U)
#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK)
/*! @} */
/*! @name GPR11 - General Purpose Register 11 */
/*! @{ */
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_MASK (0x1U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_SHIFT (0U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_EN_MASK)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_MASK (0x1FEU)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_SHIFT (1U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_TZ_START_ADDR_MASK)
#define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_MASK (0x200U)
#define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT (9U)
/*! GPR_CAAM_CAAM_IPS_MANAGER
* 0b0..not controlled by CSU/RDC slot
* 0b1..controlled by CSU/RDC slot
*/
#define IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT)) & IOMUXC_GPR_GPR11_GPR_CAAM_CAAM_IPS_MANAGER_MASK)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_MASK (0x400U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_SHIFT (10U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_EN_MASK)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_MASK (0x7800U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_SHIFT (11U)
#define IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_GPR_OCRAM_S_TZ_START_ADDR_MASK)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_MASK (0x10000U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_SHIFT (16U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_EN_MASK)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_MASK (0x1FE0000U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_SHIFT (17U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_TZ_START_ADDR_MASK)
#define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_MASK (0x2000000U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT (25U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_CAAM_CAAM_IPS_MANAGER_MASK)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_MASK (0x4000000U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_SHIFT (26U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_EN_MASK)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_MASK (0x38000000U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_SHIFT (27U)
#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_SHIFT)) & IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_S_TZ_START_ADDR_MASK)
/*! @} */
/*! @name GPR12 - General Purpose Register 12 */
/*! @{ */
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK (0xF000U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT (12U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DEVICE_TYPE_MASK)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK (0x1E0000U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT (17U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK (0x600000U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT (21U)
#define IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE1_CTRL_DIAG_CTRL_BUS_MASK)
#define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_MASK (0x80000000U)
#define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_SHIFT (31U)
#define IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_SHIFT)) & IOMUXC_GPR_GPR12_GPR_PCIE_DIAG_BUS_SEL_MASK)
/*! @} */
/*! @name GPR13 - General Purpose Register 13 */
/*! @{ */
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK (0x1U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT (0U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK (0x2U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT (1U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK (0x10U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT (4U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK (0x20U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT (5U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_MASK (0x80U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_SHIFT (7U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USB1_MASK)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_MASK (0x100U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_SHIFT (8U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USB1_MASK)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK (0x400U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT (10U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK (0x800U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT (11U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_MASK (0x2000U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_SHIFT (13U)
#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_SHIFT)) & IOMUXC_GPR_GPR13_GPR_ARCACHE_USB2_MASK)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_MASK (0x4000U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_SHIFT (14U)
#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_SHIFT)) & IOMUXC_GPR_GPR13_GPR_AWCACHE_USB2_MASK)
/*! @} */
/*! @name GPR14 - General Purpose Register 14 */
/*! @{ */
#define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_MASK (0x100U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_SHIFT (8U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_APP_CLK_PM_EN_MASK)
#define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_MASK (0x200U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_SHIFT (9U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_REF_USE_PAD_MASK)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_MASK (0x400U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_SHIFT (10U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_EN_MASK)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_MASK (0x800U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_SHIFT (11U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_CLKREQ_B_OVERRIDE_MASK)
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_MASK (0xF0000U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_SHIFT (16U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_PHY_CTRL_BUS_MASK)
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_MASK (0x3000000U)
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_SHIFT (24U)
/*! GPR_PCIE_PHY_PLL_REF_CLK_SEL
* 0b00..N/A
* 0b01..Selects reference clock from XO (pll_refclk_from_xo)
* 0b10..Selects reference clock from IO (ext_ref_clkp/n)
* 0b11..Selects reference clock from SOC PLL (pll_refclk_from_syspll)
*/
#define IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR14_GPR_PCIE_PHY_PLL_REF_CLK_SEL_MASK)
/*! @} */
/*! @name GPR15 - General Purpose Register 15 */
/*! @{ */
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_SHIFT (0U)
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_SHIFT)) & IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D_MASK)
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_MASK (0xFFFF0000U)
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_SHIFT (16U)
#define IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_SHIFT)) & IOMUXC_GPR_GPR15_GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D_MASK)
/*! @} */
/*! @name GPR16 - General Purpose Register 16 */
/*! @{ */
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_MASK (0x1U)
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_SHIFT (0U)
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_SHIFT)) & IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU3D_MASK)
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_MASK (0x2U)
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_SHIFT (1U)
#define IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_SHIFT)) & IOMUXC_GPR_GPR16_GPR_GPUMIX_GPR_AXI_LIMIT_ENABLE_GPU2D_MASK)
/*! @} */
/*! @name GPR19 - General Purpose Register 19 */
/*! @{ */
#define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_MASK (0xFFFFFFFFU)
#define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_SHIFT (0U)
#define IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_SHIFT)) & IOMUXC_GPR_GPR19_PCIE_DIAG_STATUS_MASK)
/*! @} */
/*! @name GPR20 - General Purpose Register 20 */
/*! @{ */
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_MASK (0x1U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_SHIFT (0U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_MASK (0x2U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_SHIFT (1U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_MASK (0x4U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_SHIFT (2U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_MASK (0x8U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_SHIFT (3U)
#define IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC3_M_D_8_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_MASK (0x10U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_SHIFT (4U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_MASK (0x20U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_SHIFT (5U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_MASK (0x40U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_SHIFT (6U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_MASK (0x80U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_SHIFT (7U)
#define IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC2_M_D_7_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_MASK (0x100U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_SHIFT (8U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_MASK (0x200U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_SHIFT (9U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_MASK (0x400U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_SHIFT (10U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_MASK (0x800U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_SHIFT (11U)
#define IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_USDHC1_M_D_6_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_MASK (0x1000U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_SHIFT (12U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_MASK (0x2000U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_SHIFT (13U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_MASK (0x4000U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_SHIFT (14U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_MASK (0x8000U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_SHIFT (15U)
#define IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_RAWNAND_M_D_5_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_MASK (0x10000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_SHIFT (16U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_MASK (0x20000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_SHIFT (17U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_MASK (0x40000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_SHIFT (18U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_MASK (0x80000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_SHIFT (19U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_1_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_MASK (0x100000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_SHIFT (20U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_MASK (0x200000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_SHIFT (21U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_MASK (0x400000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_SHIFT (22U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_MASK (0x800000U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_SHIFT (23U)
#define IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_ENET1_M_E_0_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_MASK (0x1000000U)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_SHIFT (24U)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_MASK (0x2000000U)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_SHIFT (25U)
#define IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_DAP_M_D_0_HADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_MASK (0x4000000U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_SHIFT (26U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_MASK (0x8000000U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_SHIFT (27U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_AWADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_MASK (0x10000000U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_SHIFT (28U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_MASK (0x20000000U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_SHIFT (29U)
#define IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_CORESIGHT_M_A_0_ARADDR32_MASK)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_MASK (0x40000000U)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_SHIFT (30U)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_SHIFT)) & IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR33_MASK)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_MASK (0x80000000U)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_SHIFT (31U)
#define IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_SHIFT)) & IOMUXC_GPR_GPR20_GPR_APBHDMA_M_D_4_HADDR32_MASK)
/*! @} */
/*! @name GPR21 - General Purpose Register 21 */
/*! @{ */
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_MASK (0x4000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_SHIFT (26U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR33_MASK)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_MASK (0x8000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_SHIFT (27U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_AWADDR32_MASK)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_MASK (0x10000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_SHIFT (28U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR33_MASK)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_MASK (0x20000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_SHIFT (29U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_3_ARADDR32_MASK)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_MASK (0x40000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_SHIFT (30U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR33_MASK)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_MASK (0x80000000U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_SHIFT (31U)
#define IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_SHIFT)) & IOMUXC_GPR_GPR21_GPR_SDMA1_M_D_2_HADDR32_MASK)
/*! @} */
/*! @name GPR22 - General Purpose Register 22 */
/*! @{ */
#define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_MASK (0x1U)
#define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_SHIFT (0U)
/*! GPR_M7_CPUWAIT
* 0b0..do not let CM7 enter wait mode
* 0b1..let CM7 enter wait mode
*/
#define IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_CPUWAIT_MASK)
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_MASK (0x4U)
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_SHIFT (2U)
/*! GPR_M7_HCLK_AUTO_GATE_EN
* 0b0..depends on the value of "GPR_M7_HCLK_GATE_EN"
* 0b1..ignore the value of "GPR_M7_HCLK_GATE_EN"
*/
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_HCLK_AUTO_GATE_EN_MASK)
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_SHIFT (3U)
/*! GPR_M7_HCLK_GATE_EN
* 0b0..gate on
* 0b1..gate off
*/
#define IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_GPR_M7_HCLK_GATE_EN_MASK)
#define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_MASK (0x10000U)
#define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_SHIFT (16U)
#define IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_SHIFT)) & IOMUXC_GPR_GPR22_SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL_MASK)
/*! @} */
/*! @name GPR24 - General Purpose Register 24 */
/*! @{ */
#define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_MASK (0xFFU)
#define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_SHIFT (0U)
#define IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_GPU2D_DEBUG_OUT_MASK)
#define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_MASK (0xFF00U)
#define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_SHIFT (8U)
#define IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_GPU3D_DEBUG_OUT_MASK)
#define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_MASK (0xFF0000U)
#define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_SHIFT (16U)
#define IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_SHIFT)) & IOMUXC_GPR_GPR24_GPR_MLMIX_DEBUG_OUT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_GPR_Register_Masks */
/* IOMUXC_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_GPR base address */
#define IOMUXC_GPR_BASE (0x30340000u)
/** Peripheral IOMUXC_GPR base pointer */
#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
/** Array initializer of IOMUXC_GPR peripheral base addresses */
#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
/** Array initializer of IOMUXC_GPR peripheral base pointers */
#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
/*!
* @}
*/ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IRQSTEER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IRQSTEER_Peripheral_Access_Layer IRQSTEER Peripheral Access Layer
* @{
*/
/** IRQSTEER - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t CHN_MASK[5]; /**< Channel n Interrupt Mask Register, array offset: 0x4, array step: 0x4 */
__IO uint32_t CHN_SET[5]; /**< Channel n Interrupt Set Register, array offset: 0x18, array step: 0x4 */
__I uint32_t CHN_STATUS[5]; /**< Channel n Interrupt Status Register, array offset: 0x2C, array step: 0x4 */
__IO uint32_t CHN_MINTDIS; /**< Channel n Master Interrupt Disable Register, offset: 0x40 */
__I uint32_t CHN_MSTRSTAT; /**< Channel n Master Status Register, offset: 0x44 */
} IRQSTEER_Type;
/* ----------------------------------------------------------------------------
-- IRQSTEER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IRQSTEER_Register_Masks IRQSTEER Register Masks
* @{
*/
/*! @name CHN_MASK - Channel n Interrupt Mask Register */
/*! @{ */
#define IRQSTEER_CHN_MASK_MASKFLD_MASK (0xFFFFFFFFU)
#define IRQSTEER_CHN_MASK_MASKFLD_SHIFT (0U)
/*! MASKFLD - Mask bits
* 0b00000000000000000000000000000000..Mask interrupt
* 0b00000000000000000000000000000001..Do not mask interrupt
*/
#define IRQSTEER_CHN_MASK_MASKFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHN_MASK_MASKFLD_SHIFT)) & IRQSTEER_CHN_MASK_MASKFLD_MASK)
/*! @} */
/* The count of IRQSTEER_CHN_MASK */
#define IRQSTEER_CHN_MASK_COUNT (5U)
/*! @name CHN_SET - Channel n Interrupt Set Register */
/*! @{ */
#define IRQSTEER_CHN_SET_FORCEFLD_MASK (0xFFFFFFFFU)
#define IRQSTEER_CHN_SET_FORCEFLD_SHIFT (0U)
/*! FORCEFLD - Force interrupt.
* 0b00000000000000000000000000000000..Normal operation
* 0b00000000000000000000000000000001..Force interrupt
*/
#define IRQSTEER_CHN_SET_FORCEFLD(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHN_SET_FORCEFLD_SHIFT)) & IRQSTEER_CHN_SET_FORCEFLD_MASK)
/*! @} */
/* The count of IRQSTEER_CHN_SET */
#define IRQSTEER_CHN_SET_COUNT (5U)
/*! @name CHN_STATUS - Channel n Interrupt Status Register */
/*! @{ */
#define IRQSTEER_CHN_STATUS_STATUS_MASK (0xFFFFFFFFU)
#define IRQSTEER_CHN_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Status of an interrupt
* 0b00000000000000000000000000000000..Interrupt is not set.
* 0b00000000000000000000000000000001..Interrupt is set.
*/
#define IRQSTEER_CHN_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHN_STATUS_STATUS_SHIFT)) & IRQSTEER_CHN_STATUS_STATUS_MASK)
/*! @} */
/* The count of IRQSTEER_CHN_STATUS */
#define IRQSTEER_CHN_STATUS_COUNT (5U)
/*! @name CHN_MINTDIS - Channel n Master Interrupt Disable Register */
/*! @{ */
#define IRQSTEER_CHN_MINTDIS_DISABLE_MASK (0x7U)
#define IRQSTEER_CHN_MINTDIS_DISABLE_SHIFT (0U)
/*! DISABLE - Each bit of this field disables the corresponding interrupts in table above.
* 0b000..Enable interrupts
* 0b001..Disable interrupts
*/
#define IRQSTEER_CHN_MINTDIS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHN_MINTDIS_DISABLE_SHIFT)) & IRQSTEER_CHN_MINTDIS_DISABLE_MASK)
/*! @} */
/*! @name CHN_MSTRSTAT - Channel n Master Status Register */
/*! @{ */
#define IRQSTEER_CHN_MSTRSTAT_STATUS_MASK (0x1U)
#define IRQSTEER_CHN_MSTRSTAT_STATUS_SHIFT (0U)
/*! STATUS - Status of all interrupts
* 0b0..No interrupts are asserted.
* 0b1..At least one interrupt is asserted.
*/
#define IRQSTEER_CHN_MSTRSTAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IRQSTEER_CHN_MSTRSTAT_STATUS_SHIFT)) & IRQSTEER_CHN_MSTRSTAT_STATUS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IRQSTEER_Register_Masks */
/* IRQSTEER - Peripheral instance base addresses */
/** Peripheral IRQ_STEER_AUDIO_PROCESSOR base address */
#define IRQ_STEER_AUDIO_PROCESSOR_BASE (0x30A80000u)
/** Peripheral IRQ_STEER_AUDIO_PROCESSOR base pointer */
#define IRQ_STEER_AUDIO_PROCESSOR ((IRQSTEER_Type *)IRQ_STEER_AUDIO_PROCESSOR_BASE)
/** Peripheral IRQ_STEER_HDMI base address */
#define IRQ_STEER_HDMI_BASE (0x32FC2000u)
/** Peripheral IRQ_STEER_HDMI base pointer */
#define IRQ_STEER_HDMI ((IRQSTEER_Type *)IRQ_STEER_HDMI_BASE)
/** Array initializer of IRQSTEER peripheral base addresses */
#define IRQSTEER_BASE_ADDRS { IRQ_STEER_AUDIO_PROCESSOR_BASE, IRQ_STEER_HDMI_BASE }
/** Array initializer of IRQSTEER peripheral base pointers */
#define IRQSTEER_BASE_PTRS { IRQ_STEER_AUDIO_PROCESSOR, IRQ_STEER_HDMI }
/*!
* @}
*/ /* end of group IRQSTEER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ISI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
* @{
*/
/** ISI - Register Layout Typedef */
typedef struct {
__IO uint32_t CHNL_CTRL; /**< Channel Control Register, offset: 0x0 */
__IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control Register, offset: 0x4 */
__IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control Register, offset: 0x8 */
__IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */
__IO uint32_t CHNL_IER; /**< Channel Interrupt Enable Register, offset: 0x10 */
__IO uint32_t CHNL_STS; /**< Channel Status Register, offset: 0x14 */
__IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor Register, offset: 0x18 */
__IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset Register, offset: 0x1C */
__IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
__IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
__IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
__IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
__IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
__IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
__IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
__IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
__IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value Register for Region of Interest 0, offset: 0x40 */
__IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 0, offset: 0x44 */
__IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 0, offset: 0x48 */
__IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value Register for Region of Interest 1, offset: 0x4C */
__IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 1, offset: 0x50 */
__IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 1, offset: 0x54 */
__IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value Register for Region of Interest 2, offset: 0x58 */
__IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 2, offset: 0x5C */
__IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 2, offset: 0x60 */
__IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value Register for Region of Interest 3, offset: 0x64 */
__IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 3, offset: 0x68 */
__IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 3, offset: 0x6C */
__IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
__IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
__IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
__IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */
__IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */
__IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */
__IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */
__IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
__IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
__IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
__IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */
__IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control Register, offset: 0x9C */
__IO uint32_t CHNL_Y_BUF1_XTND_ADDR; /**< Channel Output Y-Buffer 1 Extended Address Bits Register, offset: 0xA0 */
__IO uint32_t CHNL_U_BUF1_XTND_ADDR; /**< Channel Output U-Buffer 1 Extended Address Bits Register, offset: 0xA4 */
__IO uint32_t CHNL_V_BUF1_XTND_ADDR; /**< Channel Output V-Buffer 1 Extended Address Bits Register, offset: 0xA8 */
__IO uint32_t CHNL_Y_BUF2_XTND_ADDR; /**< Channel Output Y-Buffer 2 Extended Address Bits Register, offset: 0xAC */
__IO uint32_t CHNL_U_BUF2_XTND_ADDR; /**< Channel Output U-Buffer 2 Extended Address Bits Register, offset: 0xB0 */
__IO uint32_t CHNL_V_BUF2_XTND_ADDR; /**< Channel Output V-Buffer 2 Extended Address Bits Register, offset: 0xB4 */
__IO uint32_t CHNL_IN_BUF_XTND_ADDR; /**< Channel Input Buffer Extended Address Bits Register, offset: 0xB8 */
} ISI_Type;
/* ----------------------------------------------------------------------------
-- ISI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ISI_Register_Masks ISI Register Masks
* @{
*/
/*! @name CHNL_CTRL - Channel Control Register */
/*! @{ */
#define ISI_CHNL_CTRL_SRC_MASK (0x1U)
#define ISI_CHNL_CTRL_SRC_SHIFT (0U)
/*! SRC - Input image source port selection
* 0b0..Image will be sourced from input port 0 of the Pixel Link Crossbar
* 0b1..Image will be sourced from input port 1 of the Pixel Link Crossbar
*/
#define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)
#define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U)
#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U)
/*! SRC_TYPE - Type of selected input image source
* 0b0..Image input source is Pixel Link
* 0b1..Image input source is Memory
*/
#define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)
#define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U)
#define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U)
/*! SEC_LB_SRC - Secondary line buffer source
*/
#define ISI_CHNL_CTRL_SEC_LB_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)
#define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U)
#define ISI_CHNL_CTRL_SW_RST_SHIFT (24U)
/*! SW_RST - Software reset bit
* 0b0..No Reset
* 0b1..Channel pipeline is under software reset
*/
#define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)
#define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U)
#define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U)
/*! CHAIN_BUF - Chain line buffer control
* 0b00..No line buffers chained (supports 2048 or less horizontal resolution)
* 0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are chained.
* 0b10..4 line buffers chained (supports 8192 horizontal resolution). Line buffers of channels 'n', 'n+1', 'n+2' and 'n+3' are chained.
* 0b11..Reserved for future use
*/
#define ISI_CHNL_CTRL_CHAIN_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)
#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U)
#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U)
/*! CHNL_BYPASS - Channel bypass enable
* 0b0..Channel is not bypassed
* 0b1..Channel is bypassed
*/
#define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)
#define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U)
#define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U)
/*! CLK_EN - Channel clock enable
* 0b0..Channel processing clock is disabled
* 0b1..Channel processing clock is enabled
*/
#define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)
#define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U)
#define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U)
/*! CHNL_EN - Enable channel processing
* 0b0..Processing channel is disabled
* 0b1..Processing channel is enabled
*/
#define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
/*! @} */
/*! @name CHNL_IMG_CTRL - Channel Image Control Register */
/*! @{ */
#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U)
#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U)
/*! CSC_BYP - Color Space Conversion bypass control
* 0b0..CSC is operational
* 0b1..CSC is bypassed
*/
#define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)
#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U)
#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U)
/*! CSC_MODE - Color Space Conversion operating mode
* 0b00..Convert from YUV to RGB
* 0b01..Convert from YCbCr to RGB
* 0b10..Convert from RGB to YUV
* 0b11..Convert from RGB to YCbCr
*/
#define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U)
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U)
/*! YCBCR_MODE - YCbCr Mode
* 0b0..YCbCr mode is disabled
* 0b1..YCbCr mode is enabled
*/
#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)
#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U)
#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U)
/*! HFLIP_EN - Horizontal flip control
* 0b0..Horizantal image flip disabled
* 0b1..Horizontal image flip enabled
*/
#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U)
#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U)
/*! VFLIP_EN - Veritical flip control
* 0b0..Vertical image flip disabled
* 0b1..Vertical image flip enabled
*/
#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U)
#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U)
/*! CROP_EN - Output image cropping enable
* 0b0..Image cropping is disabled
* 0b1..Image cropping is enabled
*/
#define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)
#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U)
#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U)
/*! DEC_Y - Vertical pre-decimation control
* 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
* 0b01..Decimate by 2
* 0b10..Decimate by 4
* 0b11..Decimate by 8
*/
#define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)
#define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U)
#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U)
/*! DEC_X - Horizontal pre-decimation control
* 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
* 0b01..Decimate by 2
* 0b10..Decimate by 4
* 0b11..Decimate by 8
*/
#define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)
#define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U)
#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U)
/*! DEINT - De-interlace control
* 0b000, 0b001..No de-interlacing done
* 0b010..Weave de-interlacing (Odd, Even) method used
* 0b011..Weave de-interlacing (Even, Odd) method used
* 0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used
* 0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used
* 0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled.
*/
#define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U)
/*! GBL_ALPHA_EN - Global alpha value insertion enable
* 0b0..Global Alpha value insertion is disabled
* 0b1..Global Alpha value insertion is enabled
*/
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U)
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U)
/*! GBL_ALPHA_VAL - Global alpha value
* 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
*/
#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)
#define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x3F000000U)
#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U)
/*! FORMAT - Output image format
* 0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
* 0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
* 0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
* 0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X' indicates the waste bits.
* 0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
* 0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits.
* 0b000110..RGB888P - RGB format with 8-bits per color component (packed into 24-bits). No waste bits.
* 0b000111..BGR888P - BGR format with 8-bits per color component (packed into 24-bits). No waste bits.
* 0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
* 0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component. 'A' indicates alpha value.
* 0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 16-bits WORD). No waste bits.
* 0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD
* 0b001100..RAW10 - 10-bit RAW data packed into 16-bit WORD with 6 LSBs waste bits
* 0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
* 0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
* 0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
* 0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
* 0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
* 0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
* 0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
* 0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b010110..YUV444_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b010111..Reserved for future use
* 0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b011011..Reserved for future use
* 0b011100..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b011101..YUV444_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b011111..Reserved for future use
* 0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
* 0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
* 0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
* 0b100011..Reserved for future use
* 0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b100111..Reserved for future use
* 0b101000..YUV422_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b101011..Reserved for future use
* 0b101100..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b101101..YUV422_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b101110..YUV422_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b101111..Reserved for future use
* 0b110000..Reserved for future use
* 0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
* 0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
* 0b110011..Reserved for future use
* 0b110100..Reserved for future use
* 0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b110111..Reserved for future use
* 0b111000..Reserved for future use
* 0b111001..YUV420_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
* 0b111011..Reserved for future use
* 0b111100..Reserved for future use
* 0b111101..YUV420_2P12 with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b111110..YUV420_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b111111..Reserved for future use
*/
#define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
/*! @{ */
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U)
/*! PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
* 0b0000..No panic alert will be asserted
* 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
*/
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U)
/*! PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
* 0b0000..No panic alert will be asserted
* 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
*/
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
/*! LOAD_BUF1_ADDR - Load Buffer 1 Address from CHNLOUT_BUF1_ADDR_* registers
*/
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
/*! LOAD_BUF2_ADDR - Load Buffer 2 Address from CHNLOUT_BUF2_ADDR_* registers
*/
#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U)
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U)
/*! PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
* 0b0000..No panic alert will be asserted
* 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
*/
#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U)
/*! MAX_WR_BEATS_UV - Maximum AXI write beats for U and V-buffers
* 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
* 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
*/
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U)
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U)
/*! MAX_WR_BEATS_Y - Maximum AXI write beats for Y-buffer
* 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
* 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
*/
#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK)
/*! @} */
/*! @name CHNL_IMG_CFG - Channel Image Configuration */
/*! @{ */
#define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU)
#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U)
/*! WIDTH - Input image width (pixels)
*/
#define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)
#define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U)
#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U)
/*! HEIGHT - Input image height (lines)
*/
#define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)
/*! @} */
/*! @name CHNL_IER - Channel Interrupt Enable Register */
/*! @{ */
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U)
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U)
/*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U)
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U)
/*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)
#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x40000U)
#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (18U)
/*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)
#define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x80000U)
#define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (19U)
/*! PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x100000U)
#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (20U)
/*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)
#define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x200000U)
#define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (21U)
/*! PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK)
#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U)
#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U)
/*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)
#define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x800000U)
#define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (23U)
/*! PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK)
#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U)
#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U)
/*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U)
/*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U)
/*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U)
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U)
/*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)
#define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U)
#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U)
/*! FRM_RCVD_EN - Frame received interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)
#define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U)
#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U)
/*! LINE_RCVD_EN - Line received interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)
#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U)
#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U)
/*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
/*! @} */
/*! @name CHNL_STS - Channel Status Register */
/*! @{ */
#define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U)
#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U)
/*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
* 0b0..Buffer 1 Address inactive
* 0b1..Buffer 1 Address in use
*/
#define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)
#define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U)
#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U)
/*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
* 0b0..Buffer 2 Address inactive
* 0b1..Buffer 2 Address in use
*/
#define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)
#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U)
#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U)
/*! MEM_RD_OFLOW - Memory read FIFO overflow error status
* 0b0..No overflow occurred during memory read
* 0b1..FIFO overflow occurred during memory read
*/
#define ISI_CHNL_STS_MEM_RD_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)
#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U)
#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U)
/*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
* 0b0..No error
* 0b1..VSYNC detected later than expected
*/
#define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)
#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U)
#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U)
/*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
* 0b0..No error
* 0b1..VSYNC detected earlier than expected
*/
#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)
#define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U)
#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U)
/*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
* 0b0..No overflow
* 0b1..Overflow has occured in the channel
*/
#define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)
#define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U)
#define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U)
/*! PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
* 0b0..Buffer has not crossed the panic threshold limit
* 0b1..Panic threshold limit crossed. Software must take action.
*/
#define ISI_CHNL_STS_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK)
#define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U)
#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U)
/*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
* 0b0..No overflow
* 0b1..Overflow has occured in the channel
*/
#define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)
#define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U)
#define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U)
/*! PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
* 0b0..Buffer has not crossed the panic threshold limit
* 0b1..Panic threshold limit crossed. Software must take action.
*/
#define ISI_CHNL_STS_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK)
#define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U)
#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U)
/*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
* 0b0..No overflow
* 0b1..Overflow has occured in the channel
*/
#define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)
#define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U)
#define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U)
/*! PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
* 0b0..Buffer has not crossed the panic threshold limit
* 0b1..Panic threshold limit crossed. Software must take action.
*/
#define ISI_CHNL_STS_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK)
#define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U)
#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U)
/*! AXI_RD_ERR - AXI Bus read error interrupt flag
* 0b0..No error
* 0b1..Error occured during read
*/
#define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U)
/*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
* 0b0..No error
* 0b1..Error occured during write
*/
#define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U)
/*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
* 0b0..No error
* 0b1..Error occured during write
*/
#define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)
#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U)
#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U)
/*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
* 0b0..No error
* 0b1..Error occured during write
*/
#define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)
#define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U)
#define ISI_CHNL_STS_FRM_STRD_SHIFT (29U)
/*! FRM_STRD - Frame stored successfully interrupt flag
* 0b0..No frame being received or in progress
* 0b1..One full frame has been received and stored in memory
*/
#define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)
#define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U)
#define ISI_CHNL_STS_LINE_STRD_SHIFT (30U)
/*! LINE_STRD - Line received and stored interrupt flag
* 0b0..No new line received
* 0b1..New line received and stored into memory
*/
#define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)
#define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U)
#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U)
/*! MEM_RD_DONE - Memory read complete interrupt flag
* 0b0..Image read from memory not complete or not started
* 0b1..Image read from memory completed
*/
#define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
/*! @} */
/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
/*! @{ */
#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU)
#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U)
/*! X_SCALE - Horizontal scaling factor
*/
#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U)
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U)
/*! Y_SCALE - Vertical scaling factor
*/
#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)
/*! @} */
/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
/*! @{ */
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU)
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U)
/*! X_OFFSET - Horizontal scaling offset
*/
#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U)
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U)
/*! Y_OFFSET - Vertical scaling offset
*/
#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)
/*! @} */
/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
/*! @{ */
#define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU)
#define ISI_CHNL_CROP_ULC_Y_SHIFT (0U)
/*! Y - Upper Left Y-coordinate
*/
#define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)
#define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U)
#define ISI_CHNL_CROP_ULC_X_SHIFT (16U)
/*! X - Upper Left X-coordinate
*/
#define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)
/*! @} */
/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
/*! @{ */
#define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU)
#define ISI_CHNL_CROP_LRC_Y_SHIFT (0U)
/*! Y - Lower Right Y-coordinate
*/
#define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)
#define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U)
#define ISI_CHNL_CROP_LRC_X_SHIFT (16U)
/*! X - Lower Right X-coordinate
*/
#define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU)
#define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U)
/*! A1 - CSC Coefficient A1 value
*/
#define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)
#define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U)
/*! A2 - CSC Coefficient A2 value
*/
#define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU)
#define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U)
/*! A3 - CSC Coefficient A3 value
*/
#define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)
#define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U)
/*! B1 - CSC Coefficient B1 value
*/
#define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU)
#define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U)
/*! B2 - CSC Coefficient B2 value
*/
#define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)
#define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U)
/*! B3 - CSC Coefficient B3 value
*/
#define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU)
#define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U)
/*! C1 - CSC Coefficient C1 value
*/
#define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)
#define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U)
#define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U)
/*! C2 - CSC Coefficient C2 value
*/
#define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU)
#define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U)
/*! C3 - CSC Coefficient C3 value
*/
#define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)
#define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U)
/*! D1 - CSC Coefficient D1 value
*/
#define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)
/*! @} */
/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
/*! @{ */
#define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU)
#define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U)
/*! D2 - CSC Coefficient D2 value
*/
#define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)
#define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U)
#define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U)
/*! D3 - CSC Coefficient D3 value
*/
#define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)
/*! @} */
/*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value Register for Region of Interest 0 */
/*! @{ */
#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U)
#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U)
/*! ALPHA_EN - Alpha value insertion enable
* 0b0..Alpha value insertion is disabled
* 0b1..Alpha value insertion is enabled
*/
#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK)
#define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U)
#define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U)
/*! ALPHA - Alpha Value to be inserted with image
*/
#define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK)
/*! @} */
/*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate Register for Region of Interest 0 */
/*! @{ */
#define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U)
/*! Y - Upper Left Y-coordinate
*/
#define ISI_CHNL_ROI_0_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK)
#define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U)
/*! X - Upper Left X-coordinate
*/
#define ISI_CHNL_ROI_0_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate Register for Region of Interest 0 */
/*! @{ */
#define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U)
/*! Y - Lower Right Y-coordinate
*/
#define ISI_CHNL_ROI_0_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK)
#define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U)
/*! X - Lower Right X-coordinate
*/
#define ISI_CHNL_ROI_0_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value Register for Region of Interest 1 */
/*! @{ */
#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U)
#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U)
/*! ALPHA_EN - Alpha value insertion enable
* 0b0..Alpha value insertion is disabled
* 0b1..Alpha value insertion is enabled
*/
#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK)
#define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U)
#define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U)
/*! ALPHA - Alpha Value to be inserted with image
*/
#define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK)
/*! @} */
/*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate Register for Region of Interest 1 */
/*! @{ */
#define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U)
/*! Y - Upper Left Y-coordinate
*/
#define ISI_CHNL_ROI_1_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK)
#define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U)
/*! X - Upper Left X-coordinate
*/
#define ISI_CHNL_ROI_1_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate Register for Region of Interest 1 */
/*! @{ */
#define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U)
/*! Y - Lower Right Y-coordinate
*/
#define ISI_CHNL_ROI_1_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK)
#define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U)
/*! X - Lower Right X-coordinate
*/
#define ISI_CHNL_ROI_1_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value Register for Region of Interest 2 */
/*! @{ */
#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U)
#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U)
/*! ALPHA_EN - Alpha value insertion enable
* 0b0..Alpha value insertion is disabled
* 0b1..Alpha value insertion is enabled
*/
#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK)
#define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U)
#define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U)
/*! ALPHA - Alpha Value to be inserted with image
*/
#define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK)
/*! @} */
/*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate Register for Region of Interest 2 */
/*! @{ */
#define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U)
/*! Y - Upper Left Y-coordinate
*/
#define ISI_CHNL_ROI_2_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK)
#define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U)
/*! X - Upper Left X-coordinate
*/
#define ISI_CHNL_ROI_2_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate Register for Region of Interest 2 */
/*! @{ */
#define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U)
/*! Y - Lower Right Y-coordinate
*/
#define ISI_CHNL_ROI_2_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK)
#define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U)
/*! X - Lower Right X-coordinate
*/
#define ISI_CHNL_ROI_2_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U)
#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U)
/*! ALPHA_EN - Alpha value insertion enable
* 0b0..Alpha value insertion is disabled
* 0b1..Alpha value insertion is enabled
*/
#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK)
#define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U)
#define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U)
/*! ALPHA - Alpha Value to be inserted with image
*/
#define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK)
/*! @} */
/*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U)
/*! Y - Upper Left Y-coordinate
*/
#define ISI_CHNL_ROI_3_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK)
#define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U)
/*! X - Upper Left X-coordinate
*/
#define ISI_CHNL_ROI_3_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK)
/*! @} */
/*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate Register for Region of Interest 3 */
/*! @{ */
#define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU)
#define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U)
/*! Y - Lower Right Y-coordinate
*/
#define ISI_CHNL_ROI_3_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK)
#define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U)
#define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U)
/*! X - Lower Right X-coordinate
*/
#define ISI_CHNL_ROI_3_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the RGB or Y (luma) memory location
*/
#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location
*/
#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the V/Cr memory location
*/
#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
/*! @{ */
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU)
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U)
/*! LINE_PITCH - Output Buffer Line Pitch
*/
#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
/*! @} */
/*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
/*! @{ */
#define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U)
#define ISI_CHNL_IN_BUF_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
/*! @} */
/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
/*! @{ */
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU)
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U)
/*! LINE_PITCH - Line Pitch
*/
#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U)
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U)
/*! FRM_PITCH - Frame Pitch
*/
#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
/*! @} */
/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
/*! @{ */
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U)
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U)
/*! READ_MEM - Initiate read from memory
* 0b0..No reads from memory done
* 0b1..Reads from memory initiated
*/
#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U)
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U)
/*! IMG_TYPE - Input image format
* 0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
* 0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
* 0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
* 0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
* 0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
* 0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
* 0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
* 0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
* 0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
* 0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit WORD)
* 0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
* 0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in 32-bit DWORD)
* 0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV interleaved packed bytes
* 0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD)
* 0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
*/
#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the RGB or Y (luma) memory location
*/
#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the U/Cb or 2 plane UV/CbCr Chroma memory location
*/
#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
/*! @} */
/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
/*! @{ */
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU)
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U)
/*! ADDR - Starting address for the V/Cr memory location
*/
#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
/*! @} */
/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
/*! @{ */
#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU)
#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U)
/*! WIDTH - Scaled image width (pixels)
*/
#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U)
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U)
/*! HEIGHT - Scaled image height (lines)
*/
#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)
/*! @} */
/*! @name CHNL_FLOW_CTRL - Channel Flow Control Register */
/*! @{ */
#define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU)
#define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U)
/*! FC_DENOM - Denominator value of fraction of usable bandwidth
* 0b00000000..Invalid value. Flow control will be disabled.
*/
#define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK)
#define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U)
#define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U)
/*! FC_NUMER - Numertor value of fraction of usable bandwidth
* 0b00000000..Flow control is disabled.
*/
#define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK)
/*! @} */
/*! @name CHNL_Y_BUF1_XTND_ADDR - Channel Output Y-Buffer 1 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT (0U)
/*! Y1ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF1_XTND_ADDR_Y1ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_U_BUF1_XTND_ADDR - Channel Output U-Buffer 1 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT (0U)
/*! U1ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF1_XTND_ADDR_U1ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_V_BUF1_XTND_ADDR - Channel Output V-Buffer 1 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT (0U)
/*! V1ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF1_XTND_ADDR_V1ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_Y_BUF2_XTND_ADDR - Channel Output Y-Buffer 2 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT (0U)
/*! Y2ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_SHIFT)) & ISI_CHNL_Y_BUF2_XTND_ADDR_Y2ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_U_BUF2_XTND_ADDR - Channel Output U-Buffer 2 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT (0U)
/*! U2ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_SHIFT)) & ISI_CHNL_U_BUF2_XTND_ADDR_U2ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_V_BUF2_XTND_ADDR - Channel Output V-Buffer 2 Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK (0xFU)
#define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT (0U)
/*! V2ADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_SHIFT)) & ISI_CHNL_V_BUF2_XTND_ADDR_V2ADDR_MSB_MASK)
/*! @} */
/*! @name CHNL_IN_BUF_XTND_ADDR - Channel Input Buffer Extended Address Bits Register */
/*! @{ */
#define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK (0xFU)
#define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT (0U)
/*! XADDR_MSB - Extended Address Most Significant Bits
*/
#define ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_SHIFT)) & ISI_CHNL_IN_BUF_XTND_ADDR_XADDR_MSB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ISI_Register_Masks */
/* ISI - Peripheral instance base addresses */
/** Peripheral ISI base address */
#define ISI_BASE (0x32E00000u)
/** Peripheral ISI base pointer */
#define ISI ((ISI_Type *)ISI_BASE)
/** Array initializer of ISI peripheral base addresses */
#define ISI_BASE_ADDRS { ISI_BASE }
/** Array initializer of ISI peripheral base pointers */
#define ISI_BASE_PTRS { ISI }
/*!
* @}
*/ /* end of group ISI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LCDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
* @{
*/
/** LCDIF - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< LCDIF display control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< LCDIF display control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< LCDIF display control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< LCDIF display control Register, offset: 0xC */
__IO uint32_t DISP_PARA; /**< Display Parameter Register, offset: 0x10 */
__IO uint32_t DISP_SIZE; /**< Display Size Register, offset: 0x14 */
__IO uint32_t HSYN_PARA; /**< Horizontal Sync Parameter Register, offset: 0x18 */
__IO uint32_t VSYN_PARA; /**< Vertical Sync Parameter Register, offset: 0x1C */
__IO uint32_t VSYN_HSYN_WIDTH; /**< Vertical and Horizontal Pulse Width Parameter Register, offset: 0x20 */
__IO uint32_t INT_STATUS_D0; /**< Interrupt Status Register for domain 0, offset: 0x24 */
__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offset: 0x28 */
uint8_t RESERVED_0[4];
__IO uint32_t INT_STATUS_D1; /**< Interrupt Status Register for domain 0, offset: 0x30 */
__IO uint32_t INT_ENABLE_D1; /**< Interrupt Enable Register for domain 0, offset: 0x34 */
uint8_t RESERVED_1[456];
__IO uint32_t CTRLDESCL0_1; /**< Control Descriptor Layer Register 1, offset: 0x200 */
uint8_t RESERVED_2[4];
__IO uint32_t CTRLDESCL0_3; /**< Control Descriptor Layer Register 3, offset: 0x208 */
__IO uint32_t CTRLDESCL_LOW0_4; /**< Control Descriptor Layer Register 4, offset: 0x20C */
__IO uint32_t CTRLDESCL_HIGH0_4; /**< Control Descriptor Layer Register 4, offset: 0x210 */
__IO uint32_t CTRLDESCL0_5; /**< Control Descriptor Layer Register 5, offset: 0x214 */
uint8_t RESERVED_3[4];
__IO uint32_t CSC0_CTRL; /**< Color Space Conversion Ctrl Register, offset: 0x21C */
__IO uint32_t CSC0_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x220 */
__IO uint32_t CSC0_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x224 */
__IO uint32_t CSC0_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x228 */
__IO uint32_t CSC0_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x22C */
__IO uint32_t CSC0_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x230 */
__IO uint32_t CSC0_COEF5; /**< Color Space Conversion Coefficient Register 0, offset: 0x234 */
__IO uint32_t PANIC0_THRES; /**< Memory request priority threshold register, offset: 0x238 */
} LCDIF_Type;
/* ----------------------------------------------------------------------------
-- LCDIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Register_Masks LCDIF Register Masks
* @{
*/
/*! @name CTRL - LCDIF display control Register */
/*! @{ */
#define LCDIF_CTRL_INV_HS_MASK (0x1U)
#define LCDIF_CTRL_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal.
* 0b0..HSYNC signal not inverted (active HIGH).
* 0b1..Invert HSYNC signal (active LOW).
*/
#define LCDIF_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_HS_SHIFT)) & LCDIF_CTRL_INV_HS_MASK)
#define LCDIF_CTRL_INV_VS_MASK (0x2U)
#define LCDIF_CTRL_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal.
* 0b0..VSYNC signal not inverted (active HIGH).
* 0b1..Invert VSYNC signal (active LOW).
*/
#define LCDIF_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_VS_SHIFT)) & LCDIF_CTRL_INV_VS_MASK)
#define LCDIF_CTRL_INV_DE_MASK (0x4U)
#define LCDIF_CTRL_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
* 0b0..Data enable is active high
* 0b1..Data enable is active low
*/
#define LCDIF_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_DE_SHIFT)) & LCDIF_CTRL_INV_DE_MASK)
#define LCDIF_CTRL_INV_PXCK_MASK (0x8U)
#define LCDIF_CTRL_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock.
* 0b0..Display samples data on the falling edge
* 0b1..Display samples data on the rising edge
*/
#define LCDIF_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INV_PXCK_SHIFT)) & LCDIF_CTRL_INV_PXCK_MASK)
#define LCDIF_CTRL_NEG_MASK (0x10U)
#define LCDIF_CTRL_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
* 0b0..Output is to remain same
* 0b1..Output to be negated
*/
#define LCDIF_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_NEG_SHIFT)) & LCDIF_CTRL_NEG_MASK)
#define LCDIF_CTRL_fetch_start_option_MASK (0x300U)
#define LCDIF_CTRL_fetch_start_option_SHIFT (8U)
/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
* 0b00..fetch start as soon as FPV begins(as the end of the data_enable)
* 0b01..fetch start as soon as PWV begins
* 0b10..fetch start as soon as BPV begins
* 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
*/
#define LCDIF_CTRL_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_fetch_start_option_SHIFT)) & LCDIF_CTRL_fetch_start_option_MASK)
#define LCDIF_CTRL_SW_RESET_MASK (0x80000000U)
#define LCDIF_CTRL_SW_RESET_SHIFT (31U)
/*! SW_RESET - SW_RESET
* 0b0..No action
* 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
*/
#define LCDIF_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SW_RESET_SHIFT)) & LCDIF_CTRL_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_SET - LCDIF display control Register */
/*! @{ */
#define LCDIF_CTRL_SET_INV_HS_MASK (0x1U)
#define LCDIF_CTRL_SET_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal.
* 0b0..HSYNC signal not inverted (active HIGH).
* 0b1..Invert HSYNC signal (active LOW).
*/
#define LCDIF_CTRL_SET_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_HS_SHIFT)) & LCDIF_CTRL_SET_INV_HS_MASK)
#define LCDIF_CTRL_SET_INV_VS_MASK (0x2U)
#define LCDIF_CTRL_SET_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal.
* 0b0..VSYNC signal not inverted (active HIGH).
* 0b1..Invert VSYNC signal (active LOW).
*/
#define LCDIF_CTRL_SET_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_VS_SHIFT)) & LCDIF_CTRL_SET_INV_VS_MASK)
#define LCDIF_CTRL_SET_INV_DE_MASK (0x4U)
#define LCDIF_CTRL_SET_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
* 0b0..Data enable is active high
* 0b1..Data enable is active low
*/
#define LCDIF_CTRL_SET_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_DE_SHIFT)) & LCDIF_CTRL_SET_INV_DE_MASK)
#define LCDIF_CTRL_SET_INV_PXCK_MASK (0x8U)
#define LCDIF_CTRL_SET_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock.
* 0b0..Display samples data on the falling edge
* 0b1..Display samples data on the rising edge
*/
#define LCDIF_CTRL_SET_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INV_PXCK_SHIFT)) & LCDIF_CTRL_SET_INV_PXCK_MASK)
#define LCDIF_CTRL_SET_NEG_MASK (0x10U)
#define LCDIF_CTRL_SET_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
* 0b0..Output is to remain same
* 0b1..Output to be negated
*/
#define LCDIF_CTRL_SET_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_NEG_SHIFT)) & LCDIF_CTRL_SET_NEG_MASK)
#define LCDIF_CTRL_SET_fetch_start_option_MASK (0x300U)
#define LCDIF_CTRL_SET_fetch_start_option_SHIFT (8U)
/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
* 0b00..fetch start as soon as FPV begins(as the end of the data_enable)
* 0b01..fetch start as soon as PWV begins
* 0b10..fetch start as soon as BPV begins
* 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
*/
#define LCDIF_CTRL_SET_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_fetch_start_option_SHIFT)) & LCDIF_CTRL_SET_fetch_start_option_MASK)
#define LCDIF_CTRL_SET_SW_RESET_MASK (0x80000000U)
#define LCDIF_CTRL_SET_SW_RESET_SHIFT (31U)
/*! SW_RESET - SW_RESET
* 0b0..No action
* 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
*/
#define LCDIF_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SW_RESET_SHIFT)) & LCDIF_CTRL_SET_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_CLR - LCDIF display control Register */
/*! @{ */
#define LCDIF_CTRL_CLR_INV_HS_MASK (0x1U)
#define LCDIF_CTRL_CLR_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal.
* 0b0..HSYNC signal not inverted (active HIGH).
* 0b1..Invert HSYNC signal (active LOW).
*/
#define LCDIF_CTRL_CLR_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_HS_SHIFT)) & LCDIF_CTRL_CLR_INV_HS_MASK)
#define LCDIF_CTRL_CLR_INV_VS_MASK (0x2U)
#define LCDIF_CTRL_CLR_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal.
* 0b0..VSYNC signal not inverted (active HIGH).
* 0b1..Invert VSYNC signal (active LOW).
*/
#define LCDIF_CTRL_CLR_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_VS_SHIFT)) & LCDIF_CTRL_CLR_INV_VS_MASK)
#define LCDIF_CTRL_CLR_INV_DE_MASK (0x4U)
#define LCDIF_CTRL_CLR_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
* 0b0..Data enable is active high
* 0b1..Data enable is active low
*/
#define LCDIF_CTRL_CLR_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_DE_SHIFT)) & LCDIF_CTRL_CLR_INV_DE_MASK)
#define LCDIF_CTRL_CLR_INV_PXCK_MASK (0x8U)
#define LCDIF_CTRL_CLR_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock.
* 0b0..Display samples data on the falling edge
* 0b1..Display samples data on the rising edge
*/
#define LCDIF_CTRL_CLR_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIF_CTRL_CLR_INV_PXCK_MASK)
#define LCDIF_CTRL_CLR_NEG_MASK (0x10U)
#define LCDIF_CTRL_CLR_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
* 0b0..Output is to remain same
* 0b1..Output to be negated
*/
#define LCDIF_CTRL_CLR_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_NEG_SHIFT)) & LCDIF_CTRL_CLR_NEG_MASK)
#define LCDIF_CTRL_CLR_fetch_start_option_MASK (0x300U)
#define LCDIF_CTRL_CLR_fetch_start_option_SHIFT (8U)
/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
* 0b00..fetch start as soon as FPV begins(as the end of the data_enable)
* 0b01..fetch start as soon as PWV begins
* 0b10..fetch start as soon as BPV begins
* 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
*/
#define LCDIF_CTRL_CLR_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_fetch_start_option_SHIFT)) & LCDIF_CTRL_CLR_fetch_start_option_MASK)
#define LCDIF_CTRL_CLR_SW_RESET_MASK (0x80000000U)
#define LCDIF_CTRL_CLR_SW_RESET_SHIFT (31U)
/*! SW_RESET - SW_RESET
* 0b0..No action
* 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
*/
#define LCDIF_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SW_RESET_SHIFT)) & LCDIF_CTRL_CLR_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_TOG - LCDIF display control Register */
/*! @{ */
#define LCDIF_CTRL_TOG_INV_HS_MASK (0x1U)
#define LCDIF_CTRL_TOG_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal.
* 0b0..HSYNC signal not inverted (active HIGH).
* 0b1..Invert HSYNC signal (active LOW).
*/
#define LCDIF_CTRL_TOG_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_HS_SHIFT)) & LCDIF_CTRL_TOG_INV_HS_MASK)
#define LCDIF_CTRL_TOG_INV_VS_MASK (0x2U)
#define LCDIF_CTRL_TOG_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal.
* 0b0..VSYNC signal not inverted (active HIGH).
* 0b1..Invert VSYNC signal (active LOW).
*/
#define LCDIF_CTRL_TOG_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_VS_SHIFT)) & LCDIF_CTRL_TOG_INV_VS_MASK)
#define LCDIF_CTRL_TOG_INV_DE_MASK (0x4U)
#define LCDIF_CTRL_TOG_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
* 0b0..Data enable is active high
* 0b1..Data enable is active low
*/
#define LCDIF_CTRL_TOG_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_DE_SHIFT)) & LCDIF_CTRL_TOG_INV_DE_MASK)
#define LCDIF_CTRL_TOG_INV_PXCK_MASK (0x8U)
#define LCDIF_CTRL_TOG_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock.
* 0b0..Display samples data on the falling edge
* 0b1..Display samples data on the rising edge
*/
#define LCDIF_CTRL_TOG_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIF_CTRL_TOG_INV_PXCK_MASK)
#define LCDIF_CTRL_TOG_NEG_MASK (0x10U)
#define LCDIF_CTRL_TOG_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated.
* 0b0..Output is to remain same
* 0b1..Output to be negated
*/
#define LCDIF_CTRL_TOG_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_NEG_SHIFT)) & LCDIF_CTRL_TOG_NEG_MASK)
#define LCDIF_CTRL_TOG_fetch_start_option_MASK (0x300U)
#define LCDIF_CTRL_TOG_fetch_start_option_SHIFT (8U)
/*! fetch_start_option - Indicates when to start fetching for new frame. This signals also decide the shadow load, fifo clear time
* 0b00..fetch start as soon as FPV begins(as the end of the data_enable)
* 0b01..fetch start as soon as PWV begins
* 0b10..fetch start as soon as BPV begins
* 0b11..fetch start as soon as RESV begins(still have hsync blanking for margin)
*/
#define LCDIF_CTRL_TOG_fetch_start_option(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_fetch_start_option_SHIFT)) & LCDIF_CTRL_TOG_fetch_start_option_MASK)
#define LCDIF_CTRL_TOG_SW_RESET_MASK (0x80000000U)
#define LCDIF_CTRL_TOG_SW_RESET_SHIFT (31U)
/*! SW_RESET - SW_RESET
* 0b0..No action
* 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected.
*/
#define LCDIF_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SW_RESET_SHIFT)) & LCDIF_CTRL_TOG_SW_RESET_MASK)
/*! @} */
/*! @name DISP_PARA - Display Parameter Register */
/*! @{ */
#define LCDIF_DISP_PARA_BGND_B_MASK (0xFFU)
#define LCDIF_DISP_PARA_BGND_B_SHIFT (0U)
/*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active.
*/
#define LCDIF_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_B_SHIFT)) & LCDIF_DISP_PARA_BGND_B_MASK)
#define LCDIF_DISP_PARA_BGND_G_MASK (0xFF00U)
#define LCDIF_DISP_PARA_BGND_G_SHIFT (8U)
/*! BGND_G - Green component of the default color displayed in the sectors where no layer is active.
*/
#define LCDIF_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_G_SHIFT)) & LCDIF_DISP_PARA_BGND_G_MASK)
#define LCDIF_DISP_PARA_BGND_R_MASK (0xFF0000U)
#define LCDIF_DISP_PARA_BGND_R_SHIFT (16U)
/*! BGND_R - Red component of the default color displayed in the sectors where no layer is active.
*/
#define LCDIF_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_BGND_R_SHIFT)) & LCDIF_DISP_PARA_BGND_R_MASK)
#define LCDIF_DISP_PARA_DISP_MODE_MASK (0x3000000U)
#define LCDIF_DISP_PARA_DISP_MODE_SHIFT (24U)
/*! DISP_MODE - LCDIF operating mode.
* 0b00..Normal mode. Panel content controlled by layer configuration.
* 0b01..Test Mode1.(BGND Color Display)
* 0b10..Test Mode2.(Column Color Bar)
* 0b11..Test Mode3.(Row Color Bar)
*/
#define LCDIF_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_MODE_SHIFT)) & LCDIF_DISP_PARA_DISP_MODE_MASK)
#define LCDIF_DISP_PARA_LINE_PATTERN_MASK (0x3C000000U)
#define LCDIF_DISP_PARA_LINE_PATTERN_SHIFT (26U)
/*! LINE_PATTERN - LCDIF line output order.
* 0b0000..RGB/YUV.
* 0b0001..RBG.
* 0b0010..GBR.
* 0b0011..GRB/UYV.
* 0b0100..BRG.
* 0b0101..BGR.
* 0b0110..RGB555.
* 0b0111..RGB565.
* 0b1000..YUYV at [16:0].
* 0b1001..UYVY at [16:0].
* 0b1010..YVYU at [16:0].
* 0b1011..YUYV at [16:0].
* 0b1100..YUYV at [23:8].
* 0b1101..UYVY at [23:8].
* 0b1110..YVYU at [23:8].
* 0b1111..YUYV at [23:8].
*/
#define LCDIF_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIF_DISP_PARA_LINE_PATTERN_MASK)
#define LCDIF_DISP_PARA_SWAP_EN_MASK (0x40000000U)
#define LCDIF_DISP_PARA_SWAP_EN_SHIFT (30U)
/*! SWAP_EN - output data swap enable.
* 0b0..swap disable
* 0b1..swap enbale, output data will swap the high 16bits with the low 16bits.
*/
#define LCDIF_DISP_PARA_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_SWAP_EN_SHIFT)) & LCDIF_DISP_PARA_SWAP_EN_MASK)
#define LCDIF_DISP_PARA_DISP_ON_MASK (0x80000000U)
#define LCDIF_DISP_PARA_DISP_ON_SHIFT (31U)
/*! DISP_ON - Display panel On/Off mode.
* 0b0..Display Off.
* 0b1..Display On.
*/
#define LCDIF_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_PARA_DISP_ON_SHIFT)) & LCDIF_DISP_PARA_DISP_ON_MASK)
/*! @} */
/*! @name DISP_SIZE - Display Size Register */
/*! @{ */
#define LCDIF_DISP_SIZE_DELTA_X_MASK (0xFFFFU)
#define LCDIF_DISP_SIZE_DELTA_X_SHIFT (0U)
/*! DELTA_X - Sets the display size horizontal resolution in pixels.
*/
#define LCDIF_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_X_SHIFT)) & LCDIF_DISP_SIZE_DELTA_X_MASK)
#define LCDIF_DISP_SIZE_DELTA_Y_MASK (0xFFFF0000U)
#define LCDIF_DISP_SIZE_DELTA_Y_SHIFT (16U)
/*! DELTA_Y - Sets the display size vertical resolution in pixels.
*/
#define LCDIF_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIF_DISP_SIZE_DELTA_Y_MASK)
/*! @} */
/*! @name HSYN_PARA - Horizontal Sync Parameter Register */
/*! @{ */
#define LCDIF_HSYN_PARA_FP_H_MASK (0xFFFFU)
#define LCDIF_HSYN_PARA_FP_H_SHIFT (0U)
/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_FP_H_SHIFT)) & LCDIF_HSYN_PARA_FP_H_MASK)
#define LCDIF_HSYN_PARA_BP_H_MASK (0xFFFF0000U)
#define LCDIF_HSYN_PARA_BP_H_SHIFT (16U)
/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_HSYN_PARA_BP_H_SHIFT)) & LCDIF_HSYN_PARA_BP_H_MASK)
/*! @} */
/*! @name VSYN_PARA - Vertical Sync Parameter Register */
/*! @{ */
#define LCDIF_VSYN_PARA_FP_V_MASK (0xFFFFU)
#define LCDIF_VSYN_PARA_FP_V_SHIFT (0U)
/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_FP_V_SHIFT)) & LCDIF_VSYN_PARA_FP_V_MASK)
#define LCDIF_VSYN_PARA_BP_V_MASK (0xFFFF0000U)
#define LCDIF_VSYN_PARA_BP_V_SHIFT (16U)
/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_PARA_BP_V_SHIFT)) & LCDIF_VSYN_PARA_BP_V_MASK)
/*! @} */
/*! @name VSYN_HSYN_WIDTH - Vertical and Horizontal Pulse Width Parameter Register */
/*! @{ */
#define LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK (0xFFFFU)
#define LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT (0U)
/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_VSYN_HSYN_WIDTH_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_H_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_H_MASK)
#define LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK (0xFFFF0000U)
#define LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT (16U)
/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1.
*/
#define LCDIF_VSYN_HSYN_WIDTH_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VSYN_HSYN_WIDTH_PW_V_SHIFT)) & LCDIF_VSYN_HSYN_WIDTH_PW_V_MASK)
/*! @} */
/*! @name INT_STATUS_D0 - Interrupt Status Register for domain 0 */
/*! @{ */
#define LCDIF_INT_STATUS_D0_VSYNC_MASK (0x1U)
#define LCDIF_INT_STATUS_D0_VSYNC_SHIFT (0U)
/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame).
*/
#define LCDIF_INT_STATUS_D0_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VSYNC_SHIFT)) & LCDIF_INT_STATUS_D0_VSYNC_MASK)
#define LCDIF_INT_STATUS_D0_UNDERRUN_MASK (0x2U)
#define LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT (1U)
/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition.
*/
#define LCDIF_INT_STATUS_D0_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_UNDERRUN_SHIFT)) & LCDIF_INT_STATUS_D0_UNDERRUN_MASK)
#define LCDIF_INT_STATUS_D0_VS_BLANK_MASK (0x4U)
#define LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT (2U)
/*! VS_BLANK - Interrupt flag to indicate vertical blanking period.
*/
#define LCDIF_INT_STATUS_D0_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_VS_BLANK_SHIFT)) & LCDIF_INT_STATUS_D0_VS_BLANK_MASK)
#define LCDIF_INT_STATUS_D0_DMA_ERR_MASK (0x100U)
#define LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT (8U)
/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface.
*/
#define LCDIF_INT_STATUS_D0_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_ERR_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_ERR_MASK)
#define LCDIF_INT_STATUS_D0_DMA_DONE_MASK (0x10000U)
#define LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT (16U)
/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory.
*/
#define LCDIF_INT_STATUS_D0_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_DMA_DONE_SHIFT)) & LCDIF_INT_STATUS_D0_DMA_DONE_MASK)
#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK (0x1000000U)
#define LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT (24U)
/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed.
*/
#define LCDIF_INT_STATUS_D0_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D0_FIFO_EMPTY_SHIFT)) & LCDIF_INT_STATUS_D0_FIFO_EMPTY_MASK)
/*! @} */
/*! @name INT_ENABLE_D0 - Interrupt Enable Register for domain 0 */
/*! @{ */
#define LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK (0x1U)
#define LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT (0U)
/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame).
*/
#define LCDIF_INT_ENABLE_D0_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VSYNC_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VSYNC_EN_MASK)
#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK (0x2U)
#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT (1U)
/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition.
*/
#define LCDIF_INT_ENABLE_D0_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_UNDERRUN_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_UNDERRUN_EN_MASK)
#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK (0x4U)
#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT (2U)
/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period.
*/
#define LCDIF_INT_ENABLE_D0_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_VS_BLANK_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_VS_BLANK_EN_MASK)
#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK (0x100U)
#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT (8U)
/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface.
*/
#define LCDIF_INT_ENABLE_D0_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_ERR_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_ERR_EN_MASK)
#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK (0x10000U)
#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT (16U)
/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory.
*/
#define LCDIF_INT_ENABLE_D0_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_DMA_DONE_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_DMA_DONE_EN_MASK)
#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK (0x1000000U)
#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT (24U)
/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed.
*/
#define LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_SHIFT)) & LCDIF_INT_ENABLE_D0_FIFO_EMPTY_EN_MASK)
/*! @} */
/*! @name INT_STATUS_D1 - Interrupt Status Register for domain 0 */
/*! @{ */
#define LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK (0x1U)
#define LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT (0U)
/*! PLANE_PANIC - plane panic to indicate that which FIFO reaches the panic threshold.
*/
#define LCDIF_INT_STATUS_D1_PLANE_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_STATUS_D1_PLANE_PANIC_SHIFT)) & LCDIF_INT_STATUS_D1_PLANE_PANIC_MASK)
/*! @} */
/*! @name INT_ENABLE_D1 - Interrupt Enable Register for domain 0 */
/*! @{ */
#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK (0x1U)
#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT (0U)
/*! PLANE_PANIC_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed.
*/
#define LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_SHIFT)) & LCDIF_INT_ENABLE_D1_PLANE_PANIC_EN_MASK)
/*! @} */
/*! @name CTRLDESCL0_1 - Control Descriptor Layer Register 1 */
/*! @{ */
#define LCDIF_CTRLDESCL0_1_WIDTH_MASK (0xFFFFU)
#define LCDIF_CTRLDESCL0_1_WIDTH_SHIFT (0U)
/*! WIDTH - Width of the layer in pixels.
*/
#define LCDIF_CTRLDESCL0_1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_1_WIDTH_SHIFT)) & LCDIF_CTRLDESCL0_1_WIDTH_MASK)
#define LCDIF_CTRLDESCL0_1_HEIGHT_MASK (0xFFFF0000U)
#define LCDIF_CTRLDESCL0_1_HEIGHT_SHIFT (16U)
/*! HEIGHT - Height of the layer in pixels.
*/
#define LCDIF_CTRLDESCL0_1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_1_HEIGHT_SHIFT)) & LCDIF_CTRLDESCL0_1_HEIGHT_MASK)
/*! @} */
/*! @name CTRLDESCL0_3 - Control Descriptor Layer Register 3 */
/*! @{ */
#define LCDIF_CTRLDESCL0_3_PITCH_MASK (0xFFFFU)
#define LCDIF_CTRLDESCL0_3_PITCH_SHIFT (0U)
/*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
* is supported, but SW should align to 64B boundry.
*/
#define LCDIF_CTRLDESCL0_3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_3_PITCH_SHIFT)) & LCDIF_CTRLDESCL0_3_PITCH_MASK)
/*! @} */
/*! @name CTRLDESCL_LOW0_4 - Control Descriptor Layer Register 4 */
/*! @{ */
#define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_MASK (0xFFFFFFFFU)
#define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_SHIFT (0U)
/*! ADDR_LOW - Address of layer data in the memory. The address programmed should be 64-bit aligned.
*/
#define LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_SHIFT)) & LCDIF_CTRLDESCL_LOW0_4_ADDR_LOW_MASK)
/*! @} */
/*! @name CTRLDESCL_HIGH0_4 - Control Descriptor Layer Register 4 */
/*! @{ */
#define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK (0xFU)
#define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_SHIFT (0U)
/*! ADDR_HIGH - Address of layer data in the memory. The address programmed should be 64-bit aligned.
*/
#define LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_SHIFT)) & LCDIF_CTRLDESCL_HIGH0_4_ADDR_HIGH_MASK)
/*! @} */
/*! @name CTRLDESCL0_5 - Control Descriptor Layer Register 5 */
/*! @{ */
#define LCDIF_CTRLDESCL0_5_YUV_FORMAT_MASK (0xC000U)
#define LCDIF_CTRLDESCL0_5_YUV_FORMAT_SHIFT (14U)
/*! YUV_FORMAT - The YUV422 input format selection.
* 0b00..The YUV422 32bit memory is {Y2,V1,Y1,U1}
* 0b01..The YUV422 32bit memory is {Y2,U1,Y1,V1}
* 0b10..The YUV422 32bit memory is {V1,Y2,U1,Y1}
* 0b11..The YUV422 32bit memory is {U1,Y2,V1,Y1}
*/
#define LCDIF_CTRLDESCL0_5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_YUV_FORMAT_SHIFT)) & LCDIF_CTRLDESCL0_5_YUV_FORMAT_MASK)
#define LCDIF_CTRLDESCL0_5_BPP_MASK (0xF000000U)
#define LCDIF_CTRLDESCL0_5_BPP_SHIFT (24U)
/*! BPP - Layer encoding format (bit per pixel)
* 0b0100..16 bpp (RGB565)
* 0b0101..16 bpp (ARGB1555)
* 0b0110..16 bpp (ARGB4444)
* 0b0111..YCbCr422
* 0b1000..24 bpp (RGB888)
* 0b1001..32 bpp (ARGB8888)
* 0b1010..32 bpp (ABGR8888)
*/
#define LCDIF_CTRLDESCL0_5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_BPP_SHIFT)) & LCDIF_CTRLDESCL0_5_BPP_MASK)
#define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_MASK (0x40000000U)
#define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_SHIFT (30U)
/*! SHADOW_LOAD_EN - Shadow Load Enable
*/
#define LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_SHIFT)) & LCDIF_CTRLDESCL0_5_SHADOW_LOAD_EN_MASK)
#define LCDIF_CTRLDESCL0_5_EN_MASK (0x80000000U)
#define LCDIF_CTRLDESCL0_5_EN_SHIFT (31U)
/*! EN - Enable the layer for DMA.
* 0b0..OFF
* 0b1..ON
*/
#define LCDIF_CTRLDESCL0_5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRLDESCL0_5_EN_SHIFT)) & LCDIF_CTRLDESCL0_5_EN_MASK)
/*! @} */
/*! @name CSC0_CTRL - Color Space Conversion Ctrl Register */
/*! @{ */
#define LCDIF_CSC0_CTRL_BYPASS_MASK (0x1U)
#define LCDIF_CSC0_CTRL_BYPASS_SHIFT (0U)
/*! BYPASS - This bit controls whether the pixels entering the CSC2 unit get converted or not. When
* BYPASS is set, no operations occur on the pixels. When BYPASS is cleared, the selected CSC
* operation takes place.
*/
#define LCDIF_CSC0_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_CTRL_BYPASS_SHIFT)) & LCDIF_CSC0_CTRL_BYPASS_MASK)
#define LCDIF_CSC0_CTRL_CSC_MODE_MASK (0x6U)
#define LCDIF_CSC0_CTRL_CSC_MODE_SHIFT (1U)
/*! CSC_MODE - This field controls how the CSC unit operates on pixels when the CSC is not bypassed.
* 0x0 YUV2RGB--Convert from YUV to RGB. 0x1 YCbCr2RGB-- Convert from YCbCr to RGB. 0x2 RGB2YUV
* -- Convert from RGB to YUV. 0x3 RGB2YCbCr -- Convert from RGB to YCbCr.
*/
#define LCDIF_CSC0_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_CTRL_CSC_MODE_SHIFT)) & LCDIF_CSC0_CTRL_CSC_MODE_MASK)
/*! @} */
/*! @name CSC0_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define LCDIF_CSC0_COEF0_A1_MASK (0x7FFU)
#define LCDIF_CSC0_COEF0_A1_SHIFT (0U)
/*! A1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF0_A1_SHIFT)) & LCDIF_CSC0_COEF0_A1_MASK)
#define LCDIF_CSC0_COEF0_A2_MASK (0x7FF0000U)
#define LCDIF_CSC0_COEF0_A2_SHIFT (16U)
/*! A2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF0_A2_SHIFT)) & LCDIF_CSC0_COEF0_A2_MASK)
/*! @} */
/*! @name CSC0_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define LCDIF_CSC0_COEF1_A3_MASK (0x7FFU)
#define LCDIF_CSC0_COEF1_A3_SHIFT (0U)
/*! A3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF1_A3_SHIFT)) & LCDIF_CSC0_COEF1_A3_MASK)
#define LCDIF_CSC0_COEF1_B1_MASK (0x7FF0000U)
#define LCDIF_CSC0_COEF1_B1_SHIFT (16U)
/*! B1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF1_B1_SHIFT)) & LCDIF_CSC0_COEF1_B1_MASK)
/*! @} */
/*! @name CSC0_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define LCDIF_CSC0_COEF2_B2_MASK (0x7FFU)
#define LCDIF_CSC0_COEF2_B2_SHIFT (0U)
/*! B2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF2_B2_SHIFT)) & LCDIF_CSC0_COEF2_B2_MASK)
#define LCDIF_CSC0_COEF2_B3_MASK (0x7FF0000U)
#define LCDIF_CSC0_COEF2_B3_SHIFT (16U)
/*! B3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF2_B3_SHIFT)) & LCDIF_CSC0_COEF2_B3_MASK)
/*! @} */
/*! @name CSC0_COEF3 - Color Space Conversion Coefficient Register 3 */
/*! @{ */
#define LCDIF_CSC0_COEF3_C1_MASK (0x7FFU)
#define LCDIF_CSC0_COEF3_C1_SHIFT (0U)
/*! C1 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF3_C1_SHIFT)) & LCDIF_CSC0_COEF3_C1_MASK)
#define LCDIF_CSC0_COEF3_C2_MASK (0x7FF0000U)
#define LCDIF_CSC0_COEF3_C2_SHIFT (16U)
/*! C2 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF3_C2_SHIFT)) & LCDIF_CSC0_COEF3_C2_MASK)
/*! @} */
/*! @name CSC0_COEF4 - Color Space Conversion Coefficient Register 4 */
/*! @{ */
#define LCDIF_CSC0_COEF4_C3_MASK (0x7FFU)
#define LCDIF_CSC0_COEF4_C3_SHIFT (0U)
/*! C3 - Two's complement coefficient offset. This coefficient has a sign bit, 2 bits integer, and 8
* bits of fraction as ###.####_####.
*/
#define LCDIF_CSC0_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF4_C3_SHIFT)) & LCDIF_CSC0_COEF4_C3_MASK)
#define LCDIF_CSC0_COEF4_D1_MASK (0x1FF0000U)
#define LCDIF_CSC0_COEF4_D1_SHIFT (16U)
/*! D1 - Two's complement D1 coefficient integer offset to be added.
*/
#define LCDIF_CSC0_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF4_D1_SHIFT)) & LCDIF_CSC0_COEF4_D1_MASK)
/*! @} */
/*! @name CSC0_COEF5 - Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define LCDIF_CSC0_COEF5_D2_MASK (0x1FFU)
#define LCDIF_CSC0_COEF5_D2_SHIFT (0U)
/*! D2 - Two's complement D2 coefficient integer offset to be added.
*/
#define LCDIF_CSC0_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF5_D2_SHIFT)) & LCDIF_CSC0_COEF5_D2_MASK)
#define LCDIF_CSC0_COEF5_D3_MASK (0x1FF0000U)
#define LCDIF_CSC0_COEF5_D3_SHIFT (16U)
/*! D3 - Two's complement D3 coefficient integer offset to be added.
*/
#define LCDIF_CSC0_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC0_COEF5_D3_SHIFT)) & LCDIF_CSC0_COEF5_D3_MASK)
/*! @} */
/*! @name PANIC0_THRES - Memory request priority threshold register */
/*! @{ */
#define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_MASK (0x1FFU)
#define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_SHIFT (0U)
/*! PANIC_THRES_HIGH - This value should be set to a value of pixels, from (0+1)*128bits to
* (511+1)*128bits. When the number of pixels in the input pixel FIFO is more than this value, the panic
* control output will be removed.This signal can be used to raise the access LCDIF's access
* priority.
*/
#define LCDIF_PANIC0_THRES_PANIC_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_SHIFT)) & LCDIF_PANIC0_THRES_PANIC_THRES_HIGH_MASK)
#define LCDIF_PANIC0_THRES_PANIC_THRES_LOW_MASK (0x1FF0000U)
#define LCDIF_PANIC0_THRES_PANIC_THRES_LOW_SHIFT (16U)
/*! PANIC_THRES_LOW - This value should be set to a value of pixels, from (0+1)*128bits to
* (511+1)*128bits. When the number of pixels in the input pixel FIFO is less than this value, the panic
* control output will be raised.This signal can be used to raise the access LCDIF's access
* priority.
*/
#define LCDIF_PANIC0_THRES_PANIC_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PANIC0_THRES_PANIC_THRES_LOW_SHIFT)) & LCDIF_PANIC0_THRES_PANIC_THRES_LOW_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LCDIF_Register_Masks */
/* LCDIF - Peripheral instance base addresses */
/** Peripheral LCDIF1 base address */
#define LCDIF1_BASE (0x32E80000u)
/** Peripheral LCDIF1 base pointer */
#define LCDIF1 ((LCDIF_Type *)LCDIF1_BASE)
/** Peripheral LCDIF2 base address */
#define LCDIF2_BASE (0x32E90000u)
/** Peripheral LCDIF2 base pointer */
#define LCDIF2 ((LCDIF_Type *)LCDIF2_BASE)
/** Peripheral LCDIF3 base address */
#define LCDIF3_BASE (0x32FC6000u)
/** Peripheral LCDIF3 base pointer */
#define LCDIF3 ((LCDIF_Type *)LCDIF3_BASE)
/** Array initializer of LCDIF peripheral base addresses */
#define LCDIF_BASE_ADDRS { LCDIF1_BASE, LCDIF2_BASE, LCDIF3_BASE }
/** Array initializer of LCDIF peripheral base pointers */
#define LCDIF_BASE_PTRS { LCDIF1, LCDIF2, LCDIF3 }
/*!
* @}
*/ /* end of group LCDIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MAINCONTROLLER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MAINCONTROLLER_Peripheral_Access_Layer MAINCONTROLLER Peripheral Access Layer
* @{
*/
/** MAINCONTROLLER - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[1];
__IO uint8_t MC_CLKDIS; /**< Main Controller Synchronous Clock Domain Disable Register, offset: 0x1 */
__IO uint8_t MC_SWRSTZREQ_1; /**< Main Controller Software Reset Register Main controller software reset request per clock domain., offset: 0x2 */
__IO uint8_t MC_OPCTRL; /**< Main Controller HDCP Bypass Control Register, offset: 0x3 */
__IO uint8_t MC_FLOWCTRL; /**< Main Controller Feed Through Control Register, offset: 0x4 */
__IO uint8_t MC_PHYRSTZ; /**< Main Controller PHY Reset Register, offset: 0x5 */
__IO uint8_t MC_LOCKONCLOCK_1; /**< Main Controller Clock Present Register, offset: 0x6 */
} MAINCONTROLLER_Type;
/* ----------------------------------------------------------------------------
-- MAINCONTROLLER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MAINCONTROLLER_Register_Masks MAINCONTROLLER Register Masks
* @{
*/
/*! @name MC_CLKDIS - Main Controller Synchronous Clock Domain Disable Register */
/*! @{ */
#define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_MASK (0x1U)
#define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_SHIFT (0U)
/*! pixelclk_disable - Pixel clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_PIXELCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_MASK (0x2U)
#define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_SHIFT (1U)
/*! tmdsclk_disable - TMDS clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_TMDSCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_MASK (0x4U)
#define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_SHIFT (2U)
/*! prepclk_disable - Pixel Repetition clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_PREPCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_MASK (0x8U)
#define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_SHIFT (3U)
/*! audclk_disable - Audio Sampler clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_AUDCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_MASK (0x10U)
#define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_SHIFT (4U)
/*! cscclk_disable - Color Space Converter clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_CSCCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_MASK (0x20U)
#define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_SHIFT (5U)
/*! cecclk_disable - CEC Engine clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_CECCLK_DISABLE_MASK)
#define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_MASK (0x40U)
#define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_SHIFT (6U)
/*! hdcpclk_disable - HDCP clock synchronous disable signal.
*/
#define MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_SHIFT)) & MAINCONTROLLER_MC_CLKDIS_HDCPCLK_DISABLE_MASK)
/*! @} */
/*! @name MC_SWRSTZREQ_1 - Main Controller Software Reset Register Main controller software reset request per clock domain. */
/*! @{ */
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_MASK (0x1U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_SHIFT (0U)
/*! pixelswrst_req - Pixel software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_PIXELSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_MASK (0x2U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_SHIFT (1U)
/*! tmdsswrst_req - TMDS software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_TMDSSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_MASK (0x4U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_SHIFT (2U)
/*! prepswrst_req - Pixel Repetition software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_PREPSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_MASK (0x8U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_SHIFT (3U)
/*! ii2sswrst_req - I2S audio software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_II2SSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_MASK (0x10U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_SHIFT (4U)
/*! ispdifswrst_req - SPDIF audio software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_ISPDIFSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_MASK (0x40U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_SHIFT (6U)
/*! cecswrst_req - CEC software reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_CECSWRST_REQ_MASK)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_MASK (0x80U)
#define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_SHIFT (7U)
/*! igpaswrst_req - GPAUD interface soft reset request.
*/
#define MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_SHIFT)) & MAINCONTROLLER_MC_SWRSTZREQ_1_IGPASWRST_REQ_MASK)
/*! @} */
/*! @name MC_OPCTRL - Main Controller HDCP Bypass Control Register */
/*! @{ */
#define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_MASK (0x1U)
#define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_SHIFT (0U)
/*! hdcp_block_byp - Block HDCP bypass mechanism - 1'b0: This is the default value.
*/
#define MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_SHIFT)) & MAINCONTROLLER_MC_OPCTRL_HDCP_BLOCK_BYP_MASK)
/*! @} */
/*! @name MC_FLOWCTRL - Main Controller Feed Through Control Register */
/*! @{ */
#define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK (0x1U)
#define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_SHIFT (0U)
/*! Feed_through_off - Video path Feed Through enable bit: - 1b: Color Space Converter is in the video data path.
*/
#define MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_SHIFT)) & MAINCONTROLLER_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK)
/*! @} */
/*! @name MC_PHYRSTZ - Main Controller PHY Reset Register */
/*! @{ */
#define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_MASK (0x1U)
#define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_SHIFT (0U)
/*! phyrstz - HDMI Source PHY active low reset control for PHY GEN1, active high reset control for PHY GEN2.
*/
#define MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_SHIFT)) & MAINCONTROLLER_MC_PHYRSTZ_PHYRSTZ_MASK)
/*! @} */
/*! @name MC_LOCKONCLOCK_1 - Main Controller Clock Present Register */
/*! @{ */
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_MASK (0x1U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_SHIFT (0U)
/*! cecclk - CEC clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_CECCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_MASK (0x4U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_SHIFT (2U)
/*! audiospdifclk - SPDIF clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_AUDIOSPDIFCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_MASK (0x8U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_SHIFT (3U)
/*! i2sclk - I2S clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_I2SCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_MASK (0x10U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_SHIFT (4U)
/*! prepclk - Pixel Repetition clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_PREPCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_MASK (0x20U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_SHIFT (5U)
/*! tclk - TMDS clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_TCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_MASK (0x40U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_SHIFT (6U)
/*! pclk - Pixel clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_PCLK_MASK)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_MASK (0x80U)
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_SHIFT (7U)
/*! igpaclk - GPAUD interface clock status.
*/
#define MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK(x) (((uint8_t)(((uint8_t)(x)) << MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_SHIFT)) & MAINCONTROLLER_MC_LOCKONCLOCK_1_IGPACLK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MAINCONTROLLER_Register_Masks */
/* MAINCONTROLLER - Peripheral instance base addresses */
/** Peripheral MAINCONTROLLER base address */
#define MAINCONTROLLER_BASE (0x32FDC000u)
/** Peripheral MAINCONTROLLER base pointer */
#define MAINCONTROLLER ((MAINCONTROLLER_Type *)MAINCONTROLLER_BASE)
/** Array initializer of MAINCONTROLLER peripheral base addresses */
#define MAINCONTROLLER_BASE_ADDRS { MAINCONTROLLER_BASE }
/** Array initializer of MAINCONTROLLER peripheral base pointers */
#define MAINCONTROLLER_BASE_PTRS { MAINCONTROLLER }
/*!
* @}
*/ /* end of group MAINCONTROLLER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MEDIA_BLK_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MEDIA_BLK_CTRL_Peripheral_Access_Layer MEDIA_BLK_CTRL Peripheral Access Layer
* @{
*/
/** MEDIA_BLK_CTRL - Register Layout Typedef */
typedef struct {
__IO uint32_t SFT_RSTN; /**< Media Mix Software Reset Register, offset: 0x0 */
__IO uint32_t CLK_EN; /**< Media Mix Clock Enable Register, offset: 0x4 */
__IO uint32_t MIPI_RESET_DIV; /**< MIPI PHY Control Register, offset: 0x8 */
__IO uint32_t MIPI_M_PLLPMS; /**< Master PLL PMS Value setting Register, offset: 0xC */
__IO uint32_t MIPI_M_PLLCTL_LOW; /**< Master PLL Control Low Register, offset: 0x10 */
__IO uint32_t MIPI_M_PLLCTL_HIGH; /**< Master PLL Control High Register, offset: 0x14 */
__IO uint32_t MIPI_B_DPHYCTL_LOW; /**< Master and Slave DPHY Control Low Register, offset: 0x18 */
__IO uint32_t MIPI_B_DPHYCTL_HIGH; /**< Master and Slave DPHY Control High Register, offset: 0x1C */
__IO uint32_t MIPI_M_DPHYCTL_LOW; /**< Master and Slave DPHY Control Low Register, offset: 0x20 */
__IO uint32_t MIPI_M_DPHYCTL_HIGH; /**< Master and Slave DPHY Control High Register, offset: 0x24 */
__IO uint32_t MIPI_S_DPHYCTL_LOW; /**< Master and Slave DPHY Control Low Register, offset: 0x28 */
__IO uint32_t MIPI_S_DPHYCTL_HIGH; /**< Master and Slave DPHY Control High Register, offset: 0x2C */
uint8_t RESERVED_0[28];
__IO uint32_t LCDIF_ARCACHE_CTRL; /**< LCDIF ARCACHE Control Register, offset: 0x4C */
__IO uint32_t ISI_CACHE_CTRL; /**< ISI CACHE Control Register, offset: 0x50 */
__IO uint32_t LDO_CTRL; /**< LDO Control Register, offset: 0x54 */
__IO uint32_t LDO_TRIM; /**< LDO Trim Register, offset: 0x58 */
__IO uint32_t LDB_CTRL; /**< LDB Control Register, offset: 0x5C */
__IO uint32_t GASKET_0_CTRL; /**< Gasket 0 Control Register, offset: 0x60 */
__IO uint32_t GASKET_0_HSIZE; /**< Gasket 0 Video Horizontal Size Register, offset: 0x64 */
__IO uint32_t GASKET_0_VSIZE; /**< Gasket 0 Video Vertical Size Register, offset: 0x68 */
__IO uint32_t GASKET_0_HFP; /**< Gasket 0 Video Horizontal Front Porch Register, offset: 0x6C */
__IO uint32_t GASKET_0_HBP; /**< Gasket 0 Video Horizontal Back Porch Register, offset: 0x70 */
__IO uint32_t GASKET_0_VFP; /**< Gasket 0 Video Vertical Front Porch Register, offset: 0x74 */
__IO uint32_t GASKET_0_VBP; /**< Gasket 0 Video Vertical Back Porch Register, offset: 0x78 */
__IO uint32_t GASKET_0_ISI_PIXEL_CNT; /**< Gasket 0 ISI Pixel Count Register, offset: 0x7C */
__IO uint32_t GASKET_0_ISI_LINE_CNT; /**< Gasket 0 ISI Line Count Register, offset: 0x80 */
__IO uint32_t GASKET_0_ISI_PIXEL_CTRL; /**< Gasket 0 ISI Pixel Control Information Register, offset: 0x84 */
uint8_t RESERVED_1[8];
__IO uint32_t GASKET_1_CTRL; /**< Gasket 1 Control Register, offset: 0x90 */
__IO uint32_t GASKET_1_HSIZE; /**< Gasket 1 Video Horizontal Size Register, offset: 0x94 */
__IO uint32_t GASKET_1_VSIZE; /**< Gasket 1 Video Vertical Size Register, offset: 0x98 */
__IO uint32_t GASKET_1_HFP; /**< Gasket 1 Video Horizontal Front Porch Register, offset: 0x9C */
__IO uint32_t GASKET_1_HBP; /**< Gasket 1 Video Horizontal Back Porch Register, offset: 0xA0 */
__IO uint32_t GASKET_1_VFP; /**< Gasket 1 Video Vertical Front Porch Register, offset: 0xA4 */
__IO uint32_t GASKET_1_VBP; /**< Gasket 1 Video Vertical Back Porch Register, offset: 0xA8 */
__IO uint32_t GASKET_1_ISI_PIXEL_CNT; /**< Gasket 1 ISI Pixel Count Register, offset: 0xAC */
__IO uint32_t GASKET_1_ISI_LINE_CNT; /**< Gasket 1 ISI Line Count Register, offset: 0xB0 */
__IO uint32_t GASKET_1_ISI_PIXEL_CTRL; /**< Gasket 1 ISI Pixel Control Information Register, offset: 0xB4 */
uint8_t RESERVED_2[104];
__IO uint32_t MIPI_B2_DPHYCTL_LOW; /**< Master and Slave DPHY Control Low Register, offset: 0x120 */
__IO uint32_t MIPI_B2_DPHYCTL_HIGH; /**< Master and Slave DPHY Control High Register, offset: 0x124 */
__IO uint32_t LVDS_CTRL; /**< LVDS Control Register, offset: 0x128 */
__IO uint32_t AXI_LIMIT_CONTROL; /**< AXI Limit Control Register, offset: 0x12C */
__IO uint32_t AXI_LIMIT_THRESH0; /**< AXI Limit Threshold Register 0, offset: 0x130 */
__IO uint32_t AXI_LIMIT_THRESH1; /**< AXI Limit Threshold Register 1, offset: 0x134 */
__IO uint32_t ISP_DEWARP_CONTROL; /**< ISP Dewarp Control Register, offset: 0x138 */
} MEDIA_BLK_CTRL_Type;
/* ----------------------------------------------------------------------------
-- MEDIA_BLK_CTRL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MEDIA_BLK_CTRL_Register_Masks MEDIA_BLK_CTRL Register Masks
* @{
*/
/*! @name SFT_RSTN - Media Mix Software Reset Register */
/*! @{ */
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_MASK (0x1U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_SHIFT (0U)
/*! SFT_EN_MIPI_DSI_PCLK_RESETN - sft_en_mipi_dsi_pclk_resetn
* 0b1..software reset disable for mipi_dsi_pclk
* 0b0..software reset enable for mipi_dsi_pclk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_PCLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_MASK (0x2U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_SHIFT (1U)
/*! SFT_EN_MIPI_DSI_CLKREF_RESETN - sft_en_mipi_dsi_CLKREF_resetn
* 0b1..software reset disable for mipi_dsi_CLKREF
* 0b0..software reset enable for mipi_dsi_CLKREF
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI_CLKREF_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_MASK (0x4U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_SHIFT (2U)
/*! SFT_EN_MIPI_CSI_PCLK_RESETN - sft_en_mipi_csi_pclk_resetn
* 0b1..software reset disable for mipi_csi_pclk
* 0b0..software reset enable for mipi_csi_pclk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_PCLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_MASK (0x8U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_SHIFT (3U)
/*! SFT_EN_MIPI_CSI_ACLK_RESETN - sft_en_mipi_csi_aclk_resetn
* 0b1..software reset disable for mipi_csi_aclk
* 0b0..software reset enable for mipi_csi_aclk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI_ACLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_MASK (0x10U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_SHIFT (4U)
/*! SFT_EN_LCDIF_PIXEL_CLK_RESETN - sft_en_lcdif_pixel_clk_resetn
* 0b1..software reset disable for lcdif_pixel_clk
* 0b0..software reset enable for lcdif_pixel_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_PIXEL_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_MASK (0x20U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_SHIFT (5U)
/*! SFT_EN_LCDIF_APB_CLK_RESETN - sft_en_lcdif_apb_clk_resetn
* 0b1..software reset disable for lcdif_apb_clk
* 0b0..software reset enable for lcdif_apb_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_APB_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_MASK (0x40U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_SHIFT (6U)
/*! SFT_EN_ISI_PROC_CLK_RESETN - sft_en_isi_proc_clk_resetn
* 0b1..software reset disable for isi_proc_clk
* 0b0..software reset enable for isi_proc_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_PROC_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_MASK (0x80U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_SHIFT (7U)
/*! SFT_EN_ISI_APB_CLK_RESETN - sft_en_isi_apb_clk_resetn
* 0b1..software reset disable for isi_apb_clk
* 0b0..software reset enable for isi_apb_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISI_APB_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_MASK (0x100U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_SHIFT (8U)
/*! SFT_EN_BUS_BLK_CLK_RESETN - sft_en_bus_blk_clk_resetn
* 0b1..software reset disable for bus_blk_clk
* 0b0..software reset enable for bus_blk_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_BUS_BLK_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_MASK (0x200U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_SHIFT (9U)
/*! SFT_EN_MIPI_CSI2_PCLK_RESETN - sft_en_mipi_csi2_pclk_resetn
* 0b1..software reset disable for mipi_csi2_pclk
* 0b0..software reset enable for mipi_csi2_pclk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_PCLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_MASK (0x400U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_SHIFT (10U)
/*! SFT_EN_MIPI_CSI2_ACLK_RESETN - sft_en_mipi_csi2_aclk_resetn
* 0b1..software reset disable for mipi_csi2_aclk
* 0b0..software reset enable for mipi_csi2_aclk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_CSI2_ACLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_MASK (0x800U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_SHIFT (11U)
/*! SFT_EN_LCDIF2_PIXEL_CLK_RESETN - sft_en_lcdif2_pixel_clk_resetn
* 0b1..software reset disable for lcdif2_pixel_clk
* 0b0..software reset enable for lcdif2_pixel_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_PIXEL_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_MASK (0x1000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_SHIFT (12U)
/*! SFT_EN_LCDIF2_APB_CLK_RESETN - sft_en_lcdif2_apb_clk_resetn
* 0b1..software reset disable for lcdif2_apb_clk
* 0b0..software reset enable for lcdif2_apb_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_APB_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_MASK (0x10000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_SHIFT (16U)
/*! SFT_EN_ISP_COR_CLK_RESETN - sft_en_isp_cor_clk_resetn;
* 0b1..software reset disable for isp_cor_clk
* 0b0..software reset enable for isp_cor_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_COR_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_MASK (0x20000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_SHIFT (17U)
/*! SFT_EN_ISP_AXI_CLK_RESETN - sft_en_isp_axi_clk_resetn;
* 0b1..software reset disable for isp_axi_clk
* 0b0..software reset enable for isp_axi_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AXI_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_MASK (0x40000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_SHIFT (18U)
/*! SFT_EN_ISP_AHB_CLK_RESETN - sft_en_isp_ahb_clk_resetn;
* 0b1..software reset disable for isp_ahb_clk
* 0b0..software reset enable for isp_ahb_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_ISP_AHB_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_MASK (0x80000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_SHIFT (19U)
/*! SFT_EN_DWE_COR_CLK_RESETN - sft_en_dwe_cor_clk_resetn;
* 0b1..software reset disable for dwe_cor_clk
* 0b0..software reset enable for dwe_cor_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_COR_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_MASK (0x100000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_SHIFT (20U)
/*! SFT_EN_DWE_AXI_CLK_RESETN - sft_en_dwe_axi_clk_resetn;
* 0b1..software reset disable for dwe_axi_clk
* 0b0..software reset enable for dwe_axi_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AXI_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_MASK (0x200000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_SHIFT (21U)
/*! SFT_EN_DWE_AHB_CLK_RESETN - sft_en_dwe_ahb_clk_resetn;
* 0b1..software reset disable for dwe_ahb_clk
* 0b0..software reset enable for dwe_ahb_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_DWE_AHB_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_MASK (0x400000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_SHIFT (22U)
/*! SFT_EN_MIPI_DSI2_CLKREF_RESETN - sft_en_mipi_dsi2_CLKREF_resetn
* 0b1..software reset disable for mipi_dsi2_CLKREF
* 0b0..software reset enable for mipi_dsi2_CLKREF
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_MIPI_DSI2_CLKREF_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_MASK (0x800000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_SHIFT (23U)
/*! SFT_EN_LCDIF_AXI_CLK_RESETN - sft_en_lcdif_axi_clk_resetn
* 0b1..software reset disable for lcdif_axi_clk
* 0b0..software reset enable for lcdif_axi_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF_AXI_CLK_RESETN_MASK)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_MASK (0x1000000U)
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_SHIFT (24U)
/*! SFT_EN_LCDIF2_AXI_CLK_RESETN - sft_en_lcdif2_axi_clk_resetn
* 0b1..software reset disable for lcdif2_axi_clk
* 0b0..software reset enable for lcdif2_axi_clk
*/
#define MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_SHIFT)) & MEDIA_BLK_CTRL_SFT_RSTN_SFT_EN_LCDIF2_AXI_CLK_RESETN_MASK)
/*! @} */
/*! @name CLK_EN - Media Mix Clock Enable Register */
/*! @{ */
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_MASK (0x1U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_SHIFT (0U)
/*! SFT_EN_MIPI_DSI_PCLK - sft_en_mipi_dsi_pclk
* 0b1..clock enable for mipi_dsi_pclk
* 0b0..clock disable (gated) for mipi_dsi_pclk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_PCLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_MASK (0x2U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_SHIFT (1U)
/*! SFT_EN_MIPI_DSI_CLKREF - sft_en_mipi_dsi_CLKREF
* 0b1..clock enable for mipi_dsi_CLKREF
* 0b0..clock disable (gated) for mipi_dsi_CLKREF
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI_CLKREF_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_MASK (0x4U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_SHIFT (2U)
/*! SFT_EN_MIPI_CSI_PCLK - sft_en_mipi_csi_pclk
* 0b1..clock enable for mipi_csi_pclk
* 0b0..clock disable (gated) for mipi_csi_pclk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_PCLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_MASK (0x8U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_SHIFT (3U)
/*! SFT_EN_MIPI_CSI_ACLK - sft_en_mipi_csi_aclk
* 0b1..clock enable for mipi_csi_aclk
* 0b0..clock disable (gated) for mipi_csi_aclk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI_ACLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_MASK (0x10U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_SHIFT (4U)
/*! SFT_EN_LCDIF_PIXEL_CLK - sft_en_lcdif_pixel_clk
* 0b1..clock enable for lcdif_pixel_clk
* 0b0..clock disable (gated) for lcdif_pixel_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_PIXEL_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_MASK (0x20U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_SHIFT (5U)
/*! SFT_EN_LCDIF_APB_CLK - sft_en_lcdif_apb_clk
* 0b1..clock enable for lcdif_apb_clk
* 0b0..clock disable (gated) for lcdif_apb_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_APB_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_MASK (0x40U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_SHIFT (6U)
/*! SFT_EN_ISI_PROC_CLK - sft_en_isi_proc_clk
* 0b1..clock enable for isi_proc_clk
* 0b0..clock disable (gated) for isi_proc_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_PROC_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_MASK (0x80U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_SHIFT (7U)
/*! SFT_EN_ISI_APB_CLK - sft_en_isi_apb_clk
* 0b1..clock enable for isi_apb_clk
* 0b0..clock disable (gated) for isi_apb_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISI_APB_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_MASK (0x100U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_SHIFT (8U)
/*! SFT_EN_BUS_BLK_CLK - sft_en_bus_blk_clk
* 0b1..clock enable for bus_blk_clk
* 0b0..clock disable (gated) for bus_blk_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_BUS_BLK_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_MASK (0x200U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_SHIFT (9U)
/*! SFT_EN_MIPI_CSI2_PCLK - sft_en_mipi_csi2_pclk
* 0b1..clock enable for mipi_csi2_pclk
* 0b0..clock disable (gated) for mipi_csi2_pclk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_PCLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_MASK (0x400U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_SHIFT (10U)
/*! SFT_EN_MIPI_CSI2_ACLK - sft_en_mipi_csi2_aclk
* 0b1..clock enable for mipi_csi2_aclk
* 0b0..clock disable (gated) for mipi_csi2_aclk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_CSI2_ACLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_MASK (0x800U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_SHIFT (11U)
/*! SFT_EN_LCDIF2_PIXEL_CLK - sft_en_lcdif2_pixel_clk
* 0b1..clock enable for lcdif2_pixel_clk
* 0b0..clock disable (gated) for lcdif2_pixel_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_PIXEL_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_MASK (0x1000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_SHIFT (12U)
/*! SFT_EN_LCDIF2_APB_CLK - sft_en_lcdif2_apb_clk
* 0b1..clock enable for lcdif2_apb_clk
* 0b0..clock disable (gated) for lcdif2_apb_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_APB_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_MASK (0x10000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_SHIFT (16U)
/*! SFT_EN_ISP_COR_CLK - sft_en_isp_cor_clk
* 0b1..clock enable for isp_cor_clk
* 0b0..clock disable (gated) for isp_cor_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_COR_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_MASK (0x20000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_SHIFT (17U)
/*! SFT_EN_ISP_AXI_CLK - sft_en_isp_axi_clk
* 0b1..clock enable for isp_axi_clk
* 0b0..clock disable (gated) for isp_axi_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AXI_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_MASK (0x40000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_SHIFT (18U)
/*! SFT_EN_ISP_AHB_CLK - sft_en_isp_ahb_clk
* 0b1..clock enable for isp_ahb_clk
* 0b0..clock disable (gated) for isp_ahb_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_ISP_AHB_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_MASK (0x80000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_SHIFT (19U)
/*! SFT_EN_DWE_COR_CLK - sft_en_dwe_cor_clk
* 0b1..clock enable for dwe_cor_clk
* 0b0..clock disable (gated) for dwe_cor_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_COR_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_MASK (0x100000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_SHIFT (20U)
/*! SFT_EN_DWE_AXI_CLK - sft_en_dwe_axi_clk
* 0b1..clock enable for dwe_axi_clk
* 0b0..clock disable (gated) for dwe_axi_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AXI_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_MASK (0x200000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_SHIFT (21U)
/*! SFT_EN_DWE_AHB_CLK - sft_en_dwe_ahb_clk
* 0b1..clock enable for dwe_ahb_clk
* 0b0..clock disable (gated) for dwe_ahb_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_DWE_AHB_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_MASK (0x400000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_SHIFT (22U)
/*! SFT_EN_MIPI_DSI2_CLKREF - sft_en_mipi_dsi2_CLKREF
* 0b1..clock enable for mipi_dsi2_CLKREF
* 0b0..clock disable (gated) for mipi_dsi2_CLKREF
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_MIPI_DSI2_CLKREF_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_MASK (0x800000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_SHIFT (23U)
/*! SFT_EN_LCDIF_AXI_CLK - sft_en_lcdif_axi_clk
* 0b1..clock enable for lcdif_axi_clk
* 0b0..clock disable (gated) for lcdif_axi_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF_AXI_CLK_MASK)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_MASK (0x1000000U)
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_SHIFT (24U)
/*! SFT_EN_LCDIF2_AXI_CLK - sft_en_lcdif2_axi_clk
* 0b1..clock enable for lcdif2_axi_clk
* 0b0..clock disable (gated) for lcdif2_axi_clk
*/
#define MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_SHIFT)) & MEDIA_BLK_CTRL_CLK_EN_SFT_EN_LCDIF2_AXI_CLK_MASK)
/*! @} */
/*! @name MIPI_RESET_DIV - MIPI PHY Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_MASK (0x10000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_SHIFT (16U)
/*! GPR_MIPI_S_RESETN - GPR_MIPI_S_RESETN
* 0b1..MIPI DPHY S_RESETN reset disable
* 0b0..MIPI DPHY S_RESETN reset enable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_RESETN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_MASK (0x20000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_SHIFT (17U)
/*! GPR_MIPI_M_RESETN - GPR_MIPI_M_RESETN
* 0b1..MIPI DPHY M_RESETN reset disable
* 0b0..MIPI DPHY M_RESETN reset enable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_RESETN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_MASK (0x40000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_SHIFT (18U)
/*! GPR_CTRL_S3_BIASEN - GPR_CTRL_S3_BIASEN. Used in MIPI PHY
* 0b1..S3_BIASEN active
* 0b0..S3_BIASEN disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S3_BIASEN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_MASK (0x80000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_SHIFT (19U)
/*! GPR_CTRL_S2_BIASEN - GPR_CTRL_S2_BIASEN. Used in MIPI PHY
* 0b1..S2_BIASEN active
* 0b0..S2_BIASEN disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S2_BIASEN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_MASK (0x100000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_SHIFT (20U)
/*! GPR_CTRL_S1_BIASEN - GPR_CTRL_S1_BIASEN. Used in MIPI PHY
* 0b1..S1_BIASEN active
* 0b0..S1_BIASEN disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_S1_BIASEN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_MASK (0x200000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_SHIFT (21U)
/*! GPR_CTRL_M2_BIASEN - GPR_CTRL_M2_BIASEN. Used in MIPI PHY
* 0b1..M2_BIASEN active
* 0b0..M2_BIASEN disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M2_BIASEN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_MASK (0x400000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_SHIFT (22U)
/*! GPR_CTRL_M1_BIASEN - GPR_CTRL_M1_BIASEN. Used in MIPI PHY
* 0b1..M1_BIASEN active
* 0b0..M1_BIASEN disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_CTRL_M1_BIASEN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_SHIFT (23U)
/*! GPR_MIPI_S_DPDN_SWAP_DAT - GPR_MIPI_S_DPDN_SWAP_DAT
* 0b1..Master DPHY data lane DP and DN swap enable
* 0b0..Master DPHY data lane DP and DN swap disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_DAT_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_MASK (0x1000000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_SHIFT (24U)
/*! GPR_MIPI_S_DPDN_SWAP_CLK - GPR_MIPI_S_DPDN_SWAP_CLK
* 0b1..Slave DPHY clock lane DP and DN swap enable
* 0b0..Slave DPHY clock lane DP and DN swap disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S_DPDN_SWAP_CLK_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_MASK (0x2000000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_SHIFT (25U)
/*! GPR_MIPI_M_DPDN_SWAP_DAT - GPR_MIPI_M_DPDN_SWAP_DAT
* 0b1..Master DPHY data lane DP and DN swap enable
* 0b0..Master DPHY data lane DP and DN swap disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_DAT_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_MASK (0x4000000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_SHIFT (26U)
/*! GPR_MIPI_M_DPDN_SWAP_CLK - GPR_MIPI_M_DPDN_SWAP_CLK
* 0b1..Master DPHY clock lane DP and DN swap enable
* 0b0..Master DPHY clock lane DP and DN swap disable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M_DPDN_SWAP_CLK_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_MASK (0x20000000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_SHIFT (29U)
/*! GPR_MIPI_M2_RESETN - GPR_MIPI_M2_RESETN
* 0b1..MIPI DPHY M2_RESETN reset disable
* 0b0..MIPI DPHY M2_RESETN reset enable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_M2_RESETN_MASK)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_MASK (0x40000000U)
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_SHIFT (30U)
/*! GPR_MIPI_S2_RESETN - GPR_MIPI_S2_RESETN
* 0b1..MIPI DPHY S2_RESETN reset disable
* 0b0..MIPI DPHY S2_RESETN reset enable
*/
#define MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_RESET_DIV_GPR_MIPI_S2_RESETN_MASK)
/*! @} */
/*! @name MIPI_M_PLLPMS - Master PLL PMS Value setting Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_MASK (0x6U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_SHIFT (1U)
/*! PMS_S - PMS_S
* 0b00..Divide by 1
* 0b01..Divide by 2
* 0b10..Divide by 4
* 0b11..Divide by 8
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_S_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_MASK (0x1FF0U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_SHIFT (4U)
/*! PMS_M - PMS_M
* 0b000000000..Do not program, can cause malfunction
* 0b000011001..Divide by 25
* 0b000011010..Divide by 26
* 0b000011011..Divide by 27
* 0b000011100..Divide by 28
* 0b000011101..Divide by 29
* 0b001111010..Divide by 122
* 0b001111011..Divide by 123
* 0b001111100..Divide by 124
* 0b001111101..Divide by 125
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_M_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_MASK (0x7E000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_SHIFT (13U)
/*! PMS_P - PMS_P
* 0b000000..Do not program, can cause malfunction
* 0b000001..Divide by 1
* 0b000010..Divide by 2
* 0b000011..Divide by 3
* 0b000100..Divide by 4
* 0b000101..Divide by 5
* 0b011110..Divide by 30
* 0b011111..Divide by 31
* 0b100000..Divide by 32
* 0b100001..Divide by 33
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLPMS_PMS_P_MASK)
/*! @} */
/*! @name MIPI_M_PLLCTL_LOW - Master PLL Control Low Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_MASK (0x1U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_SHIFT (0U)
/*! AFC_ENB - Automatic Frequency Control Enable/Disable
* 0b0..AFC is enabled
* 0b1..AFC is disabled
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_ENB_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_MASK (0x3EU)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_SHIFT (1U)
/*! EXTAFC - EXTAFC
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_EXTAFC_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_MASK (0x40U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_SHIFT (6U)
/*! AFCINIT_SEL - AFC initial delay select pin
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFCINIT_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_MASK (0x300000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_SHIFT (20U)
/*! ICP - Controls the charge-pump current
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_ICP_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_MASK (0x400000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_SHIFT (22U)
/*! BYPASS - BYPASS
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_BYPASS_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_SHIFT (23U)
/*! FSEL - Monitoring frequency select pin
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FSEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_MASK (0x8000000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_SHIFT (27U)
/*! PBIAS_CTRL_EN - PBIAS voltage pull-down enable pin (active-high)
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_MASK (0x10000000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_SHIFT (28U)
/*! PBIAS_CTRL - PBIAS pull-down initial voltage control pin
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_PBIAS_CTRL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_MASK (0x20000000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_SHIFT (29U)
/*! FEED_EN - FEED_OUT enable pin (active-high)
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_FEED_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_MASK (0x40000000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_SHIFT (30U)
/*! AFC_SEL - AFC operation mode select pin
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_AFC_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_MASK (0x80000000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_SHIFT (31U)
/*! SSCG_EN - Enable pin for dithered mode. (Active-high)
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_LOW_SSCG_EN_MASK)
/*! @} */
/*! @name MIPI_M_PLLCTL_HIGH - Master PLL Control High Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_MASK (0xFFU)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_SHIFT (0U)
/*! MFR - Value of 8-bit Modulation Frequency (MF) control
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MFR_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_MASK (0x3F00U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_SHIFT (8U)
/*! MRR - Value of 6-bit Modulation Rate (MR) control
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_MRR_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_MASK (0xC000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_SHIFT (14U)
/*! SEL_PF - Value of 2-bit modulation method control
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_SEL_PF_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_MASK (0xFFFF0000U)
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_SHIFT (16U)
/*! K - Value of 16-bit Delta-Sigma Modulator (DSM)
*/
#define MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_PLLCTL_HIGH_K_MASK)
/*! @} */
/*! @name MIPI_B_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK (0x3FFU)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT (0U)
/*! ULPS_EXIT_COUNTER - ULPS_EXIT_COUNTER
* 0b0000000000..0.01 MHz
* 0b0000000011..0.10 MHz
* 0b0000011001..1.00 MHz
* 0b0000110010..2.00 MHz
* 0b0001001011..3.00 MHz
* 0b0001100100..4.00 MHz
* 0b0001111101..5.00 MHz
* 0b0010010110..6.00 MHz
* 0b0010101111..7.00 MHz
* 0b0011001000..8.00 MHz
* 0b0011100001..9.00 MHz
* 0b0011111010..10.00 MHz
* 0b0100010011..11.00 MHz
* 0b0100101100..12.00 MHz
* 0b0101000101..13.00 MHz
* 0b0101011110..14.00 MHz
* 0b0101110111..15.00 MHz
* 0b0110010000..16.00 MHz
* 0b0110101001..17.00 MHz
* 0b0111000010..18.00 MHz
* 0b0111011011..19.00 MHz
* 0b0111110100..20.00 MHz
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK (0x400U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT (10U)
/*! TX_TRIGGER_CLK_EN - TX_TRIGGER_CLK_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK (0x800U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT (11U)
/*! ERR_CONT_LP_EN - ERR_CONT_LP_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
/*! BGR_CHOPPER_EN - BGR_CHOPPER_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_MASK (0x2000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_SHIFT (13U)
/*! LP_CD_HYS - LP_CD_HYS
* 0b0..60mV
* 0b1..70mV
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_CD_HYS_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK (0x4000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT (14U)
/*! MSTR_CLK_SLEW_RATE_UP - MSTR_CLK_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK (0x18000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT (15U)
/*! MSTR_CLK_SLEW_RATE_DOWN - MSTR_CLK_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK (0x20000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT (17U)
/*! LP_RX_PULSE_REJ - LP_RX_PULSE_REJ
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
/*! LP_RX_VREF_LVL - LP_RX_VREF_LVL
* 0b00..715mV
* 0b01..743mV
* 0b10..650mV
* 0b11..682mV
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_MASK (0x100000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT (20U)
/*! VREF_SRC_SEL - VREF_SRC_SEL
* 0b0..Generated from the BGR
* 0b1..Generated from the current mirror
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_VREF_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK (0x600000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT (21U)
/*! LP_RX_HYS_CTL - LP_RX_HYS_CTL
* 0b00..80mV
* 0b01..100mV
* 0b10..120mV
* 0b11..140mV
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_SHIFT (23U)
/*! REG_VALID_1_2 - REG_VALID_1_2
* 0b0..Use "ulps_en" signal
* 0b1..Use valid signal from 1.2V regulator
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK (0x3000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT (24U)
/*! REG_LVL_CTL_1_2 - REG_LVL_CTL_1_2
* 0b00..1.2V
* 0b01..1.23V
* 0b10..1.27V
* 0b11..1.26V
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK (0x4000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT (26U)
/*! REG_VALID_CTL_1_2 - REG_VALID_CTL_1_2
* 0b0..Internal 1.2V regulator
* 0b1..External 1.2V power
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK (0x8000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT (27U)
/*! BGR_CHOPPER_FREQ_CTL - BGR_CHOPPER_FREQ_CTL
* 0b0..3MHz
* 0b1..1.5MHz
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK (0x30000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT (28U)
/*! BIAS_REF_VOLT_CTL - BIAS_REF_VOLT_CTL
* 0b00..712mV
* 0b01..724mV
* 0b10..733mV
* 0b11..706mV
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_MASK (0xC0000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_SHIFT (30U)
/*! USER_DATA_HS - User Data Pattern for HS Loopback mode
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_LOW_USER_DATA_HS_MASK)
/*! @} */
/*! @name MIPI_B_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_MASK (0x3FU)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_SHIFT (0U)
/*! USER_DATA_HS - User Data Pattern for HS Loopback mode
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_USER_DATA_HS_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_MASK (0xC0U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT (6U)
/*! HS_MODE_CTL - HS_MODE_CTL
* 0b00..Designated Pattern
* 0b01..PRBS7
* 0b10..All zero
* 0b11..User Data Pattern
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_HS_MODE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK (0x300U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT (8U)
/*! BGR_VOLT_TUNING_CTL - BGR_VOLT_TUNING_CTL
* 0b00..820mV
* 0b01..760mV
* 0b10..800mV
* 0b11..840mV
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_MASK (0x800U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT (11U)
/*! DCC_DONE_CTL - DCC_DONE_CTL
* 0b0.."DONE" from DCC block
* 0b1..U"DONE" is always 1
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_DCC_DONE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK (0x2000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT (13U)
/*! RX_SKEW_CALIB_FIX_CODE_EN - RX_SKEW_CALIB_FIX_CODE_EN
* 0b0..Disable
* 0b1..Enable
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK (0x4000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT (14U)
/*! LP_VREF_REG_SRC_SEL - LP_VREF_REG_SRC_SEL
* 0b0..Generated from BGR
* 0b1..Generated from Current Mirror
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK (0x100000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT (20U)
/*! MSTR_DATA0_SLEW_RATE_UP - MSTR_DATA0_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK (0x600000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT (21U)
/*! MSTR_DATA0_SLEW_RATE_DOWN - MSTR_DATA0_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT (23U)
/*! MSTR_DATA1_SLEW_RATE_UP - MSTR_DATA1_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK (0x3000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT (24U)
/*! MSTR_DATA1_SLEW_RATE_DOWN - MSTR_DATA1_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK (0x4000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT (26U)
/*! MSTR_DATA2_SLEW_RATE_UP - MSTR_DATA2_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK (0x18000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT (27U)
/*! MSTR_DATA2_SLEW_RATE_DOWN - MSTR_DATA2_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK (0x20000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT (29U)
/*! MSTR_DATA3_SLEW_RATE_UP - MSTR_DATA3_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK (0xC0000000U)
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT (30U)
/*! MSTR_DATA3_SLEW_RATE_DOWN - MSTR_DATA3_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK)
/*! @} */
/*! @name MIPI_M_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_MASK (0x3U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_SHIFT (0U)
/*! DATA_HS_TX_DELAY_CTL - DATA_HS_TX_DELAY_CTL
* 0b00..No change
* 0b01..25 ps
* 0b10..55 ps
* 0b11..90 ps
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_HS_TX_DELAY_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_MASK (0xCU)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_SHIFT (2U)
/*! HS_TX_REG_AMP_CTL - HS_TX_REG_AMP_CTL
* 0b00..No Change
* 0b01..12.5 uA
* 0b10..50 uA
* 0b11..16.6 uA
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_AMP_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_MASK (0x10U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_SHIFT (4U)
/*! HS_TX_REG_TURN_ON_CTL - HS_TX_REG_TURN_ON_CTL
* 0b0..No Change
* 0b1..Always Turn-On the HS Regulator
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_TURN_ON_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_MASK (0x60U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_SHIFT (5U)
/*! CLK_HS_TX_DELAY_CTL - CLK_HS_TX_DELAY_CTL
* 0b00..No change
* 0b01..25 ps
* 0b10..55 ps
* 0b11..90 ps
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_HS_TX_DELAY_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_MASK (0x380U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_SHIFT (7U)
/*! HS_TX_SLEW_RATE_CTL - HS_TX_SLEW_RATE_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_MASK (0x400U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_SHIFT (10U)
/*! HS_TX_SLEW_RATE_EN - HS_TX_SLEW_RATE_EN
* 0b0..SRC Disable
* 0b1..SRC Enable
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_SLEW_RATE_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_MASK (0x1800U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_SHIFT (11U)
/*! CLK_LANE_CAP_CTL - CLK_LANE_CAP_CTL
* 0b00..No change
* 0b01..-6.6%
* 0b10..13.3%
* 0b11..6.6%
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_LANE_CAP_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_MASK (0x6000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_SHIFT (13U)
/*! DATA_LANE_CAP_CTL - DATA_LANE_CAP_CTL
* 0b00..No change
* 0b01..-6.6%
* 0b10..13.3%
* 0b11..6.6%
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_DATA_LANE_CAP_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK (0x18000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT (15U)
/*! ANA_TIMER_HYS_CTL - ANA_TIMER_HYS_CTL
* 0b00..70mV
* 0b01..95mV
* 0b10..95mV
* 0b11..110mV
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_MASK (0xE0000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_SHIFT (17U)
/*! HS_TX_TERM_IMP_UP_CTL - HS_TX_TERM_IMP_UP_CTL
* 0b000..50 ohm
* 0b001..52 ohm
* 0b010..54 ohm
* 0b011..56 ohm
* 0b100..44 ohm
* 0b101..46 ohm
* 0b110..47 ohm
* 0b111..48 ohm
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_UP_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_MASK (0x700000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_SHIFT (20U)
/*! HS_TX_TERM_IMP_DOWN_CTL - HS_TX_TERM_IMP_DOWN_CTL
* 0b000..50 ohm
* 0b001..52 ohm
* 0b010..54 ohm
* 0b011..56 ohm
* 0b100..44 ohm
* 0b101..46 ohm
* 0b110..47 ohm
* 0b111..48 ohm
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_TERM_IMP_DOWN_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_SHIFT (23U)
/*! HS_TX_REG_CURRENT_CTL - HS_TX_REG_CURRENT_CTL
* 0b0..No change
* 0b1..2.5 uA
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_CURRENT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_MASK (0x7000000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_SHIFT (24U)
/*! HS_TX_REG_OUT_CTL - HS_TX_REG_OUT_CTL
* 0b000..400mV
* 0b001..410mV
* 0b010..420mV
* 0b011..440mV
* 0b100..200mV
* 0b101..360mV
* 0b110..380mV
* 0b111..390mV
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_REG_OUT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_MASK (0x38000000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_SHIFT (27U)
/*! HS_TX_RISE_FALL_TIME_CTL - HS_TX_RISE_FALL_TIME_CTL
* 0b000..135mV
* 0b001..130mV
* 0b010..125mV
* 0b011..120mV
* 0b100..230mV
* 0b101..225mV
* 0b110..220mV
* 0b111..215mV
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_TX_RISE_FALL_TIME_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_MASK (0x40000000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_SHIFT (30U)
/*! CLK_BUFFER_EN_CTL - CLK_BUFFER_EN_CTL
* 0b0..HS_TX enable
* 0b1..PLL lock
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_CLK_BUFFER_EN_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_MASK (0x80000000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_SHIFT (31U)
/*! HS_REG_VREF_SRC_SEL - HS_REG_VREF_SRC_SEL
* 0b0..Generated from BGR
* 0b1..Generated from Current Mirror
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_LOW_HS_REG_VREF_SRC_SEL_MASK)
/*! @} */
/*! @name MIPI_M_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_MASK (0x1U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_SHIFT (0U)
/*! CLK_SEL_CTL - CLK_SEL_CTL
* 0b0..Generated from Internal PLL
* 0b1..Generated from External PLL
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_CLK_SEL_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_MASK (0xF00U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_SHIFT (8U)
/*! TXSKEWCALHS_CTL - TXSKEWCALHS_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_MASK (0xF000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_SHIFT (12U)
/*! TXSKEWCALHS_INIT_CTL - TXSKEWCALHS_INIT_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_INIT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_MASK (0xF0000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_SHIFT (16U)
/*! TXSKEWCALHS_WAIT_CTL - TXSKEWCALHS_WAIT_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_TXSKEWCALHS_WAIT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_MASK (0x10000000U)
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_SHIFT (28U)
/*! PLL_CLK_OUT_SEL - PLL_CLK_OUT_SEL
* 0b0..Disable OUT to Other lane
* 0b1..Enable OUT to Other lane
*/
#define MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_M_DPHYCTL_HIGH_PLL_CLK_OUT_SEL_MASK)
/*! @} */
/*! @name MIPI_S_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_MASK (0x3U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_SHIFT (0U)
/*! HS_RX_BIAS_CTL - HS_RX_BIAS_CTL
* 0b00..25 uA
* 0b01..30 uA
* 0b10..37.5 uA
* 0b11..50 uA
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_BIAS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_MASK (0xCU)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_SHIFT (2U)
/*! HS_RX_DELAY_CTRL - HS_RX_DELAY_CTRL
* 0b00..0 ps
* 0b01..30 ps
* 0b10..60 ps
* 0b11..90 ps
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_DELAY_CTRL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_MASK (0x30U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_SHIFT (4U)
/*! XXX - xxx
* 0b00..-
* 0b01..30 ps
* 0b10..60 ps
* 0b11..90 ps
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_XXX_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_MASK (0xC0U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_SHIFT (6U)
/*! HS_RX_TERM_IMP_CTL - HS_RX_TERM_IMP_CTL
* 0b00..98 ohm
* 0b01..106 ohm
* 0b10..85 ohm
* 0b11..91 ohm
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_HS_RX_TERM_IMP_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_MASK (0x300U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_SHIFT (8U)
/*! CLK_LANE_CAP_CTL_TCLK_SETTLE - CLK_LANE_CAP_CTL_TCLK_SETTLE
* 0b00..No change
* 0b01..3.45%
* 0b10..6.9%
* 0b11..10.35%
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_SETTLE_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_MASK (0xC00U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_SHIFT (10U)
/*! CLK_LANE_CAP_CTL_TCLK_MISS - CLK_LANE_CAP_CTL_TCLK_MISS
* 0b00..No change
* 0b01..6.6%
* 0b10..13.2%
* 0b11..19.8%
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_LANE_CAP_CTL_TCLK_MISS_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_MASK (0x1000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_SHIFT (12U)
/*! CLK_MISS_EN - CLK_MISS_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_CLK_MISS_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK (0x6000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT (13U)
/*! ANA_TIMER_HYS_CTL - ANA_TIMER_HYS_CTL
* 0b00..70mV
* 0b01..95mV
* 0b10..95mV
* 0b11..110mV
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_ANA_TIMER_HYS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_MASK (0x30000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_SHIFT (16U)
/*! DCC_CCO_GAIN_CTL - DCC_CCO_GAIN_CTL
* 0b00..1/1
* 0b01..1/4
* 0b10..1/0.66
* 0b11..1/1.33
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_CCO_GAIN_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_MASK (0x7C0000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_SHIFT (18U)
/*! DCC_BYPASS_UP_CODE_CTL_DBG1 - DCC_BYPASS_UP_CODE_CTL_DBG1
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG1_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_MASK (0xF800000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_SHIFT (23U)
/*! DCC_BYPASS_UP_CODE_CTL_DBG2 - DCC_BYPASS_UP_CODE_CTL_DBG2
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_BYPASS_UP_CODE_CTL_DBG2_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_MASK (0x70000000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_SHIFT (28U)
/*! DCC_INIT_TOLERANCE - DCC_INIT_TOLERANCE
* 0b000..4
* 0b001..5
* 0b010..6
* 0b011..7
* 0b100..0
* 0b101..1
* 0b110..2
* 0b111..3
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_INIT_TOLERANCE_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_MASK (0x80000000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_SHIFT (31U)
/*! DCC_STABLE_CTL - DCC_STABLE_CTL
* 0b0..1 number counter running
* 0b1..2 number counter running
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_LOW_DCC_STABLE_CTL_MASK)
/*! @} */
/*! @name MIPI_S_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_MASK (0x1U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_SHIFT (0U)
/*! DCC_EN - DCC_EN
* 0b0..DCC Disable
* 0b1..DCC Enable
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_DCC_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_MASK (0x2U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_SHIFT (1U)
/*! SKEW_CALIB_EN - SKEW_CALIB_EN
* 0b0..Skew Calibration Disable
* 0b1..Skew Calibration Enable
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_MASK (0xFCU)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_SHIFT (2U)
/*! SKEW_CALIB_MAX_CODE_CTL - SKEW_CALIB_MAX_CODE_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_MAX_CODE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_MASK (0x3F00U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_SHIFT (8U)
/*! SKEW_CALIB_FAIL_MIN_CTL - SKEW_CALIB_FAIL_MIN_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_MIN_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_MASK (0x3F0000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_SHIFT (16U)
/*! SKEW_CALIB_PASS_MIN_CTL - SKEW_CALIB_PASS_MIN_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_PASS_MIN_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_MASK (0x3000000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_SHIFT (24U)
/*! SKEW_CALIB_FAIL_TOL_CTL - SKEW_CALIB_FAIL_TOL_CTL
* 0b00..Recognizes the pass although fail appears 3 times
* 0b01..Recognizes the pass although fail appears 2 times
* 0b10..Recognizes the pass although fail appears 1 time
* 0b11..Reserved
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_FAIL_TOL_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_MASK (0xC000000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_SHIFT (26U)
/*! SKEW_CALIB_CMP_WAIT_TIME_CTL - SKEW_CALIB_CMP_WAIT_TIME_CTL
* 0b00..Min (Fast)
* 0b01..Reserved
* 0b10..Reserved
* 0b11..Mx (Slow)
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_WAIT_TIME_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_MASK (0xF0000000U)
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_SHIFT (28U)
/*! SKEW_CALIB_CMP_RUN_TIME_CTL - SKEW_CALIB_CMP_RUN_TIME_CTL
*/
#define MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_S_DPHYCTL_HIGH_SKEW_CALIB_CMP_RUN_TIME_CTL_MASK)
/*! @} */
/*! @name LCDIF_ARCACHE_CTRL - LCDIF ARCACHE Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_MASK (0x1U)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_SHIFT (0U)
/*! GPR_ARCACHE_LCDIF_EN - AXI master ARCACHE control enable
* 0b0..disable LCDIF AXI master ARCACHE control
* 0b1..enable LCDIF AXI master ARCACHE control
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_EN_MASK)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_MASK (0x1EU)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_SHIFT (1U)
/*! GPR_ARCACHE_LCDIF - Control LCDIF AXI master ARCACHE type
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF_MASK)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_MASK (0x20U)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_SHIFT (5U)
/*! GPR_ARCACHE_LCDIF2_EN - AXI master ARCACHE control enable
* 0b0..disable LCDIF2 AXI master ARCACHE control
* 0b1..enable LCDIF2 AXI master ARCACHE control
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_EN_MASK)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_MASK (0x3C0U)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_SHIFT (6U)
/*! GPR_ARCACHE_LCDIF2 - Control LCDIF2 AXI master ARCACHE type
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_ARCACHE_LCDIF2_MASK)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_MASK (0x1C00U)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_SHIFT (10U)
/*! GPR_LCDIF_0_RD_HURRY - GPR_lcdif_0_rd_hurry
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_0_RD_HURRY_MASK)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_MASK (0xE000U)
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_SHIFT (13U)
/*! GPR_LCDIF_1_RD_HURRY - GPR_lcdif_1_rd_hurry
*/
#define MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_SHIFT)) & MEDIA_BLK_CTRL_LCDIF_ARCACHE_CTRL_GPR_LCDIF_1_RD_HURRY_MASK)
/*! @} */
/*! @name ISI_CACHE_CTRL - ISI CACHE Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_MASK (0x1U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_SHIFT (0U)
/*! GPR_ARCACHE_ISI_Y_EN - ISI Y channel AXI master ARCACHE control enable
* 0b0..disable
* 0b1..enable
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_EN_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_MASK (0x1EU)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_SHIFT (1U)
/*! GPR_ARCACHE_ISI_Y - Control ISI Y channel AXI master ARCACHE type
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ARCACHE_ISI_Y_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_MASK (0x20U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_SHIFT (5U)
/*! GPR_AWCACHE_ISI_Y_EN - ISI Y channel AXI master AWCACHE control enable
* 0b0..disable
* 0b1..enable
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_EN_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_MASK (0x3C0U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_SHIFT (6U)
/*! GPR_AWCACHE_ISI_Y - Control ISI Y channel AXI master AWCACHE type
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_Y_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_MASK (0x400U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_SHIFT (10U)
/*! GPR_AWCACHE_ISI_U_EN - ISI U channel AXI master AWCACHE control enable
* 0b0..disable
* 0b1..enable
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_EN_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_MASK (0x7800U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_SHIFT (11U)
/*! GPR_AWCACHE_ISI_U - Control ISI U channel AXI master AWCACHE type
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_U_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_MASK (0x8000U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_SHIFT (15U)
/*! GPR_AWCACHE_ISI_V_EN - ISI V channel AXI master AWCACHE control enable
* 0b0..disable
* 0b1..enable
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_EN_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_MASK (0xF0000U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_SHIFT (16U)
/*! GPR_AWCACHE_ISI_V - Control ISI V channel AXI master AWCACHE type
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_AWCACHE_ISI_V_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_MASK (0x700000U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_SHIFT (20U)
/*! GPR_ISI_Y_WR_HURRY - GPR_ISI_y_wr_hurry
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_Y_WR_HURRY_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_MASK (0x3800000U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_SHIFT (23U)
/*! GPR_ISI_U_WR_HURRY - GPR_ISI_u_wr_hurry
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_U_WR_HURRY_MASK)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_MASK (0x1C000000U)
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_SHIFT (26U)
/*! GPR_ISI_V_WR_HURRY - GPR_ISI_v_wr_hurry
*/
#define MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_SHIFT)) & MEDIA_BLK_CTRL_ISI_CACHE_CTRL_GPR_ISI_V_WR_HURRY_MASK)
/*! @} */
/*! @name LDO_CTRL - LDO Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_MASK (0x1FU)
#define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_SHIFT (0U)
/*! MIPI_DPHY_LDO_VOUT_CTRL - LDO output control port(high level 0.8v,low level 0v)
*/
#define MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_SHIFT)) & MEDIA_BLK_CTRL_LDO_CTRL_MIPI_DPHY_LDO_VOUT_CTRL_MASK)
/*! @} */
/*! @name LDO_TRIM - LDO Trim Register */
/*! @{ */
#define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_MASK (0x1FU)
#define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_SHIFT (0U)
/*! MIPI_DPHY_LDO_VOUT_TRIM - LDO output trimming port(high level 0.8v,low level 0v)
*/
#define MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_SHIFT)) & MEDIA_BLK_CTRL_LDO_TRIM_MIPI_DPHY_LDO_VOUT_TRIM_MASK)
/*! @} */
/*! @name LDB_CTRL - LDB Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_MASK (0x1U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_SHIFT (0U)
/*! CH0_ENABLE - ch0_enable
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_ENABLE_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_MASK (0x2U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_SHIFT (1U)
/*! CH0_DI_SELECT - ch0_di_select
* 0b0..LDB data from source 0
* 0b1..LDB data from source 1
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_DI_SELECT_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_MASK (0x4U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_SHIFT (2U)
/*! CH1_ENABLE - ch1_enable
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_ENABLE_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_MASK (0x8U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_SHIFT (3U)
/*! CH1_DI_SELECT - ch1_di_select
* 0b0..LDB data from source 0
* 0b1..LDB data from source 1
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_DI_SELECT_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_MASK (0x10U)
#define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_SHIFT (4U)
/*! SPLIT_MODE - split_mode
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_SPLIT_MODE_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_MASK (0x20U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_SHIFT (5U)
/*! CH0_DATA_WIDTH - ch0_data_width
* 0b1..24bits
* 0b0..18bits
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_DATA_WIDTH_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_MASK (0x40U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_SHIFT (6U)
/*! CH0_BIT_MAPPING - ch0_bit_mapping
* 0b1..JEIDA mapping
* 0b0..SPWG mapping
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH0_BIT_MAPPING_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_MASK (0x80U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_SHIFT (7U)
/*! CH1_DATA_WIDTH - ch1_data_width
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_DATA_WIDTH_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_MASK (0x100U)
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_SHIFT (8U)
/*! CH1_BIT_MAPPING - ch1_bit_mapping
* 0b1..JEIDA mapping
* 0b0..SPWG mapping
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_CH1_BIT_MAPPING_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_MASK (0x200U)
#define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT (9U)
/*! DI0_VSYNC_POLARITY - di0 VSYNC polarity select
* 0b1..positive polarity
* 0b0..negative polarity
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_DI0_VSYNC_POLARITY_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_MASK (0x400U)
#define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT (10U)
/*! DI1_VSYNC_POLARITY - di1 VSYNC polarity select
* 0b1..positive polarity
* 0b0..negative polarity
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_DI1_VSYNC_POLARITY_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_MASK (0x800U)
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_SHIFT (11U)
/*! REG_CH0_FIFO_RESET - reg_ch0_fifo_reset
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_REG_CH0_FIFO_RESET_MASK)
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_MASK (0x1000U)
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_SHIFT (12U)
/*! REG_CH1_FIFO_RESET - reg_ch1_fifo_reset
*/
#define MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_SHIFT)) & MEDIA_BLK_CTRL_LDB_CTRL_REG_CH1_FIFO_RESET_MASK)
/*! @} */
/*! @name GASKET_0_CTRL - Gasket 0 Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_MASK (0x1U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_SHIFT (0U)
/*! GASKET_0_ENABLE - Gasket 0 enable
* 0b1..Gasket 0 output enable
* 0b0..Gasket output disable
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_ENABLE_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_MASK (0x2U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_SHIFT (1U)
/*! GASKET_0_DOUBLE_COMP - Gasket 0 double component enable
* 0b1..Gasket 0 input double component per pixel clock for YUV422
* 0b0..Gasket 0 input single component per pixel clock for YUV422
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DOUBLE_COMP_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_MASK (0x4U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_SHIFT (2U)
/*! GASKET_0_LEFT_JUST_MODE - Gasket 0 Left justified mode
* 0b1..unused LSB equal most significant bit of valid data
* 0b0..unused LSB equal lease significant bit of valid data
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_MASK (0x8U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_SHIFT (3U)
/*! GASKET_0_YUV420_LINE_SEL - Gasket 0 YUV420 ODD/EVEN line first select
* 0b1..Gasket 0 EVEN line first for YUV420 data type
* 0b0..Gasket 0 ODD line first for YUV420 data type
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_YUV420_LINE_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_MASK (0x30U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_SHIFT (4U)
/*! GASKET_0_VC_ID - Gasket 0 Virtual channel identifier,
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_VC_ID_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_MASK (0xC0U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_SHIFT (6U)
/*! GASKET_0_INTER_MODE - Gasket 0 interlace mode
* 0b11..reserved
* 0b10..interlaced right
* 0b01..interlaced left
* 0b00..not interlaced
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_INTER_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_MASK (0x3F00U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_SHIFT (8U)
/*! GASKET_0_DATA_TYPE - Gasket 0 data type
* 0b011000..YUV420 8-bit
* 0b011001..YUV420 10-bit
* 0b011010..Legacy YUV420 8-bit
* 0b011100..YUV420 8-bit(Chroma Shifted Pixel Sampling)
* 0b011101..YUV420 10-bit(Chroma Shifted Pixel Sampling)
* 0b011110..YUV422 8-bit
* 0b011111..YUV422 10-bit
* 0b100010..RGB565
* 0b100011..RGB666
* 0b100100..RGB888
* 0b101000..RAW6
* 0b101001..RAW7
* 0b101010..RAW8
* 0b101011..RAW10
* 0b101100..RAW12
* 0b101101..RAW14
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_DATA_TYPE_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_MASK (0xC000U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_SHIFT (14U)
/*! GASKET_0_SRC_SEL - Gasket 0 source when support ISI de-interlace line_doubling mode
* 0b11..source from mipi_csi channel 3
* 0b10..source from mipi_csi channel 2
* 0b01..source from mipi_csi channel 1
* 0b00..source from mipi_csi channel 0
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_MASK (0x10000U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_SHIFT (16U)
/*! GASKET_0_LINE_DOUBLING_EN - Gasket 0 output for ISI de-interlace line_doubling mode enable
* 0b1..Gasket 0 output for ISI de-interlace line_doubling mode
* 0b0..Gasket 0 not output for ISI de-interlace line_doubling mode
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_GASKET_0_LINE_DOUBLING_EN_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_MASK (0x20000U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_SHIFT (17U)
/*! MIPI_ISP_LEFT_JUST_MODE - mipi_isp_left_just_mode
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_ISP_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_MASK (0xC0000U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_SHIFT (18U)
/*! MIPI_CSI_VS_SEL - mipi_csi_vs_sel
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_VS_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_MASK (0x100000U)
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_SHIFT (20U)
/*! MIPI_CSI_HS_POLARITY - mipi_csi_hs_polarity
*/
#define MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_CTRL_MIPI_CSI_HS_POLARITY_MASK)
/*! @} */
/*! @name GASKET_0_HSIZE - Gasket 0 Video Horizontal Size Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_SHIFT (0U)
/*! GASKET_0_HSIZE - Gasket 0 video Horizontal size(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HSIZE_GASKET_0_HSIZE_MASK)
/*! @} */
/*! @name GASKET_0_VSIZE - Gasket 0 Video Vertical Size Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_SHIFT (0U)
/*! GASKET_0_VSIZE - Gasket 0 video Vertical size(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VSIZE_GASKET_0_VSIZE_MASK)
/*! @} */
/*! @name GASKET_0_HFP - Gasket 0 Video Horizontal Front Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_SHIFT (0U)
/*! GASKET_0_HFP - Gasket 0 video Horizontal front porch(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HFP_GASKET_0_HFP_MASK)
/*! @} */
/*! @name GASKET_0_HBP - Gasket 0 Video Horizontal Back Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_SHIFT (0U)
/*! GASKET_0_HBP - Gasket 0 video Horizontal back porch(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_HBP_GASKET_0_HBP_MASK)
/*! @} */
/*! @name GASKET_0_VFP - Gasket 0 Video Vertical Front Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_SHIFT (0U)
/*! GASKET_0_VFP - Gasket 0 video Vertical front porch(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VFP_GASKET_0_VFP_MASK)
/*! @} */
/*! @name GASKET_0_VBP - Gasket 0 Video Vertical Back Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_SHIFT (0U)
/*! GASKET_0_VBP - Gasket 0 video Vertical back porch(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_VBP_GASKET_0_VBP_MASK)
/*! @} */
/*! @name GASKET_0_ISI_PIXEL_CNT - Gasket 0 ISI Pixel Count Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_SHIFT (0U)
/*! GASKET_0_ISI_PIXEL_CNT - Gasket 0 output to ISI pixel count status
*/
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CNT_GASKET_0_ISI_PIXEL_CNT_MASK)
/*! @} */
/*! @name GASKET_0_ISI_LINE_CNT - Gasket 0 ISI Line Count Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_SHIFT (0U)
/*! GASKET_0_ISI_LINE_CNT - Gasket 0 output to ISI line count status
*/
#define MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_LINE_CNT_GASKET_0_ISI_LINE_CNT_MASK)
/*! @} */
/*! @name GASKET_0_ISI_PIXEL_CTRL - Gasket 0 ISI Pixel Control Information Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_MASK (0xFFFU)
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_SHIFT (0U)
/*! GASKET_0_ISI_PIXEL_CTRL - Gasket 0 output to ISI pixel control information status
*/
#define MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_0_ISI_PIXEL_CTRL_GASKET_0_ISI_PIXEL_CTRL_MASK)
/*! @} */
/*! @name GASKET_1_CTRL - Gasket 1 Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_MASK (0x1U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_SHIFT (0U)
/*! GASKET_1_ENABLE - Gasket 1 enable
* 0b1..Gasket 1 output enable;
* 0b0..Gasket output disable
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_ENABLE_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_MASK (0x2U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_SHIFT (1U)
/*! GASKET_1_DOUBLE_COMP - Gasket 1 double component enable
* 0b1..Gasket 1 input double component per pixel clock for YUV422
* 0b0..Gasket 1 input single component per pixel clock for YUV422
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DOUBLE_COMP_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_MASK (0x4U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_SHIFT (2U)
/*! GASKET_1_LEFT_JUST_MODE - Gasket 1 Left justified mode
* 0b1..unused LSB equal most significant bit of valid data
* 0b0..unused LSB equal lease significant bit of valid data
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_MASK (0x8U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_SHIFT (3U)
/*! GASKET_1_YUV420_LINE_SEL - Gasket 1 YUV420 ODD/EVEN line first select
* 0b1..Gasket 1 EVEN line first for YUV420 data type
* 0b0..Gasket 1 ODD line first for YUV420 data type
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_YUV420_LINE_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_MASK (0x30U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_SHIFT (4U)
/*! GASKET_1_VC_ID - Gasket 1 Virtual channel identifier,
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_VC_ID_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_MASK (0xC0U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_SHIFT (6U)
/*! GASKET_1_INTER_MODE - Gasket 1 interlace mode
* 0b11..reserved
* 0b10..interlaced right
* 0b01..interlaced left
* 0b00..not interlaced
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_INTER_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_MASK (0x3F00U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_SHIFT (8U)
/*! GASKET_1_DATA_TYPE - Gasket 1 data type
* 0b011000..YUV420 8-bit
* 0b011001..YUV420 10-bit
* 0b011010..Legacy YUV420 8-bit
* 0b011100..YUV420 8-bit(Chroma Shifted Pixel Sampling)
* 0b011101..YUV420 10-bit(Chroma Shifted Pixel Sampling)
* 0b011110..YUV422 8-bit
* 0b011111..YUV422 10-bit
* 0b100010..RGB565
* 0b100011..RGB666
* 0b100100..RGB888
* 0b101000..RAW6
* 0b101001..RAW7
* 0b101010..RAW8
* 0b101011..RAW10
* 0b101100..RAW12
* 0b101101..RAW14
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_DATA_TYPE_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_MASK (0xC000U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_SHIFT (14U)
/*! GASKET_1_SRC_SEL - Gasket 1 source when support ISI de-interlace line_doubling mode
* 0b11..source from mipi_csi channel 3
* 0b10..source from mipi_csi channel 2
* 0b01..source from mipi_csi channel 1
* 0b00..source from mipi_csi channel 0
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_MASK (0x10000U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_SHIFT (16U)
/*! GASKET_1_LINE_DOUBLING_EN - Gasket 1 output for ISI de-interlace line_doubling mode enable
* 0b1..Gasket 1 output for ISI de-interlace line_doubling mode
* 0b0..Gasket 0 not output for ISI de-interlace line_doubling mode
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_GASKET_1_LINE_DOUBLING_EN_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_MASK (0x20000U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT (17U)
/*! MIPI_ISP2_LEFT_JUST_MODE - mipi_isp2_left_just_mode
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_ISP2_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_MASK (0xC0000U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_SHIFT (18U)
/*! MIPI_CSI2_VS_SEL - mipi_csi2_vs_sel
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_VS_SEL_MASK)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_MASK (0x100000U)
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_SHIFT (20U)
/*! MIPI_CSI2_HS_POLARITY - mipi_csi2_hs_polarity
*/
#define MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_CTRL_MIPI_CSI2_HS_POLARITY_MASK)
/*! @} */
/*! @name GASKET_1_HSIZE - Gasket 1 Video Horizontal Size Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_SHIFT (0U)
/*! GP0 - Gasket 1 video Horizontal size(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HSIZE_GP0_MASK)
/*! @} */
/*! @name GASKET_1_VSIZE - Gasket 1 Video Vertical Size Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_SHIFT (0U)
/*! GASKET_1_VSIZE - Gasket 1 video Vertical size(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VSIZE_GASKET_1_VSIZE_MASK)
/*! @} */
/*! @name GASKET_1_HFP - Gasket 1 Video Horizontal Front Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_SHIFT (0U)
/*! GASKET_1_HFP - Gasket 1 video Horizontal front porch(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HFP_GASKET_1_HFP_MASK)
/*! @} */
/*! @name GASKET_1_HBP - Gasket 1 Video Horizontal Back Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_SHIFT (0U)
/*! GASKET_1_HBP - Gasket 1 video Horizontal back porch(count in pixel)
*/
#define MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_HBP_GASKET_1_HBP_MASK)
/*! @} */
/*! @name GASKET_1_VFP - Gasket 1 Video Vertical Front Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_SHIFT (0U)
/*! GASKET_1_VFP - Gasket 1 video Vertical front porch(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VFP_GASKET_1_VFP_MASK)
/*! @} */
/*! @name GASKET_1_VBP - Gasket 1 Video Vertical Back Porch Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_SHIFT (0U)
/*! GASKET_1_VBP - Gasket 1 video Vertical back porch(count in line)
*/
#define MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_VBP_GASKET_1_VBP_MASK)
/*! @} */
/*! @name GASKET_1_ISI_PIXEL_CNT - Gasket 1 ISI Pixel Count Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_SHIFT (0U)
/*! GASKET_1_ISI_PIXEL_CNT - Gasket 1 output to ISI pixel count status
*/
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CNT_GASKET_1_ISI_PIXEL_CNT_MASK)
/*! @} */
/*! @name GASKET_1_ISI_LINE_CNT - Gasket 1 ISI Line Count Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_MASK (0xFFFFFFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_SHIFT (0U)
/*! GASKET_1_ISI_LINE_CNT - Gasket 1 output to ISI line count status
*/
#define MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_LINE_CNT_GASKET_1_ISI_LINE_CNT_MASK)
/*! @} */
/*! @name GASKET_1_ISI_PIXEL_CTRL - Gasket 1 ISI Pixel Control Information Register */
/*! @{ */
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_MASK (0xFFFU)
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_SHIFT (0U)
/*! GASKET_1_ISI_PIXEL_CTRL - Gasket 1 output to ISI pixel control information status
*/
#define MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_SHIFT)) & MEDIA_BLK_CTRL_GASKET_1_ISI_PIXEL_CTRL_GASKET_1_ISI_PIXEL_CTRL_MASK)
/*! @} */
/*! @name MIPI_B2_DPHYCTL_LOW - Master and Slave DPHY Control Low Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK (0x3FFU)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT (0U)
/*! ULPS_EXIT_COUNTER - ULPS_EXIT_COUNTER
* 0b0000000000..0.01 MHz
* 0b0000000011..0.10 MHz
* 0b0000011001..1.00 MHz
* 0b0000110010..2.00 MHz
* 0b0001001011..3.00 MHz
* 0b0001100100..4.00 MHz
* 0b0001111101..5.00 MHz
* 0b0010010110..6.00 MHz
* 0b0010101111..7.00 MHz
* 0b0011001000..8.00 MHz
* 0b0011100001..9.00 MHz
* 0b0011111010..10.00 MHz
* 0b0100010011..11.00 MHz
* 0b0100101100..12.00 MHz
* 0b0101000101..13.00 MHz
* 0b0101011110..14.00 MHz
* 0b0101110111..15.00 MHz
* 0b0110010000..16.00 MHz
* 0b0110101001..17.00 MHz
* 0b0111000010..18.00 MHz
* 0b0111011011..19.00 MHz
* 0b0111110100..20.00 MHz
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ULPS_EXIT_COUNTER_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK (0x400U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT (10U)
/*! TX_TRIGGER_CLK_EN - TX_TRIGGER_CLK_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_TX_TRIGGER_CLK_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK (0x800U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT (11U)
/*! ERR_CONT_LP_EN - ERR_CONT_LP_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_ERR_CONT_LP_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
/*! BGR_CHOPPER_EN - BGR_CHOPPER_EN
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_MASK (0x2000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_SHIFT (13U)
/*! LP_CD_HYS - LP_CD_HYS
* 0b0..60mV
* 0b1..70mV
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_CD_HYS_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK (0x4000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT (14U)
/*! MSTR_CLK_SLEW_RATE_UP - MSTR_CLK_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK (0x18000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT (15U)
/*! MSTR_CLK_SLEW_RATE_DOWN - MSTR_CLK_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_MSTR_CLK_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK (0x20000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT (17U)
/*! LP_RX_PULSE_REJ - LP_RX_PULSE_REJ
* 0b0..Enable
* 0b1..Disable
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_PULSE_REJ_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
/*! LP_RX_VREF_LVL - LP_RX_VREF_LVL
* 0b00..715mV
* 0b01..743mV
* 0b10..650mV
* 0b11..682mV
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_VREF_LVL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_MASK (0x100000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT (20U)
/*! VREF_SRC_SEL - VREF_SRC_SEL
* 0b0..Generated from the BGR
* 0b1..Generated from the current mirror
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_VREF_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK (0x600000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT (21U)
/*! LP_RX_HYS_CTL - LP_RX_HYS_CTL
* 0b00..80mV
* 0b01..100mV
* 0b10..120mV
* 0b11..140mV
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_LP_RX_HYS_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_SHIFT (23U)
/*! REG_VALID_1_2 - REG_VALID_1_2
* 0b0..Use "ulps_en" signal
* 0b1..Use valid signal from 1.2V regulator
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK (0x3000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT (24U)
/*! REG_LVL_CTL_1_2 - REG_LVL_CTL_1_2
* 0b00..1.2V
* 0b01..1.23V
* 0b10..1.27V
* 0b11..1.26V
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_LVL_CTL_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK (0x4000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT (26U)
/*! REG_VALID_CTL_1_2 - REG_VALID_CTL_1_2
* 0b0..Internal 1.2V regulator
* 0b1..External 1.2V power
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_REG_VALID_CTL_1_2_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK (0x8000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT (27U)
/*! BGR_CHOPPER_FREQ_CTL - BGR_CHOPPER_FREQ_CTL
* 0b0..3MHz
* 0b1..1.5MHz
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BGR_CHOPPER_FREQ_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK (0x30000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT (28U)
/*! BIAS_REF_VOLT_CTL - BIAS_REF_VOLT_CTL
* 0b00..712mV
* 0b01..724mV
* 0b10..733mV
* 0b11..706mV
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_BIAS_REF_VOLT_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_MASK (0xC0000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_SHIFT (30U)
/*! USER_DATA_HS - User Data Pattern for HS Loopback mode
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_LOW_USER_DATA_HS_MASK)
/*! @} */
/*! @name MIPI_B2_DPHYCTL_HIGH - Master and Slave DPHY Control High Register */
/*! @{ */
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_MASK (0x3FU)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_SHIFT (0U)
/*! USER_DATA_HS - User Data Pattern for HS Loopback mode
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_USER_DATA_HS_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_MASK (0xC0U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT (6U)
/*! HS_MODE_CTL - HS_MODE_CTL
* 0b00..Designated Pattern
* 0b01..PRBS7
* 0b10..All zero
* 0b11..User Data Pattern
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_HS_MODE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK (0x300U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT (8U)
/*! BGR_VOLT_TUNING_CTL - BGR_VOLT_TUNING_CTL
* 0b00..820mV
* 0b01..760mV
* 0b10..800mV
* 0b11..840mV
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_BGR_VOLT_TUNING_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_MASK (0x800U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT (11U)
/*! DCC_DONE_CTL - DCC_DONE_CTL
* 0b0.."DONE" from DCC block
* 0b1..U"DONE" is always 1
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_DCC_DONE_CTL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK (0x2000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT (13U)
/*! RX_SKEW_CALIB_FIX_CODE_EN - RX_SKEW_CALIB_FIX_CODE_EN
* 0b0..Disable
* 0b1..Enable
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_RX_SKEW_CALIB_FIX_CODE_EN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK (0x4000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT (14U)
/*! LP_VREF_REG_SRC_SEL - LP_VREF_REG_SRC_SEL
* 0b0..Generated from BGR
* 0b1..Generated from Current Mirror
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_LP_VREF_REG_SRC_SEL_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK (0x100000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT (20U)
/*! MSTR_DATA0_SLEW_RATE_UP - MSTR_DATA0_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK (0x600000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT (21U)
/*! MSTR_DATA0_SLEW_RATE_DOWN - MSTR_DATA0_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA0_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK (0x800000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT (23U)
/*! MSTR_DATA1_SLEW_RATE_UP - MSTR_DATA1_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK (0x3000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT (24U)
/*! MSTR_DATA1_SLEW_RATE_DOWN - MSTR_DATA1_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA1_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK (0x4000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT (26U)
/*! MSTR_DATA2_SLEW_RATE_UP - MSTR_DATA2_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK (0x18000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT (27U)
/*! MSTR_DATA2_SLEW_RATE_DOWN - MSTR_DATA2_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA2_SLEW_RATE_DOWN_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK (0x20000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT (29U)
/*! MSTR_DATA3_SLEW_RATE_UP - MSTR_DATA3_SLEW_RATE_UP
* 0b0..No change
* 0b1..Slew Rate UP
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_UP_MASK)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK (0xC0000000U)
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT (30U)
/*! MSTR_DATA3_SLEW_RATE_DOWN - MSTR_DATA3_SLEW_RATE_DOWN
* 0b00..No change
* 0b01..Decrease the slew rate by about 15%
* 0b10..Decrease the slew rate by about 15%
* 0b11..Decrease the slew rate by about 30%
*/
#define MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_SHIFT)) & MEDIA_BLK_CTRL_MIPI_B2_DPHYCTL_HIGH_MSTR_DATA3_SLEW_RATE_DOWN_MASK)
/*! @} */
/*! @name LVDS_CTRL - LVDS Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_MASK (0x1U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_SHIFT (0U)
/*! CH0_EN - channel0 enable
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CH0_EN_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_MASK (0x2U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_SHIFT (1U)
/*! CH1_EN - channel1 enable
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CH1_EN_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_MASK (0x4U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_SHIFT (2U)
/*! VBG_EN - Bandgap enable.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_VBG_EN_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_MASK (0x8U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_SHIFT (3U)
/*! HS_EN - hs_en
* 0b1..enable the 100 Ohm terminated resistor in the chip, at the same time, the power dissipation will also be double.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_HS_EN_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_MASK (0x10U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_SHIFT (4U)
/*! PRE_EMPH_EN - Enable pre-emphasis
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_EN_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_MASK (0xE0U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_SHIFT (5U)
/*! PRE_EMPH_ADJ - Pre-emphasis adjustment.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_PRE_EMPH_ADJ_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_MASK (0x700U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_SHIFT (8U)
/*! CM_ADJ - Output common mode(Vos) adjustment.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CM_ADJ_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_MASK (0x3800U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_SHIFT (11U)
/*! CC_ADJ - Output current adjustment.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_CC_ADJ_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_MASK (0x1C000U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_SHIFT (14U)
/*! SLEW_ADJ - Output transition time adjustment.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_SLEW_ADJ_MASK)
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_MASK (0xE0000U)
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_SHIFT (17U)
/*! VBG_ADJ - Bandgap adjustment.
*/
#define MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_SHIFT)) & MEDIA_BLK_CTRL_LVDS_CTRL_VBG_ADJ_MASK)
/*! @} */
/*! @name AXI_LIMIT_CONTROL - AXI Limit Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_MASK (0x1U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_SHIFT (0U)
/*! GPR_AXI_LIMIT_LCDIF0_EN - gpr_axi_limit_lcdif0_en
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF0_EN_MASK)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_MASK (0x2U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_SHIFT (1U)
/*! GPR_AXI_LIMIT_LCDIF1_EN - gpr_axi_limit_lcdif1_en
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_LCDIF1_EN_MASK)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_MASK (0x4U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_SHIFT (2U)
/*! GPR_AXI_LIMIT_ISI_EN - gpr_axi_limit_isi_en
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_ISI_EN_MASK)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_MASK (0x8U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_SHIFT (3U)
/*! GPR_AXI_LIMIT_DEWARP_EN - gpr_axi_limit_dewarp_en
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_CONTROL_GPR_AXI_LIMIT_DEWARP_EN_MASK)
/*! @} */
/*! @name AXI_LIMIT_THRESH0 - AXI Limit Threshold Register 0 */
/*! @{ */
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_MASK (0xFFFFU)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_SHIFT (0U)
/*! GPR_AXI_LIMIT_LCDIF0_THRESH - gpr_axi_limit_lcdif0_thresh
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF0_THRESH_MASK)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_MASK (0xFFFF0000U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_SHIFT (16U)
/*! GPR_AXI_LIMIT_LCDIF1_THRESH - gpr_axi_limit_lcdif1_thresh
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH0_GPR_AXI_LIMIT_LCDIF1_THRESH_MASK)
/*! @} */
/*! @name AXI_LIMIT_THRESH1 - AXI Limit Threshold Register 1 */
/*! @{ */
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_MASK (0xFFFFU)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_SHIFT (0U)
/*! GPR_AXI_LIMIT_ISI_THRESH - gpr_axi_limit_isi_thresh
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_ISI_THRESH_MASK)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_MASK (0xFFFF0000U)
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_SHIFT (16U)
/*! GPR_AXI_LIMIT_DEWARP_THRESH - gpr_axi_limit_dewarp_thresh
*/
#define MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_SHIFT)) & MEDIA_BLK_CTRL_AXI_LIMIT_THRESH1_GPR_AXI_LIMIT_DEWARP_THRESH_MASK)
/*! @} */
/*! @name ISP_DEWARP_CONTROL - ISP Dewarp Control Register */
/*! @{ */
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_MASK (0x1U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_SHIFT (0U)
/*! GPR_ISP_0_DISABLE - gpr_isp_0_disable
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_0_DISABLE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_MASK (0x2U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_SHIFT (1U)
/*! GPR_ISP_1_DISABLE - gpr_isp_1_disable
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_GPR_ISP_1_DISABLE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_MASK (0x1F8U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_SHIFT (3U)
/*! MIPI_ISP_DATA_TYPE - mipi_isp_data_type
* 0b101000..RAW6
* 0b101001..RAW7
* 0b101010..RAW8
* 0b101011..RAW10
* 0b101100..RAW12
* 0b101101..RAW14
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_DATA_TYPE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_MASK (0x200U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_SHIFT (9U)
/*! MIPI_ISP_LEFT_JUST_MODE - mipi_isp_left_just_mode
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK (0x7E000U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_SHIFT (13U)
/*! MIPI_ISP2_DATA_TYPE - mipi_isp2_data_type
* 0b101000..RAW6
* 0b101001..RAW7
* 0b101010..RAW8
* 0b101011..RAW10
* 0b101100..RAW12
* 0b101101..RAW14
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_DATA_TYPE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_MASK (0x80000U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT (19U)
/*! MIPI_ISP2_LEFT_JUST_MODE - mipi_isp2_left_just_mode
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_MIPI_ISP2_LEFT_JUST_MODE_MASK)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_MASK (0x1800000U)
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_SHIFT (23U)
/*! ISP_ID_MODE - isp_id_mode
* 0b11..vc_id_02 toggle 0,1,2 during no data transmit;
* 0b10..vc_id_01 toggle 0,1 during no data transmit;
* 0b01..vc_id_012 toggle 0,2 during no data transmit;
* 0b00..vc_id_disable; ID will not toggle during no data transmit;
*/
#define MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE(x) (((uint32_t)(((uint32_t)(x)) << MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_SHIFT)) & MEDIA_BLK_CTRL_ISP_DEWARP_CONTROL_ISP_ID_MODE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MEDIA_BLK_CTRL_Register_Masks */
/* MEDIA_BLK_CTRL - Peripheral instance base addresses */
/** Peripheral MEDIA_BLK_CTRL base address */
#define MEDIA_BLK_CTRL_BASE (0x32EC0000u)
/** Peripheral MEDIA_BLK_CTRL base pointer */
#define MEDIA_BLK_CTRL ((MEDIA_BLK_CTRL_Type *)MEDIA_BLK_CTRL_BASE)
/** Array initializer of MEDIA_BLK_CTRL peripheral base addresses */
#define MEDIA_BLK_CTRL_BASE_ADDRS { MEDIA_BLK_CTRL_BASE }
/** Array initializer of MEDIA_BLK_CTRL peripheral base pointers */
#define MEDIA_BLK_CTRL_BASE_PTRS { MEDIA_BLK_CTRL }
/*!
* @}
*/ /* end of group MEDIA_BLK_CTRL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MIPI_CSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_CSI_Peripheral_Access_Layer MIPI_CSI Peripheral Access Layer
* @{
*/
/** MIPI_CSI - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t CSIS_COMMON_CTRL; /**< CSIS Common Control Register, offset: 0x4 */
__IO uint32_t CSIS_CLOCK_CTRL; /**< CSIS Clock Control Register, offset: 0x8 */
uint8_t RESERVED_1[4];
__IO uint32_t INTERRUPT_MASK_0; /**< Interrupt mask register 0, offset: 0x10 */
__IO uint32_t INTERRUPT_SOURCE_0; /**< Interrupt source register 0, offset: 0x14 */
__IO uint32_t INTERRUPT_MASK_1; /**< Interrupt mask register 1, offset: 0x18 */
__IO uint32_t INTERRUPT_SOURCE_1; /**< Interrupt source register 1, offset: 0x1C */
__IO uint32_t DPHY_STATUS; /**< D-PHY status register, offset: 0x20 */
__IO uint32_t DPHY_COMMON_CTRL; /**< D-PHY common control register, offset: 0x24 */
uint8_t RESERVED_2[8];
__IO uint32_t DPHY_MASTER_SLAVE_CTRL_LOW; /**< D-PHY Master and Slave Control register Low, offset: 0x30 */
__IO uint32_t DPHY_MASTER_SLAVE_CTRL_HIGH; /**< D-PHY Master and Slave Control register HIGH, offset: 0x34 */
__IO uint32_t DPHY_SLAVE_CTRL_LOW; /**< D-PHY Slave Control register Low, offset: 0x38 */
__IO uint32_t DPHY_SLAVE_CTRL_HIGH; /**< D-PHY Slave Control register HIGH, offset: 0x3C */
__IO uint32_t ISP_CONFIG; /**< ISP Configuration Register, offset: 0x40 */
__IO uint32_t ISP_RESOLUTION; /**< ISP Resolution Register, offset: 0x44 */
__IO uint32_t ISP_SYNC; /**< ISP SYNC Register, offset: 0x48 */
uint8_t RESERVED_3[52];
__I uint32_t SHADOW_CONFIG; /**< Shadow Configuration Register, offset: 0x80 */
__I uint32_t SHADOW_RESOLUTION; /**< Shadow Resolution Register, offset: 0x84 */
__I uint32_t SHADOW_SYNC; /**< Shadow SYNC Register, offset: 0x88 */
uint8_t RESERVED_4[116];
__IO uint32_t FRAME_COUNTER; /**< Frame Counter, offset: 0x100 */
uint8_t RESERVED_5[12];
__IO uint32_t LINE_INTERRUPT_RATIO; /**< Line Interrupt Ratio, offset: 0x110 */
} MIPI_CSI_Type;
/* ----------------------------------------------------------------------------
-- MIPI_CSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_CSI_Register_Masks MIPI_CSI Register Masks
* @{
*/
/*! @name CSIS_COMMON_CTRL - CSIS Common Control Register */
/*! @{ */
#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK (0x1U)
#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT (0U)
/*! CSI_EN
* 0b0..Disable
* 0b1..Enable
*/
#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK)
#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK (0x2U)
#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT (1U)
/*! SW_RESET - Software reset
* 0b0..Ready
* 0b1..Reset
*/
#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK)
#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK (0x300U)
#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT (8U)
/*! LANE_NUMBER
* 0b00..1 data lane
* 0b01..2 data lane
* 0b10..3 data lane
* 0b11..4 data lane
*/
#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK)
#define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_MASK (0xC00U)
#define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_SHIFT (10U)
/*! INTERLEAVE_MODE - Select Interleave mode
* 0b00..CH0 only, no data interleave
* 0b01..DT (Data type) only
* 0b10..Reserved
* 0b11..Reserved
*/
#define MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_INTERLEAVE_MODE_MASK)
#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK (0x10000U)
#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT (16U)
/*! UPDATE_SHADOW - Strobe of updating shadow registers
*/
#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK)
/*! @} */
/*! @name CSIS_CLOCK_CTRL - CSIS Clock Control Register */
/*! @{ */
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK (0x10U)
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT (4U)
/*! CLKGATE_EN
* 0b0..Pixel clock is always alive
* 0b1..Pixel clock is alive during the interval of frame
*/
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT)) & MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK)
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK (0xF0000U)
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT (16U)
/*! CLKGATE_TRAIL - 0 ~ 3 (1~4 Trailing clocks)
*/
#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT)) & MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK)
/*! @} */
/*! @name INTERRUPT_MASK_0 - Interrupt mask register 0 */
/*! @{ */
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK (0x1U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT (0U)
/*! MSK_ERR_ID - Unknown ID error
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK (0x2U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT (1U)
/*! MSK_ERR_CRC - CRC error
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK (0x4U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT (2U)
/*! MSK_ERR_ECC - ECC error
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK (0x8U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT (3U)
/*! MSK_ERR_WRONG_CFG - Wrong configuration
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK (0x10U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT (4U)
/*! MSK_ERR_OVER - Image FIFO overflow interrupt
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK (0x100U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT (8U)
/*! MSK_ERR_LOST_FE - Lost of Frame End packet, CH0.
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK (0x1000U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT (12U)
/*! MSK_ERR_LOST_FS - Lost of Frame Start packet, CH0.
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK (0xF0000U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT (16U)
/*! MSK_ERR_SOT_HS - Start of transmission error [Lane3, Lane2, Lane1, Lane0]
* 0b0000..Disable (masked)
* 0b0001..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK (0x100000U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT (20U)
/*! MSK_FRAMEEND - FE packet is received, CH0.
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK (0x1000000U)
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT (24U)
/*! MSK_FRAMESTART - FS packet is received, CH0.
* 0b0..Disable (masked)
* 0b1..Enable (unmasked)
*/
#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK)
/*! @} */
/*! @name INTERRUPT_SOURCE_0 - Interrupt source register 0 */
/*! @{ */
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK (0x1U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT (0U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK (0x2U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT (1U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK (0x4U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT (2U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK (0x8U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT (3U)
/*! ERR_WRONG_CFG - Wrong configuration
*/
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK (0x10U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT (4U)
/*! ERR_OVER - Overflow is caused in image FIFO.
*/
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK (0x100U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT (8U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK (0x1000U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT (12U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK (0xF0000U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT (16U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK (0x100000U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT (20U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK (0x1000000U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT (24U)
#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK)
/*! @} */
/*! @name INTERRUPT_MASK_1 - Interrupt mask register 1 */
/*! @{ */
#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK (0x1U)
#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT (0U)
#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT)) & MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK)
/*! @} */
/*! @name INTERRUPT_SOURCE_1 - Interrupt source register 1 */
/*! @{ */
#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK (0x1U)
#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT (0U)
#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT)) & MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK)
/*! @} */
/*! @name DPHY_STATUS - D-PHY status register */
/*! @{ */
#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK (0x1U)
#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT (0U)
/*! STOPSTATECLK
* 0b0..Not Stop state
* 0b1..Stop state
*/
#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK)
#define MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK (0x2U)
#define MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT (1U)
/*! ULPSCLK
* 0b0..Not ULPS
* 0b1..ULPS
*/
#define MIPI_CSI_DPHY_STATUS_ULPSCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK)
#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK (0xF0U)
#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT (4U)
/*! STOPSTATEDAT - Data lane [3:0] is in Stop State
* 0b0000..Not Stop state
* 0b0001..Stop state
*/
#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK)
#define MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK (0xF00U)
#define MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT (8U)
/*! ULPSDAT - Data lane [3:0] is in ULPS
* 0b0000..Not ULPS
* 0b0001..ULPS
*/
#define MIPI_CSI_DPHY_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK)
/*! @} */
/*! @name DPHY_COMMON_CTRL - D-PHY common control register */
/*! @{ */
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK (0x1U)
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT (0U)
/*! ENABLE_CLK
* 0b0..Disable
* 0b1..Enable
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK)
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK (0x1EU)
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT (1U)
/*! ENABLE_DAT - D-PHY enable
* 0b0000..Disable
* 0b0001..Enable
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK (0x20U)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT (5U)
/*! S_DPDN_SWAP_DAT - Swapping Dp and Dn channel of data lanes.
* 0b0..Default
* 0b1..Swapped
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK (0x40U)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT (6U)
/*! S_DPDN_SWAP_CLK
* 0b0..Default
* 0b1..Swapped
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK (0xC00000U)
#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT (22U)
/*! S_CLKSETTLECTL - Slave clock lane control for Tclk-settle
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK)
#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK (0xFF000000U)
#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT (24U)
/*! HSSETTLE - HS-RX settle time control
*/
#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT)) & MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK)
/*! @} */
/*! @name DPHY_MASTER_SLAVE_CTRL_LOW - D-PHY Master and Slave Control register Low */
/*! @{ */
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK (0x3FFU)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT (0U)
/*! B_DPHYCTRL - ULPS EXIT Counter Value Control. You should set B_DPHYCTL[9:0] during initial or power-up sequence
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_MASK (0x400U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_SHIFT (10U)
/*! TXTRIGGER_CLK_EN - TxTrigger_Clk Enable
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_TXTRIGGER_CLK_EN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_MASK (0x800U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_SHIFT (11U)
/*! ERRCONTENTION_LP_EN - ErrContention LP Enable
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_ERRCONTENTION_LP_EN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_MASK (0x1000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_SHIFT (12U)
/*! BGR_CHOPPER_EN - BGR Chopper Function Enable
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_EN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_MASK (0x2000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_SHIFT (13U)
/*! LP_CD_HYS - LP-CD Hysteresis Level Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_CD_HYS_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_MASK (0x4000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_SHIFT (14U)
/*! MSTRCLK_LP_SLEW_RATE_UP - Master Clock Lane's LP-TX Driver Slew Rate Up Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_UP_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_MASK (0x18000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_SHIFT (15U)
/*! MSTRCLK_LP_SLEW_RATE_DOWN - Master Clock Lane's LP-TX Driver Slew Rate Down Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_MSTRCLK_LP_SLEW_RATE_DOWN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_MASK (0x20000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_SHIFT (17U)
/*! LP_RX_PULSE_REJECT - LP-RX Pulse Rejection Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_PULSE_REJECT_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_MASK (0xC0000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_SHIFT (18U)
/*! LP_RX_VREF_LVL - LP-RX Vref Level Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_VREF_LVL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_MASK (0x100000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_SHIFT (20U)
/*! VREF_SRC_SEL - Vref Source Selection
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREF_SRC_SEL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_MASK (0x600000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_SHIFT (21U)
/*! LP_RX_HYS_LVL - LP-RX Hysteresis Level Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_LP_RX_HYS_LVL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_MASK (0x800000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_SHIFT (23U)
/*! REG_1P2_LVL_SEL - 1.2V Regulator Valid Level Selection
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_SEL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_MASK (0x3000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_SHIFT (24U)
/*! REG_1P2_LVL_CTL - 1.2V Regulator Level Control (No regulator in JF)
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_REG_1P2_LVL_CTL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_MASK (0x4000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_SHIFT (26U)
/*! VREG12_EXTPWR_EN_CTL - VREG12_EXTPWR Enable Control (No regulator in JF)
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_VREG12_EXTPWR_EN_CTL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_MASK (0x8000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_SHIFT (27U)
/*! BGR_CHOPPER_FREQ - BGR Chopper Frequency Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BGR_CHOPPER_FREQ_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_MASK (0x30000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_SHIFT (28U)
/*! BIAS_REF_VOLT - Bias Reference Voltage 710m Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_BIAS_REF_VOLT_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_MASK (0xC0000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_SHIFT (30U)
/*! USER_DATA_PATTERN_LOW - User Data Pattern for HS Loopback mode
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_USER_DATA_PATTERN_LOW_MASK)
/*! @} */
/*! @name DPHY_MASTER_SLAVE_CTRL_HIGH - D-PHY Master and Slave Control register HIGH */
/*! @{ */
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_MASK (0x3FU)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_SHIFT (0U)
/*! USER_DATA_PATTERN_HIGH - User Data Pattern for HS Loopback mode
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_USER_DATA_PATTERN_HIGH_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_MASK (0xC0U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_SHIFT (6U)
/*! HS_LOOPBACK_MODE_CTL - HS Loopback Mode Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_HS_LOOPBACK_MODE_CTL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_MASK (0x300U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_SHIFT (8U)
/*! BGR_VOLT_TUNE - BGR voltage tuning control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_BGR_VOLT_TUNE_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_MASK (0x800U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_SHIFT (11U)
/*! DCC_DONE - DCC "DONE" Signal Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_DCC_DONE_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_MASK (0x2000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_SHIFT (13U)
/*! RX_SKEW_CALIB_FIX_EN - RX Skew Calibration Fixing Code Enable/Disable Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FIX_EN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_MASK (0x4000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_SHIFT (14U)
/*! LP_REG_VREF_SRC_SEL - LP Regulator Vref Source Selection (No regulator in JF)
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_LP_REG_VREF_SRC_SEL_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_MASK (0x100000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_SHIFT (20U)
/*! MST_DATA0_TX_SLEW_UP - Master Data0 Lane's LP-TX Driver Slew Rate Up Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_UP_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_MASK (0x600000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_SHIFT (21U)
/*! MST_DATA0_TX_SLEW_DOWN - Master Data0 Lane's LP-TX Driver Slew Rate Down Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA0_TX_SLEW_DOWN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_MASK (0x800000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_SHIFT (23U)
/*! MST_DATA1_TX_SLEW_UP - Master Data1 Lane's LP-TX Driver Slew Rate Up Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_UP_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_MASK (0x3000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_SHIFT (24U)
/*! MST_DATA1_TX_SLEW_DOWN - Master Data1 Lane's LP-TX Driver Slew Rate Down Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA1_TX_SLEW_DOWN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_MASK (0x4000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_SHIFT (26U)
/*! MST_DATA2_TX_SLEW_UP - Master Data2 Lane's LP-TX Driver Slew Rate Up Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_UP_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_MASK (0x18000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_SHIFT (27U)
/*! MST_DATA2_TX_SLEW_DOWN - Master Data2 Lane's LP-TX Driver Slew Rate Down Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA2_TX_SLEW_DOWN_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_MASK (0x20000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_SHIFT (29U)
/*! MST_DATA3_TX_SLEW_UP - Master Data3 Lane's LP-TX Driver Slew Rate Up Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_UP_MASK)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_MASK (0xC0000000U)
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_SHIFT (30U)
/*! MST_DATA3_TX_SLEW_DOWN - Master Data3 Lane's LP-TX Driver Slew Rate Down Control
*/
#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_SHIFT)) & MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_MST_DATA3_TX_SLEW_DOWN_MASK)
/*! @} */
/*! @name DPHY_SLAVE_CTRL_LOW - D-PHY Slave Control register Low */
/*! @{ */
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_MASK (0x3U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_SHIFT (0U)
/*! HS_RX_BIAS - HS RX Bias Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_BIAS_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_MASK (0xCU)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_SHIFT (2U)
/*! CLK_LANE_HS_RX_DELAY - Clock Lane HS RX Delay Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_LANE_HS_RX_DELAY_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_MASK (0x30U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_SHIFT (4U)
/*! DATA_LANE_HS_RX_DELAY - Data Lane HS RX Delay Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DATA_LANE_HS_RX_DELAY_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_MASK (0xC0U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_SHIFT (6U)
/*! HS_RX_TERMINATION_IMPEDENCE - HS-RX Termination Impedance Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_HS_RX_TERMINATION_IMPEDENCE_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_MASK (0x300U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_SHIFT (8U)
/*! CLOCK_LANE_CAP_TCLK_SETTLE - Clock Lane Cap. Value Control for Tclk-settle
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_SETTLE_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_MASK (0xC00U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_SHIFT (10U)
/*! CLOCK_LANE_CAP_TCLK_MISS - Clock Lane Cap. Value Control for Tclk_miss
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLOCK_LANE_CAP_TCLK_MISS_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_MASK (0x1000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_SHIFT (12U)
/*! CLK_MISS_EN - Clock Miss Function Enable/Disable Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_CLK_MISS_EN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_MASK (0x6000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_SHIFT (13U)
/*! ANA_TIMER_HYS - Analog Timer Hysteresis Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_ANA_TIMER_HYS_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_MASK (0x30000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_SHIFT (16U)
/*! DCC_CCO_GAIN - DCC CCO Gain Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_CCO_GAIN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_MASK (0x70000000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_SHIFT (28U)
/*! DCC_INIT_TOLERANCE - DCC Initial Tolerance
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_INIT_TOLERANCE_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_MASK (0x80000000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_SHIFT (31U)
/*! DCC_STABLE - DCC Stable Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_LOW_DCC_STABLE_MASK)
/*! @} */
/*! @name DPHY_SLAVE_CTRL_HIGH - D-PHY Slave Control register HIGH */
/*! @{ */
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_MASK (0x1U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_SHIFT (0U)
/*! DCC_EN - DCC Function Enable/Disable Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_DCC_EN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_MASK (0x2U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_SHIFT (1U)
/*! SKEW_CALIB_EN - Skew Calibration Function Enable/Disable Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_SKEW_CALIB_EN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_MASK (0xFCU)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_SHIFT (2U)
/*! RX_SKEW_CALIB_MAX - RX Skew Calibration Max Code Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_MAX_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_MASK (0x3F00U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_SHIFT (8U)
/*! RX_SKEW_CALIB_FAIL_MIN - RX Skew Calibration Fail-min Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_MIN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_MASK (0x3F0000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_SHIFT (16U)
/*! RX_SKEW_CALIB_PASS_MIN - RX Skew Calibration Pass-min Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_PASS_MIN_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_MASK (0x3000000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_SHIFT (24U)
/*! RX_SKEW_CALIB_FAIL_TOLERANCE - RX Skew Calibration Fail-tolerance Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_FAIL_TOLERANCE_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_MASK (0xC000000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_SHIFT (26U)
/*! RX_SKEW_CALIB_COMPARE_WAIT_TIME - RX Skew Calibration Compare-wait time Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_WAIT_TIME_MASK)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_MASK (0xF0000000U)
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_SHIFT (28U)
/*! RX_SKEW_CALIB_COMPARE_RUN_TIME - RX Skew Calibration Compare-run time Control
*/
#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_SHIFT)) & MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_RX_SKEW_CALIB_COMPARE_RUN_TIME_MASK)
/*! @} */
/*! @name ISP_CONFIG - ISP Configuration Register */
/*! @{ */
#define MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK (0xFCU)
#define MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT (2U)
/*! DATAFORMAT - Image Data Format
*/
#define MIPI_CSI_ISP_CONFIG_DATAFORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK)
#define MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK (0x400U)
#define MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT (10U)
/*! RGB_SWAP
* 0b0..MSB is R and LSB is B
* 0b1..MSB is B and LSB is R (swapped)
*/
#define MIPI_CSI_ISP_CONFIG_RGB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT)) & MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK)
#define MIPI_CSI_ISP_CONFIG_PARALLEL_MASK (0x800U)
#define MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT (11U)
/*! PARALLEL - Output bus width of CH0 is 32 bits.
* 0b0..Normal output
* 0b1..32bit data alignment
*/
#define MIPI_CSI_ISP_CONFIG_PARALLEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT)) & MIPI_CSI_ISP_CONFIG_PARALLEL_MASK)
#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK (0x3000U)
#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT (12U)
/*! PIXEL_MODE - Pixel mode selection,
*/
#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK)
/*! @} */
/*! @name ISP_RESOLUTION - ISP Resolution Register */
/*! @{ */
#define MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK (0xFFFFU)
#define MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT (0U)
/*! HRESOL - Horizontal Image resolution
*/
#define MIPI_CSI_ISP_RESOLUTION_HRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK)
#define MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK (0xFFFF0000U)
#define MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT (16U)
/*! VRESOL - Vertical Image resolution
*/
#define MIPI_CSI_ISP_RESOLUTION_VRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK)
/*! @} */
/*! @name ISP_SYNC - ISP SYNC Register */
/*! @{ */
#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK (0xFC0000U)
#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT (18U)
#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT)) & MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK)
/*! @} */
/*! @name SHADOW_CONFIG - Shadow Configuration Register */
/*! @{ */
#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK (0xFCU)
#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT (2U)
#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK)
#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK (0x400U)
#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT (10U)
#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK)
#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK (0x800U)
#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT (11U)
#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK)
#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK (0x3000U)
#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT (12U)
#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK)
/*! @} */
/*! @name SHADOW_RESOLUTION - Shadow Resolution Register */
/*! @{ */
#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK (0xFFFFU)
#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT (0U)
#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT)) & MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK)
#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK (0xFFFF0000U)
#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT (16U)
#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT)) & MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK)
/*! @} */
/*! @name SHADOW_SYNC - Shadow SYNC Register */
/*! @{ */
#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK (0xFC0000U)
#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT (18U)
#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT)) & MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK)
/*! @} */
/*! @name FRAME_COUNTER - Frame Counter */
/*! @{ */
#define MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK (0xFFFFFFFFU)
#define MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT (0U)
#define MIPI_CSI_FRAME_COUNTER_FRM_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT)) & MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK)
/*! @} */
/*! @name LINE_INTERRUPT_RATIO - Line Interrupt Ratio */
/*! @{ */
#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK (0xFFFFFFFFU)
#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT (0U)
#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT)) & MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MIPI_CSI_Register_Masks */
/* MIPI_CSI - Peripheral instance base addresses */
/** Peripheral MIPI_CSI1 base address */
#define MIPI_CSI1_BASE (0x32E40000u)
/** Peripheral MIPI_CSI1 base pointer */
#define MIPI_CSI1 ((MIPI_CSI_Type *)MIPI_CSI1_BASE)
/** Peripheral MIPI_CSI2 base address */
#define MIPI_CSI2_BASE (0x32E50000u)
/** Peripheral MIPI_CSI2 base pointer */
#define MIPI_CSI2 ((MIPI_CSI_Type *)MIPI_CSI2_BASE)
/** Array initializer of MIPI_CSI peripheral base addresses */
#define MIPI_CSI_BASE_ADDRS { MIPI_CSI1_BASE, MIPI_CSI2_BASE }
/** Array initializer of MIPI_CSI peripheral base pointers */
#define MIPI_CSI_BASE_PTRS { MIPI_CSI1, MIPI_CSI2 }
/*!
* @}
*/ /* end of group MIPI_CSI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MIPI_DSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer
* @{
*/
/** MIPI_DSI - Register Layout Typedef */
typedef struct {
__I uint32_t DSI_VERSION; /**< Specifies the DSI version register., offset: 0x0 */
__I uint32_t DSI_STATUS; /**< Specifies the status register., offset: 0x4 */
__I uint32_t DSI_RGB_STATUS; /**< Specifies the RGB FSM status register., offset: 0x8 */
__IO uint32_t DSI_SWRST; /**< Specifies the software reset register., offset: 0xC */
__IO uint32_t DSI_CLKCTRL; /**< Specifies the clock control register., offset: 0x10 */
__IO uint32_t DSI_TIMEOUT; /**< Specifies the time out register., offset: 0x14 */
__IO uint32_t DSI_CONFIG; /**< Specifies the configuration register., offset: 0x18 */
__IO uint32_t DSI_ESCMODE; /**< Specifies the escape mode register., offset: 0x1C */
__IO uint32_t DSI_MDRESOL; /**< Specifies the main display image resolution register., offset: 0x20 */
__IO uint32_t DSI_MVPORCH; /**< Specifies the main display Vporch register., offset: 0x24 */
__IO uint32_t DSI_MHPORCH; /**< Specifies the main display Hporch register., offset: 0x28 */
__IO uint32_t DSI_MSYNC; /**< Specifies the main display Sync Area register., offset: 0x2C */
__IO uint32_t DSI_SDRESOL; /**< Specifies the sub display image resolution register., offset: 0x30 */
__IO uint32_t DSI_INTSRC; /**< Specifies the interrupt source register., offset: 0x34 */
__IO uint32_t DSI_INTMSK; /**< Specifies the interrupt mask register., offset: 0x38 */
__O uint32_t DSI_PKTHDR; /**< Specifies the packet header FIFO register., offset: 0x3C */
__O uint32_t DSI_PAYLOAD; /**< Specifies the payload FIFO register., offset: 0x40 */
__I uint32_t DSI_RXFIFO; /**< Specifies the read FIFO register., offset: 0x44 */
__IO uint32_t DSI_FIFOTHLD; /**< Specifies the FIFO threshold level register., offset: 0x48 */
__IO uint32_t DSI_FIFOCTRL; /**< Specifies the FIFO status and control register., offset: 0x4C */
__IO uint32_t DSI_MEMACCHR; /**< Specifies the FIFO memory AC characteristic register., offset: 0x50 */
uint8_t RESERVED_0[36];
__IO uint32_t DSI_MULTI_PKT; /**< Specifies the Multi Packet, Packet Go register., offset: 0x78 */
uint8_t RESERVED_1[20];
__IO uint32_t DSI_PLLCTRL_1G; /**< Specifies the 1Gbps D-PHY PLL control register., offset: 0x90 */
__IO uint32_t DSI_PLLCTRL; /**< Specifies the PLL control register., offset: 0x94 */
__IO uint32_t DSI_PLLCTRL1; /**< Specifies the PLL control register 1., offset: 0x98 */
__IO uint32_t DSI_PLLCTRL2; /**< Specifies the PLL control register 2., offset: 0x9C */
__IO uint32_t DSI_PLLTMR; /**< Specifies the PLL timer register., offset: 0xA0 */
__IO uint32_t DSI_PHYCTRL_B1; /**< Specifies the D-PHY control register 1., offset: 0xA4 */
__IO uint32_t DSI_PHYCTRL_B2; /**< Specifies the D-PHY control register 2., offset: 0xA8 */
__IO uint32_t DSI_PHYCTRL_M1; /**< Specifies the D-PHY control register 1., offset: 0xAC */
__IO uint32_t DSI_PHYCTRL_M2; /**< Specifies the D-PHY control register 2., offset: 0xB0 */
__IO uint32_t DSI_PHYTIMING; /**< Specifies the D-PHY timing register., offset: 0xB4 */
__IO uint32_t DSI_PHYTIMING1; /**< Specifies the D-PHY timing register 1., offset: 0xB8 */
__IO uint32_t DSI_PHYTIMING2; /**< Specifies the D-PHY timing register 2., offset: 0xBC */
} MIPI_DSI_Type;
/* ----------------------------------------------------------------------------
-- MIPI_DSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks
* @{
*/
/*! @name DSI_VERSION - Specifies the DSI version register. */
/*! @{ */
#define MIPI_DSI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_VERSION_VERSION_SHIFT (0U)
#define MIPI_DSI_DSI_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_VERSION_VERSION_SHIFT)) & MIPI_DSI_DSI_VERSION_VERSION_MASK)
/*! @} */
/*! @name DSI_STATUS - Specifies the status register. */
/*! @{ */
#define MIPI_DSI_DSI_STATUS_STOPSTATEDAT_MASK (0xFU)
#define MIPI_DSI_DSI_STATUS_STOPSTATEDAT_SHIFT (0U)
#define MIPI_DSI_DSI_STATUS_STOPSTATEDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_DSI_DSI_STATUS_STOPSTATEDAT_MASK)
#define MIPI_DSI_DSI_STATUS_ULPSDAT_MASK (0xF0U)
#define MIPI_DSI_DSI_STATUS_ULPSDAT_SHIFT (4U)
#define MIPI_DSI_DSI_STATUS_ULPSDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_ULPSDAT_SHIFT)) & MIPI_DSI_DSI_STATUS_ULPSDAT_MASK)
#define MIPI_DSI_DSI_STATUS_STOPSTATECLK_MASK (0x100U)
#define MIPI_DSI_DSI_STATUS_STOPSTATECLK_SHIFT (8U)
#define MIPI_DSI_DSI_STATUS_STOPSTATECLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_STOPSTATECLK_SHIFT)) & MIPI_DSI_DSI_STATUS_STOPSTATECLK_MASK)
#define MIPI_DSI_DSI_STATUS_ULPSCLK_MASK (0x200U)
#define MIPI_DSI_DSI_STATUS_ULPSCLK_SHIFT (9U)
#define MIPI_DSI_DSI_STATUS_ULPSCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_ULPSCLK_SHIFT)) & MIPI_DSI_DSI_STATUS_ULPSCLK_MASK)
#define MIPI_DSI_DSI_STATUS_TXREADYHSCLK_MASK (0x400U)
#define MIPI_DSI_DSI_STATUS_TXREADYHSCLK_SHIFT (10U)
#define MIPI_DSI_DSI_STATUS_TXREADYHSCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_TXREADYHSCLK_SHIFT)) & MIPI_DSI_DSI_STATUS_TXREADYHSCLK_MASK)
#define MIPI_DSI_DSI_STATUS_DIRECTION_MASK (0x10000U)
#define MIPI_DSI_DSI_STATUS_DIRECTION_SHIFT (16U)
#define MIPI_DSI_DSI_STATUS_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_DIRECTION_SHIFT)) & MIPI_DSI_DSI_STATUS_DIRECTION_MASK)
#define MIPI_DSI_DSI_STATUS_SWRSTRLS_MASK (0x100000U)
#define MIPI_DSI_DSI_STATUS_SWRSTRLS_SHIFT (20U)
#define MIPI_DSI_DSI_STATUS_SWRSTRLS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_SWRSTRLS_SHIFT)) & MIPI_DSI_DSI_STATUS_SWRSTRLS_MASK)
#define MIPI_DSI_DSI_STATUS_PLLSTABLE_MASK (0x80000000U)
#define MIPI_DSI_DSI_STATUS_PLLSTABLE_SHIFT (31U)
#define MIPI_DSI_DSI_STATUS_PLLSTABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_PLLSTABLE_SHIFT)) & MIPI_DSI_DSI_STATUS_PLLSTABLE_MASK)
/*! @} */
/*! @name DSI_RGB_STATUS - Specifies the RGB FSM status register. */
/*! @{ */
#define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_MASK (0x1FFFU)
#define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_SHIFT (0U)
#define MIPI_DSI_DSI_RGB_STATUS_RGBSTATE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_RGBSTATE_MASK)
#define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK (0x80000000U)
#define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT (31U)
#define MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_CMDMODE_INSEL_MASK)
/*! @} */
/*! @name DSI_SWRST - Specifies the software reset register. */
/*! @{ */
#define MIPI_DSI_DSI_SWRST_SWRST_MASK (0x1U)
#define MIPI_DSI_DSI_SWRST_SWRST_SHIFT (0U)
#define MIPI_DSI_DSI_SWRST_SWRST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_SWRST_SHIFT)) & MIPI_DSI_DSI_SWRST_SWRST_MASK)
#define MIPI_DSI_DSI_SWRST_FUNCRST_MASK (0x10000U)
#define MIPI_DSI_DSI_SWRST_FUNCRST_SHIFT (16U)
#define MIPI_DSI_DSI_SWRST_FUNCRST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_FUNCRST_SHIFT)) & MIPI_DSI_DSI_SWRST_FUNCRST_MASK)
/*! @} */
/*! @name DSI_CLKCTRL - Specifies the clock control register. */
/*! @{ */
#define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_MASK (0xFFFFU)
#define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_SHIFT (0U)
#define MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ESCPRESCALER_MASK)
#define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_MASK (0xF80000U)
#define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT (19U)
#define MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_LANEESCCLKEN_MASK)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_MASK (0x1000000U)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_SHIFT (24U)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_BYTECLKEN_MASK)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_MASK (0x6000000U)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_SHIFT (25U)
#define MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_BYTECLKSRC_MASK)
#define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_MASK (0x8000000U)
#define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_SHIFT (27U)
#define MIPI_DSI_DSI_CLKCTRL_PLLBYPASS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_PLLBYPASS_MASK)
#define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_MASK (0x10000000U)
#define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_SHIFT (28U)
#define MIPI_DSI_DSI_CLKCTRL_ESCCLKEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ESCCLKEN_MASK)
#define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_MASK (0x20000000U)
#define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_SHIFT (29U)
#define MIPI_DSI_DSI_CLKCTRL_DPHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_DPHY_SEL_MASK)
#define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK (0x80000000U)
#define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT (31U)
#define MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_TXREQUESTHSCLK_MASK)
/*! @} */
/*! @name DSI_TIMEOUT - Specifies the time out register. */
/*! @{ */
#define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_MASK (0xFFFFU)
#define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_SHIFT (0U)
#define MIPI_DSI_DSI_TIMEOUT_LPDRTOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_LPDRTOUT_MASK)
#define MIPI_DSI_DSI_TIMEOUT_BTATOUT_MASK (0xFF0000U)
#define MIPI_DSI_DSI_TIMEOUT_BTATOUT_SHIFT (16U)
#define MIPI_DSI_DSI_TIMEOUT_BTATOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_BTATOUT_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_BTATOUT_MASK)
/*! @} */
/*! @name DSI_CONFIG - Specifies the configuration register. */
/*! @{ */
#define MIPI_DSI_DSI_CONFIG_LANEEN_MASK (0x1FU)
#define MIPI_DSI_DSI_CONFIG_LANEEN_SHIFT (0U)
#define MIPI_DSI_DSI_CONFIG_LANEEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_LANEEN_SHIFT)) & MIPI_DSI_DSI_CONFIG_LANEEN_MASK)
#define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_MASK (0x60U)
#define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_SHIFT (5U)
#define MIPI_DSI_DSI_CONFIG_NUMOFDATLANE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_SHIFT)) & MIPI_DSI_DSI_CONFIG_NUMOFDATLANE_MASK)
#define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_MASK (0x700U)
#define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_SHIFT (8U)
#define MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_SHIFT)) & MIPI_DSI_DSI_CONFIG_SUBPIXFORMAT_MASK)
#define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_MASK (0x7000U)
#define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_SHIFT (12U)
#define MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_SHIFT)) & MIPI_DSI_DSI_CONFIG_MAINPIXFORMAT_MASK)
#define MIPI_DSI_DSI_CONFIG_SUBVC_MASK (0x30000U)
#define MIPI_DSI_DSI_CONFIG_SUBVC_SHIFT (16U)
#define MIPI_DSI_DSI_CONFIG_SUBVC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SUBVC_SHIFT)) & MIPI_DSI_DSI_CONFIG_SUBVC_MASK)
#define MIPI_DSI_DSI_CONFIG_MAINVC_MASK (0xC0000U)
#define MIPI_DSI_DSI_CONFIG_MAINVC_SHIFT (18U)
#define MIPI_DSI_DSI_CONFIG_MAINVC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MAINVC_SHIFT)) & MIPI_DSI_DSI_CONFIG_MAINVC_MASK)
#define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_MASK (0x100000U)
#define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_SHIFT (20U)
#define MIPI_DSI_DSI_CONFIG_HSADISABLEMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HSADISABLEMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_MASK (0x200000U)
#define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_SHIFT (21U)
#define MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HBPDISABLEMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_MASK (0x400000U)
#define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_SHIFT (22U)
#define MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HFPDISABLEMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_MASK (0x800000U)
#define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_SHIFT (23U)
#define MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_HSEDISABLEMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_AUTOMODE_MASK (0x1000000U)
#define MIPI_DSI_DSI_CONFIG_AUTOMODE_SHIFT (24U)
#define MIPI_DSI_DSI_CONFIG_AUTOMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_AUTOMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_AUTOMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_VIDEOMODE_MASK (0x2000000U)
#define MIPI_DSI_DSI_CONFIG_VIDEOMODE_SHIFT (25U)
#define MIPI_DSI_DSI_CONFIG_VIDEOMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_VIDEOMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_VIDEOMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_BURSTMODE_MASK (0x4000000U)
#define MIPI_DSI_DSI_CONFIG_BURSTMODE_SHIFT (26U)
#define MIPI_DSI_DSI_CONFIG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_BURSTMODE_SHIFT)) & MIPI_DSI_DSI_CONFIG_BURSTMODE_MASK)
#define MIPI_DSI_DSI_CONFIG_SYNCINFORM_MASK (0x8000000U)
#define MIPI_DSI_DSI_CONFIG_SYNCINFORM_SHIFT (27U)
#define MIPI_DSI_DSI_CONFIG_SYNCINFORM(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SYNCINFORM_SHIFT)) & MIPI_DSI_DSI_CONFIG_SYNCINFORM_MASK)
#define MIPI_DSI_DSI_CONFIG_EOT_R03_MASK (0x10000000U)
#define MIPI_DSI_DSI_CONFIG_EOT_R03_SHIFT (28U)
#define MIPI_DSI_DSI_CONFIG_EOT_R03(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_EOT_R03_SHIFT)) & MIPI_DSI_DSI_CONFIG_EOT_R03_MASK)
#define MIPI_DSI_DSI_CONFIG_MFLUSH_VS_MASK (0x20000000U)
#define MIPI_DSI_DSI_CONFIG_MFLUSH_VS_SHIFT (29U)
#define MIPI_DSI_DSI_CONFIG_MFLUSH_VS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MFLUSH_VS_SHIFT)) & MIPI_DSI_DSI_CONFIG_MFLUSH_VS_MASK)
#define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_MASK (0x40000000U)
#define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT (30U)
#define MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_SHIFT)) & MIPI_DSI_DSI_CONFIG_CLKLANE_STOP_START_MASK)
#define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK (0x80000000U)
#define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT (31U)
#define MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_SHIFT)) & MIPI_DSI_DSI_CONFIG_NON_CONTINUOUS_CLOCK_LANE_MASK)
/*! @} */
/*! @name DSI_ESCMODE - Specifies the escape mode register. */
/*! @{ */
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_MASK (0x1U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT (0U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSCLKEXIT_MASK)
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLK_MASK (0x2U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLK_SHIFT (1U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSCLK_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSCLK_MASK)
#define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_MASK (0x4U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_SHIFT (2U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSEXIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSEXIT_MASK)
#define MIPI_DSI_DSI_ESCMODE_TXULPSDAT_MASK (0x8U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSDAT_SHIFT (3U)
#define MIPI_DSI_DSI_ESCMODE_TXULPSDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXULPSDAT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXULPSDAT_MASK)
#define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_MASK (0x10U)
#define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_SHIFT (4U)
#define MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXTRIGGERRST_MASK)
#define MIPI_DSI_DSI_ESCMODE_TXLPDT_MASK (0x40U)
#define MIPI_DSI_DSI_ESCMODE_TXLPDT_SHIFT (6U)
#define MIPI_DSI_DSI_ESCMODE_TXLPDT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TXLPDT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TXLPDT_MASK)
#define MIPI_DSI_DSI_ESCMODE_CMDLPDT_MASK (0x80U)
#define MIPI_DSI_DSI_ESCMODE_CMDLPDT_SHIFT (7U)
#define MIPI_DSI_DSI_ESCMODE_CMDLPDT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_CMDLPDT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_CMDLPDT_MASK)
#define MIPI_DSI_DSI_ESCMODE_FORCEBTA_MASK (0x10000U)
#define MIPI_DSI_DSI_ESCMODE_FORCEBTA_SHIFT (16U)
#define MIPI_DSI_DSI_ESCMODE_FORCEBTA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_FORCEBTA_SHIFT)) & MIPI_DSI_DSI_ESCMODE_FORCEBTA_MASK)
#define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__MASK (0x100000U)
#define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__SHIFT (20U)
#define MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE_(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__SHIFT)) & MIPI_DSI_DSI_ESCMODE_FORCESTOPSTATE__MASK)
#define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_MASK (0xFFE00000U)
#define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT (21U)
#define MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_SHIFT)) & MIPI_DSI_DSI_ESCMODE_STOPSTATE_CNT_MASK)
/*! @} */
/*! @name DSI_MDRESOL - Specifies the main display image resolution register. */
/*! @{ */
#define MIPI_DSI_DSI_MDRESOL_MAINHRESOL_MASK (0xFFFU)
#define MIPI_DSI_DSI_MDRESOL_MAINHRESOL_SHIFT (0U)
#define MIPI_DSI_DSI_MDRESOL_MAINHRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINHRESOL_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINHRESOL_MASK)
#define MIPI_DSI_DSI_MDRESOL_MAINVRESOL_MASK (0xFFF0000U)
#define MIPI_DSI_DSI_MDRESOL_MAINVRESOL_SHIFT (16U)
#define MIPI_DSI_DSI_MDRESOL_MAINVRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINVRESOL_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINVRESOL_MASK)
#define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_MASK (0x80000000U)
#define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_SHIFT (31U)
#define MIPI_DSI_DSI_MDRESOL_MAINSTANDBY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MAINSTANDBY_MASK)
/*! @} */
/*! @name DSI_MVPORCH - Specifies the main display Vporch register. */
/*! @{ */
#define MIPI_DSI_DSI_MVPORCH_MAINVBP_MASK (0x7FFU)
#define MIPI_DSI_DSI_MVPORCH_MAINVBP_SHIFT (0U)
#define MIPI_DSI_DSI_MVPORCH_MAINVBP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_MAINVBP_SHIFT)) & MIPI_DSI_DSI_MVPORCH_MAINVBP_MASK)
#define MIPI_DSI_DSI_MVPORCH_STABLEVFP_MASK (0x7FF0000U)
#define MIPI_DSI_DSI_MVPORCH_STABLEVFP_SHIFT (16U)
#define MIPI_DSI_DSI_MVPORCH_STABLEVFP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_STABLEVFP_SHIFT)) & MIPI_DSI_DSI_MVPORCH_STABLEVFP_MASK)
#define MIPI_DSI_DSI_MVPORCH_CMDALLOW_MASK (0xF0000000U)
#define MIPI_DSI_DSI_MVPORCH_CMDALLOW_SHIFT (28U)
#define MIPI_DSI_DSI_MVPORCH_CMDALLOW(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_CMDALLOW_SHIFT)) & MIPI_DSI_DSI_MVPORCH_CMDALLOW_MASK)
/*! @} */
/*! @name DSI_MHPORCH - Specifies the main display Hporch register. */
/*! @{ */
#define MIPI_DSI_DSI_MHPORCH_MAINHBP_MASK (0xFFFFU)
#define MIPI_DSI_DSI_MHPORCH_MAINHBP_SHIFT (0U)
#define MIPI_DSI_DSI_MHPORCH_MAINHBP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MAINHBP_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MAINHBP_MASK)
#define MIPI_DSI_DSI_MHPORCH_MAINHFP_MASK (0xFFFF0000U)
#define MIPI_DSI_DSI_MHPORCH_MAINHFP_SHIFT (16U)
#define MIPI_DSI_DSI_MHPORCH_MAINHFP(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MAINHFP_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MAINHFP_MASK)
/*! @} */
/*! @name DSI_MSYNC - Specifies the main display Sync Area register. */
/*! @{ */
#define MIPI_DSI_DSI_MSYNC_MAINHSA_MASK (0xFFFFU)
#define MIPI_DSI_DSI_MSYNC_MAINHSA_SHIFT (0U)
#define MIPI_DSI_DSI_MSYNC_MAINHSA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MAINHSA_SHIFT)) & MIPI_DSI_DSI_MSYNC_MAINHSA_MASK)
#define MIPI_DSI_DSI_MSYNC_MAINVSA_MASK (0xFFC00000U)
#define MIPI_DSI_DSI_MSYNC_MAINVSA_SHIFT (22U)
#define MIPI_DSI_DSI_MSYNC_MAINVSA(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MAINVSA_SHIFT)) & MIPI_DSI_DSI_MSYNC_MAINVSA_MASK)
/*! @} */
/*! @name DSI_SDRESOL - Specifies the sub display image resolution register. */
/*! @{ */
#define MIPI_DSI_DSI_SDRESOL_SUBHRESOL_MASK (0x7FFU)
#define MIPI_DSI_DSI_SDRESOL_SUBHRESOL_SHIFT (0U)
#define MIPI_DSI_DSI_SDRESOL_SUBHRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBHRESOL_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBHRESOL_MASK)
#define MIPI_DSI_DSI_SDRESOL_SUBVRESOL_MASK (0x7FF0000U)
#define MIPI_DSI_DSI_SDRESOL_SUBVRESOL_SHIFT (16U)
#define MIPI_DSI_DSI_SDRESOL_SUBVRESOL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBVRESOL_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBVRESOL_MASK)
#define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_MASK (0x80000000U)
#define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_SHIFT (31U)
#define MIPI_DSI_DSI_SDRESOL_SUBSTANDBY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SUBSTANDBY_MASK)
/*! @} */
/*! @name DSI_INTSRC - Specifies the interrupt source register. */
/*! @{ */
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_MASK (0x1U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_SHIFT (0U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTENTLP1_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_MASK (0x2U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_SHIFT (1U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTENTLP0_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL0_MASK (0x4U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL0_SHIFT (2U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL0_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL1_MASK (0x8U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL1_SHIFT (3U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL1_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL2_MASK (0x10U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL2_SHIFT (4U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL2_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL3_MASK (0x20U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL3_SHIFT (5U)
#define MIPI_DSI_DSI_INTSRC_ERRCONTROL3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRCONTROL3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRCONTROL3_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC0_MASK (0x40U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC0_SHIFT (6U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC0_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC1_MASK (0x80U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC1_SHIFT (7U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC1_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC2_MASK (0x100U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC2_SHIFT (8U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC2_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC3_MASK (0x200U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC3_SHIFT (9U)
#define MIPI_DSI_DSI_INTSRC_ERRSYNC3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRSYNC3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRSYNC3_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRESC0_MASK (0x400U)
#define MIPI_DSI_DSI_INTSRC_ERRESC0_SHIFT (10U)
#define MIPI_DSI_DSI_INTSRC_ERRESC0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC0_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRESC1_MASK (0x800U)
#define MIPI_DSI_DSI_INTSRC_ERRESC1_SHIFT (11U)
#define MIPI_DSI_DSI_INTSRC_ERRESC1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC1_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRESC2_MASK (0x1000U)
#define MIPI_DSI_DSI_INTSRC_ERRESC2_SHIFT (12U)
#define MIPI_DSI_DSI_INTSRC_ERRESC2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC2_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRESC3_MASK (0x2000U)
#define MIPI_DSI_DSI_INTSRC_ERRESC3_SHIFT (13U)
#define MIPI_DSI_DSI_INTSRC_ERRESC3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRESC3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRESC3_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRRXCRC_MASK (0x4000U)
#define MIPI_DSI_DSI_INTSRC_ERRRXCRC_SHIFT (14U)
#define MIPI_DSI_DSI_INTSRC_ERRRXCRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRRXCRC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRRXCRC_MASK)
#define MIPI_DSI_DSI_INTSRC_ERRRXECC_MASK (0x8000U)
#define MIPI_DSI_DSI_INTSRC_ERRRXECC_SHIFT (15U)
#define MIPI_DSI_DSI_INTSRC_ERRRXECC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ERRRXECC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ERRRXECC_MASK)
#define MIPI_DSI_DSI_INTSRC_RXACK_MASK (0x10000U)
#define MIPI_DSI_DSI_INTSRC_RXACK_SHIFT (16U)
#define MIPI_DSI_DSI_INTSRC_RXACK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXACK_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXACK_MASK)
#define MIPI_DSI_DSI_INTSRC_RXTE_MASK (0x20000U)
#define MIPI_DSI_DSI_INTSRC_RXTE_SHIFT (17U)
#define MIPI_DSI_DSI_INTSRC_RXTE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXTE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXTE_MASK)
#define MIPI_DSI_DSI_INTSRC_RXDATDONE_MASK (0x40000U)
#define MIPI_DSI_DSI_INTSRC_RXDATDONE_SHIFT (18U)
#define MIPI_DSI_DSI_INTSRC_RXDATDONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RXDATDONE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RXDATDONE_MASK)
#define MIPI_DSI_DSI_INTSRC_TATOUT_MASK (0x100000U)
#define MIPI_DSI_DSI_INTSRC_TATOUT_SHIFT (20U)
#define MIPI_DSI_DSI_INTSRC_TATOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_TATOUT_SHIFT)) & MIPI_DSI_DSI_INTSRC_TATOUT_MASK)
#define MIPI_DSI_DSI_INTSRC_LPDRTOUT_MASK (0x200000U)
#define MIPI_DSI_DSI_INTSRC_LPDRTOUT_SHIFT (21U)
#define MIPI_DSI_DSI_INTSRC_LPDRTOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_LPDRTOUT_SHIFT)) & MIPI_DSI_DSI_INTSRC_LPDRTOUT_MASK)
#define MIPI_DSI_DSI_INTSRC_FRAMEDONE_MASK (0x1000000U)
#define MIPI_DSI_DSI_INTSRC_FRAMEDONE_SHIFT (24U)
#define MIPI_DSI_DSI_INTSRC_FRAMEDONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_FRAMEDONE_SHIFT)) & MIPI_DSI_DSI_INTSRC_FRAMEDONE_MASK)
#define MIPI_DSI_DSI_INTSRC_BUSTURNOVER_MASK (0x2000000U)
#define MIPI_DSI_DSI_INTSRC_BUSTURNOVER_SHIFT (25U)
#define MIPI_DSI_DSI_INTSRC_BUSTURNOVER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_BUSTURNOVER_SHIFT)) & MIPI_DSI_DSI_INTSRC_BUSTURNOVER_MASK)
#define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_MASK (0x8000000U)
#define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_SHIFT (27U)
#define MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_SHIFT)) & MIPI_DSI_DSI_INTSRC_SYNCOVERRIDE_MASK)
#define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK (0x10000000U)
#define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT (28U)
#define MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTSRC_SFRPHFIFOEMPTY_MASK)
#define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK (0x20000000U)
#define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT (29U)
#define MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTSRC_SFRPLFIFOEMPTY_MASK)
#define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_MASK (0x40000000U)
#define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_SHIFT (30U)
#define MIPI_DSI_DSI_INTSRC_SWRSTRELEASE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_SHIFT)) & MIPI_DSI_DSI_INTSRC_SWRSTRELEASE_MASK)
#define MIPI_DSI_DSI_INTSRC_PLLSTABLE_MASK (0x80000000U)
#define MIPI_DSI_DSI_INTSRC_PLLSTABLE_SHIFT (31U)
#define MIPI_DSI_DSI_INTSRC_PLLSTABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_PLLSTABLE_SHIFT)) & MIPI_DSI_DSI_INTSRC_PLLSTABLE_MASK)
/*! @} */
/*! @name DSI_INTMSK - Specifies the interrupt mask register. */
/*! @{ */
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_MASK (0x1U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_SHIFT (0U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTENTLP1_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_MASK (0x2U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_SHIFT (1U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTENTLP0_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL0_MASK (0x4U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL0_SHIFT (2U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL0_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL1_MASK (0x8U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL1_SHIFT (3U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL1_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL2_MASK (0x10U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL2_SHIFT (4U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL2_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL3_MASK (0x20U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL3_SHIFT (5U)
#define MIPI_DSI_DSI_INTMSK_MSKCONTROL3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKCONTROL3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKCONTROL3_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC0_MASK (0x40U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC0_SHIFT (6U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC0_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC1_MASK (0x80U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC1_SHIFT (7U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC1_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC2_MASK (0x100U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC2_SHIFT (8U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC2_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC3_MASK (0x200U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC3_SHIFT (9U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNC3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNC3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNC3_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKESC0_MASK (0x400U)
#define MIPI_DSI_DSI_INTMSK_MSKESC0_SHIFT (10U)
#define MIPI_DSI_DSI_INTMSK_MSKESC0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC0_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKESC1_MASK (0x800U)
#define MIPI_DSI_DSI_INTMSK_MSKESC1_SHIFT (11U)
#define MIPI_DSI_DSI_INTMSK_MSKESC1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC1_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKESC2_MASK (0x1000U)
#define MIPI_DSI_DSI_INTMSK_MSKESC2_SHIFT (12U)
#define MIPI_DSI_DSI_INTMSK_MSKESC2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC2_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKESC3_MASK (0x2000U)
#define MIPI_DSI_DSI_INTMSK_MSKESC3_SHIFT (13U)
#define MIPI_DSI_DSI_INTMSK_MSKESC3(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKESC3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKESC3_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKRXCRC_MASK (0x4000U)
#define MIPI_DSI_DSI_INTMSK_MSKRXCRC_SHIFT (14U)
#define MIPI_DSI_DSI_INTMSK_MSKRXCRC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXCRC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXCRC_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKRXECC_MASK (0x8000U)
#define MIPI_DSI_DSI_INTMSK_MSKRXECC_SHIFT (15U)
#define MIPI_DSI_DSI_INTMSK_MSKRXECC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXECC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXECC_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKRXACK_MASK (0x10000U)
#define MIPI_DSI_DSI_INTMSK_MSKRXACK_SHIFT (16U)
#define MIPI_DSI_DSI_INTMSK_MSKRXACK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXACK_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXACK_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKRXTE_MASK (0x20000U)
#define MIPI_DSI_DSI_INTMSK_MSKRXTE_SHIFT (17U)
#define MIPI_DSI_DSI_INTMSK_MSKRXTE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXTE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXTE_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_MASK (0x40000U)
#define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_SHIFT (18U)
#define MIPI_DSI_DSI_INTMSK_MSKRXDATDONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKRXDATDONE_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKTATOUT_MASK (0x100000U)
#define MIPI_DSI_DSI_INTMSK_MSKTATOUT_SHIFT (20U)
#define MIPI_DSI_DSI_INTMSK_MSKTATOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKTATOUT_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKTATOUT_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_MASK (0x200000U)
#define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_SHIFT (21U)
#define MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKLPDRTOUT_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_MASK (0x1000000U)
#define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_SHIFT (24U)
#define MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKFRAMEDONE_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_MASK (0x2000000U)
#define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT (25U)
#define MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKBUSTURNOVER_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK (0x8000000U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT (27U)
#define MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSYNCOVERRIDE_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK (0x10000000U)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT (28U)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSFRPHFIFOEMPTY_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK (0x20000000U)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT (29U)
#define MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSFRPLFIFOEMPTY_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_MASK (0x40000000U)
#define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT (30U)
#define MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKSWRSTRELEASE_MASK)
#define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_MASK (0x80000000U)
#define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_SHIFT (31U)
#define MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MSKPLLSTABLE_MASK)
/*! @} */
/*! @name DSI_PKTHDR - Specifies the packet header FIFO register. */
/*! @{ */
#define MIPI_DSI_DSI_PKTHDR_PACKETHEADER_MASK (0xFFFFFFU)
#define MIPI_DSI_DSI_PKTHDR_PACKETHEADER_SHIFT (0U)
#define MIPI_DSI_DSI_PKTHDR_PACKETHEADER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PKTHDR_PACKETHEADER_SHIFT)) & MIPI_DSI_DSI_PKTHDR_PACKETHEADER_MASK)
/*! @} */
/*! @name DSI_PAYLOAD - Specifies the payload FIFO register. */
/*! @{ */
#define MIPI_DSI_DSI_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PAYLOAD_PAYLOAD_SHIFT (0U)
#define MIPI_DSI_DSI_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PAYLOAD_PAYLOAD_SHIFT)) & MIPI_DSI_DSI_PAYLOAD_PAYLOAD_MASK)
/*! @} */
/*! @name DSI_RXFIFO - Specifies the read FIFO register. */
/*! @{ */
#define MIPI_DSI_DSI_RXFIFO_RXDAT_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_RXFIFO_RXDAT_SHIFT (0U)
#define MIPI_DSI_DSI_RXFIFO_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RXFIFO_RXDAT_SHIFT)) & MIPI_DSI_DSI_RXFIFO_RXDAT_MASK)
/*! @} */
/*! @name DSI_FIFOTHLD - Specifies the FIFO threshold level register. */
/*! @{ */
#define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK (0x1FFU)
#define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT (0U)
#define MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_SHIFT)) & MIPI_DSI_DSI_FIFOTHLD_WFULLLEVELSFR_MASK)
/*! @} */
/*! @name DSI_FIFOCTRL - Specifies the FIFO status and control register. */
/*! @{ */
#define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_MASK (0x1U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_SHIFT (0U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITMAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITMAIN_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSUB_MASK (0x2U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSUB_SHIFT (1U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSUB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITSUB_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_NINITI80_MASK (0x4U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITI80_SHIFT (2U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITI80(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITI80_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSFR_MASK (0x8U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSFR_SHIFT (3U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITSFR_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_NINITRX_MASK (0x10U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITRX_SHIFT (4U)
#define MIPI_DSI_DSI_FIFOCTRL_NINITRX(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_NINITRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_NINITRX_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_MASK (0x100U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT (8U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLMAIN_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_MASK (0x200U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_SHIFT (9U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLMAIN_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_MASK (0x400U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT (10U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHMAIN_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_MASK (0x800U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_SHIFT (11U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHMAIN_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_MASK (0x1000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT (12U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLSUB_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_MASK (0x2000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_SHIFT (13U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSUB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLSUB_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_MASK (0x4000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT (14U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHSUB_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_MASK (0x8000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_SHIFT (15U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSUB(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHSUB_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_MASK (0x10000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_SHIFT (16U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLI80_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLI80_MASK (0x20000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLI80_SHIFT (17U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLI80(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLI80_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_MASK (0x40000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_SHIFT (18U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHI80_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHI80_MASK (0x80000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHI80_SHIFT (19U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHI80(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHI80_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_MASK (0x100000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT (20U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYLSFR_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_MASK (0x200000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_SHIFT (21U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLLSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLLSFR_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_MASK (0x400000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT (22U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYHSFR_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_MASK (0x800000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_SHIFT (23U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLHSFR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLHSFR_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_MASK (0x1000000U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_SHIFT (24U)
#define MIPI_DSI_DSI_FIFOCTRL_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EMPTYRX_MASK)
#define MIPI_DSI_DSI_FIFOCTRL_FULLRX_MASK (0x2000000U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLRX_SHIFT (25U)
#define MIPI_DSI_DSI_FIFOCTRL_FULLRX(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FULLRX_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FULLRX_MASK)
/*! @} */
/*! @name DSI_MEMACCHR - Specifies the FIFO memory AC characteristic register. */
/*! @{ */
#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK (0x7U)
#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT (0U)
#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK (0x38U)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT (3U)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK (0x40U)
#define MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT (6U)
#define MIPI_DSI_DSI_MEMACCHR_RETN_MD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK (0x80U)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT (7U)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK (0x700U)
#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT (8U)
#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK (0x3800U)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT (11U)
#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK (0x4000U)
#define MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT (14U)
#define MIPI_DSI_DSI_MEMACCHR_RETN_SD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK (0x8000U)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT (15U)
#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK)
/*! @} */
/*! @name DSI_MULTI_PKT - Specifies the Multi Packet, Packet Go register. */
/*! @{ */
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK (0xFFFFU)
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT (0U)
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_CNT_REF_MASK)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK (0xFFF0000U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT (16U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_SEND_CNT_REF_MASK)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_MASK (0x10000000U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT (28U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_GO_RDY_MASK)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_MASK (0x20000000U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT (29U)
#define MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_GO_EN_MASK)
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK (0x40000000U)
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT (30U)
#define MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_MULTI_PKT_EN_MASK)
/*! @} */
/*! @name DSI_PLLCTRL_1G - Specifies the 1Gbps D-PHY PLL control register. */
/*! @{ */
#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK (0x7U)
#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT (0U)
#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PRPRCTLCLK_MASK)
#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_MASK (0x70U)
#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT (4U)
#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PREPRCTL_MASK)
#define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_MASK (0xF00U)
#define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT (8U)
#define MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_FREQ_BAND_MASK)
#define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_MASK (0xF000U)
#define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT (12U)
#define MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_HSZEROCTL_MASK)
/*! @} */
/*! @name DSI_PLLCTRL - Specifies the PLL control register. */
/*! @{ */
#define MIPI_DSI_DSI_PLLCTRL_PMS_MASK (0xFFFFEU)
#define MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT (1U)
#define MIPI_DSI_DSI_PLLCTRL_PMS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PMS_MASK)
#define MIPI_DSI_DSI_PLLCTRL_PLLEN_MASK (0x800000U)
#define MIPI_DSI_DSI_PLLCTRL_PLLEN_SHIFT (23U)
#define MIPI_DSI_DSI_PLLCTRL_PLLEN(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PLLEN_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PLLEN_MASK)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK (0x1000000U)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT (24U)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_DAT_MASK)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK (0x2000000U)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT (25U)
#define MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DPDNSWAP_CLK_MASK)
/*! @} */
/*! @name DSI_PLLCTRL1 - Specifies the PLL control register 1. */
/*! @{ */
#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT (0U)
#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT)) & MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK)
/*! @} */
/*! @name DSI_PLLCTRL2 - Specifies the PLL control register 2. */
/*! @{ */
#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK (0xFFU)
#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT (0U)
#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT)) & MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK)
/*! @} */
/*! @name DSI_PLLTMR - Specifies the PLL timer register. */
/*! @{ */
#define MIPI_DSI_DSI_PLLTMR_PLLTIMER_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PLLTMR_PLLTIMER_SHIFT (0U)
#define MIPI_DSI_DSI_PLLTMR_PLLTIMER(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLTMR_PLLTIMER_SHIFT)) & MIPI_DSI_DSI_PLLTMR_PLLTIMER_MASK)
/*! @} */
/*! @name DSI_PHYCTRL_B1 - Specifies the D-PHY control register 1. */
/*! @{ */
#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT (0U)
#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK)
/*! @} */
/*! @name DSI_PHYCTRL_B2 - Specifies the D-PHY control register 2. */
/*! @{ */
#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT (0U)
#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK)
/*! @} */
/*! @name DSI_PHYCTRL_M1 - Specifies the D-PHY control register 1. */
/*! @{ */
#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT (0U)
#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK)
/*! @} */
/*! @name DSI_PHYCTRL_M2 - Specifies the D-PHY control register 2. */
/*! @{ */
#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK (0xFFFFFFFFU)
#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT (0U)
#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT)) & MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK)
/*! @} */
/*! @name DSI_PHYTIMING - Specifies the D-PHY timing register. */
/*! @{ */
#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK (0xFFU)
#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT (0U)
#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK (0xFF00U)
#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT (8U)
#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK)
/*! @} */
/*! @name DSI_PHYTIMING1 - Specifies the D-PHY timing register 1. */
/*! @{ */
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK (0xFFU)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT (0U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK (0xFF00U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT (8U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK (0xFF0000U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT (16U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK (0xFF000000U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT (24U)
#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK)
/*! @} */
/*! @name DSI_PHYTIMING2 - Specifies the D-PHY timing register 2. */
/*! @{ */
#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK (0xFFU)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT (0U)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK (0xFF00U)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT (8U)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK (0xFF0000U)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT (16U)
#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MIPI_DSI_Register_Masks */
/* MIPI_DSI - Peripheral instance base addresses */
/** Peripheral MIPI_DSI base address */
#define MIPI_DSI_BASE (0x32E10000u)
/** Peripheral MIPI_DSI base pointer */
#define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE)
/** Array initializer of MIPI_DSI peripheral base addresses */
#define MIPI_DSI_BASE_ADDRS { MIPI_DSI_BASE }
/** Array initializer of MIPI_DSI peripheral base pointers */
#define MIPI_DSI_BASE_PTRS { MIPI_DSI }
/*!
* @}
*/ /* end of group MIPI_DSI_Peripheral_Access_Layer */
/*!
* @brief Power mode on the other side definition.
*/
typedef enum _mu_power_mode
{
kMU_PowerModeRun = 0x00U, /*!< Run mode. */
kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */
kMU_PowerModeStop = 0x03U, /*!< STOP mode. */
} mu_power_mode_t;
/* ----------------------------------------------------------------------------
-- MU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
* @{
*/
/** MU - Register Layout Typedef */
typedef struct {
__IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array step: 0x4 */
__I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array step: 0x4 */
__IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */
__IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */
} MU_Type;
/* ----------------------------------------------------------------------------
-- MU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Register_Masks MU Register Masks
* @{
*/
/*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
/*! @{ */
#define MU_TR_BTR0_MASK (0xFFFFFFFFU)
#define MU_TR_BTR0_SHIFT (0U)
#define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK)
#define MU_TR_BTR1_MASK (0xFFFFFFFFU)
#define MU_TR_BTR1_SHIFT (0U)
#define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK)
#define MU_TR_BTR2_MASK (0xFFFFFFFFU)
#define MU_TR_BTR2_SHIFT (0U)
#define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
#define MU_TR_BTR3_MASK (0xFFFFFFFFU)
#define MU_TR_BTR3_SHIFT (0U)
#define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK)
/*! @} */
/* The count of MU_TR */
#define MU_TR_COUNT (4U)
/*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
/*! @{ */
#define MU_RR_BRR0_MASK (0xFFFFFFFFU)
#define MU_RR_BRR0_SHIFT (0U)
#define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK)
#define MU_RR_BRR1_MASK (0xFFFFFFFFU)
#define MU_RR_BRR1_SHIFT (0U)
#define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK)
#define MU_RR_BRR2_MASK (0xFFFFFFFFU)
#define MU_RR_BRR2_SHIFT (0U)
#define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK)
#define MU_RR_BRR3_MASK (0xFFFFFFFFU)
#define MU_RR_BRR3_SHIFT (0U)
#define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK)
/*! @} */
/* The count of MU_RR */
#define MU_RR_COUNT (4U)
/*! @name SR - Processor B Status Register */
/*! @{ */
#define MU_SR_Fn_MASK (0x7U)
#define MU_SR_Fn_SHIFT (0U)
/*! Fn
* 0b000..ABFn bit in ACR register is written 0 (default).
* 0b001..ABFn bit in ACR register is written 1.
*/
#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
#define MU_SR_EP_MASK (0x10U)
#define MU_SR_EP_SHIFT (4U)
/*! EP
* 0b0..The Processor B-side event is not pending (default).
* 0b1..The Processor B-side event is pending.
*/
#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
#define MU_SR_APM_MASK (0x60U)
#define MU_SR_APM_SHIFT (5U)
/*! APM
* 0b00..The System is in Run Mode.
* 0b01..The System is in WAIT Mode.
* 0b10..Reserved.
* 0b11..The System is in STOP Mode.
*/
#define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK)
#define MU_SR_ARS_MASK (0x80U)
#define MU_SR_ARS_SHIFT (7U)
/*! ARS
* 0b0..The Processor A or the Processor A-side of the MU is not in reset.
* 0b1..The Processor A or the Processor A-side of the MU is in reset.
*/
#define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK)
#define MU_SR_FUP_MASK (0x100U)
#define MU_SR_FUP_SHIFT (8U)
/*! FUP
* 0b0..No flags updated, initiated by the Processor B, in progress (default)
* 0b1..Processor B initiated flags update, processing
*/
#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
#define MU_SR_TEn_MASK (0xF00000U)
#define MU_SR_TEn_SHIFT (20U)
/*! TEn
* 0b0000..BTRn register is not empty.
* 0b0001..BTRn register is empty (default).
*/
#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
#define MU_SR_RFn_MASK (0xF000000U)
#define MU_SR_RFn_SHIFT (24U)
/*! RFn
* 0b0000..BRRn register is not full (default).
* 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B.
*/
#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
#define MU_SR_GIPn_MASK (0xF0000000U)
#define MU_SR_GIPn_SHIFT (28U)
/*! GIPn
* 0b0000..Processor B general purpose interrupt n is not pending. (default)
* 0b0001..Processor B general purpose interrupt n is pending.
*/
#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
/*! @} */
/*! @name CR - Processor B Control Register */
/*! @{ */
#define MU_CR_BAFn_MASK (0x7U)
#define MU_CR_BAFn_SHIFT (0U)
/*! BAFn
* 0b000..Clears the Fn bit in the ASR register.
* 0b001..Sets the Fn bit in the ASR register.
*/
#define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK)
#define MU_CR_HRM_MASK (0x10U)
#define MU_CR_HRM_SHIFT (4U)
/*! HRM
* 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
* 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
*/
#define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK)
#define MU_CR_GIRn_MASK (0xF0000U)
#define MU_CR_GIRn_SHIFT (16U)
/*! GIRn
* 0b0000..Processor B General Interrupt n is not requested to the Processor A (default).
* 0b0001..Processor B General Interrupt n is requested to the Processor A.
*/
#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
#define MU_CR_TIEn_MASK (0xF00000U)
#define MU_CR_TIEn_SHIFT (20U)
/*! TIEn
* 0b0000..Disables Processor B Transmit Interrupt n. (default)
* 0b0001..Enables Processor B Transmit Interrupt n.
*/
#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
#define MU_CR_RIEn_MASK (0xF000000U)
#define MU_CR_RIEn_SHIFT (24U)
/*! RIEn
* 0b0000..Disables Processor B Receive Interrupt n. (default)
* 0b0001..Enables Processor B Receive Interrupt n.
*/
#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
#define MU_CR_GIEn_MASK (0xF0000000U)
#define MU_CR_GIEn_SHIFT (28U)
/*! GIEn
* 0b0000..Disables Processor B General Interrupt n. (default)
* 0b0001..Enables Processor B General Interrupt n.
*/
#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MU_Register_Masks */
/* MU - Peripheral instance base addresses */
/** Peripheral MUB base address */
#define MUB_BASE (0x30AB0000u)
/** Peripheral MUB base pointer */
#define MUB ((MU_Type *)MUB_BASE)
/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS { MUB_BASE }
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS { MUB }
/** Interrupt vectors for the MU peripheral type */
#define MU_IRQS { MU1_M7_IRQn }
/* Backward compatibility */
#define MU_SR_PM_MASK MU_SR_APM_MASK
#define MU_SR_PM_SHIFT MU_SR_APM_SHIFT
#define MU_SR_PM(x) MU_SR_APM(x)
#define MU_SR_RS_MASK MU_SR_ARS_MASK
#define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT
#define MU_SR_RS(x) MU_SR_ARS(x)
#define MU_CR_Fn_MASK MU_CR_BAFn_MASK
#define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT
#define MU_CR_Fn(x) MU_CR_BAFn(x)
/*!
* @}
*/ /* end of group MU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- NPU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup NPU_Peripheral_Access_Layer NPU Peripheral Access Layer
* @{
*/
/** NPU - Register Layout Typedef */
typedef struct {
__IO uint32_t AQHICLOCKCONTROL; /**< Clock Control Register, offset: 0x0 */
__I uint32_t AQHIIDLE; /**< Idle Status Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__I uint32_t AQAXISTATUS; /**< AXI Status Register, offset: 0xC */
__I uint32_t AQINTRACKNOWLEDGE; /**< Interrupt Acknowledge Register, offset: 0x10 */
__IO uint32_t AQINTRENBL; /**< Interrupt Enable Register, offset: 0x14 */
uint8_t RESERVED_1[96];
__IO uint32_t GCTOTALCYCLES; /**< Total Cycles Register, offset: 0x78 */
uint8_t RESERVED_2[132];
__IO uint32_t GCMODULEPOWERCONTROLS; /**< Module Power Level Control Register, offset: 0x100 */
uint8_t RESERVED_3[8];
__IO uint32_t GCPULSEEATER; /**< Pulse eater Control Register, offset: 0x10C */
uint8_t RESERVED_4[632];
__IO uint32_t GCREGMMUAHBCONTROL; /**< MMU Control Register, offset: 0x388 */
__IO uint32_t GCREGMMUAHBTABLEARRAYBASEADDRESSLOW; /**< MMU Table Array Base Lower 32-bit Address Register, offset: 0x38C */
__IO uint32_t GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH; /**< MMU Table Array Base Higher 32-bit Address Register, offset: 0x390 */
__IO uint32_t GCREGMMUAHBTABLEARRAYSIZE; /**< MMU Table Array Size Control Register, offset: 0x394 */
__IO uint32_t GCREGMMUAHBSAFENONSECUREADDRESS; /**< MMU NonSecure Address Register, offset: 0x398 */
__IO uint32_t GCREGMMUAHBSAFESECUREADDRESS; /**< MMU Secure Address Register, offset: 0x39C */
uint8_t RESERVED_5[4];
__O uint32_t GCREGCMDBUFFERAHBCTRL; /**< Command Buffer Control Register, offset: 0x3A4 */
__IO uint32_t GCREGHIAHBCONTROL; /**< MMU Host Interface Control Register, offset: 0x3A8 */
__IO uint32_t GCREGAXIAHBCONFIG; /**< MMU AXI Configuration Register, offset: 0x3AC */
uint8_t RESERVED_6[100];
__IO uint32_t AQMEMORYDEBUG; /**< Memory Debug Register, offset: 0x414 */
uint8_t RESERVED_7[20];
__IO uint32_t AQREGISTERTIMINGCONTROL; /**< Register Timing Control Register, offset: 0x42C */
uint8_t RESERVED_8[548];
__O uint32_t AQCMDBUFFERADDR; /**< Command Buffer Base Address Register, offset: 0x654 */
uint8_t RESERVED_9[12];
__I uint32_t AQFEDEBUGCURCMDADR; /**< Command Decoder Address Register, offset: 0x664 */
} NPU_Type;
/* ----------------------------------------------------------------------------
-- NPU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup NPU_Register_Masks NPU Register Masks
* @{
*/
/*! @name AQHICLOCKCONTROL - Clock Control Register */
/*! @{ */
#define NPU_AQHICLOCKCONTROL_CLK3D_DIS_MASK (0x1U)
#define NPU_AQHICLOCKCONTROL_CLK3D_DIS_SHIFT (0U)
/*! CLK3D_DIS - Disable 3D clock
* 0b1..The clock is frozen
*/
#define NPU_AQHICLOCKCONTROL_CLK3D_DIS(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_CLK3D_DIS_SHIFT)) & NPU_AQHICLOCKCONTROL_CLK3D_DIS_MASK)
#define NPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK (0x2U)
#define NPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT (1U)
/*! CLK2D_DIS - Disable 2D clock
*/
#define NPU_AQHICLOCKCONTROL_CLK2D_DIS(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT)) & NPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK)
#define NPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU)
#define NPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT (2U)
/*! FSCALE_VAL - Core clock frequency scale value
*/
#define NPU_AQHICLOCKCONTROL_FSCALE_VAL(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT)) & NPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK)
#define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U)
#define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U)
/*! FSCALE_CMD_LOAD - Core clock frequency scale value enable
* 0b1..The frequency scale factor is updated with the value FSCALE_VAL[6:0]. The bit sets back to 0 after that.
*/
#define NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT)) & NPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK)
#define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_MASK (0x400U)
#define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_SHIFT (10U)
/*! DIS_RAM_CLK_GATING - Disable clock gating for RAMs
*/
#define NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_SHIFT)) & NPU_AQHICLOCKCONTROL_DIS_RAM_CLK_GATING_MASK)
#define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_MASK (0x2000U)
#define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_SHIFT (13U)
/*! DIS_RAM_PWR_OPT - Disable RAM power optimization
*/
#define NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_SHIFT)) & NPU_AQHICLOCKCONTROL_DIS_RAM_PWR_OPT_MASK)
#define NPU_AQHICLOCKCONTROL_IDLE3_D_MASK (0x10000U)
#define NPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT (16U)
/*! IDLE3_D - 3D pipe is idle
*/
#define NPU_AQHICLOCKCONTROL_IDLE3_D(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT)) & NPU_AQHICLOCKCONTROL_IDLE3_D_MASK)
#define NPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK (0x80000U)
#define NPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT (19U)
/*! ISOLATE_GPU - Isolate GPU
*/
#define NPU_AQHICLOCKCONTROL_ISOLATE_GPU(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT)) & NPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK)
#define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_MASK (0xF00000U)
#define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_SHIFT (20U)
/*! MULTI_PIPE_REG_SEL - Multiple Pipe Register Select
*/
#define NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_SHIFT)) & NPU_AQHICLOCKCONTROL_MULTI_PIPE_REG_SEL_MASK)
/*! @} */
/*! @name AQHIIDLE - Idle Status Register */
/*! @{ */
#define NPU_AQHIIDLE_IDLE_FE_MASK (0x1U)
#define NPU_AQHIIDLE_IDLE_FE_SHIFT (0U)
/*! IDLE_FE - FE is idle
*/
#define NPU_AQHIIDLE_IDLE_FE(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_IDLE_FE_SHIFT)) & NPU_AQHIIDLE_IDLE_FE_MASK)
#define NPU_AQHIIDLE_IDLE_SH_MASK (0x8U)
#define NPU_AQHIIDLE_IDLE_SH_SHIFT (3U)
/*! IDLE_SH - SH is idle
*/
#define NPU_AQHIIDLE_IDLE_SH(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_IDLE_SH_SHIFT)) & NPU_AQHIIDLE_IDLE_SH_MASK)
#define NPU_AQHIIDLE_AXI_LP_MASK (0x80000000U)
#define NPU_AQHIIDLE_AXI_LP_SHIFT (31U)
/*! AXI_LP - AXI is in low power mode
*/
#define NPU_AQHIIDLE_AXI_LP(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQHIIDLE_AXI_LP_SHIFT)) & NPU_AQHIIDLE_AXI_LP_MASK)
/*! @} */
/*! @name AQAXISTATUS - AXI Status Register */
/*! @{ */
#define NPU_AQAXISTATUS_WR_ERR_ID_MASK (0xFU)
#define NPU_AQAXISTATUS_WR_ERR_ID_SHIFT (0U)
/*! WR_ERR_ID - Write Error ID
*/
#define NPU_AQAXISTATUS_WR_ERR_ID(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_WR_ERR_ID_SHIFT)) & NPU_AQAXISTATUS_WR_ERR_ID_MASK)
#define NPU_AQAXISTATUS_RD_ERR_ID_MASK (0xF0U)
#define NPU_AQAXISTATUS_RD_ERR_ID_SHIFT (4U)
/*! RD_ERR_ID - Read Error ID
*/
#define NPU_AQAXISTATUS_RD_ERR_ID(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_RD_ERR_ID_SHIFT)) & NPU_AQAXISTATUS_RD_ERR_ID_MASK)
#define NPU_AQAXISTATUS_DET_WR_ERR_MASK (0x100U)
#define NPU_AQAXISTATUS_DET_WR_ERR_SHIFT (8U)
/*! DET_WR_ERR - Detect Write Error
* 0b1..Detect write error
*/
#define NPU_AQAXISTATUS_DET_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_DET_WR_ERR_SHIFT)) & NPU_AQAXISTATUS_DET_WR_ERR_MASK)
#define NPU_AQAXISTATUS_DET_RD_ERR_MASK (0x200U)
#define NPU_AQAXISTATUS_DET_RD_ERR_SHIFT (9U)
/*! DET_RD_ERR - Detect Read Error
* 0b1..Detect read error
*/
#define NPU_AQAXISTATUS_DET_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQAXISTATUS_DET_RD_ERR_SHIFT)) & NPU_AQAXISTATUS_DET_RD_ERR_MASK)
/*! @} */
/*! @name AQINTRACKNOWLEDGE - Interrupt Acknowledge Register */
/*! @{ */
#define NPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFU)
#define NPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U)
/*! INTR_VEC - Interrupt Vector
*/
#define NPU_AQINTRACKNOWLEDGE_INTR_VEC(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT)) & NPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK)
/*! @} */
/*! @name AQINTRENBL - Interrupt Enable Register */
/*! @{ */
#define NPU_AQINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFU)
#define NPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT (0U)
/*! INTR_ENBL_VEC - Interrupt Vector Enable
*/
#define NPU_AQINTRENBL_INTR_ENBL_VEC(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT)) & NPU_AQINTRENBL_INTR_ENBL_VEC_MASK)
/*! @} */
/*! @name GCTOTALCYCLES - Total Cycles Register */
/*! @{ */
#define NPU_GCTOTALCYCLES_CYCLES_MASK (0xFFFFFFFFU)
#define NPU_GCTOTALCYCLES_CYCLES_SHIFT (0U)
/*! CYCLES - Cycles
*/
#define NPU_GCTOTALCYCLES_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCTOTALCYCLES_CYCLES_SHIFT)) & NPU_GCTOTALCYCLES_CYCLES_MASK)
/*! @} */
/*! @name GCMODULEPOWERCONTROLS - Module Power Level Control Register */
/*! @{ */
#define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_MASK (0x1U)
#define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_SHIFT (0U)
/*! EN_MOD_CLK_GATING - Enables module level clock gating
*/
#define NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_EN_MOD_CLK_GATING_MASK)
#define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_MASK (0x2U)
#define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_SHIFT (1U)
/*! DIS_STALL_MOD_CLK_GATING - Disables module level clock gating for stall condition
*/
#define NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_DIS_STALL_MOD_CLK_GATING_MASK)
#define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_MASK (0x4U)
#define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_SHIFT (2U)
/*! DIS_STARVE_MOD_CLK_GATING - Disables module level clock gating for starve/idle condition
*/
#define NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_DIS_STARVE_MOD_CLK_GATING_MASK)
#define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U)
#define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U)
/*! TURN_ON_COUNTER - Number of clock cycles to wait after turning on the clock
*/
#define NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK)
#define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000U)
#define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U)
/*! TURN_OFF_COUNTER - Counter value for clock gating the module if the module is idle for this amount of clock cycles
*/
#define NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT)) & NPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK)
/*! @} */
/*! @name GCPULSEEATER - Pulse eater Control Register */
/*! @{ */
#define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_MASK (0x1U)
#define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_SHIFT (0U)
/*! FSCALE_CMD_LOAD_SH - Fscale_cmd_load for shader
*/
#define NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_SHIFT)) & NPU_GCPULSEEATER_FSCALE_CMD_LOAD_SH_MASK)
#define NPU_GCPULSEEATER_FSCALE_VAL_SH_MASK (0xFEU)
#define NPU_GCPULSEEATER_FSCALE_VAL_SH_SHIFT (1U)
/*! FSCALE_VAL_SH - Fscale value for shader
*/
#define NPU_GCPULSEEATER_FSCALE_VAL_SH(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCPULSEEATER_FSCALE_VAL_SH_SHIFT)) & NPU_GCPULSEEATER_FSCALE_VAL_SH_MASK)
/*! @} */
/*! @name GCREGMMUAHBCONTROL - MMU Control Register */
/*! @{ */
#define NPU_GCREGMMUAHBCONTROL_MMU_MASK (0x1U)
#define NPU_GCREGMMUAHBCONTROL_MMU_SHIFT (0U)
/*! MMU - Enable the MMU
* 0b0..Disable
* 0b1..Enable
*/
#define NPU_GCREGMMUAHBCONTROL_MMU(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBCONTROL_MMU_SHIFT)) & NPU_GCREGMMUAHBCONTROL_MMU_MASK)
/*! @} */
/*! @name GCREGMMUAHBTABLEARRAYBASEADDRESSLOW - MMU Table Array Base Lower 32-bit Address Register */
/*! @{ */
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_MASK (0xFFFFFFFFU)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_SHIFT (0U)
/*! ADDRESS - Address
*/
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSLOW_ADDRESS_MASK)
/*! @} */
/*! @name GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH - MMU Table Array Base Higher 32-bit Address Register */
/*! @{ */
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_MASK (0xFFU)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHIFT (0U)
/*! MASTER_TLB - Upper 8-bits of the master TLB address to form a true 40-bit address
*/
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_MASK)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_MASK (0x100U)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_SHIFT (8U)
/*! MASTER_TLB_SECURE - Bit that defines whether the master TLB address is secure or not
*/
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SECURE_MASK)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_MASK (0x200U)
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_SHIFT (9U)
/*! MASTER_TLB_SHAREABLE - Bit that defines whether the master TLB address is shareable or not
*/
#define NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYBASEADDRESSHIGH_MASTER_TLB_SHAREABLE_MASK)
/*! @} */
/*! @name GCREGMMUAHBTABLEARRAYSIZE - MMU Table Array Size Control Register */
/*! @{ */
#define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_MASK (0xFFFFU)
#define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_SHIFT (0U)
/*! SIZE - Size
*/
#define NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_SHIFT)) & NPU_GCREGMMUAHBTABLEARRAYSIZE_SIZE_MASK)
/*! @} */
/*! @name GCREGMMUAHBSAFENONSECUREADDRESS - MMU NonSecure Address Register */
/*! @{ */
#define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_MASK (0xFFFFFFFFU)
#define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_SHIFT (0U)
/*! ADDRESS - Address
*/
#define NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBSAFENONSECUREADDRESS_ADDRESS_MASK)
/*! @} */
/*! @name GCREGMMUAHBSAFESECUREADDRESS - MMU Secure Address Register */
/*! @{ */
#define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_MASK (0xFFFFFFFFU)
#define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_SHIFT (0U)
/*! ADDRESS - Address
*/
#define NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_SHIFT)) & NPU_GCREGMMUAHBSAFESECUREADDRESS_ADDRESS_MASK)
/*! @} */
/*! @name GCREGCMDBUFFERAHBCTRL - Command Buffer Control Register */
/*! @{ */
#define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_MASK (0xFFFFU)
#define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_SHIFT (0U)
/*! PREFETCH - Prefetch
*/
#define NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_SHIFT)) & NPU_GCREGCMDBUFFERAHBCTRL_PREFETCH_MASK)
#define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_MASK (0x10000U)
#define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_SHIFT (16U)
/*! ENABLE - Enable the command parser
* 0b0..Disable
* 0b1..Enable
*/
#define NPU_GCREGCMDBUFFERAHBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_SHIFT)) & NPU_GCREGCMDBUFFERAHBCTRL_ENABLE_MASK)
/*! @} */
/*! @name GCREGHIAHBCONTROL - MMU Host Interface Control Register */
/*! @{ */
#define NPU_GCREGHIAHBCONTROL_SOFT_RESET_MASK (0x1U)
#define NPU_GCREGHIAHBCONTROL_SOFT_RESET_SHIFT (0U)
/*! SOFT_RESET - Soft Reset
* 0b0..Disable
* 0b1..Enable
*/
#define NPU_GCREGHIAHBCONTROL_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGHIAHBCONTROL_SOFT_RESET_SHIFT)) & NPU_GCREGHIAHBCONTROL_SOFT_RESET_MASK)
#define NPU_GCREGHIAHBCONTROL_DEBUG_MODE_MASK (0x2U)
#define NPU_GCREGHIAHBCONTROL_DEBUG_MODE_SHIFT (1U)
/*! DEBUG_MODE - Debug Mode
* 0b0..Disable
* 0b1..Enable
*/
#define NPU_GCREGHIAHBCONTROL_DEBUG_MODE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGHIAHBCONTROL_DEBUG_MODE_SHIFT)) & NPU_GCREGHIAHBCONTROL_DEBUG_MODE_MASK)
/*! @} */
/*! @name GCREGAXIAHBCONFIG - MMU AXI Configuration Register */
/*! @{ */
#define NPU_GCREGAXIAHBCONFIG_AWID_MASK (0xFU)
#define NPU_GCREGAXIAHBCONFIG_AWID_SHIFT (0U)
#define NPU_GCREGAXIAHBCONFIG_AWID(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AWID_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AWID_MASK)
#define NPU_GCREGAXIAHBCONFIG_ARID_MASK (0xF0U)
#define NPU_GCREGAXIAHBCONFIG_ARID_SHIFT (4U)
#define NPU_GCREGAXIAHBCONFIG_ARID(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_ARID_SHIFT)) & NPU_GCREGAXIAHBCONFIG_ARID_MASK)
#define NPU_GCREGAXIAHBCONFIG_AWCACHE_MASK (0xF00U)
#define NPU_GCREGAXIAHBCONFIG_AWCACHE_SHIFT (8U)
/*! AWCACHE - AW Cache value
*/
#define NPU_GCREGAXIAHBCONFIG_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AWCACHE_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AWCACHE_MASK)
#define NPU_GCREGAXIAHBCONFIG_ARCACHE_MASK (0xF000U)
#define NPU_GCREGAXIAHBCONFIG_ARCACHE_SHIFT (12U)
/*! ARCACHE - AR Cache value
*/
#define NPU_GCREGAXIAHBCONFIG_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_ARCACHE_SHIFT)) & NPU_GCREGAXIAHBCONFIG_ARCACHE_MASK)
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_MASK (0x30000U)
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_SHIFT (16U)
/*! AXDOMAIN_SHARED - Ax Domain value
*/
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXDOMAIN_SHARED_MASK)
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_MASK (0xC0000U)
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_SHIFT (18U)
/*! AXDOMAIN_NON_SHARED - Ax Domain value
*/
#define NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXDOMAIN_NON_SHARED_MASK)
#define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_MASK (0xF00000U)
#define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_SHIFT (20U)
/*! AXCACHE_OVERRIDE_SHARED - Ax Cache value
*/
#define NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED(x) (((uint32_t)(((uint32_t)(x)) << NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_SHIFT)) & NPU_GCREGAXIAHBCONFIG_AXCACHE_OVERRIDE_SHARED_MASK)
/*! @} */
/*! @name AQMEMORYDEBUG - Memory Debug Register */
/*! @{ */
#define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU)
#define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U)
/*! MAX_OUTSTANDING_READS - Maximum Outstanding Reads
*/
#define NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT)) & NPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK)
/*! @} */
/*! @name AQREGISTERTIMINGCONTROL - Register Timing Control Register */
/*! @{ */
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU)
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U)
/*! FOR_RF1P - For 1 port RAM
*/
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U)
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U)
/*! FOR_RF2P - For 2 port RAM
*/
#define NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000U)
#define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U)
/*! FAST_RTC - RTC for fast RAM
*/
#define NPU_AQREGISTERTIMINGCONTROL_FAST_RTC(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000U)
#define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U)
/*! FAST_WTC - WTC for fast RAM
*/
#define NPU_AQREGISTERTIMINGCONTROL_FAST_WTC(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000U)
#define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U)
/*! POWER_DOWN - Power Down Memory
*/
#define NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_MASK (0x200000U)
#define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_SHIFT (21U)
/*! DEEP_SLEEP - Deep sleep
*/
#define NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_DEEP_SLEEP_MASK)
#define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_MASK (0x400000U)
#define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_SHIFT (22U)
/*! LIGHT_SLEEP - Light sleep
*/
#define NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_SHIFT)) & NPU_AQREGISTERTIMINGCONTROL_LIGHT_SLEEP_MASK)
/*! @} */
/*! @name AQCMDBUFFERADDR - Command Buffer Base Address Register */
/*! @{ */
#define NPU_AQCMDBUFFERADDR_ADDRESS_MASK (0x7FFFFFFFU)
#define NPU_AQCMDBUFFERADDR_ADDRESS_SHIFT (0U)
/*! ADDRESS - Address
*/
#define NPU_AQCMDBUFFERADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQCMDBUFFERADDR_ADDRESS_SHIFT)) & NPU_AQCMDBUFFERADDR_ADDRESS_MASK)
#define NPU_AQCMDBUFFERADDR_TYPE_MASK (0x80000000U)
#define NPU_AQCMDBUFFERADDR_TYPE_SHIFT (31U)
/*! TYPE - Type
* 0b0..System
* 0b1..Virtual System
*/
#define NPU_AQCMDBUFFERADDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQCMDBUFFERADDR_TYPE_SHIFT)) & NPU_AQCMDBUFFERADDR_TYPE_MASK)
/*! @} */
/*! @name AQFEDEBUGCURCMDADR - Command Decoder Address Register */
/*! @{ */
#define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_MASK (0xFFFFFFF8U)
#define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_SHIFT (3U)
/*! CUR_CMD_ADR - Command decoder Address
*/
#define NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR(x) (((uint32_t)(((uint32_t)(x)) << NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_SHIFT)) & NPU_AQFEDEBUGCURCMDADR_CUR_CMD_ADR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group NPU_Register_Masks */
/* NPU - Peripheral instance base addresses */
/** Peripheral NPU base address */
#define NPU_BASE (0x38500000u)
/** Peripheral NPU base pointer */
#define NPU ((NPU_Type *)NPU_BASE)
/** Array initializer of NPU peripheral base addresses */
#define NPU_BASE_ADDRS { NPU_BASE }
/** Array initializer of NPU peripheral base pointers */
#define NPU_BASE_PTRS { NPU }
/*!
* @}
*/ /* end of group NPU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OCOTP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
* @{
*/
/** OCOTP - Register Layout Typedef */
typedef struct {
__IO uint32_t HW_OCOTP_CTRL; /**< OTP Controller Control Register, offset: 0x0 */
__IO uint32_t HW_OCOTP_CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */
__IO uint32_t HW_OCOTP_CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */
__IO uint32_t HW_OCOTP_CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */
__IO uint32_t HW_OCOTP_TIMING; /**< OTP Controller Timing Register, offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t HW_OCOTP_DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
uint8_t RESERVED_1[12];
__IO uint32_t HW_OCOTP_READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */
uint8_t RESERVED_2[12];
__IO uint32_t HW_OCOTP_READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */
uint8_t RESERVED_3[28];
__IO uint32_t HW_OCOTP_SCS; /**< Software Controllable Signals Register, offset: 0x60 */
__IO uint32_t HW_OCOTP_SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */
__IO uint32_t HW_OCOTP_SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */
__IO uint32_t HW_OCOTP_SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */
uint8_t RESERVED_4[32];
__I uint32_t HW_OCOTP_VERSION; /**< OTP Controller Version Register, offset: 0x90 */
uint8_t RESERVED_5[876];
__I uint32_t HW_OCOTP_LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
uint8_t RESERVED_6[108];
__IO uint32_t HW_OCOTP_BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */
uint8_t RESERVED_7[12];
__IO uint32_t HW_OCOTP_BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */
uint8_t RESERVED_8[12];
__IO uint32_t HW_OCOTP_BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */
uint8_t RESERVED_9[12];
__IO uint32_t HW_OCOTP_BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */
uint8_t RESERVED_10[12];
__IO uint32_t HW_OCOTP_BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */
uint8_t RESERVED_11[332];
__IO uint32_t HW_OCOTP_SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */
uint8_t RESERVED_12[12];
__IO uint32_t HW_OCOTP_SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */
uint8_t RESERVED_13[12];
__IO uint32_t HW_OCOTP_USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */
uint8_t RESERVED_14[28];
__IO uint32_t HW_OCOTP_MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */
uint8_t RESERVED_15[12];
__IO uint32_t HW_OCOTP_MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */
uint8_t RESERVED_16[12];
__IO uint32_t HW_OCOTP_MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */
uint8_t RESERVED_17[284];
__IO uint32_t HW_OCOTP_GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */
uint8_t RESERVED_18[12];
__IO uint32_t HW_OCOTP_GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */
uint8_t RESERVED_19[12];
__IO uint32_t HW_OCOTP_GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */
uint8_t RESERVED_20[12];
__IO uint32_t HW_OCOTP_GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */
} OCOTP_Type;
/* ----------------------------------------------------------------------------
-- OCOTP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Register_Masks OCOTP Register Masks
* @{
*/
/*! @name HW_OCOTP_CTRL - OTP Controller Control Register */
/*! @{ */
#define OCOTP_HW_OCOTP_CTRL_ADDR_MASK (0x1FFU)
#define OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT (0U)
#define OCOTP_HW_OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ADDR_MASK)
#define OCOTP_HW_OCOTP_CTRL_BUSY_MASK (0x200U)
#define OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT (9U)
#define OCOTP_HW_OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_BUSY_MASK)
#define OCOTP_HW_OCOTP_CTRL_ERROR_MASK (0x400U)
#define OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT (10U)
#define OCOTP_HW_OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ERROR_MASK)
#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x800U)
#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (11U)
#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK)
#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_CTRL_SET - OTP Controller Control Register */
/*! @{ */
#define OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK (0xFFU)
#define OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT (0U)
#define OCOTP_HW_OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK)
#define OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK (0x100U)
#define OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT (8U)
#define OCOTP_HW_OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK)
#define OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK (0x200U)
#define OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT (9U)
#define OCOTP_HW_OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK)
#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_CTRL_CLR - OTP Controller Control Register */
/*! @{ */
#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK (0xFFU)
#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK)
#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK)
#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK)
#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_CTRL_TOG - OTP Controller Control Register */
/*! @{ */
#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK (0xFFU)
#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK)
#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK)
#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK)
#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_TIMING - OTP Controller Timing Register */
/*! @{ */
#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK)
#define OCOTP_HW_OCOTP_TIMING_RELAX_MASK (0xF000U)
#define OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT (12U)
#define OCOTP_HW_OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RELAX_MASK)
#define OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
#define OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT (16U)
#define OCOTP_HW_OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK)
#define OCOTP_HW_OCOTP_TIMING_WAIT_MASK (0xFC00000U)
#define OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT (22U)
#define OCOTP_HW_OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_HW_OCOTP_TIMING_WAIT_MASK)
/*! @} */
/*! @name HW_OCOTP_DATA - OTP Controller Write Data Register */
/*! @{ */
#define OCOTP_HW_OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_DATA_DATA_SHIFT (0U)
#define OCOTP_HW_OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_DATA_DATA_MASK)
/*! @} */
/*! @name HW_OCOTP_READ_CTRL - OTP Controller Write Data Register */
/*! @{ */
#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK)
/*! @} */
/*! @name HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register */
/*! @{ */
#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK)
/*! @} */
/*! @name HW_OCOTP_SCS - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK (0x1U)
#define OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT (0U)
#define OCOTP_HW_OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK)
#define OCOTP_HW_OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_HW_OCOTP_SCS_SPARE_SHIFT (1U)
#define OCOTP_HW_OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SPARE_MASK)
#define OCOTP_HW_OCOTP_SCS_LOCK_MASK (0x80000000U)
#define OCOTP_HW_OCOTP_SCS_LOCK_SHIFT (31U)
#define OCOTP_HW_OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_LOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_SCS_SET - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT (1U)
#define OCOTP_HW_OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK)
#define OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
#define OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT (31U)
#define OCOTP_HW_OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_SCS_CLR - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT (1U)
#define OCOTP_HW_OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK)
#define OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
#define OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT (31U)
#define OCOTP_HW_OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_SCS_TOG - Software Controllable Signals Register */
/*! @{ */
#define OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
#define OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT (1U)
#define OCOTP_HW_OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK)
#define OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
#define OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT (31U)
#define OCOTP_HW_OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK)
/*! @} */
/*! @name HW_OCOTP_VERSION - OTP Controller Version Register */
/*! @{ */
#define OCOTP_HW_OCOTP_VERSION_STEP_MASK (0xFFFFU)
#define OCOTP_HW_OCOTP_VERSION_STEP_SHIFT (0U)
#define OCOTP_HW_OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_STEP_SHIFT)) & OCOTP_HW_OCOTP_VERSION_STEP_MASK)
#define OCOTP_HW_OCOTP_VERSION_MINOR_MASK (0xFF0000U)
#define OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT (16U)
#define OCOTP_HW_OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MINOR_MASK)
#define OCOTP_HW_OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
#define OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT (24U)
#define OCOTP_HW_OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MAJOR_MASK)
/*! @} */
/*! @name HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) */
/*! @{ */
#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK)
#define OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK (0x400U)
#define OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT (10U)
#define OCOTP_HW_OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK)
#define OCOTP_HW_OCOTP_LOCK_USB_ID_MASK (0x3000U)
#define OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT (12U)
#define OCOTP_HW_OCOTP_LOCK_USB_ID(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_HW_OCOTP_LOCK_USB_ID_MASK)
#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK (0xC000U)
#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT (14U)
#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK)
#define OCOTP_HW_OCOTP_LOCK_GP1_MASK (0x300000U)
#define OCOTP_HW_OCOTP_LOCK_GP1_SHIFT (20U)
#define OCOTP_HW_OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP1_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP1_MASK)
#define OCOTP_HW_OCOTP_LOCK_GP2_MASK (0xC00000U)
#define OCOTP_HW_OCOTP_LOCK_GP2_SHIFT (22U)
#define OCOTP_HW_OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP2_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP2_MASK)
/*! @} */
/*! @name HW_OCOTP_BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */
/*! @{ */
#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */
/*! @{ */
#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */
/*! @{ */
#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */
/*! @{ */
#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */
/*! @{ */
#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */
/*! @{ */
#define OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */
/*! @{ */
#define OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_USB_ID - Value of OTP Bank8 Word2 (USB ID info) */
/*! @{ */
#define OCOTP_HW_OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_USB_ID_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_HW_OCOTP_USB_ID_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */
/*! @{ */
#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */
/*! @{ */
#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */
/*! @{ */
#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_GP10 - Value of OTP Bank14 Word0 () */
/*! @{ */
#define OCOTP_HW_OCOTP_GP10_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_GP10_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_GP10_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP10_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP10_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_GP11 - Value of OTP Bank14 Word1 () */
/*! @{ */
#define OCOTP_HW_OCOTP_GP11_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_GP11_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_GP11_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP11_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP11_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_GP20 - Value of OTP Bank14 Word2 () */
/*! @{ */
#define OCOTP_HW_OCOTP_GP20_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_GP20_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP20_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP20_BITS_MASK)
/*! @} */
/*! @name HW_OCOTP_GP21 - Value of OTP Bank14 Word3 () */
/*! @{ */
#define OCOTP_HW_OCOTP_GP21_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_HW_OCOTP_GP21_BITS_SHIFT (0U)
#define OCOTP_HW_OCOTP_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP21_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP21_BITS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group OCOTP_Register_Masks */
/* OCOTP - Peripheral instance base addresses */
/** Peripheral OCOTP base address */
#define OCOTP_BASE (0x30350000u)
/** Peripheral OCOTP base pointer */
#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
/** Array initializer of OCOTP peripheral base addresses */
#define OCOTP_BASE_ADDRS { OCOTP_BASE }
/** Array initializer of OCOTP peripheral base pointers */
#define OCOTP_BASE_PTRS { OCOTP }
/*!
* @}
*/ /* end of group OCOTP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PCIE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCIE_Peripheral_Access_Layer PCIE Peripheral Access Layer
* @{
*/
/** PCIE - Register Layout Typedef */
typedef struct {
__IO uint32_t TYPE1_DEV_ID_VEND_ID_REG; /**< Device ID and Vendor ID Register., offset: 0x0 */
__IO uint32_t TYPE1_STATUS_COMMAND_REG; /**< Status and Command Register., offset: 0x4 */
__IO uint32_t TYPE1_CLASS_CODE_REV_ID_REG; /**< Class Code and Revision ID Register., offset: 0x8 */
__IO uint32_t TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG; /**< Header Type, Latency Timer, and Cache Line Size Register., offset: 0xC */
uint8_t RESERVED_0[8];
__IO uint32_t SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG; /**< Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register., offset: 0x18 */
__IO uint32_t SEC_STAT_IO_LIMIT_IO_BASE_REG; /**< Secondary Status, and I/O Limit and Base Register., offset: 0x1C */
__IO uint32_t MEM_LIMIT_MEM_BASE_REG; /**< Memory Limit and Base Register., offset: 0x20 */
__IO uint32_t PREF_MEM_LIMIT_PREF_MEM_BASE_REG; /**< Prefetchable Memory Limit and Base Register., offset: 0x24 */
__I uint32_t PREF_BASE_UPPER_REG; /**< Prefetchable Base Upper 32 Bits Register., offset: 0x28 */
__I uint32_t PREF_LIMIT_UPPER_REG; /**< Prefetchable Limit Upper 32 Bits Register., offset: 0x2C */
__I uint32_t IO_LIMIT_UPPER_IO_BASE_UPPER_REG; /**< I/O Limit and Base Upper 16 Bits Register., offset: 0x30 */
__IO uint32_t TYPE1_CAP_PTR_REG; /**< Capabilities Pointer Register., offset: 0x34 */
__IO uint32_t TYPE1_EXP_ROM_BASE_REG; /**< Expansion ROM Base Address Register., offset: 0x38 */
__IO uint32_t BRIDGE_CTRL_INT_PIN_INT_LINE_REG; /**< Bridge Control, Interrupt Pin, and Interrupt Line Register., offset: 0x3C */
__IO uint32_t CAP_ID_NXT_PTR_REG; /**< Power Management Capabilities Register., offset: 0x40 */
__IO uint32_t CON_STATUS_REG; /**< Power Management Control and Status Register., offset: 0x44 */
uint8_t RESERVED_1[8];
__IO uint32_t PCI_MSI_CAP_ID_NEXT_CTRL_REG; /**< MSI Capability ID, Next Pointer, Capability/Control Registers., offset: 0x50 */
__IO uint32_t MSI_CAP_OFF_04H_REG; /**< MSI Message Lower Address Register., offset: 0x54 */
__IO uint32_t MSI_CAP_OFF_08H_REG; /**< For a 32 bit MSI Message, this register contains Data., offset: 0x58 */
__IO uint32_t MSI_CAP_OFF_0CH_REG; /**< For a 64 bit MSI Message, this register contains Data., offset: 0x5C */
__IO uint32_t MSI_CAP_OFF_10H_REG; /**< Used for MSI when Vector Masking Capable., offset: 0x60 */
__I uint32_t MSI_CAP_OFF_14H_REG; /**< Used for MSI 64 bit messaging when Vector Masking Capable., offset: 0x64 */
uint8_t RESERVED_2[8];
__IO uint32_t PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG; /**< PCI Express Capabilities, ID, Next Pointer Register., offset: 0x70 */
__IO uint32_t DEVICE_CAPABILITIES_REG; /**< Device Capabilities Register., offset: 0x74 */
__IO uint32_t DEVICE_CONTROL_DEVICE_STATUS; /**< Device Control and Status Register., offset: 0x78 */
__IO uint32_t LINK_CAPABILITIES_REG; /**< Link Capabilities Register., offset: 0x7C */
__IO uint32_t LINK_CONTROL_LINK_STATUS_REG; /**< Link Control and Status Register., offset: 0x80 */
__IO uint32_t SLOT_CAPABILITIES_REG; /**< Slot Capabilities Register., offset: 0x84 */
__IO uint32_t SLOT_CONTROL_SLOT_STATUS; /**< Slot Control and Status Register., offset: 0x88 */
__IO uint32_t ROOT_CONTROL_ROOT_CAPABILITIES_REG; /**< Root Control and Capabilities Register., offset: 0x8C */
__IO uint32_t ROOT_STATUS_REG; /**< Root Status Register., offset: 0x90 */
__I uint32_t DEVICE_CAPABILITIES2_REG; /**< Device Capabilities 2 Register., offset: 0x94 */
__IO uint32_t DEVICE_CONTROL2_DEVICE_STATUS2_REG; /**< Device Control 2 and Status 2 Register., offset: 0x98 */
__I uint32_t LINK_CAPABILITIES2_REG; /**< Link Capabilities 2 Register., offset: 0x9C */
__IO uint32_t LINK_CONTROL2_LINK_STATUS2_REG; /**< Link Control 2 and Status 2 Register., offset: 0xA0 */
uint8_t RESERVED_3[92];
__IO uint32_t AER_EXT_CAP_HDR_OFF; /**< Advanced Error Reporting Extended Capability Header., offset: 0x100 */
__IO uint32_t UNCORR_ERR_STATUS_OFF; /**< Uncorrectable Error Status Register., offset: 0x104 */
__IO uint32_t UNCORR_ERR_MASK_OFF; /**< Uncorrectable Error Mask Register., offset: 0x108 */
__IO uint32_t UNCORR_ERR_SEV_OFF; /**< Uncorrectable Error Severity Register., offset: 0x10C */
__IO uint32_t CORR_ERR_STATUS_OFF; /**< Correctable Error Status Register., offset: 0x110 */
__IO uint32_t CORR_ERR_MASK_OFF; /**< Correctable Error Mask Register., offset: 0x114 */
__IO uint32_t ADV_ERR_CAP_CTRL_OFF; /**< Advanced Error Capabilities and Control Register., offset: 0x118 */
__I uint32_t HDR_LOG_0_OFF; /**< Header Log Register 0., offset: 0x11C */
__I uint32_t HDR_LOG_1_OFF; /**< Header Log Register 1., offset: 0x120 */
__I uint32_t HDR_LOG_2_OFF; /**< Header Log Register 2., offset: 0x124 */
__I uint32_t HDR_LOG_3_OFF; /**< Header Log Register 3., offset: 0x128 */
__IO uint32_t ROOT_ERR_CMD_OFF; /**< Root Error Command Register., offset: 0x12C */
__IO uint32_t ROOT_ERR_STATUS_OFF; /**< Root Error Status Register., offset: 0x130 */
__I uint32_t ERR_SRC_ID_OFF; /**< Error Source Identification Register., offset: 0x134 */
__I uint32_t TLP_PREFIX_LOG_1_OFF; /**< TLP Prefix Log Register 1., offset: 0x138 */
__I uint32_t TLP_PREFIX_LOG_2_OFF; /**< TLP Prefix Log Register 2., offset: 0x13C */
__I uint32_t TLP_PREFIX_LOG_3_OFF; /**< TLP Prefix Log Register 3., offset: 0x140 */
__I uint32_t TLP_PREFIX_LOG_4_OFF; /**< TLP Prefix Log Register 4., offset: 0x144 */
uint8_t RESERVED_4[16];
__IO uint32_t L1SUB_CAP_HEADER_REG; /**< L1 Substates Extended Capability Header., offset: 0x158 */
__IO uint32_t L1SUB_CAPABILITY_REG; /**< L1 Substates Capability Register., offset: 0x15C */
__IO uint32_t L1SUB_CONTROL1_REG; /**< L1 Substates Control 1 Register., offset: 0x160 */
__IO uint32_t L1SUB_CONTROL2_REG; /**< L1 Substates Control 2 Register., offset: 0x164 */
uint8_t RESERVED_5[1432];
__IO uint32_t ACK_LATENCY_TIMER_OFF; /**< Ack Latency Timer and Replay Timer Register., offset: 0x700 */
__IO uint32_t VENDOR_SPEC_DLLP_OFF; /**< Vendor Specific DLLP Register., offset: 0x704 */
__IO uint32_t PORT_FORCE_OFF; /**< Port Force Link Register., offset: 0x708 */
__IO uint32_t ACK_F_ASPM_CTRL_OFF; /**< Ack Frequency and L0-L1 ASPM Control Register., offset: 0x70C */
__IO uint32_t PORT_LINK_CTRL_OFF; /**< Port Link Control Register., offset: 0x710 */
__IO uint32_t LANE_SKEW_OFF; /**< Lane Skew Register., offset: 0x714 */
__IO uint32_t TIMER_CTRL_MAX_FUNC_NUM_OFF; /**< Timer Control and Max Function Number Register., offset: 0x718 */
__IO uint32_t SYMBOL_TIMER_FILTER_1_OFF; /**< Symbol Timer Register and Filter Mask 1 Register., offset: 0x71C */
__IO uint32_t FILTER_MASK_2_OFF; /**< Filter Mask 2 Register., offset: 0x720 */
__IO uint32_t AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF; /**< AMBA Multiple Outbound Decomposed NP SubRequests Control Register., offset: 0x724 */
__I uint32_t PL_DEBUG0_OFF; /**< Debug Register 0, offset: 0x728 */
__I uint32_t PL_DEBUG1_OFF; /**< Debug Register 1, offset: 0x72C */
__I uint32_t TX_P_FC_CREDIT_STATUS_OFF; /**< Transmit Posted FC Credit Status, offset: 0x730 */
__I uint32_t TX_NP_FC_CREDIT_STATUS_OFF; /**< Transmit Non-Posted FC Credit Status, offset: 0x734 */
__I uint32_t TX_CPL_FC_CREDIT_STATUS_OFF; /**< Transmit Completion FC Credit Status, offset: 0x738 */
__IO uint32_t QUEUE_STATUS_OFF; /**< Queue Status, offset: 0x73C */
__I uint32_t VC_TX_ARBI_1_OFF; /**< VC Transmit Arbitration Register 1, offset: 0x740 */
uint8_t RESERVED_6[4];
__IO uint32_t VC0_P_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Posted Receive Queue Control., offset: 0x748 */
__IO uint32_t VC0_NP_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Non-Posted Receive Queue Control., offset: 0x74C */
__IO uint32_t VC0_CPL_RX_Q_CTRL_OFF; /**< Segmented-Buffer VC0 Completion Receive Queue Control., offset: 0x750 */
uint8_t RESERVED_7[184];
__IO uint32_t GEN2_CTRL_OFF; /**< Link Width and Speed Change Control Register., offset: 0x80C */
__I uint32_t PHY_STATUS_OFF; /**< PHY Status Register., offset: 0x810 */
__IO uint32_t PHY_CONTROL_OFF; /**< PHY Control Register., offset: 0x814 */
uint8_t RESERVED_8[4];
__IO uint32_t TRGT_MAP_CTRL_OFF; /**< Programmable Target Map Control Register., offset: 0x81C */
__IO uint32_t MSI_CTRL_ADDR_OFF; /**< Integrated MSI Reception Module (iMRM) Address Register., offset: 0x820 */
__IO uint32_t MSI_CTRL_UPPER_ADDR_OFF; /**< Integrated MSI Reception Module Upper Address Register., offset: 0x824 */
__IO uint32_t MSI_CTRL_INT_0_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x828 */
__IO uint32_t MSI_CTRL_INT_0_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x82C */
__IO uint32_t MSI_CTRL_INT_0_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x830 */
__IO uint32_t MSI_CTRL_INT_1_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x834 */
__IO uint32_t MSI_CTRL_INT_1_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x838 */
__IO uint32_t MSI_CTRL_INT_1_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x83C */
__IO uint32_t MSI_CTRL_INT_2_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x840 */
__IO uint32_t MSI_CTRL_INT_2_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x844 */
__IO uint32_t MSI_CTRL_INT_2_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x848 */
__IO uint32_t MSI_CTRL_INT_3_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x84C */
__IO uint32_t MSI_CTRL_INT_3_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x850 */
__IO uint32_t MSI_CTRL_INT_3_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x854 */
__IO uint32_t MSI_CTRL_INT_4_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x858 */
__IO uint32_t MSI_CTRL_INT_4_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x85C */
__IO uint32_t MSI_CTRL_INT_4_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x860 */
__IO uint32_t MSI_CTRL_INT_5_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x864 */
__IO uint32_t MSI_CTRL_INT_5_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x868 */
__IO uint32_t MSI_CTRL_INT_5_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x86C */
__IO uint32_t MSI_CTRL_INT_6_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x870 */
__IO uint32_t MSI_CTRL_INT_6_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x874 */
__IO uint32_t MSI_CTRL_INT_6_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x878 */
__IO uint32_t MSI_CTRL_INT_7_EN_OFF; /**< Integrated MSI Reception Module Interrupt#i Enable Register., offset: 0x87C */
__IO uint32_t MSI_CTRL_INT_7_MASK_OFF; /**< Integrated MSI Reception Module Interrupt#i Mask Register., offset: 0x880 */
__IO uint32_t MSI_CTRL_INT_7_STATUS_OFF; /**< Integrated MSI Reception Module Interrupt#i Status Register., offset: 0x884 */
__IO uint32_t MSI_GPIO_IO_OFF; /**< Integrated MSI Reception Module General Purpose IO Register., offset: 0x888 */
__IO uint32_t CLOCK_GATING_CTRL_OFF; /**< RADM clock gating enable control register., offset: 0x88C */
uint8_t RESERVED_9[36];
__IO uint32_t ORDER_RULE_CTRL_OFF; /**< Order Rule Control Register., offset: 0x8B4 */
__IO uint32_t PIPE_LOOPBACK_CONTROL_OFF; /**< PIPE Loopback Control Register., offset: 0x8B8 */
__IO uint32_t MISC_CONTROL_1_OFF; /**< DBI Read-Only Write Enable Register., offset: 0x8BC */
__IO uint32_t MULTI_LANE_CONTROL_OFF; /**< UpConfigure Multi-lane Control Register., offset: 0x8C0 */
__IO uint32_t PHY_INTEROP_CTRL_OFF; /**< PHY Interoperability Control Register., offset: 0x8C4 */
__IO uint32_t TRGT_CPL_LUT_DELETE_ENTRY_OFF; /**< TRGT_CPL_LUT Delete Entry Control register., offset: 0x8C8 */
__IO uint32_t LINK_FLUSH_CONTROL_OFF; /**< Link Reset Request Flush Control Register., offset: 0x8CC */
__IO uint32_t AMBA_ERROR_RESPONSE_DEFAULT_OFF; /**< AXI Bridge Slave Error Response Register., offset: 0x8D0 */
__IO uint32_t AMBA_LINK_TIMEOUT_OFF; /**< Link Down AXI Bridge Slave Timeout Register., offset: 0x8D4 */
__IO uint32_t AMBA_ORDERING_CTRL_OFF; /**< AMBA Ordering Control., offset: 0x8D8 */
uint8_t RESERVED_10[20];
__IO uint32_t AXI_MSTR_MSG_ADDR_LOW_OFF; /**< Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to., offset: 0x8F0 */
__IO uint32_t AXI_MSTR_MSG_ADDR_HIGH_OFF; /**< Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to., offset: 0x8F4 */
__I uint32_t PCIE_VERSION_NUMBER_OFF; /**< PCIe Controller IIP Release Version Number., offset: 0x8F8 */
__I uint32_t PCIE_VERSION_TYPE_OFF; /**< PCIe Controller IIP Release Version Type., offset: 0x8FC */
uint8_t RESERVED_11[576];
__IO uint32_t AUX_CLK_FREQ_OFF; /**< Auxiliary Clock Frequency Control Register., offset: 0xB40 */
__IO uint32_t L1_SUBSTATES_OFF; /**< L1 Substates Timing Register., offset: 0xB44 */
uint8_t RESERVED_12[3142840];
__IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_0; /**< iATU Region Control 1 Register., offset: 0x300000 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_0; /**< iATU Region Control 2 Register., offset: 0x300004 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Base Address Register., offset: 0x300008 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Base Address Register., offset: 0x30000C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_0; /**< iATU Limit Address Register., offset: 0x300010 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Lower Target Address Register., offset: 0x300014 */
__IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0; /**< iATU Upper Target Address Register., offset: 0x300018 */
uint8_t RESERVED_13[228];
__IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_0; /**< iATU Region Control 1 Register., offset: 0x300100 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_0; /**< iATU Region Control 2 Register., offset: 0x300104 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_0; /**< iATU Lower Base Address Register., offset: 0x300108 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_0; /**< iATU Upper Base Address Register., offset: 0x30010C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_0; /**< iATU Limit Address Register., offset: 0x300110 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_0; /**< iATU Lower Target Address Register., offset: 0x300114 */
uint8_t RESERVED_14[232];
__IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_1; /**< iATU Region Control 1 Register., offset: 0x300200 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_1; /**< iATU Region Control 2 Register., offset: 0x300204 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Base Address Register., offset: 0x300208 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Base Address Register., offset: 0x30020C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_1; /**< iATU Limit Address Register., offset: 0x300210 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Lower Target Address Register., offset: 0x300214 */
__IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1; /**< iATU Upper Target Address Register., offset: 0x300218 */
uint8_t RESERVED_15[228];
__IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_1; /**< iATU Region Control 1 Register., offset: 0x300300 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_1; /**< iATU Region Control 2 Register., offset: 0x300304 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_1; /**< iATU Lower Base Address Register., offset: 0x300308 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_1; /**< iATU Upper Base Address Register., offset: 0x30030C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_1; /**< iATU Limit Address Register., offset: 0x300310 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_1; /**< iATU Lower Target Address Register., offset: 0x300314 */
uint8_t RESERVED_16[232];
__IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_2; /**< iATU Region Control 1 Register., offset: 0x300400 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_2; /**< iATU Region Control 2 Register., offset: 0x300404 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Base Address Register., offset: 0x300408 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Base Address Register., offset: 0x30040C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_2; /**< iATU Limit Address Register., offset: 0x300410 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Lower Target Address Register., offset: 0x300414 */
__IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2; /**< iATU Upper Target Address Register., offset: 0x300418 */
uint8_t RESERVED_17[228];
__IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_2; /**< iATU Region Control 1 Register., offset: 0x300500 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_2; /**< iATU Region Control 2 Register., offset: 0x300504 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_2; /**< iATU Lower Base Address Register., offset: 0x300508 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_2; /**< iATU Upper Base Address Register., offset: 0x30050C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_2; /**< iATU Limit Address Register., offset: 0x300510 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_2; /**< iATU Lower Target Address Register., offset: 0x300514 */
uint8_t RESERVED_18[232];
__IO uint32_t IATU_REGION_CTRL_1_OFF_OUTBOUND_3; /**< iATU Region Control 1 Register., offset: 0x300600 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_OUTBOUND_3; /**< iATU Region Control 2 Register., offset: 0x300604 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Base Address Register., offset: 0x300608 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Base Address Register., offset: 0x30060C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_OUTBOUND_3; /**< iATU Limit Address Register., offset: 0x300610 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Lower Target Address Register., offset: 0x300614 */
__IO uint32_t IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3; /**< iATU Upper Target Address Register., offset: 0x300618 */
uint8_t RESERVED_19[228];
__IO uint32_t IATU_REGION_CTRL_1_OFF_INBOUND_3; /**< iATU Region Control 1 Register., offset: 0x300700 */
__IO uint32_t IATU_REGION_CTRL_2_OFF_INBOUND_3; /**< iATU Region Control 2 Register., offset: 0x300704 */
__IO uint32_t IATU_LWR_BASE_ADDR_OFF_INBOUND_3; /**< iATU Lower Base Address Register., offset: 0x300708 */
__IO uint32_t IATU_UPPER_BASE_ADDR_OFF_INBOUND_3; /**< iATU Upper Base Address Register., offset: 0x30070C */
__IO uint32_t IATU_LIMIT_ADDR_OFF_INBOUND_3; /**< iATU Limit Address Register., offset: 0x300710 */
__IO uint32_t IATU_LWR_TARGET_ADDR_OFF_INBOUND_3; /**< iATU Lower Target Address Register., offset: 0x300714 */
uint8_t RESERVED_20[522472];
__IO uint32_t DMA_CTRL_DATA_ARB_PRIOR_OFF; /**< DMA Arbitration Scheme for TRGT1 Interface., offset: 0x380000 */
uint8_t RESERVED_21[4];
__IO uint32_t DMA_CTRL_OFF; /**< DMA Number of Channels Register., offset: 0x380008 */
__IO uint32_t DMA_WRITE_ENGINE_EN_OFF; /**< DMA Write Engine Enable Register., offset: 0x38000C */
__IO uint32_t DMA_WRITE_DOORBELL_OFF; /**< DMA Write Doorbell Register., offset: 0x380010 */
uint8_t RESERVED_22[4];
__IO uint32_t DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Write Engine Channel Arbitration Weight Low Register., offset: 0x380018 */
__IO uint32_t DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF; /**< DMA Write Engine Channel Arbitration Weight High Register., offset: 0x38001C */
uint8_t RESERVED_23[12];
__IO uint32_t DMA_READ_ENGINE_EN_OFF; /**< DMA Read Engine Enable Register., offset: 0x38002C */
__IO uint32_t DMA_READ_DOORBELL_OFF; /**< DMA Read Doorbell Register., offset: 0x380030 */
uint8_t RESERVED_24[4];
__IO uint32_t DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF; /**< DMA Read Engine Channel Arbitration Weight Low Register., offset: 0x380038 */
__IO uint32_t DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF; /**< DMA Read Engine Channel Arbitration Weight High Register., offset: 0x38003C */
uint8_t RESERVED_25[12];
__IO uint32_t DMA_WRITE_INT_STATUS_OFF; /**< DMA Write Interrupt Status Register., offset: 0x38004C */
uint8_t RESERVED_26[4];
__IO uint32_t DMA_WRITE_INT_MASK_OFF; /**< DMA Write Interrupt Mask Register., offset: 0x380054 */
__IO uint32_t DMA_WRITE_INT_CLEAR_OFF; /**< DMA Write Interrupt Clear Register., offset: 0x380058 */
__I uint32_t DMA_WRITE_ERR_STATUS_OFF; /**< DMA Write Error Status Register, offset: 0x38005C */
__IO uint32_t DMA_WRITE_DONE_IMWR_LOW_OFF; /**< DMA Write Done IMWr Address Low Register., offset: 0x380060 */
__IO uint32_t DMA_WRITE_DONE_IMWR_HIGH_OFF; /**< DMA Write Done IMWr Interrupt Address High Register., offset: 0x380064 */
__IO uint32_t DMA_WRITE_ABORT_IMWR_LOW_OFF; /**< DMA Write Abort IMWr Address Low Register., offset: 0x380068 */
__IO uint32_t DMA_WRITE_ABORT_IMWR_HIGH_OFF; /**< DMA Write Abort IMWr Address High Register., offset: 0x38006C */
__IO uint32_t DMA_WRITE_CH01_IMWR_DATA_OFF; /**< DMA Write Channel 1 and 0 IMWr Data Register., offset: 0x380070 */
__IO uint32_t DMA_WRITE_CH23_IMWR_DATA_OFF; /**< DMA Write Channel 3 and 2 IMWr Data Register., offset: 0x380074 */
__IO uint32_t DMA_WRITE_CH45_IMWR_DATA_OFF; /**< DMA Write Channel 5 and 4 IMWr Data Register., offset: 0x380078 */
__IO uint32_t DMA_WRITE_CH67_IMWR_DATA_OFF; /**< DMA Write Channel 7 and 6 IMWr Data Register., offset: 0x38007C */
uint8_t RESERVED_27[16];
__IO uint32_t DMA_WRITE_LINKED_LIST_ERR_EN_OFF; /**< DMA Write Linked List Error Enable Register., offset: 0x380090 */
uint8_t RESERVED_28[12];
__IO uint32_t DMA_READ_INT_STATUS_OFF; /**< DMA Read Interrupt Status Register., offset: 0x3800A0 */
uint8_t RESERVED_29[4];
__IO uint32_t DMA_READ_INT_MASK_OFF; /**< DMA Read Interrupt Mask Register., offset: 0x3800A8 */
__IO uint32_t DMA_READ_INT_CLEAR_OFF; /**< DMA Read Interrupt Clear Register., offset: 0x3800AC */
uint8_t RESERVED_30[4];
__I uint32_t DMA_READ_ERR_STATUS_LOW_OFF; /**< DMA Read Error Status Low Register., offset: 0x3800B4 */
__I uint32_t DMA_READ_ERR_STATUS_HIGH_OFF; /**< DMA Read Error Status High Register., offset: 0x3800B8 */
uint8_t RESERVED_31[8];
__IO uint32_t DMA_READ_LINKED_LIST_ERR_EN_OFF; /**< DMA Read Linked List Error Enable Register., offset: 0x3800C4 */
uint8_t RESERVED_32[4];
__IO uint32_t DMA_READ_DONE_IMWR_LOW_OFF; /**< DMA Read Done IMWr Address Low Register., offset: 0x3800CC */
__IO uint32_t DMA_READ_DONE_IMWR_HIGH_OFF; /**< DMA Read Done IMWr Address High Register., offset: 0x3800D0 */
__IO uint32_t DMA_READ_ABORT_IMWR_LOW_OFF; /**< DMA Read Abort IMWr Address Low Register., offset: 0x3800D4 */
__IO uint32_t DMA_READ_ABORT_IMWR_HIGH_OFF; /**< DMA Read Abort IMWr Address High Register., offset: 0x3800D8 */
__IO uint32_t DMA_READ_CH01_IMWR_DATA_OFF; /**< DMA Read Channel 1 and 0 IMWr Data Register., offset: 0x3800DC */
__IO uint32_t DMA_READ_CH23_IMWR_DATA_OFF; /**< DMA Read Channel 3 and 2 IMWr Data Register., offset: 0x3800E0 */
__IO uint32_t DMA_READ_CH45_IMWR_DATA_OFF; /**< DMA Read Channel 5 and 4 IMWr Data Register., offset: 0x3800E4 */
__IO uint32_t DMA_READ_CH67_IMWR_DATA_OFF; /**< DMA Read Channel 7 and 6 IMWr Data Register., offset: 0x3800E8 */
uint8_t RESERVED_33[276];
__IO uint32_t DMA_CH_CONTROL1_OFF_WRCH_0; /**< DMA Write Channel Control 1 Register., offset: 0x380200 */
uint8_t RESERVED_34[4];
__IO uint32_t DMA_TRANSFER_SIZE_OFF_WRCH_0; /**< DMA Write Transfer Size Register., offset: 0x380208 */
__IO uint32_t DMA_SAR_LOW_OFF_WRCH_0; /**< DMA Write SAR Low Register., offset: 0x38020C */
__IO uint32_t DMA_SAR_HIGH_OFF_WRCH_0; /**< DMA Write SAR High Register., offset: 0x380210 */
__IO uint32_t DMA_DAR_LOW_OFF_WRCH_0; /**< DMA Write DAR Low Register., offset: 0x380214 */
__IO uint32_t DMA_DAR_HIGH_OFF_WRCH_0; /**< DMA Write DAR High Register., offset: 0x380218 */
__IO uint32_t DMA_LLP_LOW_OFF_WRCH_0; /**< DMA Write Linked List Pointer Low Register., offset: 0x38021C */
__IO uint32_t DMA_LLP_HIGH_OFF_WRCH_0; /**< DMA Write Linked List Pointer High Register., offset: 0x380220 */
uint8_t RESERVED_35[220];
__IO uint32_t DMA_CH_CONTROL1_OFF_RDCH_0; /**< DMA Read Channel Control 1 Register., offset: 0x380300 */
uint8_t RESERVED_36[4];
__IO uint32_t DMA_TRANSFER_SIZE_OFF_RDCH_0; /**< DMA Read Transfer Size Register., offset: 0x380308 */
__IO uint32_t DMA_SAR_LOW_OFF_RDCH_0; /**< DMA Read SAR Low Register., offset: 0x38030C */
__IO uint32_t DMA_SAR_HIGH_OFF_RDCH_0; /**< DMA Read SAR High Register., offset: 0x380310 */
__IO uint32_t DMA_DAR_LOW_OFF_RDCH_0; /**< DMA Read DAR Low Register., offset: 0x380314 */
__IO uint32_t DMA_DAR_HIGH_OFF_RDCH_0; /**< DMA Read DAR High Register., offset: 0x380318 */
__IO uint32_t DMA_LLP_LOW_OFF_RDCH_0; /**< DMA Read Linked List Pointer Low Register., offset: 0x38031C */
__IO uint32_t DMA_LLP_HIGH_OFF_RDCH_0; /**< DMA Read Linked List Pointer High Register., offset: 0x380320 */
} PCIE_Type;
/* ----------------------------------------------------------------------------
-- PCIE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCIE_Register_Masks PCIE Register Masks
* @{
*/
/*! @name TYPE1_DEV_ID_VEND_ID_REG - Device ID and Vendor ID Register. */
/*! @{ */
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK (0xFFFFU)
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT (0U)
/*! VENDOR_ID - Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid
* vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to
* populate this register with a value of FFFFh, which is an invalid value for Vendor ID. Note:
* The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then
* R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_SHIFT)) & PCIE_TYPE1_DEV_ID_VEND_ID_REG_VENDOR_ID_MASK)
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK (0xFFFF0000U)
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT (16U)
/*! DEVICE_ID - Device ID. The Device ID register identifies the particular Function. This
* identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_SHIFT)) & PCIE_TYPE1_DEV_ID_VEND_ID_REG_DEVICE_ID_MASK)
/*! @} */
/*! @name TYPE1_STATUS_COMMAND_REG - Status and Command Register. */
/*! @{ */
#define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK (0x1U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT (0U)
/*! IO_EN - IO Space Enable. This bit controls a Function's response to I/O Space accesses received
* on its primary side. - When set, the Function is enabled to decode the address and further
* process I/O Space accesses. - When clear, all received I/O accesses are caused to be handled as
* Unsupported Requests. You cannot write to this register if your configuration has no IO bars;
* that is, the internal signal has_io_bar =0. Note: The access attributes of this field are as
* follows: - Dbi: !has_io_bar ? RO : RW
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_IO_EN_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MSE_MASK (0x2U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT (1U)
/*! MSE - Memory Space Enable. This bit controls a Function's response to Memory Space accesses
* received on its primary side. - When set, the Function is enabled to decode the address and
* further process Memory Space accesses. - When clear, all received Memory Space accesses are caused
* to be handled as Unsupported Requests. You cannot write to this register if your configuration
* has no MEM bars; that is, the internal signal has_mem_bar =0. Note: The access attributes of
* this field are as follows: - Dbi: !has_mem_bar ? RO : RW
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_MSE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MSE_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MSE_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_BME_MASK (0x4U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_BME_SHIFT (2U)
/*! BME - Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the
* Upstream direction. When this bit is 0b, Memory and I/O Requests received at a Root Port must
* be handled as Unsupported Requests (UR) For Non-Posted Requests a Completion with UR
* completion status must be returned. This bit does not affect forwarding of Completions in either the
* Upstream or Downstream direction. The forwarding of Requests other than Memory or I/O Requests
* is not controlled by this bit.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_BME(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_BME_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_BME_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SCO_MASK (0x8U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT (3U)
/*! SCO - Special Cycle Enable. This bit was originally described in the PCI Local Bus
* Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_SCO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SCO_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SCO_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK (0x10U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT (4U)
/*! MWI_EN - Memory Write and Invalidate. This bit was originally described in the PCI Local Bus
* Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not
* apply to PCI Express. The controller hardwires this bit to 0b. For PCI Express to PCI/PCI-X
* Bridges, refer to the PCI Express to PCI/PCI-X Bridge Specification for requirements for this
* register.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MWI_EN_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK (0x20U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT (5U)
/*! VGAPS - VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification
* and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI
* Express. The controller hardwires this bit to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_VGAPS_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_MASK (0x40U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT (6U)
/*! PERREN - Parity Error Response. This bit controls the logging of poisoned TLPs in the Master
* Data Parity Error bit in the Status register. For more details see the "Error Registers" section
* of the PCI Express Specification.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_PERREN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_PERREN_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK (0x80U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT (7U)
/*! IDSEL - IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local
* Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires
* this bit to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_IDSEL_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_MASK (0x100U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT (8U)
/*! SERREN - SERR# Enable. When set, this bit enables reporting upstream of Non-fatal and Fatal
* errors detected by the Function. Note: The errors are reported if enabled either through this bit
* or through the PCI Express specific bits in the Device Control register. For more details see
* the "Error Registers" section of the PCI Express Specification. In addition, this bit controls
* transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error Messages forwarded
* from the secondary interface. This bit does not affect the transmission of forwarded ERR_COR
* messages.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_SERREN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SERREN_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MASK (0x200U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SHIFT (9U)
/*! RSVDP_9 - Reserved for future use.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_9_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK (0x400U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT (10U)
/*! INT_EN - Interrupt Disable. Controls the ability of a Function to generate INTx emulation
* interrupts. When set, Functions are prevented from asserting INTx interrupts. Note: - Any INTx
* emulation interrupts already asserted by the Function must be deasserted when this bit is set. INTx
* interrupts use virtual wires that must, if asserted, be deasserted using the appropriate
* Deassert_INTx message(s) when this bit is set. - Only the INTx virtual wire interrupt(s)
* associated with the Function(s) for which this bit is set are affected. - For Functions that generate
* INTx interrupts on their own behalf, this bit is required. This bit has no effect on interrupts
* forwarded from the secondary side. For Functions that do not generate INTx interrupts on
* their own behalf this bit is optional. If this bit is not implemented, the controller hardwires it
* to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_INT_EN_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_MASK (0xF800U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT (11U)
/*! RESERV - Reserved.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RESERV_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MASK (0x60000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SHIFT (17U)
/*! RSVDP_17 - Reserved for future use.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_17_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK (0x80000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT (19U)
/*! INT_STATUS - Interrupt Status. When set, indicates that an INTx emulation interrupt is pending
* internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary
* side are not reflected in this bit. Setting the Interrupt Disable bit has no effect on the
* state of this bit. For Functions that do not generate INTx interrupts, the controller hardwires
* this bit to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_INT_STATUS_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK (0x100000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT (20U)
/*! CAP_LIST - Capabilities List. Indicates the presence of an Extended Capability list item. Since
* all PCI Express device Functions are required to implement the PCI Express Capability
* structure, the controller hardwires this bit to 1b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_CAP_LIST_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK (0x200000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT (21U)
/*! FAST_66MHZ_CAP - 66 MHz Capable. This bit was originally described in the PCI Local Bus
* Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to
* 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_FAST_66MHZ_CAP_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MASK (0x400000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SHIFT (22U)
/*! RSVDP_22 - Reserved for future use.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RSVDP_22_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK (0x800000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT (23U)
/*! FAST_B2B_CAP - Fast Back-to-Back Transactions Capable. This bit was originally described in the
* PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller
* hardwires this bit to 0b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_FAST_B2B_CAP_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK (0x1000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT (24U)
/*! MASTER_DPE - Master Data Parity Error. This bit is set by a Function if the Parity Error
* Response bit in the Command register is 1b and either of the following two conditions occurs: - Port
* receives a Poisoned Completion going downstream - Port transmits a Poisoned Request upstream
* If the Parity Error Response bit is 0b, this bit is never set.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_MASTER_DPE_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK (0x6000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT (25U)
/*! DEV_SEL_TIMING - DEVSEL Timing. This field was originally described in the PCI Local Bus
* Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_DEV_SEL_TIMING_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK (0x8000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT (27U)
/*! SIGNALED_TARGET_ABORT - Signaled Target Abort. This bit is set when a Function completes a
* Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the
* Completer Abort was generated by its primary side.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK (0x10000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT (28U)
/*! RCVD_TARGET_ABORT - Received Target Abort. This bit is set when a Requester receives a
* Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received
* by a Function's primary side.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK (0x20000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT (29U)
/*! RCVD_MASTER_ABORT - Received Master Abort. This bit is set when a Requester receives a
* Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is
* received by a Function's primary side.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK (0x40000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT (30U)
/*! SIGNALED_SYS_ERROR - Signaled System Error. This bit is set when a Function sends an ERR_FATAL
* or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1b.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_SIGNALED_SYS_ERROR_MASK)
#define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK (0x80000000U)
#define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT (31U)
/*! DETECTED_PARITY_ERROR - Detected Parity Error. This bit is set by a Function whenever it
* receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command
* register. The bit is set when the Poisoned TLP is received by a Function's primary side.
*/
#define PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_SHIFT)) & PCIE_TYPE1_STATUS_COMMAND_REG_DETECTED_PARITY_ERROR_MASK)
/*! @} */
/*! @name TYPE1_CLASS_CODE_REV_ID_REG - Class Code and Revision ID Register. */
/*! @{ */
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK (0xFFU)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT (0U)
/*! REVISION_ID - Revision ID. The value of this field specifies a Function specific revision
* identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should
* be viewed as a vendor defined extension to the Device ID. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This
* register field is sticky.
*/
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_REVISION_ID_MASK)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK (0xFF00U)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT (8U)
/*! PROGRAM_INTERFACE - Programming Interface. This field identifies a specific register level
* programming interface (if any) so that device independent software can interact with the Function.
* Encodings for interface are provided in the PCI Code and ID Assignment Specification. All
* unspecified encodings are reserved. Note: The access attributes of this field are as follows: -
* Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_PROGRAM_INTERFACE_MASK)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK (0xFF0000U)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT (16U)
/*! SUBCLASS_CODE - Sub-Class Code. Specifies a base class sub-class, which identifies more
* specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and
* ID Assignment Specification. All unspecified encodings are reserved. Note: The access
* attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
* Note: This register field is sticky.
*/
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_SUBCLASS_CODE_MASK)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK (0xFF000000U)
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT (24U)
/*! BASE_CLASS_CODE - Base Class Code. A code that broadly classifies the type of operation the
* Function performs. Encodings for base class, are provided in the PCI Code and ID Assignment
* Specification. All unspecified encodings are reserved. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register
* field is sticky.
*/
#define PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_SHIFT)) & PCIE_TYPE1_CLASS_CODE_REV_ID_REG_BASE_CLASS_CODE_MASK)
/*! @} */
/*! @name TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG - Header Type, Latency Timer, and Cache Line Size Register. */
/*! @{ */
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK (0xFFU)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT (0U)
/*! CACHE_LINE_SIZE - Cache Line Size. The Cache Line Size register is programmed by the system
* firmware or the operating system to system cache line size. However, legacy conventional PCI
* software may not always be able to program this register correctly especially in the case of
* Hot-Plug devices. This read-write register is implemented for legacy compatibility purposes but has
* no effect on any PCI Express device behavior.
*/
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_MASK)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK (0xFF00U)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT (8U)
/*! LATENCY_MASTER_TIMER - Latency Timer. This register is also referred to as Primary Latency
* Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the
* PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The
* controller hardwires this register to 00h.
*/
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_MASK)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK (0x7F0000U)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT (16U)
/*! HEADER_TYPE - Header Layout. This field identifies the layout of the second part of the
* predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This
* encoding was originally described in the PC Card Standard Electrical Specification and is used
* in previous versions of the programming model. Careful consideration should be given to any
* attempt to repurpose it.
*/
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_HEADER_TYPE_MASK)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK (0x800000U)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT (23U)
/*! MULTI_FUNC - Multi-Function Device. - When set, indicates that the device may contain multiple
* Functions, but not necessarily. Software is permitted to probe for Functions other than
* Function 0. - When clear, software must not probe for Functions other than Function 0 unless
* explicitly indicated by another mechanism, such as an ARI or SR-IOV Capability structure. Except where
* stated otherwise, it is recommended that this bit be set if there are multiple Functions, and
* clear if there is only one Function. Note: This register field is sticky.
*/
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_MULTI_FUNC_MASK)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK (0xFF000000U)
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT (24U)
/*! BIST - BIST. This register is used for control and status of BIST. Functions that do not support
* BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent
* normal operation of the PCI Express Link. Bit descriptions: - [31]: BIST Capable. When set, this
* bit indicates that the Function supports BIST. When Clear, the Function does not support BIST.
* - [30]: Start BIST. If BIST Capable is set, set this bit to invoke BIST. The Function resets
* the bit when BIST is complete. Software is permitted to fail the device if this bit is not
* Clear (BIST is not complete) 2 seconds after it had been set. Writing this bit to 0b has no
* effect. The controller hardwires this bit to 0b if BIST Capable is clear. - [29:28]: Reserved. -
* [27:24]: Completion Code. This field encodes the status of the most recent test. A value of
* 0000b means that the Function has passed its test. Non-zero values mean the Function failed.
* Function-specific failure codes can be encoded in the non-zero values. This field's value is only
* meaningful when BIST Capable is set and Start BIST is Clear. This field must be hardwired to
* 0000b if BIST Capable is clear.
*/
#define PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_SHIFT)) & PCIE_TYPE1_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG_BIST_MASK)
/*! @} */
/*! @name SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG - Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, and Primary Bus Number Register. */
/*! @{ */
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK (0xFFU)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT (0U)
/*! PRIM_BUS - Primary Bus Number. This register is not used by PCI Express Functions. It is
* implemented for compatibility with legacy software.
*/
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_PRIM_BUS_MASK)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK (0xFF00U)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT (8U)
/*! SEC_BUS - Secondary Bus Number. The Secondary Bus Number register is used to record the bus
* number of the PCI bus segment to which the secondary interface of the bridge is connected.
* Configuration software programs the value in this register. The bridge uses this register to
* determine when to respond to and convert a Type 1 configuration transaction on the primary interface
* into a Type 0 transaction on the secondary interface.
*/
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_BUS_MASK)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK (0xFF0000U)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT (16U)
/*! SUB_BUS - Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus
* number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
* Configuration software programs the value in this register. The bridge uses this register in
* conjunction with the Secondary Bus Number register to determine when to respond to and pass on
* a Type 1 configuration transaction on the primary interface to the secondary interface.
*/
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SUB_BUS_MASK)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK (0xFF000000U)
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT (24U)
/*! SEC_LAT_TIMER - Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h.
*/
#define PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_SHIFT)) & PCIE_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG_SEC_LAT_TIMER_MASK)
/*! @} */
/*! @name SEC_STAT_IO_LIMIT_IO_BASE_REG - Secondary Status, and I/O Limit and Base Register. */
/*! @{ */
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK (0x1U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT (0U)
/*! IO_DECODE - I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing
* capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O
* addressing (for ISA compatibility). For the purpose of address decoding, the bridge assumes
* that the upper 16 address bits, Address[31:16], of the I/O base address (not implemented in I/O
* base register) are zero. Note: The bridge must still perform a full 32-bit decode of the I/O
* address (that is, check that Address[31:16] are 0000h). In this case, the I/O address range
* supported by the bridge will be restricted to the first 64 KB of I/O Space (0000 0000h to 0000
* FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Base Upper 16 Bits
* hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Base address. In this
* case, system configuration software is permitted to locate the I/O address range supported by
* the bridge anywhere in the 4-GB I/O Space. Note: The 4-KB alignment and granularity restrictions
* still apply when the bridge supports 32-bit I/O addressing. Note: The access attributes of
* this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK (0xEU)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT (1U)
/*! IO_RESERV - Reserved.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK (0xF0U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT (4U)
/*! IO_BASE - I/O Base Address. These bits correspond to the address[15:12] of IO address range. For
* the purpose of address decoding, the bridge assumes that the lower 12 address bits,
* address[11:0], of the I/O base address (not implemented in the I/O Base register) are zero.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_BASE_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK (0x100U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT (8U)
/*! IO_DECODE_BIT8 - I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing
* capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only
* 16-bit I/O addressing (for ISA compatibility). For the purpose of address decoding, the
* bridge assumes that the upper 16 address bits, Address[31:16], of the I/O limit address (not
* implemented in I/O Limit register) are zero. Note: The bridge must still perform a full 32-bit
* decode of the I/O address (that is, check that Address[31:16] are 0000h). In this case, the I/O
* address range supported by the bridge will be restricted to the first 64 KB of I/O Space (0000
* 0000h to 0000 FFFFh). - 01h: The bridge supports 32-bit I/O address decoding, and the I/O Limit
* Upper 16 Bits hold the upper 16 bits, corresponding to Address[31:16], of the 32-bit Limit
* address. In this case, system configuration software is permitted to locate the I/O address range
* supported by the bridge anywhere in the 4-GB I/O Space. Note: The 4-KB alignment and
* granularity restrictions still apply when the bridge supports 32-bit I/O addressing. Note: The access
* attributes of this field are as follows: - Dbi: R
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_DECODE_BIT8_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK (0xE00U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT (9U)
/*! IO_RESERV1 - Reserved.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_RESERV1_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK (0xF000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT (12U)
/*! IO_LIMIT - I/O Limit Address. These bits correspond to the address[15:12] of IO address range.
* For the purpose of address decoding, the bridge assumes that the lower 12 address bits,
* address[11:0], of the I/O limit address (not implemented in the I/O Limit register) are FFFh. The I/O
* Limit register can be programmed to a smaller value than the I/O Base register, if there are
* no I/O addresses on the secondary side of the bridge. In this case, the bridge will not
* forward any I/O transactions from the primary bus to the secondary and will forward all I/O
* transactions from the secondary bus to the primary bus.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_IO_LIMIT_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK (0x7F0000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT (16U)
/*! SEC_STAT_RESERV - Reserved.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RESERV_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MASK (0x800000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SHIFT (23U)
/*! RSVDP_23 - Reserved for future use.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_23_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK (0x1000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT (24U)
/*! SEC_STAT_MDPE - Master Data Parity Error. This bit is set by a Function if the Parity Error
* Response Enable bit in the Bridge Control register is set, and either of the following two
* conditions occurs: - Port receives a Poisoned Completion coming Upstream - Port transmits a Poisoned
* Request Downstream If the Parity Error Response Enable bit is clear, this bit is never set.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_MDPE_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MASK (0x6000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SHIFT (25U)
/*! RSVDP_25 - Reserved for future use.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_RSVDP_25_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK (0x8000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT (27U)
/*! SEC_STAT_SIG_TRGT_ABRT - Signaled Target Abort. This bit is set when the secondary side of the
* Function (for Requests completed by the Type 1 header Function itself) completes a Posted or
* Non-Posted request as a Completer Abort error.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_SIG_TRGT_ABRT_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK (0x10000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT (28U)
/*! SEC_STAT_RCVD_TRGT_ABRT - Received Target Abort. This bit is set when the secondary side of a
* Function (for requests initiated by the Type 1 header Function itself) receives a Completion
* with Completer Abort Completion status.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_TRGT_ABRT_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK (0x20000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT (29U)
/*! SEC_STAT_RCVD_MSTR_ABRT - Received Master Abort. This bit is set when the secondary side of a
* Function (for requests initiated by the Type 1 header Function itself) receives a Completion
* with Unsupported Request Completion status.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_MSTR_ABRT_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK (0x40000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT (30U)
/*! SEC_STAT_RCVD_SYS_ERR - Received System Error. This bit is set when the secondary side of a
* Function receives an ERR_FATAL or ERR_NONFATAL message.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_RCVD_SYS_ERR_MASK)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK (0x80000000U)
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT (31U)
/*! SEC_STAT_DPE - Detected Parity Error. This bit is set by a Function when a Poisoned TLP is
* received by its secondary side, regardless of the state the Parity Error Response Enable bit in the
* Bridge Control register.
*/
#define PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_SHIFT)) & PCIE_SEC_STAT_IO_LIMIT_IO_BASE_REG_SEC_STAT_DPE_MASK)
/*! @} */
/*! @name MEM_LIMIT_MEM_BASE_REG - Memory Limit and Base Register. */
/*! @{ */
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK (0xFU)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT (0U)
/*! MEM_BASE_RESERV - Reserved.
*/
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_RESERV_MASK)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK (0xFFF0U)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT (4U)
/*! MEM_BASE - Memory Base Address. These bits correspond to the upper 12 address bits,
* Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the
* lower 20 address bits, Address[19:0], of the memory base address (not implemented in the Memory
* Base register) are zero.
*/
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_BASE_MASK)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK (0xF0000U)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT (16U)
/*! MEM_LIMIT_RESERV - Reserved.
*/
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_RESERV_MASK)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK (0xFFF00000U)
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT (20U)
/*! MEM_LIMIT - Memory Limit Address. These bits correspond to the upper 12 address bits,
* Address[31:20], of 32-bit addresses. For the purpose of address decoding, the bridge assumes that the
* lower 20 address bits, Address[19:0], of the memory limit address (not implemented in the Memory
* Limit register) are F FFFFh. The Memory Limit register must be programmed to a smaller value
* than the Memory Base register if there is no memory-mapped address space on the secondary side
* of the bridge.
*/
#define PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_SHIFT)) & PCIE_MEM_LIMIT_MEM_BASE_REG_MEM_LIMIT_MASK)
/*! @} */
/*! @name PREF_MEM_LIMIT_PREF_MEM_BASE_REG - Prefetchable Memory Limit and Base Register. */
/*! @{ */
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK (0x1U)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT (0U)
/*! PREF_MEM_DECODE - Prefetchable Memory Base Decode. This bit encodes whether or not the bridge
* supports 64-bit addresses. The value of PREF_MEM_DECODE indicates the following: - 0b: Indicates
* that the bridge supports only 32 bit addresses. - 1b: Indicates that the bridge supports 64
* bit addresses. Prefetchable Base Upper 32 Bits registers holds the rest of the 64-bit
* prefetchable base address. Note: The access attributes of this field are as follows: - Dbi: if
* (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_DECODE_MASK)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK (0xEU)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT (1U)
/*! PREF_RESERV - Reserved.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV_MASK)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK (0xFFF0U)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT (4U)
/*! PREF_MEM_BASE - Prefetchable Memory Base Address. If the Prefetchable Memory Base register
* indicates support for 32-bit addressing, then the Prefetchable Base Upper 32 Bits register is
* implemented as a read-only register that returns zero when read. If the Prefetchable Memory Base
* register indicates support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits
* register is implemented as a read/write register which must be initialized by configuration
* software. If a 64-bit prefetchable memory address range is supported, the Prefetchable Base Upper 32
* Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the 64-bit
* base addresses which specify the prefetchable memory address range.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_BASE_MASK)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK (0x10000U)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT (16U)
/*! PREF_MEM_LIMIT_DECODE - Prefetchable Memory Limit Decode. This bit encodes whether or not the
* bridge supports 64-bit addresses. The value of PREF_MEM_LIMIT_DECODE indicates the following: -
* 0b: Indicates that the bridge supports only 32 bit addresses - 1b: Indicates that the bridge
* supports 64 bit addresses. Prefetchable Limit Upper 32 Bits registers holds the rest of the
* 64-bit prefetchable limit address.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_DECODE_MASK)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK (0xE0000U)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT (17U)
/*! PREF_RESERV1 - Reserved.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_RESERV1_MASK)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK (0xFFF00000U)
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT (20U)
/*! PREF_MEM_LIMIT - Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register
* indicates support for 32-bit addressing, then the Prefetchable Limit Upper 32 Bits register is
* implemented as a read-only register that returns zero when read. If the Prefetchable Memory
* Limit registers indicate support for 64-bit addressing, then the Prefetchable Limit Upper 32 Bits
* register is implemented as a read/write register which must be initialized by configuration
* software. If a 64-bit prefetchable memory address range is supported, the Prefetchable Limit
* Upper 32 Bits register specifies the upper 32 bits, corresponding to Address[63:32], of the
* 64-bit limit addresses which specify the prefetchable memory address range.
*/
#define PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_SHIFT)) & PCIE_PREF_MEM_LIMIT_PREF_MEM_BASE_REG_PREF_MEM_LIMIT_MASK)
/*! @} */
/*! @name PREF_BASE_UPPER_REG - Prefetchable Base Upper 32 Bits Register. */
/*! @{ */
#define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK (0xFFFFFFFFU)
#define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT (0U)
/*! PREF_MEM_BASE_UPPER - Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register
* indicates support for 32-bit addressing, then this register is implemented as read-only
* register that returns zero when read. If the Prefetchable Memory Base register indicate support for
* 64-bit addressing, then this register is implemented as read/write register which must be
* initialized by configuration software. This register specifies the upper 32 bits, corresponding to
* Address[63:32], of the 64-bit base addresses which specify the prefetchable memory address
* range. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1)
* then R/W else R
*/
#define PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_SHIFT)) & PCIE_PREF_BASE_UPPER_REG_PREF_MEM_BASE_UPPER_MASK)
/*! @} */
/*! @name PREF_LIMIT_UPPER_REG - Prefetchable Limit Upper 32 Bits Register. */
/*! @{ */
#define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK (0xFFFFFFFFU)
#define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT (0U)
/*! PREF_MEM_LIMIT_UPPER - Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit
* register indicate support for 64-bit addressing, then this register is implemented as read/write
* register which must be initialized by configuration software. This register specifies the upper 32
* bits, corresponding to Address[63:32], of the 64-bit base addresses which specify the
* prefetchable memory address range. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_SHIFT)) & PCIE_PREF_LIMIT_UPPER_REG_PREF_MEM_LIMIT_UPPER_MASK)
/*! @} */
/*! @name IO_LIMIT_UPPER_IO_BASE_UPPER_REG - I/O Limit and Base Upper 16 Bits Register. */
/*! @{ */
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK (0xFFFFU)
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT (0U)
/*! IO_BASE_UPPER - I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit
* I/O address decoding, then this register is implemented as a read-only register which return
* zero when read. If the I/O base register indicates support for 32-bit I/O addressing, then this
* register must be initialized by configuration software. If 32-bit I/O address decoding is
* supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the
* 32-bit base address, that specify the I/O address range. See the PCI-to-PCI Bridge Architecture
* Specification for additional details. Note: The access attributes of this field are as follows: -
* Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_SHIFT)) & PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_BASE_UPPER_MASK)
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK (0xFFFF0000U)
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT (16U)
/*! IO_LIMIT_UPPER - I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit
* I/O address decoding, then this register is implemented as a read-only register which return
* zero when read. If the I/O Limit register indicates support for 32-bit I/O addressing, then
* this register must be initialized by configuration software. If 32-bit I/O address decoding is
* supported, this register specifies the upper 16 bits, corresponding to Address[31:16], of the
* 32-bit limit address, that specify the I/O address range. See the PCI-to-PCI Bridge
* Architecture Specification for additional details). Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_SHIFT)) & PCIE_IO_LIMIT_UPPER_IO_BASE_UPPER_REG_IO_LIMIT_UPPER_MASK)
/*! @} */
/*! @name TYPE1_CAP_PTR_REG - Capabilities Pointer Register. */
/*! @{ */
#define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK (0xFFU)
#define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT (0U)
/*! CAP_POINTER - Capabilities Pointer. This register is used to point to a linked list of
* capabilities implemented by this Function. Since all PCI Express Functions are required to implement
* the PCI Express Capability structure, this register must point to a valid capability structure
* and either this structure is the PCI Express Capability structure, or a subsequent list item
* points to the PCI Express Capability structure. The bottom two bits are Reserved and must be set
* to 00b. Software must mask these bits off before using this register as a pointer in
* Configuration Space to the first entry of a linked list of new capabilities. Note: The access
* attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
* Note: This register field is sticky.
*/
#define PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_SHIFT)) & PCIE_TYPE1_CAP_PTR_REG_CAP_POINTER_MASK)
#define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_MASK (0xFFFFFF00U)
#define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_TYPE1_CAP_PTR_REG_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_SHIFT)) & PCIE_TYPE1_CAP_PTR_REG_RSVDP_8_MASK)
/*! @} */
/*! @name TYPE1_EXP_ROM_BASE_REG - Expansion ROM Base Address Register. */
/*! @{ */
#define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK (0x1U)
#define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT (0U)
/*! ROM_BAR_ENABLE - Expansion ROM Enable. This bit controls whether or not the Function accepts
* accesses to its expansion ROM. When this bit is 0b, the Function's expansion ROM address space is
* disabled. When the bit is 1b, address decoding is enabled using the parameters in the other
* part of the Expansion ROM Base Address register. The Memory Space Enable bit in the Command
* register has precedence over the Expansion ROM Enable bit. A Function must claim accesses to its
* expansion ROM only if both the Memory Space Enable bit and the Expansion ROM Enable bit are
* set. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_ROM_BAR_ENABLE_MASK)
#define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MASK (0x7FEU)
#define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_RSVDP_1_MASK)
#define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK (0xFFFFF800U)
#define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT (11U)
/*! EXP_ROM_BASE_ADDRESS - Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base
* address. The number of bits (out of these 21) that a Function actually implements depends on how
* much address space the Function requires. The mask for this ROM BAR exists (if implemented) as a
* shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or
* the CS2 address bit for the AXI bridge) is required to write to the second register at this
* address. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_SHIFT)) & PCIE_TYPE1_EXP_ROM_BASE_REG_EXP_ROM_BASE_ADDRESS_MASK)
/*! @} */
/*! @name BRIDGE_CTRL_INT_PIN_INT_LINE_REG - Bridge Control, Interrupt Pin, and Interrupt Line Register. */
/*! @{ */
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK (0xFFU)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT (0U)
/*! INT_LINE - Interrupt Line. The Interrupt Line register communicates interrupt line routing
* information. The register must be implemented by any Function that uses an interrupt pin. Values in
* this register are programmed by system software and are system architecture specific. The
* Function itself does not use this value; rather the value in this register is used by device
* drivers and operating systems.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_LINE_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK (0xFF00U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT (8U)
/*! INT_PIN - Interrupt PIN. The Interrupt Pin register register that identifies the legacy
* interrupt Message(s) the Function uses. Valid values are: - 01h, 02h, 03h, and 04h: map to legacy
* interrupt Messages for INTA, INTB, INTC, and INTD respectively. - 00h: indicates that the Function
* uses no legacy interrupt Message(s). - 05h through FFh: Reserved. PCI Express defines one
* legacy interrupt Message for a single Function device and up to four legacy interrupt Messages
* for a multi-Function device. For a single Function device, only INTA may be used. Any Function
* on a multi-Function device can use any of the INTx Messages. If a device implements a single
* legacy interrupt Message, it must be INTA; if it implements two legacy interrupt Messages, they
* must be INTA and INTB; and so forth. For a multi-Function device, all Functions may use the
* same INTx Message or each may have its own (up to a maximum of four Functions) or any
* combination thereof. A single Function can never generate an interrupt request on more than one INTx
* Message. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1)
* then R/W else R Note: This register field is sticky.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_INT_PIN_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK (0x10000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT (16U)
/*! PERE - Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the
* Master Data Parity Error bit in the Secondary Status register.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_PERE_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK (0x20000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT (17U)
/*! SERR_EN - SERR# Enable. This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL from secondary to primary.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SERR_EN_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK (0x40000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT (18U)
/*! ISA_EN - ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only
* to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the
* first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge will
* block any forwarding from primary to secondary of I/O transactions addressing the last 768
* bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions will
* be forwarded if they address the last 768 bytes in each 1-KB block. The following actions are
* taken based on the value of the ISA_EN bit: - 0b: Forward downstream all I/O addresses in the
* address range defined by the I/O Base and I/O Limit registers - 1b: Forward upstream ISA I/O
* addresses in the address range defined by the I/O Base and I/O Limit registers that are in the
* first 64 KB of PCI I/O address space (top 768 bytes of each 1-KB block.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_ISA_EN_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK (0x80000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT (19U)
/*! VGA_EN - VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA
* Enable bit is set, the bridge will positively decode and forward the following accesses on
* the primary interface to the secondary interface (and, conversely, block the forwarding of these
* addresses from the secondary to primary interface): - Memory accesses in the range 000A 0000h
* to 000B FFFFh - I/O addresses in the first 64 KB of the I/O address space (Address[31:16] are
* 0000h) where Address[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA
* address aliases determined by the setting of VGA 16-bit Decode ) If the VGA Enable bit is set,
* forwarding of these accesses is independent of the I/O address range and memory address ranges
* defined by the I/O Base and Limit registers, the Memory Base and Limit registers, and the
* Prefetchable Memory Base and Limit registers of the bridge. (Forwarding of these accesses is also
* independent of the setting of the ISA Enable bit (in the Bridge Control register) when the
* VGA Enable bit is set. Forwarding of these accesses is qualified by the I/O Space Enable and
* Memory Space Enable bits in the Command register.) The following actions are taken based on the
* value of the VGA_EN bit: - 0b: Do not forward VGA compatible memory and I/O addresses from the
* primary to the secondary interface (addresses defined above) unless they are enabled for
* forwarding by the defined I/O and memory address ranges - 1b: Forward VGA compatible memory and I/O
* addresses (addresses defined above) from the primary interface to the secondary interface (if
* the I/O Space Enable and Memory Space Enable bits are set) independent of the I/O and memory
* address ranges and independent of the ISA Enable bit For Functions that do not support VGA,
* the controller hardwires this bit to 0b. Note: The access attributes of this field are as
* follows: - Dbi: R
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_EN_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK (0x100000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT (20U)
/*! VGA_16B_DEC - VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit
* enables system configuration software to select between 10-bit and 16-bit I/O address decoding
* for all VGA I/O register accesses that are forwarded from primary to secondary. The following
* actions are taken based on the value of the VGA_16B_DEC bit: - 0b: Execute 10-bit address
* decodes on VGA I/O accesses - 1b: Execute 16-bit address decodes on VGA I/O accesses For Functions
* that do not support VGA, the controller hardwires this bit to 0b. Note: The access attributes
* of this field are as follows: - Dbi: R
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_VGA_16B_DEC_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK (0x200000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT (21U)
/*! MSTR_ABORT_MODE - Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge
* Architecture Specification. Its functionality does not apply to PCI Express. The controller
* hardwires this bit to 0b. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_MSTR_ABORT_MODE_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK (0x400000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT (22U)
/*! SBR - Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI
* Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus
* Specification. Software and systems must honor first-access-following-reset timing
* requirements, unless the Readiness Notifications mechanism is used or if the Immediate Readiness bit in
* the relevant Function's Status Register register is set. Port configuration registers must not
* be changed, except as required to update Port status.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_SBR_MASK)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK (0xFF800000U)
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT (23U)
/*! BRIDGE_CTRL_RESERV - Reserved.
*/
#define PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV(x) (((uint32_t)(((uint32_t)(x)) << PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_SHIFT)) & PCIE_BRIDGE_CTRL_INT_PIN_INT_LINE_REG_BRIDGE_CTRL_RESERV_MASK)
/*! @} */
/*! @name CAP_ID_NXT_PTR_REG - Power Management Capabilities Register. */
/*! @{ */
#define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK (0xFFU)
#define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT (0U)
/*! PM_CAP_ID - Power Management Capability ID. For a description of this standard PCIe register
* field, see the PCI Express Specification.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_CAP_ID_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK (0xFF00U)
#define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT (8U)
/*! PM_NEXT_POINTER - Next Capability Pointer. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK (0x70000U)
#define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT (16U)
/*! PM_SPEC_VER - Power Management Spec Version. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_MASK (0x80000U)
#define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT (19U)
/*! PME_CLK - PCI Clock Requirement. For a description of this standard PCIe register field, see the
* PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_PME_CLK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PME_CLK_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_DSI_MASK (0x200000U)
#define PCIE_CAP_ID_NXT_PTR_REG_DSI_SHIFT (21U)
/*! DSI - Device Specific Initialization Bit. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as follows:
* - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_DSI(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_DSI_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_DSI_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK (0x1C00000U)
#define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT (22U)
/*! AUX_CURR - Auxiliary Current Requirements. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_AUX_CURR_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK (0x2000000U)
#define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT (25U)
/*! D1_SUPPORT - D1 State Support. For a description of this standard PCIe register field, see the
* PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
* (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_D1_SUPPORT_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK (0x4000000U)
#define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT (26U)
/*! D2_SUPPORT - D2 State Support. For a description of this standard PCIe register field, see the
* PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
* (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_D2_SUPPORT_MASK)
#define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK (0xF8000000U)
#define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT (27U)
/*! PME_SUPPORT - Power Management Event Support. For a description of this standard PCIe register
* field, see the PCI Express Specification. The read value from this field is the write value &&
* (sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1), where D1_SUPPORT and D2_SUPPORT are
* fields in this register. The reset value PME_SUPPORT_n && (sys_aux_pwr_det, 1'b1, D2_SUPPORT,
* D1_SUPPORT, 1'b1), where PME_SUPPORT_n is a configuration parameter. Note: The access attributes
* of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
* register field is sticky.
*/
#define PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT)) & PCIE_CAP_ID_NXT_PTR_REG_PME_SUPPORT_MASK)
/*! @} */
/*! @name CON_STATUS_REG - Power Management Control and Status Register. */
/*! @{ */
#define PCIE_CON_STATUS_REG_POWER_STATE_MASK (0x3U)
#define PCIE_CON_STATUS_REG_POWER_STATE_SHIFT (0U)
/*! POWER_STATE - Power State. For a description of this standard PCIe register field, see the PCI
* Express Specification. You can write to this register. However, the read-back value is the
* actual power state, not the write value. Note: The access attributes of this field are as follows:
* - Dbi: R/W
*/
#define PCIE_CON_STATUS_REG_POWER_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_POWER_STATE_SHIFT)) & PCIE_CON_STATUS_REG_POWER_STATE_MASK)
#define PCIE_CON_STATUS_REG_RSVDP_2_MASK (0x4U)
#define PCIE_CON_STATUS_REG_RSVDP_2_SHIFT (2U)
/*! RSVDP_2 - Reserved for future use.
*/
#define PCIE_CON_STATUS_REG_RSVDP_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_2_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_2_MASK)
#define PCIE_CON_STATUS_REG_NO_SOFT_RST_MASK (0x8U)
#define PCIE_CON_STATUS_REG_NO_SOFT_RST_SHIFT (3U)
/*! NO_SOFT_RST - No soft Reset. For a description of this standard PCIe register field, see the PCI
* Express Specification. Note: The access attributes of this field are as follows: - Dbi: if
* (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_CON_STATUS_REG_NO_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_NO_SOFT_RST_SHIFT)) & PCIE_CON_STATUS_REG_NO_SOFT_RST_MASK)
#define PCIE_CON_STATUS_REG_RSVDP_4_MASK (0xF0U)
#define PCIE_CON_STATUS_REG_RSVDP_4_SHIFT (4U)
/*! RSVDP_4 - Reserved for future use.
*/
#define PCIE_CON_STATUS_REG_RSVDP_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_4_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_4_MASK)
#define PCIE_CON_STATUS_REG_PME_ENABLE_MASK (0x100U)
#define PCIE_CON_STATUS_REG_PME_ENABLE_SHIFT (8U)
/*! PME_ENABLE - PME Enable. For a description of this standard PCIe register field, see the PCI
* Express Specification. The PMC registers this value under aux power. Sometimes it might remember
* the old value, even if you try to clear it by writing '0'. Note: This register field is sticky.
*/
#define PCIE_CON_STATUS_REG_PME_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_PME_ENABLE_SHIFT)) & PCIE_CON_STATUS_REG_PME_ENABLE_MASK)
#define PCIE_CON_STATUS_REG_DATA_SELECT_MASK (0x1E00U)
#define PCIE_CON_STATUS_REG_DATA_SELECT_SHIFT (9U)
/*! DATA_SELECT - Data Select. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_SELECT_SHIFT)) & PCIE_CON_STATUS_REG_DATA_SELECT_MASK)
#define PCIE_CON_STATUS_REG_DATA_SCALE_MASK (0x6000U)
#define PCIE_CON_STATUS_REG_DATA_SCALE_SHIFT (13U)
/*! DATA_SCALE - Data Scaling Factor. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_SCALE_SHIFT)) & PCIE_CON_STATUS_REG_DATA_SCALE_MASK)
#define PCIE_CON_STATUS_REG_PME_STATUS_MASK (0x8000U)
#define PCIE_CON_STATUS_REG_PME_STATUS_SHIFT (15U)
/*! PME_STATUS - PME Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_PME_STATUS_SHIFT)) & PCIE_CON_STATUS_REG_PME_STATUS_MASK)
#define PCIE_CON_STATUS_REG_RSVDP_16_MASK (0x3F0000U)
#define PCIE_CON_STATUS_REG_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_CON_STATUS_REG_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_RSVDP_16_SHIFT)) & PCIE_CON_STATUS_REG_RSVDP_16_MASK)
#define PCIE_CON_STATUS_REG_B2_B3_SUPPORT_MASK (0x400000U)
#define PCIE_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT (22U)
/*! B2_B3_SUPPORT - B2B3 Support for D3hot. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_B2_B3_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT)) & PCIE_CON_STATUS_REG_B2_B3_SUPPORT_MASK)
#define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK (0x800000U)
#define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT (23U)
/*! BUS_PWR_CLK_CON_EN - Bus Power/Clock Control Enable. For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT)) & PCIE_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_MASK)
#define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK (0xFF000000U)
#define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT (24U)
/*! DATA_REG_ADD_INFO - Power Data Information Register. For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT)) & PCIE_CON_STATUS_REG_DATA_REG_ADD_INFO_MASK)
/*! @} */
/*! @name PCI_MSI_CAP_ID_NEXT_CTRL_REG - MSI Capability ID, Next Pointer, Capability/Control Registers. */
/*! @{ */
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK (0xFFU)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT (0U)
/*! PCI_MSI_CAP_ID - MSI Capability ID. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK (0xFF00U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT (8U)
/*! PCI_MSI_CAP_NEXT_OFFSET - MSI Capability Next Pointer. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
* sticky.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK (0x10000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT (16U)
/*! PCI_MSI_ENABLE - MSI Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK (0xE0000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT (17U)
/*! PCI_MSI_MULTIPLE_MSG_CAP - MSI Multiple Message Capable. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
* sticky.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK (0x700000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT (20U)
/*! PCI_MSI_MULTIPLE_MSG_EN - MSI Multiple Message Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK (0x800000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT (23U)
/*! PCI_MSI_64_BIT_ADDR_CAP - MSI 64-bit Address Capable. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK (0x1000000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT (24U)
/*! PCI_PVM_SUPPORT - MSI Per Vector Masking Capable. For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK (0x2000000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT (25U)
/*! PCI_MSI_EXT_DATA_CAP - Extended Message Data Capable. For a description of this standard PCIe
* register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express
* Specification. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN ==
* 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_CAP_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK (0x4000000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT (26U)
/*! PCI_MSI_EXT_DATA_EN - Extended Message Data Enable. For a description of this standard PCIe
* register, see the PCI-SIG ECN for Extended MSI Data, Feb 24, 2016, affecting PCI Express
* Specification. Note: The access attributes of this field are as follows: - Dbi:
* PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_MSI_EXT_DATA_CAP ? RW : RO
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_EXT_DATA_EN_MASK)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MASK (0xF8000000U)
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT (27U)
/*! RSVDP_27 - Reserved for future use.
*/
#define PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT)) & PCIE_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_27_MASK)
/*! @} */
/*! @name MSI_CAP_OFF_04H_REG - MSI Message Lower Address Register. */
/*! @{ */
#define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_MASK (0x3U)
#define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_SHIFT)) & PCIE_MSI_CAP_OFF_04H_REG_RSVDP_0_MASK)
#define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK (0xFFFFFFFCU)
#define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT (2U)
/*! PCI_MSI_CAP_OFF_04H - MSI Message Lower Address Field. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: R/W
*/
#define PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT)) & PCIE_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_MASK)
/*! @} */
/*! @name MSI_CAP_OFF_08H_REG - For a 32 bit MSI Message, this register contains Data. */
/*! @{ */
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK (0xFFFFU)
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT (0U)
/*! PCI_MSI_CAP_OFF_08H - For a 32-bit MSI Message, this field contains Data. For 64-bit it contains
* lower 16 bits of the Upper Address. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
*/
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT)) & PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_MASK)
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK (0xFFFF0000U)
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT (16U)
/*! PCI_MSI_CAP_OFF_0AH - For a 32 bit MSI Message, this field contains Ext MSI Data. For 64-bit it
* contains upper 16 bits of the Upper Address. For a description of this standard PCIe register
* field, see the PCI Express Specification Note: The access attributes of this field are as
* follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP || `DEFAULT_EXT_MSI_DATA_CAPABLE ? R/W : R
*/
#define PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT)) & PCIE_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_MASK)
/*! @} */
/*! @name MSI_CAP_OFF_0CH_REG - For a 64 bit MSI Message, this register contains Data. */
/*! @{ */
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK (0xFFFFU)
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT (0U)
/*! PCI_MSI_CAP_OFF_0CH - For a 64-bit MSI Message, this field contains Data. For 32-bit, it
* contains the lower Mask Bits if PVM is enabled. For a description of this standard PCIe register
* field, see the PCI Express Specification Note: The access attributes of this field are as follows:
* - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R
*/
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT)) & PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_MASK)
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK (0xFFFF0000U)
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT (16U)
/*! PCI_MSI_CAP_OFF_0EH - For a 64-bit MSI Message, this field contains Data. For 32-bit, it
* contains the upper Mask Bits if PVM is enabled. For a description of this standard PCIe register
* field, see the PCI Express Specification Note: The access attributes of this field are as follows:
* - Dbi: (!MSI_64_EN && MSI_PVM_EN_VALUE) ? RW: MSI_64_EN && DEFAULT_EXT_MSI_DATA_CAPABLE ? RW
* : RO
*/
#define PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT)) & PCIE_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_MASK)
/*! @} */
/*! @name MSI_CAP_OFF_10H_REG - Used for MSI when Vector Masking Capable. */
/*! @{ */
#define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT (0U)
/*! PCI_MSI_CAP_OFF_10H - Used for MSI when Vector Masking Capable. For 32-bit contains Pending
* Bits. For 64-bit, contains Mask Bits. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R
*/
#define PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_SHIFT)) & PCIE_MSI_CAP_OFF_10H_REG_PCI_MSI_CAP_OFF_10H_MASK)
/*! @} */
/*! @name MSI_CAP_OFF_14H_REG - Used for MSI 64 bit messaging when Vector Masking Capable. */
/*! @{ */
#define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT (0U)
/*! PCI_MSI_CAP_OFF_14H - Used for MSI 64-bit messaging when Vector Masking Capable. Contains
* Pending Bits. For a description of this standard PCIe register field, see the PCI Express
* Specification.
*/
#define PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_SHIFT)) & PCIE_MSI_CAP_OFF_14H_REG_PCI_MSI_CAP_OFF_14H_MASK)
/*! @} */
/*! @name PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG - PCI Express Capabilities, ID, Next Pointer Register. */
/*! @{ */
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK (0xFFU)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT (0U)
/*! PCIE_CAP_ID - PCIE Capability ID. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK (0xFF00U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT (8U)
/*! PCIE_CAP_NEXT_PTR - PCIE Next Capability Pointer. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK (0xF0000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT (16U)
/*! PCIE_CAP_REG - PCIE Capability Version Number. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK (0xF00000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT (20U)
/*! PCIE_DEV_PORT_TYPE - PCIE Device/PortType. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK (0x1000000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT (24U)
/*! PCIE_SLOT_IMP - PCIe Slot Implemented Valid. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK (0x3E000000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT (25U)
/*! PCIE_INT_MSG_NUM - PCIE Interrupt Message Number. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK (0x40000000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT (30U)
/*! RSVD - Reserved. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_MASK)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MASK (0x80000000U)
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT (31U)
/*! RSVDP_31 - Reserved for future use.
*/
#define PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT)) & PCIE_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_MASK)
/*! @} */
/*! @name DEVICE_CAPABILITIES_REG - Device Capabilities Register. */
/*! @{ */
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK (0x7U)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT (0U)
/*! PCIE_CAP_MAX_PAYLOAD_SIZE - Max Payload Size Supported. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
* sticky.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_MASK)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK (0x18U)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT (3U)
/*! PCIE_CAP_PHANTOM_FUNC_SUPPORT - Phantom Functions Supported. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is
* sticky.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK (0x20U)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT (5U)
/*! PCIE_CAP_EXT_TAG_SUPP - Extended Tag Field Supported. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_MASK (0x7FC0U)
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_SHIFT (6U)
/*! RSVDP_6 - Reserved for future use.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_RSVDP_6_MASK)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK (0x8000U)
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT (15U)
/*! PCIE_CAP_ROLE_BASED_ERR_REPORT - Role-based Error Reporting Implemented. For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: The access
* attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
* register field is sticky.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_MASK (0xFFFF0000U)
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT)) & PCIE_DEVICE_CAPABILITIES_REG_RSVDP_16_MASK)
/*! @} */
/*! @name DEVICE_CONTROL_DEVICE_STATUS - Device Control and Status Register. */
/*! @{ */
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK (0x1U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT (0U)
/*! PCIE_CAP_CORR_ERR_REPORT_EN - Correctable Error Reporting Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK (0x2U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT (1U)
/*! PCIE_CAP_NON_FATAL_ERR_REPORT_EN - Non-fatal Error Reporting Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK (0x4U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT (2U)
/*! PCIE_CAP_FATAL_ERR_REPORT_EN - Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK (0x8U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT (3U)
/*! PCIE_CAP_UNSUPPORT_REQ_REP_EN - Unsupported Request Reporting Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK (0x10U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT (4U)
/*! PCIE_CAP_EN_REL_ORDER - Enable Relaxed Ordering. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK (0xE0U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT (5U)
/*! PCIE_CAP_MAX_PAYLOAD_SIZE_CS - Max Payload Size. Max_Payload_Size . This field sets maximum TLP
* payload size for the Function. Permissible values that can be programmed are indicated by the
* Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities
* register (DEVICE_CAPABILITIES_REG).
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK (0x100U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT (8U)
/*! PCIE_CAP_EXT_TAG_EN - Extended Tag Field Enable. For a description of this standard PCIe
* register field, see the PCI Express Specification. The write value is gated with the
* PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as
* follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK (0x200U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT (9U)
/*! PCIE_CAP_PHANTOM_FUNC_EN - Phantom Functions Enable. For a description of this standard PCIe
* register field, see the PCI Express Specification. The write value is gated with the
* PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field
* are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK (0x400U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT (10U)
/*! PCIE_CAP_AUX_POWER_PM_EN - Aux Power PM Enable. For a description of this standard PCIe register
* field, see the PCI Express Specification. This bit is derived by sampling the sys_aux_pwr_det
* input. Note: This register field is sticky.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK (0x800U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT (11U)
/*! PCIE_CAP_EN_NO_SNOOP - Enable No Snoop. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: R
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK (0x7000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT (12U)
/*! PCIE_CAP_MAX_READ_REQ_SIZE - Max Read Request Size. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK (0x8000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT (15U)
/*! PCIE_CAP_INITIATE_FLR - Initiate Function Level Reset (for endpoints). For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK (0x10000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT (16U)
/*! PCIE_CAP_CORR_ERR_DETECTED - Correctable Error Detected Status. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK (0x20000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT (17U)
/*! PCIE_CAP_NON_FATAL_ERR_DETECTED - Non-Fatal Error Detected Status. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK (0x40000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT (18U)
/*! PCIE_CAP_FATAL_ERR_DETECTED - Fatal Error Detected Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK (0x80000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT (19U)
/*! PCIE_CAP_UNSUPPORTED_REQ_DETECTED - Unsupported Request Detected Status. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK (0x100000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT (20U)
/*! PCIE_CAP_AUX_POWER_DETECTED - Aux Power Detected Status. For a description of this standard PCIe
* register field, see the PCI Express Specification. This bit is derived by sampling the
* sys_aux_pwr_det input.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK (0x200000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT (21U)
/*! PCIE_CAP_TRANS_PENDING - Transactions Pending Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_MASK)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MASK (0xFFC00000U)
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT (22U)
/*! RSVDP_22 - Reserved for future use.
*/
#define PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT)) & PCIE_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_MASK)
/*! @} */
/*! @name LINK_CAPABILITIES_REG - Link Capabilities Register. */
/*! @{ */
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK (0xFU)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT (0U)
/*! PCIE_CAP_MAX_LINK_SPEED - Maximum Link Speed. For a description of this standard PCIe register
* field, see the PCI Express Specification. In M-PCIe mode, the reset and dynamic values of this
* field are calculated by the controller. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK (0x3F0U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT (4U)
/*! PCIE_CAP_MAX_LINK_WIDTH - Maximum Link Width. For a description of this standard PCIe register
* field, see the PCI Express Specification. In M-PCIe mode, the reset and dynamic values of this
* field are calculated by the controller. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK (0xC00U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT (10U)
/*! PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT - Level of ASPM (Active State Power Management) Support.
* For a description of this standard PCIe register field, see the PCI Express Specification.
* Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W
* else R Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK (0x7000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT (12U)
/*! PCIE_CAP_L0S_EXIT_LATENCY - LOs Exit Latency. For a description of this standard PCIe register
* field, see the PCI Express Specification. There are two each of these register fields, this one
* and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of
* the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the
* controller and which one is accessed by a read request. Common Clock operation is supported
* (possible) in the controller when one or more of the following expressions is true: - CX_NFTS
* !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY
* !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the controller when you
* set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
* (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2
* address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The
* access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
* Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK (0x38000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT (15U)
/*! PCIE_CAP_L1_EXIT_LATENCY - L1 Exit Latency. For a description of this standard PCIe register
* field, see the PCI Express Specification. There are two each of these register fields, this one
* and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the
* Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the
* controller and which one is accessed by a read request. Common Clock operation is supported
* (possible) in the controller when one or more of the following expressions is true: - CX_NFTS
* !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY
* !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the controller when you set
* the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register
* (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address
* bit for the AXI bridge) is required to write to the shadow field at this location. Note: The
* access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
* Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK (0x40000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT (18U)
/*! PCIE_CAP_CLOCK_POWER_MAN - Clock Power Management. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK (0x80000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT (19U)
/*! PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP - Surprise Down Error Reporting Capable. For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: The access
* attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This
* register field is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK (0x100000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT (20U)
/*! PCIE_CAP_DLL_ACTIVE_REP_CAP - Data Link Layer Link Active Reporting Capable. For a description
* of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK (0x200000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT (21U)
/*! PCIE_CAP_LINK_BW_NOT_CAP - Link Bandwidth Notification Capable. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field
* is sticky.
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK (0x400000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT (22U)
/*! PCIE_CAP_ASPM_OPT_COMPLIANCE - ASPM Optionality Compliance. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_MASK)
#define PCIE_LINK_CAPABILITIES_REG_RSVDP_23_MASK (0x800000U)
#define PCIE_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT (23U)
/*! RSVDP_23 - Reserved for future use.
*/
#define PCIE_LINK_CAPABILITIES_REG_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_RSVDP_23_MASK)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK (0xFF000000U)
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT (24U)
/*! PCIE_CAP_PORT_NUM - Port Number. For a description of this standard PCIe register field, see the
* PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT)) & PCIE_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_MASK)
/*! @} */
/*! @name LINK_CONTROL_LINK_STATUS_REG - Link Control and Status Register. */
/*! @{ */
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK (0x3U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT (0U)
/*! PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL - Active State Power Management (ASPM) Control. Software
* must not enable L0s in either direction on a given Link unless components on both sides of the
* Link each support L0s; otherwise, the result is undefined. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MASK (0x4U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT (2U)
/*! RSVDP_2 - Reserved for future use.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK (0x8U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT (3U)
/*! PCIE_CAP_RCB - Read Completion Boundary (RCB). Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK (0x10U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT (4U)
/*! PCIE_CAP_LINK_DISABLE - Initiate Link Disable. For a description of this standard PCIe register
* field, see the PCI Express Specification. In a DSP that supports crosslink, the controller
* gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access
* attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 &&
* PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK (0x20U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT (5U)
/*! PCIE_CAP_RETRAIN_LINK - Initiate Link Retrain. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: see description
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK (0x40U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT (6U)
/*! PCIE_CAP_COMMON_CLK_CONFIG - Common Clock Configuration. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK (0x80U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT (7U)
/*! PCIE_CAP_EXTENDED_SYNCH - Extended Synch. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK (0x100U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT (8U)
/*! PCIE_CAP_EN_CLK_POWER_MAN - Enable Clock Power Management. For a description of this standard
* PCIe register field, see the PCI Express Specification. The write value is gated with the
* PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field
* are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS Note: This
* register field is sticky.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK (0x200U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT (9U)
/*! PCIE_CAP_HW_AUTO_WIDTH_DISABLE - Hardware Autonomous Width Disable. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
* this field are as follows: - Dbi: R/W
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK (0x400U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT (10U)
/*! PCIE_CAP_LINK_BW_MAN_INT_EN - Link Bandwidth Management Interrupt Enable. For a description of
* this standard PCIe register field, see the PCI Express Specification. The write value is gated
* with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes
* of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK (0x800U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT (11U)
/*! PCIE_CAP_LINK_AUTO_BW_INT_EN - Link Autonomous Bandwidth Management Interrupt Enable. For a
* description of this standard PCIe register field, see the PCI Express Specification. The write
* value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access
* attributes of this field are as follows: - Dbi:
* LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MASK (0x3000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT (12U)
/*! RSVDP_12 - Reserved for future use.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK (0xC000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT (14U)
/*! PCIE_CAP_DRS_SIGNALING_CONTROL - DRS Signaling Control. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: LINK_CAPABILITIES2_REG.DRS_SUPPORTED ? RW : RO
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK (0xF0000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT (16U)
/*! PCIE_CAP_LINK_SPEED - Current Link Speed. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK (0x3F00000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT (20U)
/*! PCIE_CAP_NEGO_LINK_WIDTH - Negotiated Link Width. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MASK (0x4000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK (0x8000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT (27U)
/*! PCIE_CAP_LINK_TRAINING - LTSSM is in Configuration or Recovery State. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK (0x10000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT (28U)
/*! PCIE_CAP_SLOT_CLK_CONFIG - Slot Clock Configuration. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK (0x20000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT (29U)
/*! PCIE_CAP_DLL_ACTIVE - Data Link Layer Active. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK (0x40000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT (30U)
/*! PCIE_CAP_LINK_BW_MAN_STATUS - Link Bandwidth Management Status. For a description of this
* standard PCIe register field, see the PCI Express Specification. The write value is gated with the
* PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_MASK)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK (0x80000000U)
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT (31U)
/*! PCIE_CAP_LINK_AUTO_BW_STATUS - Link Autonomous Bandwidth Status. For a description of this
* standard PCIe register field, see the PCI Express Specification. The write value is gated with the
* PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.
*/
#define PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT)) & PCIE_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_MASK)
/*! @} */
/*! @name SLOT_CAPABILITIES_REG - Slot Capabilities Register. */
/*! @{ */
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK (0x1U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT (0U)
/*! PCIE_CAP_ATTENTION_INDICATOR_BUTTON - Attention Button Present. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_BUTTON_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK (0x2U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT (1U)
/*! PCIE_CAP_POWER_CONTROLLER - Power Controller Present. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_CONTROLLER_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK (0x4U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT (2U)
/*! PCIE_CAP_MRL_SENSOR - MRL Present. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_MRL_SENSOR_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK (0x8U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT (3U)
/*! PCIE_CAP_ATTENTION_INDICATOR - Attention Indicator Present. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ATTENTION_INDICATOR_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK (0x10U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT (4U)
/*! PCIE_CAP_POWER_INDICATOR - Power Indicator Present. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_POWER_INDICATOR_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK (0x20U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT (5U)
/*! PCIE_CAP_HOT_PLUG_SURPRISE - Hot Plug Surprise possible. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_SURPRISE_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK (0x40U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT (6U)
/*! PCIE_CAP_HOT_PLUG_CAPABLE - Hot Plug Capable. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_HOT_PLUG_CAPABLE_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK (0x7F80U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT (7U)
/*! PCIE_CAP_SLOT_POWER_LIMIT_VALUE - Slot Power Limit Value. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_VALUE_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK (0x18000U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT (15U)
/*! PCIE_CAP_SLOT_POWER_LIMIT_SCALE - Slot Power Limit Scale. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_SLOT_POWER_LIMIT_SCALE_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK (0x20000U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT (17U)
/*! PCIE_CAP_ELECTROMECH_INTERLOCK - Electromechanical Interlock Present. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes
* of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_ELECTROMECH_INTERLOCK_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK (0x40000U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT (18U)
/*! PCIE_CAP_NO_CMD_CPL_SUPPORT - No Command Completed Support. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_NO_CMD_CPL_SUPPORT_MASK)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK (0xFFF80000U)
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT (19U)
/*! PCIE_CAP_PHY_SLOT_NUM - Physical Slot Number. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
*/
#define PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_SHIFT)) & PCIE_SLOT_CAPABILITIES_REG_PCIE_CAP_PHY_SLOT_NUM_MASK)
/*! @} */
/*! @name SLOT_CONTROL_SLOT_STATUS - Slot Control and Status Register. */
/*! @{ */
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK (0x1U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT (0U)
/*! PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN - Attention Button Pressed Enable. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK (0x2U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT (1U)
/*! PCIE_CAP_POWER_FAULT_DETECTED_EN - Power Fault Detected Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK (0x4U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT (2U)
/*! PCIE_CAP_MRL_SENSOR_CHANGED_EN - MRL Sensor Changed Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK (0x8U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT (3U)
/*! PCIE_CAP_PRESENCE_DETECT_CHANGE_EN - Presence Detect Changed Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_CHANGE_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK (0x10U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT (4U)
/*! PCIE_CAP_CMD_CPL_INT_EN - Command Completed Interrupt Enable. For a description of this standard
* PCIe register field, see the PCI Express Specification. Write value is gated with
* PCIE_CAP_NO_CMD_CPL_SUPPORT field in SLOT_CAPABILITIES_REG. Note: The access attributes of this field are
* as follows: - Dbi: SLOT_CAPABILITIES_REG.PCIE_CAP_NO_CMD_CPL_SUPPORT ? RO : RW
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPL_INT_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK (0x20U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT (5U)
/*! PCIE_CAP_HOT_PLUG_INT_EN - Hot Plug Interrupt Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_HOT_PLUG_INT_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK (0xC0U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT (6U)
/*! PCIE_CAP_ATTENTION_INDICATOR_CTRL - Attention Indicator Control. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_INDICATOR_CTRL_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK (0x300U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT (8U)
/*! PCIE_CAP_POWER_INDICATOR_CTRL - Power Indicator Control. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_INDICATOR_CTRL_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK (0x400U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT (10U)
/*! PCIE_CAP_POWER_CONTROLLER_CTRL - Power Controller Control. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_CONTROLLER_CTRL_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK (0x800U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT (11U)
/*! PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL - Electromechanical Interlock Control. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK (0x1000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT (12U)
/*! PCIE_CAP_DLL_STATE_CHANGED_EN - Data Link Layer State Changed Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_EN_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_MASK (0xE000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_SHIFT (13U)
/*! RSVDP_13 - Reserved for future use.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_13_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK (0x10000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT (16U)
/*! PCIE_CAP_ATTENTION_BUTTON_PRESSED - Attention Button Pressed. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ATTENTION_BUTTON_PRESSED_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK (0x20000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT (17U)
/*! PCIE_CAP_POWER_FAULT_DETECTED - Power Fault Detected. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_POWER_FAULT_DETECTED_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK (0x40000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT (18U)
/*! PCIE_CAP_MRL_SENSOR_CHANGED - MRL Sensor Changed. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_CHANGED_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK (0x80000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT (19U)
/*! PCIE_CAP_PRESENCE_DETECTED_CHANGED - Presence Detect Changed. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECTED_CHANGED_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK (0x100000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT (20U)
/*! PCIE_CAP_CMD_CPLD - Command Completed. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_CMD_CPLD_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK (0x200000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT (21U)
/*! PCIE_CAP_MRL_SENSOR_STATE - MRL Sensor State. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_MRL_SENSOR_STATE_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK (0x400000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT (22U)
/*! PCIE_CAP_PRESENCE_DETECT_STATE - Presence Detect State. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: R
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_PRESENCE_DETECT_STATE_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK (0x800000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT (23U)
/*! PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS - Electromechanical Interlock Status. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK (0x1000000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT (24U)
/*! PCIE_CAP_DLL_STATE_CHANGED - Data Link Layer State Changed. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_PCIE_CAP_DLL_STATE_CHANGED_MASK)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MASK (0xFE000000U)
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SHIFT (25U)
/*! RSVDP_25 - Reserved for future use.
*/
#define PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_SHIFT)) & PCIE_SLOT_CONTROL_SLOT_STATUS_RSVDP_25_MASK)
/*! @} */
/*! @name ROOT_CONTROL_ROOT_CAPABILITIES_REG - Root Control and Capabilities Register. */
/*! @{ */
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK (0x1U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT (0U)
/*! PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN - System Error on Correctable Error Enable. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK (0x2U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT (1U)
/*! PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN - System Error on Non-fatal Error Enable. For a description
* of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK (0x4U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT (2U)
/*! PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN - System Error on Fatal Error Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK (0x8U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT (3U)
/*! PCIE_CAP_PME_INT_EN - PME Interrupt Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_PME_INT_EN_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK (0x10U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT (4U)
/*! PCIE_CAP_CRS_SW_VISIBILITY_EN - Configuration Request Retry Status (CRS) Software Visibility
* Enable. For a description of this standard PCIe register field, see the PCI Express
* Specification. Note: The access attributes of this field are as follows: - Dbi:
* ROOT_CONTROL_ROOT_CAPABILITIES_REG.PCIE_CAP_CRS_SW_VISIBILITY ? RW : RO
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_EN_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MASK (0xFFE0U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SHIFT (5U)
/*! RSVDP_5 - Reserved for future use.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_5_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK (0x10000U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT (16U)
/*! PCIE_CAP_CRS_SW_VISIBILITY - CRS Software Visibility Capable. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W (Sticky) else R (Sticky) Note:
* This register field is sticky.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_PCIE_CAP_CRS_SW_VISIBILITY_MASK)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MASK (0xFFFE0000U)
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SHIFT (17U)
/*! RSVDP_17 - Reserved for future use.
*/
#define PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_SHIFT)) & PCIE_ROOT_CONTROL_ROOT_CAPABILITIES_REG_RSVDP_17_MASK)
/*! @} */
/*! @name ROOT_STATUS_REG - Root Status Register. */
/*! @{ */
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK (0xFFFFU)
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT (0U)
/*! PCIE_CAP_PME_REQ_ID - PME Requester ID. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_REQ_ID_MASK)
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK (0x10000U)
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT (16U)
/*! PCIE_CAP_PME_STATUS - PME Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_STATUS_MASK)
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK (0x20000U)
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT (17U)
/*! PCIE_CAP_PME_PENDING - PME Pending. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_SHIFT)) & PCIE_ROOT_STATUS_REG_PCIE_CAP_PME_PENDING_MASK)
#define PCIE_ROOT_STATUS_REG_RSVDP_18_MASK (0xFFFC0000U)
#define PCIE_ROOT_STATUS_REG_RSVDP_18_SHIFT (18U)
/*! RSVDP_18 - Reserved for future use.
*/
#define PCIE_ROOT_STATUS_REG_RSVDP_18(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_STATUS_REG_RSVDP_18_SHIFT)) & PCIE_ROOT_STATUS_REG_RSVDP_18_MASK)
/*! @} */
/*! @name DEVICE_CAPABILITIES2_REG - Device Capabilities 2 Register. */
/*! @{ */
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK (0xFU)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT (0U)
/*! PCIE_CAP_CPL_TIMEOUT_RANGE - Completion Timeout Ranges Supported. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK (0x10U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT (4U)
/*! PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT - Completion Timeout Disable Supported. For a description
* of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK (0x20U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT (5U)
/*! PCIE_CAP_ARI_FORWARD_SUPPORT - ARI Forwarding Supported. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK (0x40U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT (6U)
/*! PCIE_CAP_ATOMIC_ROUTING_SUPP - Atomic Operation Routing Supported. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK (0x80U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT (7U)
/*! PCIE_CAP_32_ATOMIC_CPL_SUPP - 32 Bit AtomicOp Completer Supported. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK (0x100U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT (8U)
/*! PCIE_CAP_64_ATOMIC_CPL_SUPP - 64 Bit AtomicOp Completer Supported. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK (0x200U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT (9U)
/*! PCIE_CAP_128_CAS_CPL_SUPP - 128 Bit CAS Completer Supported. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK (0x400U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT (10U)
/*! PCIE_CAP_NO_RO_EN_PR2PR_PAR - No Relaxed Ordering Enabled PR-PR Passing. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK (0x800U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT (11U)
/*! PCIE_CAP_LTR_SUPP - LTR Mechanism Supported. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK (0x1000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT (12U)
/*! PCIE_CAP_TPH_CMPLT_SUPPORT_0 - TPH Completer Supported Bit 0. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK (0x2000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT (13U)
/*! PCIE_CAP_TPH_CMPLT_SUPPORT_1 - TPH Completer Supported Bit 1. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK (0x10000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT (16U)
/*! PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT - 10-Bit Tag Completer Supported. For a description of this
* standard PCIe register field, see the PCI Express Base Specification 4.0.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK (0x20000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT (17U)
/*! PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT - 10-Bit Tag Requester Supported. For a description of this
* standard PCIe register field, see the PCI Express Base Specification 4.0.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_MASK (0xC0000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT (18U)
/*! PCIE_CAP_OBFF_SUPPORT - (OBFF) Optimized Buffer Flush/fill Supported. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_MASK)
#define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_MASK (0x7F000000U)
#define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT)) & PCIE_DEVICE_CAPABILITIES2_REG_RSVDP_24_MASK)
/*! @} */
/*! @name DEVICE_CONTROL2_DEVICE_STATUS2_REG - Device Control 2 and Status 2 Register. */
/*! @{ */
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK (0xFU)
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT (0U)
/*! PCIE_CAP_CPL_TIMEOUT_VALUE - Completion Timeout Value. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: R/W
*/
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_MASK)
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK (0x10U)
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT (4U)
/*! PCIE_CAP_CPL_TIMEOUT_DISABLE - Completion Timeout Disable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_MASK)
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK (0x20U)
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT (5U)
/*! PCIE_CAP_ARI_FORWARD_SUPPORT_CS - ARI Forwarding Enable. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field
* are as follows: - Dbi: R/W
*/
#define PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT)) & PCIE_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_MASK)
/*! @} */
/*! @name LINK_CAPABILITIES2_REG - Link Capabilities 2 Register. */
/*! @{ */
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_MASK (0x1U)
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_0_MASK)
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK (0xFEU)
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT (1U)
/*! PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR - Supported Link Speeds Vector. For a description of this
* standard PCIe register field, see the PCI Express Specification. This field has a default of
* (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 :
* (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in
* the LINK_CAPABILITIES_REG register.
*/
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_MASK)
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK (0x100U)
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT (8U)
/*! PCIE_CAP_CROSS_LINK_SUPPORT - Cross Link Supported. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_MASK)
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_MASK (0x7FFE00U)
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT (9U)
/*! RSVDP_9 - Reserved for future use.
*/
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_9_MASK)
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_MASK (0x7E000000U)
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_SHIFT (25U)
/*! RSVDP_25 - Reserved for future use.
*/
#define PCIE_LINK_CAPABILITIES2_REG_RSVDP_25(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_SHIFT)) & PCIE_LINK_CAPABILITIES2_REG_RSVDP_25_MASK)
/*! @} */
/*! @name LINK_CONTROL2_LINK_STATUS2_REG - Link Control 2 and Status 2 Register. */
/*! @{ */
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK (0xFU)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT (0U)
/*! PCIE_CAP_TARGET_LINK_SPEED - Target Link Speed. For a description of this standard PCIe register
* field, see the PCI Express Specification. In M-PCIe mode, the contents of this field are
* derived from other registers. Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK (0x10U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT (4U)
/*! PCIE_CAP_ENTER_COMPLIANCE - Enter Compliance Mode. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK (0x20U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT (5U)
/*! PCIE_CAP_HW_AUTO_SPEED_DISABLE - Hardware Autonomous Speed Disable. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
* this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK (0x40U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT (6U)
/*! PCIE_CAP_SEL_DEEMPHASIS - Controls Selectable De-emphasis for 5 GT/s. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes
* of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
* Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK (0x380U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT (7U)
/*! PCIE_CAP_TX_MARGIN - Controls Transmit Margin for Debug or Compliance. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK (0x400U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT (10U)
/*! PCIE_CAP_ENTER_MODIFIED_COMPLIANCE - Enter Modified Compliance. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK (0x800U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT (11U)
/*! PCIE_CAP_COMPLIANCE_SOS - Sets Compliance Skip Ordered Sets transmission. For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: The access
* attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK (0xF000U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT (12U)
/*! PCIE_CAP_COMPLIANCE_PRESET - Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: The
* access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
* sticky.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK (0x10000U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT (16U)
/*! PCIE_CAP_CURR_DEEMPHASIS - Current De-emphasis Level. For a description of this standard PCIe
* register field, see the PCI Express Specification. In M-PCIe mode this register is always 0x0.
* In C-PCIe mode, its contents are derived by sampling the PIPE
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MASK (0xC000000U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_RSVDP_26_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MASK (0x70000000U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT (28U)
/*! DOWNSTREAM_COMPO_PRESENCE - Downstream Component Presence. For a description of this standard
* PCIe register field, see the PCI Express Base Specification 4.0.
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_MASK)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MASK (0x80000000U)
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT (31U)
/*! DRS_MESSAGE_RECEIVED - DRS Message Received. For a description of this standard PCIe register
* field, see the PCI Express Base Specification 4.0. Note: The access attributes of this field are
* as follows: - Dbi: RW1C
*/
#define PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT)) & PCIE_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_MASK)
/*! @} */
/*! @name AER_EXT_CAP_HDR_OFF - Advanced Error Reporting Extended Capability Header. */
/*! @{ */
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK (0xFFFFU)
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT (0U)
/*! CAP_ID - AER Extended Capability ID. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_CAP_ID_MASK)
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK (0xF0000U)
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT (16U)
/*! CAP_VERSION - Capability Version. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_CAP_VERSION_MASK)
#define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK (0xFFF00000U)
#define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT (20U)
/*! NEXT_OFFSET - Next Capability Offset. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT)) & PCIE_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_MASK)
/*! @} */
/*! @name UNCORR_ERR_STATUS_OFF - Uncorrectable Error Status Register. */
/*! @{ */
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_MASK (0xFU)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_0_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK (0x10U)
#define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT (4U)
/*! DL_PROTOCOL_ERR_STATUS - Data Link Protocol Error Status. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK (0x20U)
#define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT (5U)
/*! SURPRISE_DOWN_ERR_STATUS - Surprise Down Error Status (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_SURPRISE_DOWN_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_MASK (0xFC0U)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_SHIFT (6U)
/*! RSVDP_6 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_6_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK (0x1000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT (12U)
/*! POIS_TLP_ERR_STATUS - Poisoned TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK (0x2000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT (13U)
/*! FC_PROTOCOL_ERR_STATUS - Flow Control Protocol Error Status. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK (0x4000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT (14U)
/*! CMPLT_TIMEOUT_ERR_STATUS - Completion Timeout Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK (0x8000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT (15U)
/*! CMPLT_ABORT_ERR_STATUS - Completer Abort Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK (0x10000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT (16U)
/*! UNEXP_CMPLT_ERR_STATUS - Unexpected Completion Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK (0x20000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT (17U)
/*! REC_OVERFLOW_ERR_STATUS - Receiver Overflow Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK (0x40000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT (18U)
/*! MALF_TLP_ERR_STATUS - Malformed TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK (0x80000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT (19U)
/*! ECRC_ERR_STATUS - ECRC Error Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK (0x100000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT (20U)
/*! UNSUPPORTED_REQ_ERR_STATUS - Unsupported Request Error Status. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK (0x400000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT (22U)
/*! INTERNAL_ERR_STATUS - Uncorrectable Internal Error Status. For a description of this standard
* PCIe register field, see the PCI Express Specification. The controller sets this bit when your
* application asserts app_err_bus[9]. It does not set this bit when it detects internal
* uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these
* errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire,
* Datapath, and RAM Protection)" section in the Databook.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_MASK (0x800000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_SHIFT (23U)
/*! RSVDP_23 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_23_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_MASK (0x2000000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_SHIFT (25U)
/*! TLP_PRFX_BLOCKED_ERR_STATUS - TLP Prefix Blocked Error Status. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: Not supported.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_MASK)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_MASK (0xFC000000U)
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_STATUS_OFF_RSVDP_26_MASK)
/*! @} */
/*! @name UNCORR_ERR_MASK_OFF - Uncorrectable Error Mask Register. */
/*! @{ */
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_MASK (0xFU)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_0_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK (0x10U)
#define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT (4U)
/*! DL_PROTOCOL_ERR_MASK - Data Link Protocol Error Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK (0x20U)
#define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT (5U)
/*! SURPRISE_DOWN_ERR_MASK - Surprise Down Error Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ? RW : RO Note: This
* register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_SURPRISE_DOWN_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_MASK (0xFC0U)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_SHIFT (6U)
/*! RSVDP_6 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_6_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK (0x1000U)
#define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT (12U)
/*! POIS_TLP_ERR_MASK - Poisoned TLP Error Mask. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK (0x2000U)
#define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT (13U)
/*! FC_PROTOCOL_ERR_MASK - Flow Control Protocol Error Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK (0x4000U)
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT (14U)
/*! CMPLT_TIMEOUT_ERR_MASK - Completion Timeout Error Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK (0x8000U)
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT (15U)
/*! CMPLT_ABORT_ERR_MASK - Completer Abort Error Mask (Optional). For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK (0x10000U)
#define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT (16U)
/*! UNEXP_CMPLT_ERR_MASK - Unexpected Completion Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK (0x20000U)
#define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT (17U)
/*! REC_OVERFLOW_ERR_MASK - Receiver Overflow Mask (Optional). For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK (0x40000U)
#define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT (18U)
/*! MALF_TLP_ERR_MASK - Malformed TLP Mask. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK (0x80000U)
#define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT (19U)
/*! ECRC_ERR_MASK - ECRC Error Mask (Optional). For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK (0x100000U)
#define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT (20U)
/*! UNSUPPORTED_REQ_ERR_MASK - Unsupported Request Error Mask. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK (0x400000U)
#define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT (22U)
/*! INTERNAL_ERR_MASK - Uncorrectable Internal Error Mask (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_MASK (0x800000U)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_SHIFT (23U)
/*! RSVDP_23 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_23_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK (0x1000000U)
#define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT (24U)
/*! ATOMIC_EGRESS_BLOCKED_ERR_MASK - AtomicOp Egress Block Mask (Optional). For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: The access attributes
* of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK (0x2000000U)
#define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT (25U)
/*! TLP_PRFX_BLOCKED_ERR_MASK - TLP Prefix Blocked Error Mask. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: Not supported. Note: The access
* attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_MASK)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_MASK (0xFC000000U)
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_MASK_OFF_RSVDP_26_MASK)
/*! @} */
/*! @name UNCORR_ERR_SEV_OFF - Uncorrectable Error Severity Register. */
/*! @{ */
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_MASK (0xFU)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_0_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK (0x10U)
#define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT (4U)
/*! DL_PROTOCOL_ERR_SEVERITY - Data Link Protocol Error Severity. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK (0x20U)
#define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT (5U)
/*! SURPRISE_DOWN_ERR_SVRITY - Surprise Down Error Severity (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of
* this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP ?
* RW : RO Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_SURPRISE_DOWN_ERR_SVRITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_MASK (0xFC0U)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_SHIFT (6U)
/*! RSVDP_6 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_6_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK (0x1000U)
#define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT (12U)
/*! POIS_TLP_ERR_SEVERITY - Poisoned TLP Severity. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK (0x2000U)
#define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT (13U)
/*! FC_PROTOCOL_ERR_SEVERITY - Flow Control Protocol Error Severity (Optional). For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: This register
* field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK (0x4000U)
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT (14U)
/*! CMPLT_TIMEOUT_ERR_SEVERITY - Completion Timeout Error Severity. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK (0x8000U)
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT (15U)
/*! CMPLT_ABORT_ERR_SEVERITY - Completer Abort Error Severity (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK (0x10000U)
#define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT (16U)
/*! UNEXP_CMPLT_ERR_SEVERITY - Unexpected Completion Error Severity. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK (0x20000U)
#define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT (17U)
/*! REC_OVERFLOW_ERR_SEVERITY - Receiver Overflow Error Severity (Optional). For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: This register field
* is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK (0x40000U)
#define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT (18U)
/*! MALF_TLP_ERR_SEVERITY - Malformed TLP Severity. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK (0x80000U)
#define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT (19U)
/*! ECRC_ERR_SEVERITY - ECRC Error Severity (Optional). For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are
* as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK (0x100000U)
#define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT (20U)
/*! UNSUPPORTED_REQ_ERR_SEVERITY - Unsupported Request Error Severity. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK (0x400000U)
#define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT (22U)
/*! INTERNAL_ERR_SEVERITY - Uncorrectable Internal Error Severity (Optional). For a description of
* this standard PCIe register field, see the PCI Express Specification. Note: This register field
* is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_MASK (0x800000U)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_SHIFT (23U)
/*! RSVDP_23 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_23_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MASK (0x1000000U)
#define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT (24U)
/*! ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY - AtomicOp Egress Blocked Severity (Optional). For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: The access
* attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
* sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK (0x2000000U)
#define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT (25U)
/*! TLP_PRFX_BLOCKED_ERR_SEVERITY - TLP Prefix Blocked Error Severity (Optional). For a description
* of this standard PCIe register field, see the PCI Express Specification. Note: Not supported.
* Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This
* register field is sticky.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_MASK)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_MASK (0xFC000000U)
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_SHIFT)) & PCIE_UNCORR_ERR_SEV_OFF_RSVDP_26_MASK)
/*! @} */
/*! @name CORR_ERR_STATUS_OFF - Correctable Error Status Register. */
/*! @{ */
#define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK (0x1U)
#define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT (0U)
/*! RX_ERR_STATUS - Receiver Error Status (Optional). For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_MASK (0x3EU)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_1_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK (0x40U)
#define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT (6U)
/*! BAD_TLP_STATUS - Bad TLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK (0x80U)
#define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT (7U)
/*! BAD_DLLP_STATUS - Bad DLLP Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK (0x100U)
#define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT (8U)
/*! REPLAY_NO_ROLEOVER_STATUS - REPLAY_NUM Rollover Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_MASK (0xE00U)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_SHIFT (9U)
/*! RSVDP_9 - Reserved for future use.
*/
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_9_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK (0x1000U)
#define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT (12U)
/*! RPL_TIMER_TIMEOUT_STATUS - Replay Timer Timeout Status. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK (0x2000U)
#define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT (13U)
/*! ADVISORY_NON_FATAL_ERR_STATUS - Advisory Non-Fatal Error Status. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK (0x4000U)
#define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT (14U)
/*! CORRECTED_INT_ERR_STATUS - Corrected Internal Error Status (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK (0x8000U)
#define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT (15U)
/*! HEADER_LOG_OVERFLOW_STATUS - Header Log Overflow Error Status (Optional). For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_MASK)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_MASK (0xFFFF0000U)
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_CORR_ERR_STATUS_OFF_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_SHIFT)) & PCIE_CORR_ERR_STATUS_OFF_RSVDP_16_MASK)
/*! @} */
/*! @name CORR_ERR_MASK_OFF - Correctable Error Mask Register. */
/*! @{ */
#define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK (0x1U)
#define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT (0U)
/*! RX_ERR_MASK - Receiver Error Mask (Optional). For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RX_ERR_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_1_MASK (0x3EU)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_1_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_1_MASK)
#define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK (0x40U)
#define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT (6U)
/*! BAD_TLP_MASK - Bad TLP Mask. For a description of this standard PCIe register field, see the PCI
* Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_BAD_TLP_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK (0x80U)
#define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT (7U)
/*! BAD_DLLP_MASK - Bad DLLP Mask. For a description of this standard PCIe register field, see the
* PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK (0x100U)
#define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT (8U)
/*! REPLAY_NO_ROLEOVER_MASK - REPLAY_NUM Rollover Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_9_MASK (0xE00U)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_9_SHIFT (9U)
/*! RSVDP_9 - Reserved for future use.
*/
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_9_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_9_MASK)
#define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK (0x1000U)
#define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT (12U)
/*! RPL_TIMER_TIMEOUT_MASK - Replay Timer Timeout Mask. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK (0x2000U)
#define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT (13U)
/*! ADVISORY_NON_FATAL_ERR_MASK - Advisory Non-Fatal Error Mask. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK (0x4000U)
#define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT (14U)
/*! CORRECTED_INT_ERR_MASK - Corrected Internal Error Mask (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK (0x8000U)
#define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT (15U)
/*! HEADER_LOG_OVERFLOW_MASK - Header Log Overflow Error Mask (Optional). For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_MASK)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_16_MASK (0xFFFF0000U)
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_CORR_ERR_MASK_OFF_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CORR_ERR_MASK_OFF_RSVDP_16_SHIFT)) & PCIE_CORR_ERR_MASK_OFF_RSVDP_16_MASK)
/*! @} */
/*! @name ADV_ERR_CAP_CTRL_OFF - Advanced Error Capabilities and Control Register. */
/*! @{ */
#define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK (0x1FU)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT (0U)
/*! FIRST_ERR_POINTER - First Error Pointer. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK (0x20U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT (5U)
/*! ECRC_GEN_CAP - ECRC Generation Capable. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK (0x40U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT (6U)
/*! ECRC_GEN_EN - ECRC Generation Enable. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK (0x80U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT (7U)
/*! ECRC_CHECK_CAP - ECRC Check Capable. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK (0x100U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT (8U)
/*! ECRC_CHECK_EN - ECRC Check Enable. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK (0x200U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT (9U)
/*! MULTIPLE_HEADER_CAP - Multiple Header Recording Capable. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK (0x400U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT (10U)
/*! MULTIPLE_HEADER_EN - Multiple Header Recording Enable. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_MASK)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_MASK (0xFFFFF000U)
#define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_SHIFT (12U)
/*! RSVDP_12 - Reserved for future use.
*/
#define PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_SHIFT)) & PCIE_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_MASK)
/*! @} */
/*! @name HDR_LOG_0_OFF - Header Log Register 0. */
/*! @{ */
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK (0xFFU)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT (0U)
/*! FIRST_DWORD_FIRST_BYTE - Byte 0 of Header log register of First 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_MASK)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT (8U)
/*! FIRST_DWORD_SECOND_BYTE - Byte 1 of Header log register of First 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_MASK)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT (16U)
/*! FIRST_DWORD_THIRD_BYTE - Byte 2 of Header log register of First 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_MASK)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT (24U)
/*! FIRST_DWORD_FOURTH_BYTE - Byte 3 of Header log register of First 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_MASK)
/*! @} */
/*! @name HDR_LOG_1_OFF - Header Log Register 1. */
/*! @{ */
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK (0xFFU)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT (0U)
/*! SECOND_DWORD_FIRST_BYTE - Byte 0 of Header log register of Second 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_MASK)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT (8U)
/*! SECOND_DWORD_SECOND_BYTE - Byte 1 of Header log register of Second 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_MASK)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT (16U)
/*! SECOND_DWORD_THIRD_BYTE - Byte 2 of Header log register of Second 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_MASK)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT (24U)
/*! SECOND_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Second 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_MASK)
/*! @} */
/*! @name HDR_LOG_2_OFF - Header Log Register 2. */
/*! @{ */
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK (0xFFU)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT (0U)
/*! THIRD_DWORD_FIRST_BYTE - Byte 0 of Header log register of Third 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_MASK)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT (8U)
/*! THIRD_DWORD_SECOND_BYTE - Byte 1 of Header log register of Third 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_MASK)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT (16U)
/*! THIRD_DWORD_THIRD_BYTE - Byte 2 of Header log register of Third 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_MASK)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT (24U)
/*! THIRD_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Third 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_MASK)
/*! @} */
/*! @name HDR_LOG_3_OFF - Header Log Register 3. */
/*! @{ */
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK (0xFFU)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT (0U)
/*! FOURTH_DWORD_FIRST_BYTE - Byte 0 of Header log register of Fourth 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_MASK)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT (8U)
/*! FOURTH_DWORD_SECOND_BYTE - Byte 1 of Header log register of Fourth 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_MASK)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT (16U)
/*! FOURTH_DWORD_THIRD_BYTE - Byte 2 of Header log register of Fourth 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_MASK)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT (24U)
/*! FOURTH_DWORD_FOURTH_BYTE - Byte 3 of Header log register of Fourth 32 bit Data Word. For a
* description of this standard PCIe register field, see the PCI Express Specification. Note: This
* register field is sticky.
*/
#define PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT)) & PCIE_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_MASK)
/*! @} */
/*! @name ROOT_ERR_CMD_OFF - Root Error Command Register. */
/*! @{ */
#define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK (0x1U)
#define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT (0U)
/*! CORR_ERR_REPORTING_EN - Correctable Error Reporting Enable. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_CORR_ERR_REPORTING_EN_MASK)
#define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK (0x2U)
#define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT (1U)
/*! NON_FATAL_ERR_REPORTING_EN - Non-Fatal Error Reporting Enable. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_NON_FATAL_ERR_REPORTING_EN_MASK)
#define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK (0x4U)
#define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT (2U)
/*! FATAL_ERR_REPORTING_EN - Fatal Error Reporting Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_FATAL_ERR_REPORTING_EN_MASK)
#define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_MASK (0xFFFFFFF8U)
#define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_SHIFT (3U)
/*! RSVDP_3 - Reserved for future use.
*/
#define PCIE_ROOT_ERR_CMD_OFF_RSVDP_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_SHIFT)) & PCIE_ROOT_ERR_CMD_OFF_RSVDP_3_MASK)
/*! @} */
/*! @name ROOT_ERR_STATUS_OFF - Root Error Status Register. */
/*! @{ */
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK (0x1U)
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT (0U)
/*! ERR_COR_RX - Correctable Error Received. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ERR_COR_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK (0x2U)
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT (1U)
/*! MUL_ERR_COR_RX - Multiple Correctable Errors Received. For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_COR_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK (0x4U)
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT (2U)
/*! ERR_FATAL_NON_FATAL_RX - Fatal or Non-Fatal Error Received. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ERR_FATAL_NON_FATAL_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK (0x8U)
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT (3U)
/*! MUL_ERR_FATAL_NON_FATAL_RX - Multiple Fatal or Non-Fatal Errors Received. For a description of
* this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_MUL_ERR_FATAL_NON_FATAL_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK (0x10U)
#define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT (4U)
/*! FIRST_UNCORR_FATAL - First Uncorrectable Error is Fatal. For a description of this standard PCIe
* register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_FIRST_UNCORR_FATAL_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK (0x20U)
#define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT (5U)
/*! NON_FATAL_ERR_MSG_RX - One or more Non-Fatal Error Messages Received. For a description of this
* standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_NON_FATAL_ERR_MSG_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK (0x40U)
#define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT (6U)
/*! FATAL_ERR_MSG_RX - One or more Fatal Error Messages Received. For a description of this standard
* PCIe register field, see the PCI Express Specification.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_FATAL_ERR_MSG_RX_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_MASK (0x7FFFF80U)
#define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_SHIFT (7U)
/*! RSVDP_7 - Reserved for future use.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_RSVDP_7_MASK)
#define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK (0xF8000000U)
#define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT (27U)
/*! ADV_ERR_INT_MSG_NUM - Advanced Error Interrupt Message Number. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: The access attributes of this
* field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This
* register field is sticky.
*/
#define PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_SHIFT)) & PCIE_ROOT_ERR_STATUS_OFF_ADV_ERR_INT_MSG_NUM_MASK)
/*! @} */
/*! @name ERR_SRC_ID_OFF - Error Source Identification Register. */
/*! @{ */
#define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK (0xFFFFU)
#define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT (0U)
/*! ERR_COR_SOURCE_ID - Source of Correctable Error. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_SHIFT)) & PCIE_ERR_SRC_ID_OFF_ERR_COR_SOURCE_ID_MASK)
#define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK (0xFFFF0000U)
#define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT (16U)
/*! ERR_FATAL_NON_FATAL_SOURCE_ID - Source of Fatal/Non-Fatal Error. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_SHIFT)) & PCIE_ERR_SRC_ID_OFF_ERR_FATAL_NON_FATAL_SOURCE_ID_MASK)
/*! @} */
/*! @name TLP_PREFIX_LOG_1_OFF - TLP Prefix Log Register 1. */
/*! @{ */
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK (0xFFU)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT (0U)
/*! CFG_TLP_PFX_LOG_1_FIRST_BYTE - Byte 0 of Error TLP Prefix Log 1. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT (8U)
/*! CFG_TLP_PFX_LOG_1_SECOND_BYTE - Byte 1 of Error TLP Prefix Log 1. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT (16U)
/*! CFG_TLP_PFX_LOG_1_THIRD_BYTE - Byte 2 of Error TLP Prefix Log 1. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT (24U)
/*! CFG_TLP_PFX_LOG_1_FOURTH_BYTE - Byte 3 of Error TLP Prefix Log 1. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is
* sticky.
*/
#define PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_MASK)
/*! @} */
/*! @name TLP_PREFIX_LOG_2_OFF - TLP Prefix Log Register 2. */
/*! @{ */
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK (0xFFU)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT (0U)
/*! CFG_TLP_PFX_LOG_2_FIRST_BYTE - Byte 0 Error TLP Prefix Log 2. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT (8U)
/*! CFG_TLP_PFX_LOG_2_SECOND_BYTE - Byte 1 Error TLP Prefix Log 2. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT (16U)
/*! CFG_TLP_PFX_LOG_2_THIRD_BYTE - Byte 2 Error TLP Prefix Log 2. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT (24U)
/*! CFG_TLP_PFX_LOG_2_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 2. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_MASK)
/*! @} */
/*! @name TLP_PREFIX_LOG_3_OFF - TLP Prefix Log Register 3. */
/*! @{ */
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK (0xFFU)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT (0U)
/*! CFG_TLP_PFX_LOG_3_FIRST_BYTE - Byte 0 Error TLP Prefix Log 3. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT (8U)
/*! CFG_TLP_PFX_LOG_3_SECOND_BYTE - Byte 1 Error TLP Prefix Log 3. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT (16U)
/*! CFG_TLP_PFX_LOG_3_THIRD_BYTE - Byte 2 Error TLP Prefix Log 3. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT (24U)
/*! CFG_TLP_PFX_LOG_3_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 3. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_MASK)
/*! @} */
/*! @name TLP_PREFIX_LOG_4_OFF - TLP Prefix Log Register 4. */
/*! @{ */
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK (0xFFU)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT (0U)
/*! CFG_TLP_PFX_LOG_4_FIRST_BYTE - Byte 0 Error TLP Prefix Log 4. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK (0xFF00U)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT (8U)
/*! CFG_TLP_PFX_LOG_4_SECOND_BYTE - Byte 1 Error TLP Prefix Log 4. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK (0xFF0000U)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT (16U)
/*! CFG_TLP_PFX_LOG_4_THIRD_BYTE - Byte 2 Error TLP Prefix Log 4. For a description of this standard
* PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_MASK)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK (0xFF000000U)
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT (24U)
/*! CFG_TLP_PFX_LOG_4_FOURTH_BYTE - Byte 3 Error TLP Prefix Log 4. For a description of this
* standard PCIe register field, see the PCI Express Specification. Note: This register field is sticky.
*/
#define PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT)) & PCIE_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_MASK)
/*! @} */
/*! @name L1SUB_CAP_HEADER_REG - L1 Substates Extended Capability Header. */
/*! @{ */
#define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK (0xFFFFU)
#define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT (0U)
/*! EXTENDED_CAP_ID - L1SUB Extended Capability ID. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field
* is sticky.
*/
#define PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_EXTENDED_CAP_ID_MASK)
#define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK (0xF0000U)
#define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT (16U)
/*! CAP_VERSION - Capability Version. For a description of this standard PCIe register field, see
* the PCI Express Specification. Note: The access attributes of this field are as follows: - Dbi:
* if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_CAP_VERSION_MASK)
#define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK (0xFFF00000U)
#define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT (20U)
/*! NEXT_OFFSET - Next Capability Offset. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky.
*/
#define PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_SHIFT)) & PCIE_L1SUB_CAP_HEADER_REG_NEXT_OFFSET_MASK)
/*! @} */
/*! @name L1SUB_CAPABILITY_REG - L1 Substates Capability Register. */
/*! @{ */
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK (0x1U)
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT (0U)
/*! L1_2_PCIPM_SUPPORT - PCI-PM L12 Supported. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_2_PCIPM_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK (0x2U)
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT (1U)
/*! L1_1_PCIPM_SUPPORT - PCI-PM L11 Supported. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_1_PCIPM_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK (0x4U)
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT (2U)
/*! L1_2_ASPM_SUPPORT - ASPM L12 Supported. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_2_ASPM_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK (0x8U)
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT (3U)
/*! L1_1_ASPM_SUPPORT - ASPM L11 Supported. For a description of this standard PCIe register field,
* see the PCI Express Specification. Note: The access attributes of this field are as follows: -
* Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_1_ASPM_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK (0x10U)
#define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT (4U)
/*! L1_PMSUB_SUPPORT - L1 PM Substates ECN Supported. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_L1_PMSUB_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_MASK (0xE0U)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_SHIFT (5U)
/*! RSVDP_5 - Reserved for future use.
*/
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_5_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK (0xFF00U)
#define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT (8U)
/*! COMM_MODE_SUPPORT - Port Common Mode Restore Time. For a description of this standard PCIe
* register field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_COMM_MODE_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK (0x30000U)
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT (16U)
/*! PWR_ON_SCALE_SUPPORT - Port T Power On Scale. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_PWR_ON_SCALE_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_MASK (0x40000U)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_SHIFT (18U)
/*! RSVDP_18 - Reserved for future use.
*/
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_18(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_18_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK (0xF80000U)
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT (19U)
/*! PWR_ON_VALUE_SUPPORT - Port T Power On Value. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_PWR_ON_VALUE_SUPPORT_MASK)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_MASK (0xFF000000U)
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_L1SUB_CAPABILITY_REG_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_SHIFT)) & PCIE_L1SUB_CAPABILITY_REG_RSVDP_24_MASK)
/*! @} */
/*! @name L1SUB_CONTROL1_REG - L1 Substates Control 1 Register. */
/*! @{ */
#define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK (0x1U)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT (0U)
/*! L1_2_PCIPM_EN - PCI-PM L12 Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_PCIPM_EN_MASK)
#define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK (0x2U)
#define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT (1U)
/*! L1_1_PCIPM_EN - PCI-PM L11 Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_1_PCIPM_EN_MASK)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK (0x4U)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT (2U)
/*! L1_2_ASPM_EN - ASPM L12 Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_ASPM_EN_MASK)
#define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK (0x8U)
#define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT (3U)
/*! L1_1_ASPM_EN - ASPM L11 Enable. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_1_ASPM_EN_MASK)
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_4_MASK (0xF0U)
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_4_SHIFT (4U)
/*! RSVDP_4 - Reserved for future use.
*/
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_RSVDP_4_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_RSVDP_4_MASK)
#define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK (0xFF00U)
#define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT (8U)
/*! T_COMMON_MODE - Common Mode Restore Time. For a description of this standard PCIe register
* field, see the PCI Express Specification. Note: The access attributes of this field are as follows:
* - Dbi: R/W
*/
#define PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_T_COMMON_MODE_MASK)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK (0x3FF0000U)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT (16U)
/*! L1_2_TH_VAL - LTR L12 Threshold Value. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_TH_VAL_MASK)
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_26_MASK (0x1C000000U)
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_L1SUB_CONTROL1_REG_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_RSVDP_26_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_RSVDP_26_MASK)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK (0xE0000000U)
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT (29U)
/*! L1_2_TH_SCA - LTR L12 Threshold Scale. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_SHIFT)) & PCIE_L1SUB_CONTROL1_REG_L1_2_TH_SCA_MASK)
/*! @} */
/*! @name L1SUB_CONTROL2_REG - L1 Substates Control 2 Register. */
/*! @{ */
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK (0x3U)
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT (0U)
/*! T_POWER_ON_SCALE - T Power On Scale. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_SCALE_MASK)
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_2_MASK (0x4U)
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_2_SHIFT (2U)
/*! RSVDP_2 - Reserved for future use.
*/
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_RSVDP_2_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_RSVDP_2_MASK)
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK (0xF8U)
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT (3U)
/*! T_POWER_ON_VALUE - T Power On Value. For a description of this standard PCIe register field, see the PCI Express Specification.
*/
#define PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_T_POWER_ON_VALUE_MASK)
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_8_MASK (0xFFFFFF00U)
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_L1SUB_CONTROL2_REG_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1SUB_CONTROL2_REG_RSVDP_8_SHIFT)) & PCIE_L1SUB_CONTROL2_REG_RSVDP_8_MASK)
/*! @} */
/*! @name ACK_LATENCY_TIMER_OFF - Ack Latency Timer and Replay Timer Register. */
/*! @{ */
#define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK (0xFFFFU)
#define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT (0U)
/*! ROUND_TRIP_LATENCY_TIME_LIMIT - Ack Latency Timer Limit. The Ack latency timer expires when it
* reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer
* limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After
* reset, the controller updates the default according to the Negotiated Link Width,
* Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0
* specification. The limit must reflect the round trip latency from requester to completer. If there is a
* change in the payload size or link width, the controller will override any value that you have
* written to this register field, and reset the field back to the specification-defined value.
* It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF
* register.
*/
#define PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT)) & PCIE_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_MASK)
#define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK (0xFFFF0000U)
#define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT (16U)
/*! REPLAY_TIME_LIMIT - Replay Timer Limit. The replay timer expires when it reaches this limit. The
* controller initiates a replay upon reception of a NAK or when the replay timer expires. For
* more details, see "Transmit Replay". You can modify the effective timer limit with the
* TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the controller
* updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The
* value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a
* change in the payload size or link speed, the controller will override any value that you have
* written to this register field, and reset the field back to the specification-defined value.
* It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the
* TIMER_CTRL_MAX_FUNC_NUM_OFF register.
*/
#define PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT)) & PCIE_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_MASK)
/*! @} */
/*! @name VENDOR_SPEC_DLLP_OFF - Vendor Specific DLLP Register. */
/*! @{ */
#define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK (0xFFFFFFFFU)
#define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT (0U)
/*! VENDOR_SPEC_DLLP - Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your
* application writes the 8-bit DLLP Type and 24-bits of Payload data into this register, then
* sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to send the DLLP. - [7:0] = Type
* - [31:8] = Payload (24 bits) The dllp type is in bits [7:0] while the remainder is the vendor
* defined payload. Note: This register field is sticky.
*/
#define PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_SHIFT)) & PCIE_VENDOR_SPEC_DLLP_OFF_VENDOR_SPEC_DLLP_MASK)
/*! @} */
/*! @name PORT_FORCE_OFF - Port Force Link Register. */
/*! @{ */
#define PCIE_PORT_FORCE_OFF_LINK_NUM_MASK (0xFFU)
#define PCIE_PORT_FORCE_OFF_LINK_NUM_SHIFT (0U)
/*! LINK_NUM - Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_PORT_FORCE_OFF_LINK_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_LINK_NUM_SHIFT)) & PCIE_PORT_FORCE_OFF_LINK_NUM_MASK)
#define PCIE_PORT_FORCE_OFF_FORCED_LTSSM_MASK (0xF00U)
#define PCIE_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT (8U)
/*! FORCED_LTSSM - Forced Link Command. The link command that the controller is forced to transmit
* when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd
* variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
*/
#define PCIE_PORT_FORCE_OFF_FORCED_LTSSM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT)) & PCIE_PORT_FORCE_OFF_FORCED_LTSSM_MASK)
#define PCIE_PORT_FORCE_OFF_RSVDP_12_MASK (0x7000U)
#define PCIE_PORT_FORCE_OFF_RSVDP_12_SHIFT (12U)
/*! RSVDP_12 - Reserved for future use.
*/
#define PCIE_PORT_FORCE_OFF_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_12_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_12_MASK)
#define PCIE_PORT_FORCE_OFF_FORCE_EN_MASK (0x8000U)
#define PCIE_PORT_FORCE_OFF_FORCE_EN_SHIFT (15U)
/*! FORCE_EN - Force Link. The controller supports a testing and debug capability to allow your
* software to force the LTSSM state machine into a specific state, and to force the controller to
* transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces
* the LTSSM to the state specified by the Forced LTSSM State field. - Forces the controller to
* transmit the command specified by the Forced Link Command field. This is a self-clearing register
* field. Reading from this register field always returns a "0".
*/
#define PCIE_PORT_FORCE_OFF_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_FORCE_EN_SHIFT)) & PCIE_PORT_FORCE_OFF_FORCE_EN_MASK)
#define PCIE_PORT_FORCE_OFF_LINK_STATE_MASK (0x3F0000U)
#define PCIE_PORT_FORCE_OFF_LINK_STATE_SHIFT (16U)
/*! LINK_STATE - Forced LTSSM State. The LTSSM state that the controller is forced to when you set
* the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in
* workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky.
*/
#define PCIE_PORT_FORCE_OFF_LINK_STATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_LINK_STATE_SHIFT)) & PCIE_PORT_FORCE_OFF_LINK_STATE_MASK)
#define PCIE_PORT_FORCE_OFF_RSVDP_22_MASK (0x400000U)
#define PCIE_PORT_FORCE_OFF_RSVDP_22_SHIFT (22U)
/*! RSVDP_22 - Reserved for future use.
*/
#define PCIE_PORT_FORCE_OFF_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_22_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_22_MASK)
#define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK (0x800000U)
#define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT (23U)
/*! DO_DESKEW_FOR_SRIS - Use the transitions from TS2 to Logical Idle Symbol, SKP OS to Logical Idle
* Symbol, and FTS Sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if
* DO_DESKEW_FOR_SRIS is set to 1. Note: This register field is sticky.
*/
#define PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_SHIFT)) & PCIE_PORT_FORCE_OFF_DO_DESKEW_FOR_SRIS_MASK)
#define PCIE_PORT_FORCE_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_PORT_FORCE_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_PORT_FORCE_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_FORCE_OFF_RSVDP_24_SHIFT)) & PCIE_PORT_FORCE_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name ACK_F_ASPM_CTRL_OFF - Ack Frequency and L0-L1 ASPM Control Register. */
/*! @{ */
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK (0xFFU)
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT (0U)
/*! ACK_FREQ - Ack Frequency. The controller accumulates the number of pending ACKs specified here
* (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature
* is turned off. The controller schedules a low-priority ACK DLLP for every TLP that it
* receives. - 1-255: Indicates that the controller will schedule a high-priority ACK after receiving
* this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never
* later. For a typical system, you do not have to modify the default setting. For more details,
* see "ACK/NAK Scheduling". Note: This register field is sticky.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK (0xFF00U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT (8U)
/*! ACK_N_FTS - N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when
* transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request
* is 255. The controller does not support a value of zero; a value of zero can cause the LTSSM
* to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for
* M-PCIe. Note: This register field is sticky.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK (0xFF0000U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT (16U)
/*! COMMON_CLK_N_FTS - Common Clock N_FTS. This is the N_FTS when common clock is used. The number
* of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The
* maximum number of FTS ordered-sets that a component can request is 255. This field is only
* writable (sticky) when all of the following configuration parameter equations are true: -
* CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY -
* DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The controller does not support a value of zero; a
* value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field
* is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as
* follows: - Dbi: R
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK (0x7000000U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT (24U)
/*! L0S_ENTRANCE_LATENCY - L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us -
* 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to
* STALL while in L0 for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK (0x38000000U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT (27U)
/*! L1_ENTRANCE_LATENCY - L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us -
* 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a
* value greater that 32us has no effect unless extended sync is used, or all of the credits are
* infinite. Note: This register field is sticky.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK (0x40000000U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT (30U)
/*! ENTER_ASPM - ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been
* idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit
* are in L0s. Note: This register field is sticky.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_MASK)
#define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MASK (0x80000000U)
#define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SHIFT (31U)
/*! RSVDP_31 - Reserved for future use.
*/
#define PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SHIFT)) & PCIE_ACK_F_ASPM_CTRL_OFF_RSVDP_31_MASK)
/*! @} */
/*! @name PORT_LINK_CTRL_OFF - Port Link Control Register. */
/*! @{ */
#define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK (0x1U)
#define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT (0U)
/*! VENDOR_SPECIFIC_DLLP_REQ - Vendor Specific DLLP Request. When software writes a '1' to this bit,
* the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of
* VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always returns a '0'.
*/
#define PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK (0x2U)
#define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT (1U)
/*! SCRAMBLE_DISABLE - Scramble Disable. Turns off data scrambling. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK (0x4U)
#define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT (2U)
/*! LOOPBACK_ENABLE - Loopback Enable. Turns on loopback. For more details, see "Loopback". For
* M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during
* Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback
* mode from L0 state - only from Configuration.start. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK (0x8U)
#define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT (3U)
/*! RESET_ASSERT - Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state
* (downstream port only). Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RESET_ASSERT_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_MASK (0x10U)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_SHIFT (4U)
/*! RSVDP_4 - Reserved for future use.
*/
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_4_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK (0x20U)
#define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT (5U)
/*! DLL_LINK_EN - DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the
* controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is
* sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_DLL_LINK_EN_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK (0x40U)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT (6U)
/*! LINK_DISABLE - LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_DISABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK (0x80U)
#define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT (7U)
/*! FAST_LINK_MODE - Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for
* speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs
* and to link up faster. The default scaling factor can be changed using the
* DEFAULT_FAST_LINK_SCALING_FACTOR parameter or through the FAST_LINK_SCALING_FACTOR field in the
* TIMER_CTRL_MAX_FUNC_NUM_OFF register. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin
* to '1'. For more details, see the "Fast Link Simulation Mode" section in the "Integrating the
* Core with the PHY or Application RTL or Verification IP" chapter of the User Guide. For
* M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If
* this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32). Note: This register
* field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_MASK (0xF00U)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT (8U)
/*! LINK_RATE - LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_LINK_RATE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_RATE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_MASK (0xF000U)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_SHIFT (12U)
/*! RSVDP_12 - Reserved for future use.
*/
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_12_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK (0x3F0000U)
#define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT (16U)
/*! LINK_CAPABLE - Link Mode Enable. Sets the number of lanes in the link that you want to connect
* to the link partner. When you have unused lanes in your system, then you must change the value
* in this register to reflect the number of lanes. You must also change the value in the
* "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more
* information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing
* the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 -
* 011111: x16 - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe.
* Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_LINK_CAPABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK (0x1000000U)
#define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT (24U)
/*! BEACON_ENABLE - BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_BEACON_ENABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK (0x2000000U)
#define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT (25U)
/*! CORRUPT_LCRC_ENABLE - CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK (0x4000000U)
#define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT (26U)
/*! EXTENDED_SYNCH - EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK (0x8000000U)
#define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT (27U)
/*! TRANSMIT_LANE_REVERSALE_ENABLE - TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_MASK)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_MASK (0xF0000000U)
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_SHIFT (28U)
/*! RSVDP_28 - Reserved for future use.
*/
#define PCIE_PORT_LINK_CTRL_OFF_RSVDP_28(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_SHIFT)) & PCIE_PORT_LINK_CTRL_OFF_RSVDP_28_MASK)
/*! @} */
/*! @name LANE_SKEW_OFF - Lane Skew Register. */
/*! @{ */
#define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK (0xFFFFFFU)
#define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT (0U)
/*! INSERT_LANE_SKEW - INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT)) & PCIE_LANE_SKEW_OFF_INSERT_LANE_SKEW_MASK)
#define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK (0x1000000U)
#define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT (24U)
/*! FLOW_CTRL_DISABLE - Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT)) & PCIE_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_MASK)
#define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK (0x2000000U)
#define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT (25U)
/*! ACK_NAK_DISABLE - Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT)) & PCIE_LANE_SKEW_OFF_ACK_NAK_DISABLE_MASK)
#define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_MASK (0x4000000U)
#define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_SHIFT (26U)
/*! GEN34_ELASTIC_BUFFER_MODE - Selects Elasticity Buffer operating mode in Gen3 or Gen4 rate: 0:
* Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode This register bit only affects Gen3
* or Gen4 operating rate. For Gen1 or Gen2 operating rate the Elasticity Buffer operating mode is
* always the Nominal Half Full Buffer mode. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_SHIFT)) & PCIE_LANE_SKEW_OFF_GEN34_ELASTIC_BUFFER_MODE_MASK)
#define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK (0x78000000U)
#define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT (27U)
/*! IMPLEMENT_NUM_LANES - Implementation-specific Number of Lanes. Set the implementation-specific
* number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes -
* 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be used when in Loopback Master.
* The number of lanes programmed must be equal to or less than the valid number of lanes set in
* LINK_CAPABLE field. You must configure this field before initiating Loopback by writing in the
* LOOPBACK_ENABLE field. The controller will transition from Loopback.Entry to Loopback.Active
* after receiving two consecutive TS1 Ordered Sets with the Loopback bit asserted on the
* implementation specific number of lanes configured in this field. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_SHIFT)) & PCIE_LANE_SKEW_OFF_IMPLEMENT_NUM_LANES_MASK)
#define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK (0x80000000U)
#define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT (31U)
/*! DISABLE_LANE_TO_LANE_DESKEW - Disable Lane-to-Lane Deskew. Causes the controller to disable the
* internal Lane-to-Lane deskew logic. Note: This register field is sticky.
*/
#define PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT)) & PCIE_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_MASK)
/*! @} */
/*! @name TIMER_CTRL_MAX_FUNC_NUM_OFF - Timer Control and Max Function Number Register. */
/*! @{ */
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK (0xFFU)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT (0U)
/*! MAX_FUNC_NUM - Maximum function number that can be used in a request. Configuration requests
* targeted at function numbers above this value are returned with UR (unsupported request). Note:
* This register field is sticky.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MASK (0x3F00U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK (0x7C000U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT (14U)
/*! TIMER_MOD_REPLAY_TIMER - Replay Timer Limit Modifier. Increases the time-out value for the
* replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock
* cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more
* details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed,
* the controller automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For
* M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock
* cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed. Note: This register field is sticky.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK (0xF80000U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT (19U)
/*! TIMER_MOD_ACK_NAK - Ack Latency Timer Modifier. Increases the timer value for the Ack latency
* timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer
* value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the
* ACK_LATENCY_TIMER_OFF register. Note: This register field is sticky.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK (0x1F000000U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT (24U)
/*! UPDATE_FREQ_TIMER - UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK (0x60000000U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT (29U)
/*! FAST_LINK_SCALING_FACTOR - Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM
* timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024
* (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) -
* 3: Scaling Factor is 16 (1ms is 64us) Default is set by the hidden configuration parameter
* DEFAULT_FAST_LINK_SCALING_FACTOR which defaults to '0'. Not used for M-PCIe. Note: This register
* field is sticky.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_MASK)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MASK (0x80000000U)
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SHIFT (31U)
/*! RSVDP_31 - Reserved for future use.
*/
#define PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SHIFT)) & PCIE_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_MASK)
/*! @} */
/*! @name SYMBOL_TIMER_FILTER_1_OFF - Symbol Timer Register and Filter Mask 1 Register. */
/*! @{ */
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK (0x7FFU)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT (0U)
/*! SKP_INT_VAL - SKP Interval Value. The number of symbol times to wait between transmitting SKP
* ordered sets. Note that the controller actually waits the number of symbol times in this
* register plus 1 between transmitting SKP ordered sets. Your application must program this register
* accordingly. For example, if 1536 were programmed into this register (in a 250 MHz controller),
* then the controller actually transmits SKP ordered sets once every 1537 symbol times. The
* value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz
* controller, programming the value programmed to this register should be scaled down by a factor of
* 2 (because one clock tick = two symbol times in this case). Note: This value is not used at
* Gen3 speed; the skip interval is hardcoded to 370 blocks. For M-PCIe configurations, if the
* 2K_PPM_DISABLED field in the M-PCIe Configuration Attribute is changed, then this field is changed
* automatically as follows. - 2K_PPM_DISABLED=1: 1280 / CX_NB - 2K_PPM_DISABLED=0: 228/CX_NB
* You need to set this field again if necessary when 2K_PPM_DISABLED is changed. Note: This
* register field is sticky.
*/
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_MASK)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK (0x7800U)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT (11U)
/*! EIDLE_TIMER - EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_MASK)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK (0x8000U)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT (15U)
/*! DISABLE_FC_WD_TIMER - Disable FC Watchdog Timer. Note: This register field is sticky.
*/
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_MASK)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK (0xFFFF0000U)
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT (16U)
/*! MASK_RADM_1 - Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error
* handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies
* the associated filtering rule and '1' masks the associated filtering rule. [31]:
* CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For
* RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For
* RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO
* transaction being received [29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor
* MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message
* TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this
* bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit
* is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs.
* Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The controller never passes ATS
* Invalidate messages to the SII interface regardless of this filter rule setting. The controller
* passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for
* the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised
* with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors
* - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW. [27]:
* CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be
* passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a
* violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for
* completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation
* results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca
* - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic
* Class match for completions; a violation results in a malformed TLP error, and possibly AER of
* unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions [23]:
* CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in
* cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function
* match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for
* completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca
* - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag
* Error Rules for completions; a violation result in cpl_abort, and possibly AER of
* unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions [20]:
* CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read
* TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_REQ_AS_UR - 0: Treat CFG type1
* TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC -
* When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config
* requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0:
* Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS -
* 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native
* controller always passes poisoned completions to your application except when you are using
* the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as
* UR - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky.
*/
#define PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT)) & PCIE_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_MASK)
/*! @} */
/*! @name FILTER_MASK_2_OFF - Filter Mask 2 Register. */
/*! @{ */
#define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_MASK (0xFFFFFFFFU)
#define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT (0U)
/*! MASK_RADM_2 - Filter Mask 2. This field modifies the RADM filtering and error handling rules.
* For more details, see the "Receive Filtering" section. In each case, '0' applies the associated
* filtering rule and '1' masks the associated filtering rule. [31:8]: Reserved [7]:
* CX_FLT_MASK_PRS_DROP - 0: Allow PRS message to pass through - 1: Drop PRS Messages silently - This bit is
* ignored when the CX_FLT_MASK_MSG_DROP bit in the MASK_RADM_1 field of the
* SYMBOL_TIMER_FILTER_1_OFF register is set to '1'. [6]: CX_FLT_UNMASK_TD - 0: Disable unmask TD bit if
* CX_STRIP_ECRC_ENABLE - 1: Enable unmask TD bit if CX_STRIP_ECRC_ENABLE [5]: CX_FLT_UNMASK_UR_POIS_TRGT0 -
* 0: Disable unmask CX_FLT_MASK_UR_POIS with TRGT0 destination - 1: Enable unmask
* CX_FLT_MASK_UR_POIS with TRGT0 destination [4]: CX_FLT_MASK_LN_VENMSG1_DROP - 0: Allow LN message to pass
* through - 1: Drop LN Messages silently [3]: CX_FLT_MASK_HANDLE_FLUSH - 0: Disable controller
* Filter to handle flush request - 1: Enable controller Filter to handle flush request [2]:
* CX_FLT_MASK_DABORT_4UCPL - 0: Enable DLLP abort for unexpected completion - 1: Do not enable DLLP
* abort for unexpected completion [1]: CX_FLT_MASK_VENMSG1_DROP - 0: Vendor MSG Type 1 dropped
* silently - 1: Vendor MSG Type 1 not dropped [0]: CX_FLT_MASK_VENMSG0_DROP - 0: Vendor MSG Type 0
* dropped with UR error reporting - 1: Vendor MSG Type 0 not dropped Note: This register field is
* sticky.
*/
#define PCIE_FILTER_MASK_2_OFF_MASK_RADM_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_SHIFT)) & PCIE_FILTER_MASK_2_OFF_MASK_RADM_2_MASK)
/*! @} */
/*! @name AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF - AMBA Multiple Outbound Decomposed NP SubRequests Control Register. */
/*! @{ */
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MASK (0x1U)
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SHIFT (0U)
/*! OB_RD_SPLIT_BURST_EN - Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when
* set to "0" disables the possibility of having multiple outstanding non-posted requests that were
* derived from decomposition of an outbound AMBA request. For more details, see "AXI Bridge
* Ordering" in the AXI chapter of the Databook. You should not clear this register unless your
* application master is requesting an amount of read data greater than Max_Read_Request_Size, and
* the remote device (or switch) is reordering completions that have different tags. Note: The
* access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is
* sticky.
*/
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_SHIFT)) & PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_OB_RD_SPLIT_BURST_EN_MASK)
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MASK (0xFFFFFFFEU)
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_SHIFT)) & PCIE_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF_RSVDP_1_MASK)
/*! @} */
/*! @name PL_DEBUG0_OFF - Debug Register 0 */
/*! @{ */
#define PCIE_PL_DEBUG0_OFF_DEB_REG_0_MASK (0xFFFFFFFFU)
#define PCIE_PL_DEBUG0_OFF_DEB_REG_0_SHIFT (0U)
/*! DEB_REG_0 - The value on cxpl_debug_info[31:0].
*/
#define PCIE_PL_DEBUG0_OFF_DEB_REG_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PL_DEBUG0_OFF_DEB_REG_0_SHIFT)) & PCIE_PL_DEBUG0_OFF_DEB_REG_0_MASK)
/*! @} */
/*! @name PL_DEBUG1_OFF - Debug Register 1 */
/*! @{ */
#define PCIE_PL_DEBUG1_OFF_DEB_REG_1_MASK (0xFFFFFFFFU)
#define PCIE_PL_DEBUG1_OFF_DEB_REG_1_SHIFT (0U)
/*! DEB_REG_1 - The value on cxpl_debug_info[63:32].
*/
#define PCIE_PL_DEBUG1_OFF_DEB_REG_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PL_DEBUG1_OFF_DEB_REG_1_SHIFT)) & PCIE_PL_DEBUG1_OFF_DEB_REG_1_MASK)
/*! @} */
/*! @name TX_P_FC_CREDIT_STATUS_OFF - Transmit Posted FC Credit Status */
/*! @{ */
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK (0xFFFU)
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT (0U)
/*! TX_P_DATA_FC_CREDIT - Transmit Posted Data FC Credits. The posted Data credits advertised by the
* receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends
* on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts,
* xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are
* infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_MASK)
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK (0xFF000U)
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT (12U)
/*! TX_P_HEADER_FC_CREDIT - Transmit Posted Header FC Credits. The posted Header credits advertised
* by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value
* depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts,
* xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are
* infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_MASK)
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name TX_NP_FC_CREDIT_STATUS_OFF - Transmit Non-Posted FC Credit Status */
/*! @{ */
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK (0xFFFU)
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT (0U)
/*! TX_NP_DATA_FC_CREDIT - Transmit Non-Posted Data FC Credits. The non-posted Data credits
* advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default
* value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts,
* xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data)
* are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_MASK)
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK (0xFF000U)
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT (12U)
/*! TX_NP_HEADER_FC_CREDIT - Transmit Non-Posted Header FC Credits. The non-posted Header credits
* advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.
* Default value depends on the number of advertised credits for header and data [12'b0,
* xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and
* data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_MASK)
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name TX_CPL_FC_CREDIT_STATUS_OFF - Transmit Completion FC Credit Status */
/*! @{ */
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK (0xFFFU)
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT (0U)
/*! TX_CPL_DATA_FC_CREDIT - Transmit Completion Data FC Credits. The Completion Data credits
* advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default
* value depends on the number of advertised credits for header and data [12'b0,
* xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and
* data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_MASK)
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK (0xFF000U)
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT (12U)
/*! TX_CPL_HEADER_FC_CREDIT - Transmit Completion Header FC Credits. The Completion Header credits
* advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP.
* Default value depends on the number of advertised credits for header and data [12'b0,
* xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header
* and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
*/
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_MASK)
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT)) & PCIE_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name QUEUE_STATUS_OFF - Queue Status */
/*! @{ */
#define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK (0x1U)
#define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT (0U)
/*! RX_TLP_FC_CREDIT_NON_RETURN - Received TLP FC Credits Not Returned. Indicates that the
* controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for
* that TLP have been restored by the receiver at the other end of the link.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_MASK)
#define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK (0x2U)
#define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT (1U)
/*! TX_RETRY_BUFFER_NE - Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
*/
#define PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_MASK)
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK (0x4U)
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT (2U)
/*! RX_QUEUE_NON_EMPTY - Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_MASK)
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK (0x8U)
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT (3U)
/*! RX_QUEUE_OVERFLOW - Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_QUEUE_OVERFLOW_MASK)
#define PCIE_QUEUE_STATUS_OFF_RSVDP_4_MASK (0x1FF0U)
#define PCIE_QUEUE_STATUS_OFF_RSVDP_4_SHIFT (4U)
/*! RSVDP_4 - Reserved for future use.
*/
#define PCIE_QUEUE_STATUS_OFF_RSVDP_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RSVDP_4_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RSVDP_4_MASK)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK (0x2000U)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT (13U)
/*! RX_SERIALIZATION_Q_NON_EMPTY - Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_NON_EMPTY_MASK)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_MASK (0x4000U)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_SHIFT (14U)
/*! RX_SERIALIZATION_Q_WRITE_ERR - Receive Serialization Queue Write Error. Indicates insufficient
* buffer space available to write to the serialization queue.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_WRITE_ERR_MASK)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_MASK (0x8000U)
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_SHIFT (15U)
/*! RX_SERIALIZATION_Q_READ_ERR - Receive Serialization Read Error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP.
*/
#define PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RX_SERIALIZATION_Q_READ_ERR_MASK)
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK (0x1FFF0000U)
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT (16U)
/*! TIMER_MOD_FLOW_CONTROL - FC Latency Timer Override Value. When you set the "FC Latency Timer
* Override Enable" in this register, the value in this field will override the FC latency timer
* value that the controller calculates according to the PCIe specification. For more details, see
* "Flow Control". Note: This register field is sticky.
*/
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_MASK)
#define PCIE_QUEUE_STATUS_OFF_RSVDP_29_MASK (0x60000000U)
#define PCIE_QUEUE_STATUS_OFF_RSVDP_29_SHIFT (29U)
/*! RSVDP_29 - Reserved for future use.
*/
#define PCIE_QUEUE_STATUS_OFF_RSVDP_29(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_RSVDP_29_SHIFT)) & PCIE_QUEUE_STATUS_OFF_RSVDP_29_MASK)
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK (0x80000000U)
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT (31U)
/*! TIMER_MOD_FLOW_CONTROL_EN - FC Latency Timer Override Enable. When this bit is set, the value
* from the "FC Latency Timer Override Value" field in this register will override the FC latency
* timer value that the controller calculates according to the PCIe specification. Note: This
* register field is sticky.
*/
#define PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT)) & PCIE_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_MASK)
/*! @} */
/*! @name VC_TX_ARBI_1_OFF - VC Transmit Arbitration Register 1 */
/*! @{ */
#define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK (0xFFU)
#define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT (0U)
/*! WRR_WEIGHT_VC_0 - WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
*/
#define PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT)) & PCIE_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_MASK)
/*! @} */
/*! @name VC0_P_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Posted Receive Queue Control. */
/*! @{ */
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK (0xFFFU)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT (0U)
/*! VC0_P_DATA_CREDIT - VC0 Posted Data Credits. The number of initial posted data credits for VC0,
* used only in the segmented-buffer configuration. Note: The access attributes of this field are
* as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK (0xFF000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT (12U)
/*! VC0_P_HEADER_CREDIT - VC0 Posted Header Credits. The number of initial posted header credits for
* VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
* field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK (0x100000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT (20U)
/*! RESERVED4 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED4_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK (0xE00000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT (21U)
/*! VC0_P_TLP_Q_MODE - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK (0x3000000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT (24U)
/*! VC0_P_HDR_SCALE - VC0 Scale Posted Header Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_HDR_SCALE_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK (0xC000000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT (26U)
/*! VC0_P_DATA_SCALE - VC0 Scale Posted Data Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_SCALE_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK (0x30000000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT (28U)
/*! RESERVED5 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_RESERVED5_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK (0x40000000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT (30U)
/*! TLP_TYPE_ORDERING_VC0 - TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0
* receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules
* (recommended) - 0: Strict ordering: posted, completion, then non-posted Note: This register field
* is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_MASK)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK (0x80000000U)
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT (31U)
/*! VC_ORDERING_RX_Q - VC Ordering for Receive Queues. Determines the VC ordering rule for the
* receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher
* numbered VCs have higher priority - 0: Round robin Note: This register field is sticky.
*/
#define PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT)) & PCIE_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_MASK)
/*! @} */
/*! @name VC0_NP_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Non-Posted Receive Queue Control. */
/*! @{ */
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK (0xFFFU)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT (0U)
/*! VC0_NP_DATA_CREDIT - VC0 Non-Posted Data Credits. The number of initial non-posted data credits
* for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
* field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK (0xFF000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT (12U)
/*! VC0_NP_HEADER_CREDIT - VC0 Non-Posted Header Credits. The number of initial non-posted header
* credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of
* this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK (0x100000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT (20U)
/*! RESERVED6 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK (0xE00000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT (21U)
/*! VC0_NP_TLP_Q_MODE - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK (0x3000000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT (24U)
/*! VC0_NP_HDR_SCALE - VC0 Scale Non-Posted Header Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HDR_SCALE_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK (0xC000000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT (26U)
/*! VC0_NP_DATA_SCALE - VC0 Scale Non-Posted Data Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_SCALE_MASK)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK (0xF0000000U)
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT (28U)
/*! RESERVED7 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT)) & PCIE_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_MASK)
/*! @} */
/*! @name VC0_CPL_RX_Q_CTRL_OFF - Segmented-Buffer VC0 Completion Receive Queue Control. */
/*! @{ */
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK (0xFFFU)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT (0U)
/*! VC0_CPL_DATA_CREDIT - VC0 Completion Data Credits. The number of initial Completion data credits
* for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this
* field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK (0xFF000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT (12U)
/*! VC0_CPL_HEADER_CREDIT - VC0 Completion Header Credits. The number of initial Completion header
* credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes
* of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK (0x100000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT (20U)
/*! RESERVED8 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK (0xE00000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT (21U)
/*! VC0_CPL_TLP_Q_MODE - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK (0x3000000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT (24U)
/*! VC0_CPL_HDR_SCALE - VC0 Scale CPL Header Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HDR_SCALE_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK (0xC000000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT (26U)
/*! VC0_CPL_DATA_SCALE - VC0 Scale CPL Data Credites. Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_SCALE_MASK)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK (0xF0000000U)
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT (28U)
/*! RESERVED9 - Reserved. Note: This register field is sticky.
*/
#define PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT)) & PCIE_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_MASK)
/*! @} */
/*! @name GEN2_CTRL_OFF - Link Width and Speed Change Control Register. */
/*! @{ */
#define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK (0xFFU)
#define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT (0U)
/*! FAST_TRAINING_SEQ - Sets the Number of Fast Training Sequences (N_FTS) that the controller
* advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link
* partner about the PHY's ability to recover synchronization after a low power state. The number
* should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to
* go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for
* M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note:
* This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_SHIFT)) & PCIE_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_MASK)
#define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_MASK (0x1F00U)
#define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT (8U)
/*! NUM_OF_LANES - Predetermined Number of Lanes. Defines the number of lanes which are connected
* and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that
* detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in
* Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or
* broken lane during the Detect Substate. However, it is also possible that such a lane might also
* fail to exit Electrical Idle and therefore prevent a valid link from being configured. This
* value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI
* Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes
* - 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the
* value in this register to reflect the number of lanes. You must also change the value in the "Link
* Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as
* the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then
* you must reduce the value in this register. For more information, see "How to Tie Off Unused
* Lanes." For information on upsizing and downsizing the link width, see "Link Establishment."
* This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are
* as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_NUM_OF_LANES(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT)) & PCIE_GEN2_CTRL_OFF_NUM_OF_LANES_MASK)
#define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_MASK (0xE000U)
#define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT (13U)
/*! PRE_DET_LANE - Predetermined Lane for Auto Flip. This field defines which physical lane is
* connected to logical Lane0 by the flip operation performed in Detect. Allowed values are: - 3'b000:
* Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1,
* depending on which lane is detected - 3'b001: Connect logical Lane0 to physical lane 1 -
* 3'b010: Connect logical Lane0 to physical lane 3 - 3'b011: Connect logical Lane0 to physical lane 7
* - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the
* receiver detect procedure to a particular lane when the default detect and polling procedure
* performed on all lanes cannot be successful. A notable example of when it is useful to program this
* field to a value different from the default, is when a lane is asymmetrically broken, that is,
* it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.
* Note: This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this
* field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_PRE_DET_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT)) & PCIE_GEN2_CTRL_OFF_PRE_DET_LANE_MASK)
#define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK (0x10000U)
#define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT (16U)
/*! AUTO_LANE_FLIP_CTRL_EN - Enable Auto flipping of the lanes. You must set the
* CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For
* more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed
* to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
* (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT)) & PCIE_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_MASK)
#define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK (0x20000U)
#define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT (17U)
/*! DIRECT_SPEED_CHANGE - Directed Speed Change. Writing "1" to this field instructs the LTSSM to
* initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the
* speed change occurs, the controller will clear the contents of this field; and a read to this
* field by your software will return a "0". To manually initiate the speed change: - Write to
* LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this
* field - Assert this field If you set the default of this field using the
* DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link
* up, and the controller clears the contents of this field. If you want to prevent this
* automatic speed change, then write a lower speed value to the Target Link Speed field of the Link
* Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI
* before link up. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes
* of this field are as follows: - Dbi: R/W
*/
#define PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_SHIFT)) & PCIE_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_MASK)
#define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK (0x40000U)
#define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT (18U)
/*! CONFIG_PHY_TX_CHANGE - Config PHY Tx Swing. Controls the PHY transmitter voltage swing level.
* The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing -
* 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of
* this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_SHIFT)) & PCIE_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_MASK)
#define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK (0x80000U)
#define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT (19U)
/*! CONFIG_TX_COMP_RX - Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit
* TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved
* (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
* (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_SHIFT)) & PCIE_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_MASK)
#define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK (0x100000U)
#define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT (20U)
/*! SEL_DEEMPHASIS - Used to set the de-emphasis level for upstream ports. This bit selects the
* level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed
* to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W
* (sticky) Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_SHIFT)) & PCIE_GEN2_CTRL_OFF_SEL_DEEMPHASIS_MASK)
#define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK (0x200000U)
#define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT (21U)
/*! GEN1_EI_INFERENCE - Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine
* inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1
* speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the
* PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of
* corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just
* detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use
* RxValid signal to infer Electrical Idle Note: This register field is sticky.
*/
#define PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT)) & PCIE_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_MASK)
#define PCIE_GEN2_CTRL_OFF_RSVDP_22_MASK (0xFFC00000U)
#define PCIE_GEN2_CTRL_OFF_RSVDP_22_SHIFT (22U)
/*! RSVDP_22 - Reserved for future use.
*/
#define PCIE_GEN2_CTRL_OFF_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_GEN2_CTRL_OFF_RSVDP_22_SHIFT)) & PCIE_GEN2_CTRL_OFF_RSVDP_22_MASK)
/*! @} */
/*! @name PHY_STATUS_OFF - PHY Status Register. */
/*! @{ */
#define PCIE_PHY_STATUS_OFF_PHY_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_PHY_STATUS_OFF_PHY_STATUS_SHIFT (0U)
/*! PHY_STATUS - PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO
* register reflecting the values on the static phy_cfg_status input signals. The usage is left
* completely to the user and does not in any way influence controller functionality. You can use it
* for any static sideband status signalling requirements that you have for your PHY. This field
* is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_PHY_STATUS_OFF_PHY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_STATUS_OFF_PHY_STATUS_SHIFT)) & PCIE_PHY_STATUS_OFF_PHY_STATUS_MASK)
/*! @} */
/*! @name PHY_CONTROL_OFF - PHY Control Register. */
/*! @{ */
#define PCIE_PHY_CONTROL_OFF_PHY_CONTROL_MASK (0xFFFFFFFFU)
#define PCIE_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT (0U)
/*! PHY_CONTROL - PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO
* register driving the values on the static cfg_phy_control output signals. The usage is left
* completely to the user and does not in any way influence controller functionality. You can use it for
* any static sideband control signalling requirements that you have for your PHY. This field is
* reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_PHY_CONTROL_OFF_PHY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_CONTROL_OFF_PHY_CONTROL_SHIFT)) & PCIE_PHY_CONTROL_OFF_PHY_CONTROL_MASK)
/*! @} */
/*! @name TRGT_MAP_CTRL_OFF - Programmable Target Map Control Register. */
/*! @{ */
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK (0x3FU)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT (0U)
/*! TARGET_MAP_PF - Target Values for each BAR on the PF Function selected by the index number. This
* register does not respect the Byte Enable setting. any write will affect all register bits.
*/
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_PF_MASK)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK (0x40U)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT (6U)
/*! TARGET_MAP_ROM - Target Value for the ROM page of the PF Function selected by the index number.
* This register does not respect the Byte Enable setting. any write will affect all register
* bits.
*/
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_ROM_MASK)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK (0xE000U)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT (13U)
/*! TARGET_MAP_RESERVED_13_15 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R (sticky)
*/
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_13_15_MASK)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK (0x1F0000U)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT (16U)
/*! TARGET_MAP_INDEX - The number of the PF Function on which the Target Values are set. This
* register does not respect the Byte Enable setting. any write will affect all register bits.
*/
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_INDEX_MASK)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK (0xFFE00000U)
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT (21U)
/*! TARGET_MAP_RESERVED_21_31 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R (sticky)
*/
#define PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_SHIFT)) & PCIE_TRGT_MAP_CTRL_OFF_TARGET_MAP_RESERVED_21_31_MASK)
/*! @} */
/*! @name MSI_CTRL_ADDR_OFF - Integrated MSI Reception Module (iMRM) Address Register. */
/*! @{ */
#define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT (0U)
/*! MSI_CTRL_ADDR - Integrated MSI Reception Module Address. System specified address for MSI memory
* write transaction termination. Within the AXI Bridge, every received Memory Write request is
* examined to see if it targets the MSI Address that has been specified in this register; and
* also to see if it satisfies the definition of an MSI interrupt request. When these conditions
* are satisfied the Memory Write request is marked as an MSI request. Note: This register field is
* sticky.
*/
#define PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_SHIFT)) & PCIE_MSI_CTRL_ADDR_OFF_MSI_CTRL_ADDR_MASK)
/*! @} */
/*! @name MSI_CTRL_UPPER_ADDR_OFF - Integrated MSI Reception Module Upper Address Register. */
/*! @{ */
#define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT (0U)
/*! MSI_CTRL_UPPER_ADDR - Integrated MSI Reception Module Upper Address. System specified upper
* address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI
* address. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_SHIFT)) & PCIE_MSI_CTRL_UPPER_ADDR_OFF_MSI_CTRL_UPPER_ADDR_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_0_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT (0U)
/*! MSI_CTRL_INT_0_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_SHIFT)) & PCIE_MSI_CTRL_INT_0_EN_OFF_MSI_CTRL_INT_0_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_0_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_0_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_0_MASK_OFF_MSI_CTRL_INT_0_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_0_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_0_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_0_STATUS_OFF_MSI_CTRL_INT_0_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_1_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT (0U)
/*! MSI_CTRL_INT_1_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_SHIFT)) & PCIE_MSI_CTRL_INT_1_EN_OFF_MSI_CTRL_INT_1_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_1_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_1_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_1_MASK_OFF_MSI_CTRL_INT_1_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_1_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_1_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_1_STATUS_OFF_MSI_CTRL_INT_1_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_2_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT (0U)
/*! MSI_CTRL_INT_2_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_SHIFT)) & PCIE_MSI_CTRL_INT_2_EN_OFF_MSI_CTRL_INT_2_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_2_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_2_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_2_MASK_OFF_MSI_CTRL_INT_2_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_2_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_2_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_2_STATUS_OFF_MSI_CTRL_INT_2_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_3_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT (0U)
/*! MSI_CTRL_INT_3_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_SHIFT)) & PCIE_MSI_CTRL_INT_3_EN_OFF_MSI_CTRL_INT_3_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_3_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_3_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_3_MASK_OFF_MSI_CTRL_INT_3_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_3_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_3_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_3_STATUS_OFF_MSI_CTRL_INT_3_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_4_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT (0U)
/*! MSI_CTRL_INT_4_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_SHIFT)) & PCIE_MSI_CTRL_INT_4_EN_OFF_MSI_CTRL_INT_4_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_4_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_4_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_4_MASK_OFF_MSI_CTRL_INT_4_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_4_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_4_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_4_STATUS_OFF_MSI_CTRL_INT_4_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_5_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT (0U)
/*! MSI_CTRL_INT_5_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_SHIFT)) & PCIE_MSI_CTRL_INT_5_EN_OFF_MSI_CTRL_INT_5_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_5_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_5_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_5_MASK_OFF_MSI_CTRL_INT_5_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_5_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_5_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_5_STATUS_OFF_MSI_CTRL_INT_5_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_6_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT (0U)
/*! MSI_CTRL_INT_6_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_SHIFT)) & PCIE_MSI_CTRL_INT_6_EN_OFF_MSI_CTRL_INT_6_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_6_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_6_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_6_MASK_OFF_MSI_CTRL_INT_6_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_6_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_6_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_6_STATUS_OFF_MSI_CTRL_INT_6_STATUS_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_7_EN_OFF - Integrated MSI Reception Module Interrupt#i Enable Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT (0U)
/*! MSI_CTRL_INT_7_EN - MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI
* is received from a disabled interrupt, no status bit gets set in MSI controller interrupt
* status register. Each bit corresponds to a single MSI Interrupt Vector. Note: This register field
* is sticky.
*/
#define PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_SHIFT)) & PCIE_MSI_CTRL_INT_7_EN_OFF_MSI_CTRL_INT_7_EN_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_7_MASK_OFF - Integrated MSI Reception Module Interrupt#i Mask Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT (0U)
/*! MSI_CTRL_INT_7_MASK - MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI
* is received for a masked interrupt, the corresponding status bit gets set in the interrupt
* status register but the msi_ctrl_int output is not set HIGH. Each bit corresponds to a single MSI
* Interrupt Vector. Note: This register field is sticky.
*/
#define PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_SHIFT)) & PCIE_MSI_CTRL_INT_7_MASK_OFF_MSI_CTRL_INT_7_MASK_MASK)
/*! @} */
/*! @name MSI_CTRL_INT_7_STATUS_OFF - Integrated MSI Reception Module Interrupt#i Status Register. */
/*! @{ */
#define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK (0xFFFFFFFFU)
#define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT (0U)
/*! MSI_CTRL_INT_7_STATUS - MSI Interrupt#i Status. When an MSI is detected for EP#i, one bit in
* this register is set. The decoding of the data payload of the MSI Memory Write request determines
* which bit gets set. A status is bit is cleared by writing a 1 to the bit. Each bit
* corresponds to a single MSI Interrupt Vector.
*/
#define PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_SHIFT)) & PCIE_MSI_CTRL_INT_7_STATUS_OFF_MSI_CTRL_INT_7_STATUS_MASK)
/*! @} */
/*! @name MSI_GPIO_IO_OFF - Integrated MSI Reception Module General Purpose IO Register. */
/*! @{ */
#define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK (0xFFFFFFFFU)
#define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT (0U)
/*! MSI_GPIO_REG - MSI GPIO Register. The contents of this register drives the top-level GPIO
* msi_ctrl_io[31:0] Note: This register field is sticky.
*/
#define PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_SHIFT)) & PCIE_MSI_GPIO_IO_OFF_MSI_GPIO_REG_MASK)
/*! @} */
/*! @name CLOCK_GATING_CTRL_OFF - RADM clock gating enable control register. */
/*! @{ */
#define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK (0x1U)
#define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT (0U)
/*! RADM_CLK_GATING_EN - Enable Radm clock gating feature. - 0: Disable - 1: Enable(default)
*/
#define PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_SHIFT)) & PCIE_CLOCK_GATING_CTRL_OFF_RADM_CLK_GATING_EN_MASK)
#define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_MASK (0xFFFFFFFEU)
#define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_SHIFT)) & PCIE_CLOCK_GATING_CTRL_OFF_RSVDP_1_MASK)
/*! @} */
/*! @name ORDER_RULE_CTRL_OFF - Order Rule Control Register. */
/*! @{ */
#define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK (0xFFU)
#define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT (0U)
/*! NP_PASS_P - Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P
* queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P
*/
#define PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_NP_PASS_P_MASK)
#define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK (0xFF00U)
#define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT (8U)
/*! CPL_PASS_P - Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted
* P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P
*/
#define PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_CPL_PASS_P_MASK)
#define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_MASK (0xFFFF0000U)
#define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_SHIFT)) & PCIE_ORDER_RULE_CTRL_OFF_RSVDP_16_MASK)
/*! @} */
/*! @name PIPE_LOOPBACK_CONTROL_OFF - PIPE Loopback Control Register. */
/*! @{ */
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK (0xFFFFU)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT (0U)
/*! LPBK_RXVALID - LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_MASK)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK (0x3F0000U)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT (16U)
/*! RXSTATUS_LANE - RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_MASK)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MASK (0xC00000U)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SHIFT (22U)
/*! RSVDP_22 - Reserved for future use.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_MASK)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK (0x7000000U)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT (24U)
/*! RXSTATUS_VALUE - RXSTATUS_VALUE is an internally reserved field. Do not use.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_MASK)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MASK (0x78000000U)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SHIFT (27U)
/*! RSVDP_27 - Reserved for future use.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_MASK)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK (0x80000000U)
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT (31U)
/*! PIPE_LOOPBACK - PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky.
*/
#define PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT)) & PCIE_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_MASK)
/*! @} */
/*! @name MISC_CONTROL_1_OFF - DBI Read-Only Write Enable Register. */
/*! @{ */
#define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK (0x1U)
#define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT (0U)
/*! DBI_RO_WR_EN - Write to RO Registers Using DBI. When you set this field to "1", then some RO and
* HwInit bits are writable from the local application through the DBI. For more details, see
* "Writing to Read-Only Registers." Note: This register field is sticky.
*/
#define PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_MASK)
#define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK (0x2U)
#define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT (1U)
/*! DEFAULT_TARGET - Default target a received IO or MEM request with UR/CA/CRS is sent to by the
* controller. - 0: The controller drops all incoming I/O or MEM requests (after corresponding
* error reporting). A completion with UR status will be generated for non-posted requests. - 1: The
* controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application
* For more details, see "ECRC Handling" and "Request TLP Routing Rules" in "Receive Routing"
* section of the "Controller Operations" chapter of the Databook. Default value is DEFAULT_TARGET
* configuration parameter. Note: This register field is sticky.
*/
#define PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_DEFAULT_TARGET_MASK)
#define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK (0x4U)
#define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT (2U)
/*! UR_CA_MASK_4_TRGT1 - This field only applies to request TLPs (with UR filtering status) that you
* have chosen to forward to the application (when you set DEFAULT_TARGET in this register). -
* When you set this field to '1', the core suppresses error logging, Error Message generation,
* and CPL generation (for non-posted requests). - For more details, refer to the "Advanced Error
* Handling For Received TLPs" chapter of the Databook. You should set this if you have set the
* Default Target port logic register to '1'. Default is CX_MASK_UR_CA_4_TRGT1 configuration
* parameter. Note: This register field is sticky.
*/
#define PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_MASK)
#define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK (0x8U)
#define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT (3U)
/*! SIMPLIFIED_REPLAY_TIMER - Enables Simplified Replay Timer (Gen4). For more details, see
* "Transmit Replay" in the Controller Operations chapter of the Databook. Simplified Replay Timer Values
* are: - A value from 24,000 to 31,000 Symbol Times when Extended Synch is 0b. - A value from
* 80,000 to 100,000 Symbol Times when Extended Synch is 1b. Must not be changed while link is in
* use. Note: This register field is sticky.
*/
#define PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_SIMPLIFIED_REPLAY_TIMER_MASK)
#define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK (0x20U)
#define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT (5U)
/*! ARI_DEVICE_NUMBER - When ARI is enabled, this field enables use of the device ID. Note: This register field is sticky.
*/
#define PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_ARI_DEVICE_NUMBER_MASK)
#define PCIE_MISC_CONTROL_1_OFF_RSVDP_6_MASK (0xFFFFFFC0U)
#define PCIE_MISC_CONTROL_1_OFF_RSVDP_6_SHIFT (6U)
/*! RSVDP_6 - Reserved for future use.
*/
#define PCIE_MISC_CONTROL_1_OFF_RSVDP_6(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MISC_CONTROL_1_OFF_RSVDP_6_SHIFT)) & PCIE_MISC_CONTROL_1_OFF_RSVDP_6_MASK)
/*! @} */
/*! @name MULTI_LANE_CONTROL_OFF - UpConfigure Multi-lane Control Register. */
/*! @{ */
#define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK (0x3FU)
#define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT (0U)
/*! TARGET_LINK_WIDTH - Target Link Width. Values correspond to: - 6'b000000: Core does not start
* upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 -
* 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32 This field is
* reserved (fixed to '0') for M-PCIe.
*/
#define PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_MASK)
#define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK (0x40U)
#define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT (6U)
/*! DIRECT_LINK_WIDTH_CHANGE - Directed Link Width Change. The controller always moves to
* Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable
* variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is
* '0', the controller starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH
* value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the controller does not
* start upconfigure or autonomous width downsizing in the Configuration state. The controller
* self-clears this field when the controller accepts this request. This field is reserved (fixed
* to '0') for M-PCIe.
*/
#define PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_MASK)
#define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK (0x80U)
#define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT (7U)
/*! UPCONFIGURE_SUPPORT - Upconfigure Support. The controller sends this value as the Link
* Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved
* (fixed to '0') for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_MASK)
#define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_MASK (0xFFFFFF00U)
#define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_SHIFT)) & PCIE_MULTI_LANE_CONTROL_OFF_RSVDP_8_MASK)
/*! @} */
/*! @name PHY_INTEROP_CTRL_OFF - PHY Interoperability Control Register. */
/*! @{ */
#define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK (0x7FU)
#define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT (0U)
/*! RXSTANDBY_CONTROL - Rxstandby Control. Bits 0..5 determine if the controller asserts the
* RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to
* perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN -
* [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 -
* [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This
* field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_MASK)
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_MASK (0x80U)
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_SHIFT (7U)
/*! RSVDP_7 - Reserved for future use.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_7_MASK)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK (0x100U)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT (8U)
/*! L1SUB_EXIT_MODE - L1 Exit Control Using phy_mac_pclkack_n. - 1: Core exits L1 without waiting
* for the PHY to assert phy_mac_pclkack_n. - 0: Core waits for the PHY to assert phy_mac_pclkack_n
* before exiting L1. Note: This register field is sticky.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1SUB_EXIT_MODE_MASK)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK (0x200U)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT (9U)
/*! L1_NOWAIT_P1 - L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition
* to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before
* entering L1. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note:
* This register field is sticky.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_MASK)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK (0x400U)
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT (10U)
/*! L1_CLK_SEL - L1 Clock control bit. - 1: Controller does not request aux_clk switch and core_clk
* gating in L1. - 0: Controller requests aux_clk switch and core_clk gating in L1. Note: This
* register field is sticky.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_L1_CLK_SEL_MASK)
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_MASK (0xFFFFF800U)
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_SHIFT (11U)
/*! RSVDP_11 - Reserved for future use.
*/
#define PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_SHIFT)) & PCIE_PHY_INTEROP_CTRL_OFF_RSVDP_11_MASK)
/*! @} */
/*! @name TRGT_CPL_LUT_DELETE_ENTRY_OFF - TRGT_CPL_LUT Delete Entry Control register. */
/*! @{ */
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK (0x7FFFFFFFU)
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT (0U)
/*! LOOK_UP_ID - This number selects one entry to delete of the TRGT_CPL_LUT.
*/
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT)) & PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_MASK)
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK (0x80000000U)
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT (31U)
/*! DELETE_EN - This is a one-shot bit. A '1' write to this bit triggers the deletion of the target
* completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing
* register field. Reading from this register field always returns a '0'.
*/
#define PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT)) & PCIE_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_MASK)
/*! @} */
/*! @name LINK_FLUSH_CONTROL_OFF - Link Reset Request Flush Control Register. */
/*! @{ */
#define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK (0x1U)
#define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT (0U)
/*! AUTO_FLUSH_EN - Enables automatic flushing of pending requests before sending the reset request
* to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process
* is initiated if any of the following events occur: - Hot reset request. A downstream port
* (DSP) can "hot reset" an upstream port (USP) by sending two consecutive TS1 ordered sets with the
* hot reset bit asserted. - Warm (Soft) reset request. Generated when exiting from D3 to D0 and
* cfg_pm_no_soft_rst=0. - Link down reset request. A high to low transition on smlh_req_rst_not
* indicates the link has gone down and the controller is requesting a reset. If you disable
* automatic flushing, your application is responsible for resetting the PCIe controller and the AXI
* Bridge. For more details see "Warm and Hot Resets" section in the Architecture chapter of the
* Databook. Note: This register field is sticky.
*/
#define PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_AUTO_FLUSH_EN_MASK)
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MASK (0xFFFFFEU)
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_RSVDP_1_MASK)
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MASK (0xFF000000U)
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SHIFT (24U)
/*! RSVD_I_8 - This is an internally reserved field. Do not use. Note: This register field is sticky.
*/
#define PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_SHIFT)) & PCIE_LINK_FLUSH_CONTROL_OFF_RSVD_I_8_MASK)
/*! @} */
/*! @name AMBA_ERROR_RESPONSE_DEFAULT_OFF - AXI Bridge Slave Error Response Register. */
/*! @{ */
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK (0x1U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT (0U)
/*! AMBA_ERROR_RESPONSE_GLOBAL - Global Slave Error Response Mapping. Determines the AXI slave
* response for all error scenarios on non-posted requests. For more details see "Error Handling" in
* the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for non-posted requests) and
* ignore the setting in bit [2] of this register. - 1: ERROR for normal link (data) accesses and
* look at bit [2] for other scenarios. AXI: - 0: OKAY (with FFFF data for non-posted requests) -
* 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines the PCIe-to-AXI Slave error
* response mapping) The error response mapping is not applicable to Non-existent Vendor ID register
* reads. Note: This register field is sticky.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_GLOBAL_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MASK (0x2U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_1_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK (0x4U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT (2U)
/*! AMBA_ERROR_RESPONSE_VENDORID - Vendor ID Non-existent Slave Error Response Mapping. Determines
* the AXI slave response for errors on reads to non-existent Vendor ID register. For more details
* see "Error Handling" in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data). The
* controller ignores the setting in the bit when bit 0 of this register is '0'. - 1: ERROR AXI:
* - 0: OKAY (with FFFF data). - 1: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP field determines
* the PCIe-to-AXI Slave error response mapping) Note: This register field is sticky.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_VENDORID_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK (0x18U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT (3U)
/*! AMBA_ERROR_RESPONSE_CRS - CRS Slave Error Response Mapping. Determines the AXI slave response
* for CRS completions. For more details see "Error Handling" in the AXI chapter of the Databook.
* AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all FFFF_FFFF data for all CRS
* completions - 10: OKAY with FFFF_0001 data for CRS completions to vendor ID read requests, OKAY
* with FFFF_FFFF data for all other CRS completions - 11: SLVERR/DECERR (the AXI_ERROR_RESPONSE_MAP
* field determines the PCIe-to-AXI Slave error response mapping) Note: This register field is
* sticky.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_CRS_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MASK (0x3E0U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SHIFT (5U)
/*! RSVDP_5 - Reserved for future use.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_5_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK (0xFC00U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT (10U)
/*! AMBA_ERROR_RESPONSE_MAP - AXI Slave Response Error Map. Allows you to selectively map the errors
* received from the PCIe completion (for non-posted requests) to the AXI slave responses,
* slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is always mapped to OKAY. - [0] - 0:
* UR (unsupported request) -> DECERR - 1: UR (unsupported request) -> SLVERR - [1] - 0: CRS
* (configuration retry status) -> DECERR - 1: CRS (configuration retry status) -> SLVERR - [2] - 0:
* CA (completer abort) -> DECERR - 1: CA (completer abort) -> SLVERR - [3]: Reserved - [4]:
* Reserved - [5]: - 0: Completion Timeout -> DECERR - 1: Completion Timeout -> SLVERR The AXI
* bridge internally drops (processes internally but not passed to your application) a completion that
* has been marked by the Rx filter as UC or MLF, and does not pass its status directly down to
* the slave interface. It waits for a timeout and then signals "Completion Timeout" to the slave
* interface. The controller sets the AXI slave read databus to 0xFFFF for all error responses.
* Note: This register field is sticky.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_AMBA_ERROR_RESPONSE_MAP_MASK)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MASK (0xFFFF0000U)
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SHIFT (16U)
/*! RSVDP_16 - Reserved for future use.
*/
#define PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_SHIFT)) & PCIE_AMBA_ERROR_RESPONSE_DEFAULT_OFF_RSVDP_16_MASK)
/*! @} */
/*! @name AMBA_LINK_TIMEOUT_OFF - Link Down AXI Bridge Slave Timeout Register. */
/*! @{ */
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK (0xFFU)
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT (0U)
/*! LINK_TIMEOUT_PERIOD_DEFAULT - Timeout Value (ms). The timer will timeout and then flush the
* bridge TX request queues after this amount of time. The timer counts when there are pending
* outbound AXI slave interface requests and the PCIe TX link is not transmitting any of these
* requests. The timer is clocked by core_clk. For an M-PCIe configuration: - Time unit of this field is
* 4 ms. - Margin of error for RateA clock is < 1%. - Margin of error for RateB clock is between
* 16% and 17%. Note: This register field is sticky.
*/
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_PERIOD_DEFAULT_MASK)
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK (0x100U)
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT (8U)
/*! LINK_TIMEOUT_ENABLE_DEFAULT - Disable Flush. You can disable the flush feature by setting this field to "1". Note: This register field is sticky.
*/
#define PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_LINK_TIMEOUT_ENABLE_DEFAULT_MASK)
#define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MASK (0xFFFFFE00U)
#define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SHIFT (9U)
/*! RSVDP_9 - Reserved for future use.
*/
#define PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_SHIFT)) & PCIE_AMBA_LINK_TIMEOUT_OFF_RSVDP_9_MASK)
/*! @} */
/*! @name AMBA_ORDERING_CTRL_OFF - AMBA Ordering Control. */
/*! @{ */
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MASK (0x1U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SHIFT (0U)
/*! RSVDP_0 - Reserved for future use.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_0_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK (0x2U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT (1U)
/*! AX_SNP_EN - AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to
* serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding
* same ID NP Read or Write on the wire and used to avoid AXI RAR and WAW hazards at the remote
* link partner. For more details, see the "Optional Serialization of AXI Slave Non-posted
* Requests" section in the AXI chapter of the Databook.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_SNP_EN_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MASK (0x4U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SHIFT (2U)
/*! RSVDP_2 - Reserved for future use.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_2_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK (0x18U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT (3U)
/*! AX_MSTR_ORDR_P_EVENT_SEL - AXI Master Posted Ordering Event Selector. This field selects how the
* master interface determines when a P write is completed when enforcing the PCIe ordering
* rule, "NP must not pass P" at the AXI Master Interface. The AXI protocol does not support ordering
* between channels. Therefore, NP reads can pass P on your AXI bus fabric. This can result in
* an ordering violation when the read overtakes a P that is going to the same address. Therefore,
* the bridge master does not issue any NP requests until all outstanding P writes reach their
* destination. It does this by waiting for the all of the write responses on the B channel. This
* can affect the performance of the master read channel. For scenarios where the interconnect
* serializes the AXI master "AW", "W" and "AR" channels,you can increase the performance by
* reducing the need to wait until the complete Posted transaction has effectively reached the
* application slave. - 00: B'last event: wait for the all of the write responses on the B channel
* thereby ensuring that the complete Posted transaction has effectively reached the application slave
* (default). - 01: AW'last event: wait until the complete Posted transaction has left the AXI
* address channel at the bridge master. - 10: W'last event: wait until the complete Posted
* transaction has left the AXI data channel at the bridge master. - 11: Reserved Note 2: This setting
* will not affect: - MSI interrupt catcher and P data ordering. This is always driven by the
* B'last event. - DMA read engine TLP ordering. This is always driven by the B'last event. - NP
* write transactions which are always serialized with P write transactions.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ORDR_P_EVENT_SEL_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MASK (0x60U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SHIFT (5U)
/*! RSVDP_5 - Reserved for future use.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_5_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK (0x80U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT (7U)
/*! AX_MSTR_ZEROLREAD_FW - AXI Master Zero Length Read Forward to the application. The DW PCIe
* controller AXI bridge is able to terminate in order with the Posted transactions the zero length
* read, implementing the PCIe express flush semantics of the Posted transactions. - 0x0: The zero
* length Read is terminated at the DW PCIe AXI bridge master - 0x1: The zero length Read is
* forward to the application.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_AX_MSTR_ZEROLREAD_FW_MASK)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MASK (0xFFFFFF00U)
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_SHIFT)) & PCIE_AMBA_ORDERING_CTRL_OFF_RSVDP_8_MASK)
/*! @} */
/*! @name AXI_MSTR_MSG_ADDR_LOW_OFF - Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. */
/*! @{ */
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK (0xFFFU)
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT (0U)
/*! CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED - Reserved for future use. Note: This register field is sticky.
*/
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED_MASK)
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK (0xFFFFF000U)
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT (12U)
/*! CFG_AXIMSTR_MSG_ADDR_LOW - Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky.
*/
#define PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_LOW_OFF_CFG_AXIMSTR_MSG_ADDR_LOW_MASK)
/*! @} */
/*! @name AXI_MSTR_MSG_ADDR_HIGH_OFF - Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to. */
/*! @{ */
#define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT (0U)
/*! CFG_AXIMSTR_MSG_ADDR_HIGH - Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky.
*/
#define PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_SHIFT)) & PCIE_AXI_MSTR_MSG_ADDR_HIGH_OFF_CFG_AXIMSTR_MSG_ADDR_HIGH_MASK)
/*! @} */
/*! @name PCIE_VERSION_NUMBER_OFF - PCIe Controller IIP Release Version Number. */
/*! @{ */
#define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK (0xFFFFFFFFU)
#define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT (0U)
/*! VERSION_NUMBER - Version Number.
*/
#define PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_SHIFT)) & PCIE_PCIE_VERSION_NUMBER_OFF_VERSION_NUMBER_MASK)
/*! @} */
/*! @name PCIE_VERSION_TYPE_OFF - PCIe Controller IIP Release Version Type. */
/*! @{ */
#define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK (0xFFFFFFFFU)
#define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT (0U)
/*! VERSION_TYPE - Version Type.
*/
#define PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_SHIFT)) & PCIE_PCIE_VERSION_TYPE_OFF_VERSION_TYPE_MASK)
/*! @} */
/*! @name AUX_CLK_FREQ_OFF - Auxiliary Clock Frequency Control Register. */
/*! @{ */
#define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK (0x3FFU)
#define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT (0U)
/*! AUX_CLK_FREQ - The aux_clk frequency in MHz. This value is used to provide a 1 us reference for
* counting time during low-power states with aux_clk when the PHY has removed the pipe_clk.
* Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the
* actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then
* there is an error in the time counted by the controller that can be expressed in percentage
* as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err%
* =(3/2.5-1)*100 =20%, meaning that the time counted by the controller on aux_clk will be 20% greater than
* the time in us programmed in the corresponding time register (for example T_POWER_ON). Note:
* This register field is sticky.
*/
#define PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT)) & PCIE_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_MASK)
#define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_MASK (0xFFFFFC00U)
#define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_SHIFT (10U)
/*! RSVDP_10 - Reserved for future use.
*/
#define PCIE_AUX_CLK_FREQ_OFF_RSVDP_10(x) (((uint32_t)(((uint32_t)(x)) << PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_SHIFT)) & PCIE_AUX_CLK_FREQ_OFF_RSVDP_10_MASK)
/*! @} */
/*! @name L1_SUBSTATES_OFF - L1 Substates Timing Register. */
/*! @{ */
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK (0x3U)
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT (0U)
/*! L1SUB_T_POWER_OFF - Duration (in 1us units) of L1.2.Entry. Range is 0.3. Note: The timeout value
* can vary by 50%. Note: This register field is sticky.
*/
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_POWER_OFF_MASK)
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK (0x3CU)
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT (2U)
/*! L1SUB_T_L1_2 - Duration (in 1us units) of L1.2. Range is 0.15. Note: The timeout value can vary
* by 50%. Note: This register field is sticky.
*/
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_L1_2_MASK)
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MASK (0xC0U)
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SHIFT (6U)
/*! L1SUB_T_PCLKACK - Max delay (in 1us units) between a MAC request to remove the clock on
* mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this
* time the request is aborted. Range is 0..3 Note: This register field is sticky.
*/
#define PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_SHIFT)) & PCIE_L1_SUBSTATES_OFF_L1SUB_T_PCLKACK_MASK)
#define PCIE_L1_SUBSTATES_OFF_RSVDP_8_MASK (0xFFFFFF00U)
#define PCIE_L1_SUBSTATES_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_L1_SUBSTATES_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_L1_SUBSTATES_OFF_RSVDP_8_SHIFT)) & PCIE_L1_SUBSTATES_OFF_RSVDP_8_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_0 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT (0U)
/*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT (5U)
/*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT (8U)
/*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT (9U)
/*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
* region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
* used in generating the function part of the requester ID (RID) field of the TLP is taken from
* this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
* the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
* field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
* "Max_Payload_Size" values are used. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_0_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_0 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
* region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
* changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
* outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
* then the ST field of the TLP is changed to the value in this register. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK (0xFF00U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT (8U)
/*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
* is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT (16U)
/*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
* substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
* this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
* Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
* in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
* field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_TAG_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT (19U)
/*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
* translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
* field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_FUNC_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK (0x100000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT (20U)
/*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
* Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
* Non-Posted Requests outstanding. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_SNP_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK (0x400000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT (22U)
/*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
* TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
* having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
* inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
* a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
* sent. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INHIBIT_PAYLOAD_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT (23U)
/*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
* iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
* the outbound TLP header with the contents of the LWR_TARGET_RW field in
* IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
* to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
* translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
* forms the new address of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_HEADER_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT (27U)
/*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
* pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
* set it to '0'. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_DMA_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
* XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
* TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
* of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
* TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
* of the PCIe configuration space. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. In systems with a 32-bit address space, this register is not used and therefore
* writing to this register has no effect. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_0 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_0_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
/*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
* (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
* address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
* aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
* the start address of the new address of the translated region (bits n-1:0) are always '0'). -
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
* IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
* header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
* the transmission of Vendor Defined Messages where the controller determines the content of
* bytes 12 to 15 of the TLP header. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0_LWR_TARGET_RW_OUTBOUND_MASK)
/*! @} */
/*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 - iATU Upper Target Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT (0U)
/*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
* of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0_UPPER_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_INBOUND_0 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT (0U)
/*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT (5U)
/*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT (8U)
/*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT (9U)
/*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
* controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
* this value, then address translation proceeds. This check is only performed if the "Function
* Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
* destination function number as specified in the routing ID of the TLP header matches the function, then
* address translation proceeds. This check is only performed if the "Function Number Match
* Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_0_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_INBOUND_0 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
* to this value, then address translation proceeds (when all other enabled field-matches are
* successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
* Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
* matched to this value, then address translation proceeds. This check is only performed if the
* "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
* the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK (0x700U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT (8U)
/*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
* normal internal BAR address matching mechanism " is the same as this field, address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
* 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
* translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
* the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_BAR_NUM_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT (13U)
/*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
* translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
* iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
* mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
* translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
* This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_TYPE_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK (0x4000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT (14U)
/*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TC_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK (0x8000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT (15U)
/*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_TD_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT (16U)
/*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
* (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_ATTR_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT (19U)
/*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
* field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
* MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUNC_NUM_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK (0x200000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT (21U)
/*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
* TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
* (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
* that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
* occurs (in MEM transactions) for address translation to proceed. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MSG_CODE_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
/*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
* be translated to a single address location as determined by the target address register of the
* iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
* Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_SINGLE_ADDR_LOC_TRANS_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK (0x3000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT (24U)
/*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
* region. This overrides the normal RADM filter response. Note that this feature is not available
* for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
* response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
* / undefined / reserved. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_RESPONSE_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
/*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
* the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
* identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
* The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
* For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
* inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_FUZZY_TYPE_MATCH_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
* configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
* allows a CFG configuration space to be located in any 256MB window of your application memory space
* using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
* bits [27:12] of the translated address. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK (0x40000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT (30U)
/*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
* of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
* Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
* "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
* follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
* header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
* transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
* to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
* routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
* processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
* MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
* Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
* the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
* but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
* [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
* lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
* information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
* 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_0_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_0 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_0_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_0 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_0_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_INBOUND_0 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_0_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_0 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT (0U)
/*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
* region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
* kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
* these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
* target address must align to the iATU region size; otherwise it must align to the BAR size. A
* write to this location is ignored by the PCIe controller. - Field size depends on
* log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
* log2(BAR_MASK+1) in BAR match mode.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_HW_MASK)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT (16U)
/*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
* region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
* of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
* mode. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_0_LWR_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_1 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT (0U)
/*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT (5U)
/*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT (8U)
/*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT (9U)
/*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
* region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
* used in generating the function part of the requester ID (RID) field of the TLP is taken from
* this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
* the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
* field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
* "Max_Payload_Size" values are used. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_1_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_1 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
* region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
* changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
* outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
* then the ST field of the TLP is changed to the value in this register. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK (0xFF00U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT (8U)
/*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
* is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT (16U)
/*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
* substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
* this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
* Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
* in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
* field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_TAG_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT (19U)
/*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
* translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
* field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_FUNC_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK (0x100000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT (20U)
/*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
* Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
* Non-Posted Requests outstanding. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_SNP_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK (0x400000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT (22U)
/*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
* TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
* having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
* inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
* a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
* sent. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INHIBIT_PAYLOAD_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT (23U)
/*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
* iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
* the outbound TLP header with the contents of the LWR_TARGET_RW field in
* IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
* to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
* translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
* forms the new address of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_HEADER_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT (27U)
/*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
* pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
* set it to '0'. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_DMA_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
* XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
* TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
* of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
* TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
* of the PCIe configuration space. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_1_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_1_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. In systems with a 32-bit address space, this register is not used and therefore
* writing to this register has no effect. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_1_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_1 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_1_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
/*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
* (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
* address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
* aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
* the start address of the new address of the translated region (bits n-1:0) are always '0'). -
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
* IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
* header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
* the transmission of Vendor Defined Messages where the controller determines the content of
* bytes 12 to 15 of the TLP header. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_1_LWR_TARGET_RW_OUTBOUND_MASK)
/*! @} */
/*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1 - iATU Upper Target Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT (0U)
/*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
* of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_1_UPPER_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_INBOUND_1 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT (0U)
/*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT (5U)
/*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT (8U)
/*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT (9U)
/*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
* controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
* this value, then address translation proceeds. This check is only performed if the "Function
* Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
* destination function number as specified in the routing ID of the TLP header matches the function, then
* address translation proceeds. This check is only performed if the "Function Number Match
* Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_1_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_INBOUND_1 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
* to this value, then address translation proceeds (when all other enabled field-matches are
* successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
* Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
* matched to this value, then address translation proceeds. This check is only performed if the
* "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
* the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK (0x700U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT (8U)
/*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
* normal internal BAR address matching mechanism " is the same as this field, address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
* 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
* translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
* the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_BAR_NUM_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT (13U)
/*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
* translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
* iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
* mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
* translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
* This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_TYPE_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK (0x4000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT (14U)
/*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TC_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK (0x8000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT (15U)
/*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_TD_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT (16U)
/*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
* (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_ATTR_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT (19U)
/*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
* field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
* MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUNC_NUM_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK (0x200000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT (21U)
/*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
* TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
* (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
* that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
* occurs (in MEM transactions) for address translation to proceed. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MSG_CODE_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
/*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
* be translated to a single address location as determined by the target address register of the
* iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
* Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_SINGLE_ADDR_LOC_TRANS_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK (0x3000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT (24U)
/*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
* region. This overrides the normal RADM filter response. Note that this feature is not available
* for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
* response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
* / undefined / reserved. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_RESPONSE_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
/*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
* the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
* identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
* The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
* For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
* inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_FUZZY_TYPE_MATCH_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
* configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
* allows a CFG configuration space to be located in any 256MB window of your application memory space
* using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
* bits [27:12] of the translated address. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK (0x40000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT (30U)
/*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
* of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
* Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
* "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
* follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
* header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
* transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
* to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
* routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
* processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
* MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
* Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
* the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
* but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
* [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
* lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
* information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
* 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_1_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_1 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_1_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_1 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_1_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_INBOUND_1 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_1_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_1 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT (0U)
/*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
* region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
* kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
* these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
* target address must align to the iATU region size; otherwise it must align to the BAR size. A
* write to this location is ignored by the PCIe controller. - Field size depends on
* log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
* log2(BAR_MASK+1) in BAR match mode.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_HW_MASK)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT (16U)
/*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
* region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
* of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
* mode. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_1_LWR_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_2 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT (0U)
/*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT (5U)
/*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT (8U)
/*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT (9U)
/*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
* region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
* used in generating the function part of the requester ID (RID) field of the TLP is taken from
* this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
* the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
* field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
* "Max_Payload_Size" values are used. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_2_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_2 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
* region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
* changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
* outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
* then the ST field of the TLP is changed to the value in this register. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK (0xFF00U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT (8U)
/*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
* is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT (16U)
/*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
* substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
* this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
* Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
* in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
* field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_TAG_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT (19U)
/*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
* translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
* field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_FUNC_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK (0x100000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT (20U)
/*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
* Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
* Non-Posted Requests outstanding. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_SNP_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK (0x400000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT (22U)
/*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
* TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
* having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
* inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
* a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
* sent. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INHIBIT_PAYLOAD_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT (23U)
/*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
* iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
* the outbound TLP header with the contents of the LWR_TARGET_RW field in
* IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
* to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
* translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
* forms the new address of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_HEADER_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT (27U)
/*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
* pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
* set it to '0'. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_DMA_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
* XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
* TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
* of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
* TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
* of the PCIe configuration space. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_2_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_2_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. In systems with a 32-bit address space, this register is not used and therefore
* writing to this register has no effect. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_2_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_2 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_2_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
/*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
* (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
* address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
* aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
* the start address of the new address of the translated region (bits n-1:0) are always '0'). -
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
* IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
* header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
* the transmission of Vendor Defined Messages where the controller determines the content of
* bytes 12 to 15 of the TLP header. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_2_LWR_TARGET_RW_OUTBOUND_MASK)
/*! @} */
/*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2 - iATU Upper Target Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT (0U)
/*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
* of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_2_UPPER_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_INBOUND_2 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT (0U)
/*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT (5U)
/*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT (8U)
/*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT (9U)
/*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
* controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
* this value, then address translation proceeds. This check is only performed if the "Function
* Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
* destination function number as specified in the routing ID of the TLP header matches the function, then
* address translation proceeds. This check is only performed if the "Function Number Match
* Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_2_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_INBOUND_2 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
* to this value, then address translation proceeds (when all other enabled field-matches are
* successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
* Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
* matched to this value, then address translation proceeds. This check is only performed if the
* "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
* the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK (0x700U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT (8U)
/*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
* normal internal BAR address matching mechanism " is the same as this field, address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
* 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
* translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
* the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_BAR_NUM_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT (13U)
/*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
* translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
* iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
* mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
* translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
* This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_TYPE_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK (0x4000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT (14U)
/*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TC_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK (0x8000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT (15U)
/*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_TD_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT (16U)
/*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
* (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_ATTR_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT (19U)
/*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
* field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
* MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUNC_NUM_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK (0x200000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT (21U)
/*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
* TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
* (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
* that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
* occurs (in MEM transactions) for address translation to proceed. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MSG_CODE_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
/*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
* be translated to a single address location as determined by the target address register of the
* iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
* Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_SINGLE_ADDR_LOC_TRANS_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK (0x3000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT (24U)
/*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
* region. This overrides the normal RADM filter response. Note that this feature is not available
* for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
* response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
* / undefined / reserved. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_RESPONSE_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
/*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
* the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
* identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
* The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
* For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
* inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_FUZZY_TYPE_MATCH_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
* configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
* allows a CFG configuration space to be located in any 256MB window of your application memory space
* using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
* bits [27:12] of the translated address. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK (0x40000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT (30U)
/*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
* of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
* Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
* "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
* follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
* header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
* transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
* to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
* routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
* processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
* MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
* Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
* the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
* but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
* [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
* lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
* information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
* 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_2_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_2 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_2_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_2 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_2_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_INBOUND_2 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_2_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_2 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT (0U)
/*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
* region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
* kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
* these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
* target address must align to the iATU region size; otherwise it must align to the BAR size. A
* write to this location is ignored by the PCIe controller. - Field size depends on
* log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
* log2(BAR_MASK+1) in BAR match mode.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_HW_MASK)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT (16U)
/*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
* region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
* of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
* mode. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_2_LWR_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_OUTBOUND_3 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT (0U)
/*! TYPE - When the address of an outbound TLP is matched to this region, then the TYPE field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT (5U)
/*! TC - When the address of an outbound TLP is matched to this region, then the TC field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT (8U)
/*! TD - When the address of an outbound TLP is matched to this region, then the TD field of the TLP
* is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT (9U)
/*! ATTR - When the address of an outbound TLP is matched to this region, then the ATTR field of the
* TLP is changed to the value in this register. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - When the address of an outbound TLP is matched to this
* region and the FUNC_BYPASS field in the "iATU Control 2 Register" is '0', then the function number
* used in generating the function part of the requester ID (RID) field of the TLP is taken from
* this 5-bit register. The value in this register must be 0x0 unless multifunction operation in
* the controller is enabled (CX_NFUNC > 1). - When you are using the AXI Bridge, then this
* field is swapped before AXI decomposition occurs so that the correct "Max_Read_Request_Size" and
* "Max_Payload_Size" values are used. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_OUTBOUND_3_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_OUTBOUND_3 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs (Message Code). When the address of an outbound TLP is matched to this
* region, and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is
* changed to the value in this register. Memory TLPs: (ST;Steering Tag). When the ST field of an
* outbound TLP is matched to this region, and the translated TLP TYPE field targets memory space;
* then the ST field of the TLP is changed to the value in this register. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK (0xFF00U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT (8U)
/*! TAG - TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN
* is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT (16U)
/*! TAG_SUBSTITUTE_EN - TAG Substitute Enable. When enabled and region address is matched, the iATU
* substitutes the TAG field of the outbound TLP header with the contents of the TAG field in
* this register. The expected usage scenario is translation from AXI MWr to Vendor Defined
* Msg/MsgD. Note (CX_TPH_ENABLE=1): TAG substitution for MWr will not occur because this field (byte 6)
* in the TLP header is the ST field. ST substitution can still take place using the MSG_CODE
* field in IATU_REGION_CTRL_2_OFF_OUTBOUND_i. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_TAG_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT (19U)
/*! FUNC_BYPASS - Function Number Translation Bypass. In this mode, the function number of the
* translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM
* field of the "iATU Control 1 Register" or the VF_NUMBER field of the "iATU Control 3 Register."
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_FUNC_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK (0x100000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT (20U)
/*! SNP - Serialize Non-Posted Requests. In this mode, when the AXI Bridge is populated, same AXI ID
* Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID
* Non-Posted Requests outstanding. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_SNP_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK (0x400000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT (22U)
/*! INHIBIT_PAYLOAD - Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be
* TLP without data. When enabled and region address is matched, the iATU marks all TLPs as
* having no payload data by forcing the TLP header Fmt[1] bit =0, regardless of the application
* inputs such as slv_wstrb. - 1: Fmt[1] =0 so that only TLP type without data is sent. For example,
* a Msg instead of MsgD will be sent. - 0: Fmt[1] =0/1 so that TLPs with or without data can be
* sent. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INHIBIT_PAYLOAD_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT (23U)
/*! HEADER_SUBSTITUTE_EN - Header Substitute Enable. When enabled and region address is matched, the
* iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of
* the outbound TLP header with the contents of the LWR_TARGET_RW field in
* IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i. - 1: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register is used
* to fill bytes 8-to-11 (for 3 DWORD header) or bytes 12-to-15 (for 4 DWORD header) of the
* translated TLP header. - 0: LWR_TARGET_RW in the iATU_LWR_TARGET_ADDR_OFF_OUTBOUND_i register
* forms the new address of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_HEADER_SUBSTITUTE_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT (27U)
/*! DMA_BYPASS - DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to
* pass through the iATU untranslated. Note: This field is reserved for the SW product. You must
* set it to '0'. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_DMA_BYPASS_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the
* XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG
* TLP. This supports the Enhanced Configuration Address Mapping (ECAM) mechanism (Section 7.2.2
* of the PCI Express Base 3.1 Specification, revision 1.0) by allowing all outgoing I/O and MEM
* TLPs (that have been translated to CFG) to be mapped from memory space into any 256 MB region
* of the PCIe configuration space. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_OUTBOUND_3_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_OUTBOUND_3_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. In systems with a 32-bit address space, this register is not used and therefore
* writing to this register has no effect. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_3_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_OUTBOUND_3 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_OUTBOUND_3_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK (0xFFFFFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT (0U)
/*! LWR_TARGET_RW_OUTBOUND - When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0'
* (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new
* address of the translated region; - LWR_TARGET_RW[n-1:0] are not used. (The start address must be
* aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB boundary, so the lower bits of
* the start address of the new address of the translated region (bits n-1:0) are always '0'). -
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region). When HEADER_SUBSTITUTE_EN in
* IATU_REGION_CTRL_2_OFF_OUTBOUND_i is '1': - LWR_TARGET_RW[31:0] forms bytes 8-11 (for 3 dword
* header) or bytes 12-15 (for 4 dword header) of the outbound TLP header. Usage scenarios include
* the transmission of Vendor Defined Messages where the controller determines the content of
* bytes 12 to 15 of the TLP header. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_3_LWR_TARGET_RW_OUTBOUND_MASK)
/*! @} */
/*! @name IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3 - iATU Upper Target Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT (0U)
/*! UPPER_TARGET_RW - Forms bits [63:32] of the start address (Upper Target part) of the new address
* of the translated region. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_SHIFT)) & PCIE_IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_3_UPPER_TARGET_RW_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_1_OFF_INBOUND_3 - iATU Region Control 1 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK (0x1FU)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT (0U)
/*! TYPE - When the TYPE field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TYPE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK (0xE0U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT (5U)
/*! TC - When the TC field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TC Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TC_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK (0x100U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT (8U)
/*! TD - When the TD field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed if
* the "TD Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_TD_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK (0x600U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT (9U)
/*! ATTR - When the ATTR field of an inbound TLP is matched to this value, then address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "ATTR Match Enable" bit of the "iATU Control 2 Register" is set. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_ATTR_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT (13U)
/*! INCREASE_REGION_SIZE - Increase the maximum ATU Region size. When set, the maximum ATU Region
* size is determined by CX_ATU_MAX_REGION_SIZEMaximum Size of iATU Region When clear, the maximum
* ATU Region size is 4 GB (default). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_INCREASE_REGION_SIZE_MASK)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK (0x700000U)
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT (20U)
/*! CTRL_1_FUNC_NUM - Function Number. - MEM-I/O: When the Address and BAR matching logic in the
* controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to
* this value, then address translation proceeds. This check is only performed if the "Function
* Number Match Enable" bit of the "iATU Control 2 Register" is set. - CFG0/CFG1: When the
* destination function number as specified in the routing ID of the TLP header matches the function, then
* address translation proceeds. This check is only performed if the "Function Number Match
* Enable" bit of the "iATU Control 2 Register" is set. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_1_OFF_INBOUND_3_CTRL_1_FUNC_NUM_MASK)
/*! @} */
/*! @name IATU_REGION_CTRL_2_OFF_INBOUND_3 - iATU Region Control 2 Register. */
/*! @{ */
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK (0xFFU)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT (0U)
/*! MSG_CODE - MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched
* to this value, then address translation proceeds (when all other enabled field-matches are
* successful). This check is only performed if the "Message Code Match Enable" bit of the "iATU
* Control 2 Register" is set. Memory TLPs: (ST;Steering Tag). When the ST field of an inbound TLP is
* matched to this value, then address translation proceeds. This check is only performed if the
* "ST Match Enable" bit of the "iATU Control2 Register" is set. The setting is independent of
* the setting of the TH field. Only Valid when the CX_TPH_ENABLE configuration parameter is 1.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK (0x700U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT (8U)
/*! BAR_NUM - BAR Number. When the BAR number of an inbound MEM or IO TLP " that is matched by the
* normal internal BAR address matching mechanism " is the same as this field, address translation
* proceeds (when all other enabled field-matches are successful). This check is only performed
* if the "Match Mode" bit of the "iATU Control 2 Register" is set. - 000b - BAR0 - 001b - BAR1 -
* 010b - BAR2 - 011b - BAR3 - 100b - BAR4 - 101b - BAR5 - 110b - ROM - 111b - reserved - IO
* translation would require either 00100b or 00101b in the inbound TLP TYPE; the BAR Number set in
* the range 000b - 101b and that BAR configured as an IO BAR. Note: This register field is
* sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_BAR_NUM_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK (0x2000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT (13U)
/*! MSG_TYPE_MATCH_MODE - Message Type Match Mode. When enabled, and if single address location
* translate enable is set, then inbound TLPs of type MSG/MSGd which match the type field of the
* iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be translated. Message type match
* mode overrides any value of MATCH_MODE field in this register. Usage scenarios for this are
* translation of VDM or ATS messages when AXI bridge is configured on client interface. Note:
* This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_TYPE_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK (0x4000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT (14U)
/*! TC_MATCH_EN - TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TC_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK (0x8000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT (15U)
/*! TD_MATCH_EN - TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD
* field of the "iATU Control 1 Register") occurs for address translation to proceed. Note: This
* register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_TD_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK (0x10000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT (16U)
/*! ATTR_MATCH_EN - ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match
* (see ATTR field of the "iATU Control 1 Register") occurs for address translation to proceed.
* Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_ATTR_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK (0x80000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT (19U)
/*! FUNC_NUM_MATCH_EN - Function Number Match Enable. Ensures that a successful Function Number TLP
* field comparison match (see Function Number field of the "iATU Control 1 Register") occurs (in
* MEM-I/O and CFG0/CFG1 transactions) for address translation to proceed. Note: This register
* field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUNC_NUM_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK (0x200000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT (21U)
/*! MSG_CODE_MATCH_EN - Message Code Match Enable (Msg TLPS). Ensures that a successful message Code
* TLP field comparison match (see Message Code field of the "iATU Control 2 Register") occurs
* (in MSG transactions) for address translation to proceed. ST Match Enable (Mem TLPs). Ensures
* that a successful ST TLP field comparison match (see ST field of the "iATU Control 2 Register")
* occurs (in MEM transactions) for address translation to proceed. Only Valid when the
* CX_TPH_ENABLE configuration parameter is 1 Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MSG_CODE_MATCH_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK (0x800000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT (23U)
/*! SINGLE_ADDR_LOC_TRANS_EN - Single Address Location Translate Enable. When enabled, Rx TLPs can
* be translated to a single address location as determined by the target address register of the
* iATU region. The main usage scenario is translation of Messages (such as Vendor Defined or ATS
* Messages) to MWr TLPs when the AXI bridge is enabled. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_SINGLE_ADDR_LOC_TRANS_EN_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK (0x3000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT (24U)
/*! RESPONSE_CODE - Response Code. Defines the type of response to give for accesses matching this
* region. This overrides the normal RADM filter response. Note that this feature is not available
* for any region where Single Address Location Translate is enabled. - 00 - Normal RADM filter
* response is used. - 01 - Unsupported request (UR) - 10 - Completer abort (CA) - 11 - Not used
* / undefined / reserved. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_RESPONSE_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK (0x8000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT (27U)
/*! FUZZY_TYPE_MATCH_CODE - Fuzzy Type Match Mode. When enabled, the iATU relaxes the matching of
* the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as
* identical. Similarly with CfgWr0 and CfgWr1. - MWr, MRd and MRdLk TLPs are seen as identical -
* The Routing field of Msg/MsgD TLPs is ignored - FetchAdd, Swap and CAS are seen as identical.
* For example, CFG0 in the TYPE field in the "iATU Control 1 Register" matches against an
* inbound CfgRd0, CfgRd1, CfgWr0 or CfgWr1 TLP. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_FUZZY_TYPE_MATCH_CODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK (0x10000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT (28U)
/*! CFG_SHIFT_MODE - CFG Shift Mode. This is useful for CFG transactions where the PCIe
* configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This
* allows a CFG configuration space to be located in any 256MB window of your application memory space
* using a 28-bit effective address. Shifts bits [31:16] of the untranslated address to form
* bits [27:12] of the translated address. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_CFG_SHIFT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK (0x20000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT (29U)
/*! INVERT_MODE - Invert Mode. When set the address matching region is inverted. Therefore, an
* address match occurs when the untranslated address is in the region outside the defined range (Base
* Address to Limit Address). Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_INVERT_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK (0x40000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT (30U)
/*! MATCH_MODE - Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type
* of TLP that is received as follows: For MEM-I/O TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU operates using addresses as in the outbound direction. The
* Region Base and Limit Registers must be setup. - 1:BAR Match Mode. BAR matching is used. The
* "BAR Number" field is relevant. Not used for RC. For CFG0 TLPs, this field is interpreted as
* follows: - 0: Routing ID Match Mode. The iATU interprets the Routing ID (Bytes 8 to 11 of TLP
* header) as an address. This corresponds to the upper 16 bits of the address in MEM-I/O
* transactions. The Routing ID of the TLP must be within the base and limit of the iATU region for matching
* to proceed. - 1: Accept Mode. The iATU accepts all CFG0 transactions as address matches. The
* routing ID in the CFG0 TLP is ignored. This is useful as all received CFG0 TLPs should be
* processed regardless of the Bus number. For MSG/MSGD TLPs, this field is interpreted as follows: -
* 0: Address Match Mode. The iATU treats the third dword and fourth dword of the inbound
* MSG/MSGD TLP as an address and it is matched against the Region Base and Limit Registers. - 1:
* Vendor ID Match Mode. This mode is relevant for ID-routed Vendor Defined Messages. The iATU ignores
* the Routing ID (Bus, Device, Function) in bits [31:16] of the third dword of the TLP header,
* but matches against the Vendor ID in bits [15:0] of the third dword of the TLP header. Bits
* [15:0] of the Region Upper Base register should be programmed with the required Vendor ID. The
* lower Base and Limit Register should be programmed to translate TLPs based on vendor specific
* information in the fourth dword of the TLP header. - If SINGLE_ADDRESS_LOCATION_TRANSLATE_EN =
* 1 AND MSG_TYPE_MATCH_MODE = 1, then Match Mode is ignored. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_MATCH_MODE_MASK)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK (0x80000000U)
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT (31U)
/*! REGION_EN - Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky.
*/
#define PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_SHIFT)) & PCIE_IATU_REGION_CTRL_2_OFF_INBOUND_3_REGION_EN_MASK)
/*! @} */
/*! @name IATU_LWR_BASE_ADDR_OFF_INBOUND_3 - iATU Lower Base Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT (0U)
/*! LWR_BASE_HW - Forms bits [n-1:0] of the start address of the address region to be translated.
* The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* n is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region)
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_HW_MASK)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT (16U)
/*! LWR_BASE_RW - Forms bits [31:n] of the start address of the address region to be translated. n
* is log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_SHIFT)) & PCIE_IATU_LWR_BASE_ADDR_OFF_INBOUND_3_LWR_BASE_RW_MASK)
/*! @} */
/*! @name IATU_UPPER_BASE_ADDR_OFF_INBOUND_3 - iATU Upper Base Address Register. */
/*! @{ */
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK (0xFFFFFFFFU)
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT (0U)
/*! UPPER_BASE_RW - Forms bits [63:32] of the start (and end) address of the address region to be
* translated. Note: This register field is sticky.
*/
#define PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_SHIFT)) & PCIE_IATU_UPPER_BASE_ADDR_OFF_INBOUND_3_UPPER_BASE_RW_MASK)
/*! @} */
/*! @name IATU_LIMIT_ADDR_OFF_INBOUND_3 - iATU Limit Address Register. */
/*! @{ */
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK (0xFFFFU)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT (0U)
/*! LIMIT_ADDR_HW - Forms lower bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_HW_MASK)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT (16U)
/*! LIMIT_ADDR_RW - Forms upper bits of the end address of the address region to be translated. The
* end address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region kB
* boundary, so these bits are always 0. A write to this location is ignored by the PCIe controller.
* Note: This register field is sticky.
*/
#define PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_SHIFT)) & PCIE_IATU_LIMIT_ADDR_OFF_INBOUND_3_LIMIT_ADDR_RW_MASK)
/*! @} */
/*! @name IATU_LWR_TARGET_ADDR_OFF_INBOUND_3 - iATU Lower Target Address Register. */
/*! @{ */
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK (0xFFFFU)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT (0U)
/*! LWR_TARGET_HW - Forms the LSB's of the Lower Target part of the new address of the translated
* region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region
* kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so that
* these bits are always '0'. If the BAR is smaller than the iATU region size, then the iATU
* target address must align to the iATU region size; otherwise it must align to the BAR size. A
* write to this location is ignored by the PCIe controller. - Field size depends on
* log2(CX_ATU_MIN_REGION_SIZEMinimum Size of iATU Region) in address match mode. - Field size depends on
* log2(BAR_MASK+1) in BAR match mode.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_HW_MASK)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK (0xFFFF0000U)
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT (16U)
/*! LWR_TARGET_RW - Forms MSB's of the Lower Target part of the new address of the translated
* region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZEMinimum Size
* of iATU Region) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match
* mode. Note: This register field is sticky.
*/
#define PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_SHIFT)) & PCIE_IATU_LWR_TARGET_ADDR_OFF_INBOUND_3_LWR_TARGET_RW_MASK)
/*! @} */
/*! @name DMA_CTRL_DATA_ARB_PRIOR_OFF - DMA Arbitration Scheme for TRGT1 Interface. */
/*! @{ */
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK (0x7U)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT (0U)
/*! RTRGT1_WEIGHT - Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RTRGT1_WEIGHT_MASK)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK (0x38U)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT (3U)
/*! WR_CTRL_TRGT_WEIGHT - DMA Write Channel MRd Requests. For DMA data requests and LL
* element/descriptor access. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_WR_CTRL_TRGT_WEIGHT_MASK)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK (0x1C0U)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT (6U)
/*! RD_CTRL_TRGT_WEIGHT - DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RD_CTRL_TRGT_WEIGHT_MASK)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK (0xE00U)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT (9U)
/*! RDBUFF_TRGT_WEIGHT - DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RDBUFF_TRGT_WEIGHT_MASK)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MASK (0xFFFFF000U)
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SHIFT (12U)
/*! RSVDP_12 - Reserved for future use.
*/
#define PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_SHIFT)) & PCIE_DMA_CTRL_DATA_ARB_PRIOR_OFF_RSVDP_12_MASK)
/*! @} */
/*! @name DMA_CTRL_OFF - DMA Number of Channels Register. */
/*! @{ */
#define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK (0xFU)
#define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT (0U)
/*! NUM_DMA_WR_CHAN - Number of Write Channels. You can read this register to determine the number
* of write channels the DMA controller has been configured to support.
*/
#define PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_SHIFT)) & PCIE_DMA_CTRL_OFF_NUM_DMA_WR_CHAN_MASK)
#define PCIE_DMA_CTRL_OFF_RSVDP_4_MASK (0xFFF0U)
#define PCIE_DMA_CTRL_OFF_RSVDP_4_SHIFT (4U)
/*! RSVDP_4 - Reserved for future use.
*/
#define PCIE_DMA_CTRL_OFF_RSVDP_4(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_4_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_4_MASK)
#define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK (0xF0000U)
#define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT (16U)
/*! NUM_DMA_RD_CHAN - Number of Read Channels. You can read this register to determine the number of
* read channels the DMA controller has been configured to support.
*/
#define PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_SHIFT)) & PCIE_DMA_CTRL_OFF_NUM_DMA_RD_CHAN_MASK)
#define PCIE_DMA_CTRL_OFF_RSVDP_20_MASK (0xF00000U)
#define PCIE_DMA_CTRL_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_DMA_CTRL_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_20_MASK)
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK (0x1000000U)
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT (24U)
/*! DIS_C2W_CACHE_WR - Disable DMA Write Channels "completion to memory write" context cache
* pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are
* as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_SHIFT)) & PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_WR_MASK)
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK (0x2000000U)
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT (25U)
/*! DIS_C2W_CACHE_RD - Disable DMA Read Channels "completion to memory write" context cache
* pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are
* as follows: - Dbi: R/W
*/
#define PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_SHIFT)) & PCIE_DMA_CTRL_OFF_DIS_C2W_CACHE_RD_MASK)
#define PCIE_DMA_CTRL_OFF_RSVDP_26_MASK (0xFC000000U)
#define PCIE_DMA_CTRL_OFF_RSVDP_26_SHIFT (26U)
/*! RSVDP_26 - Reserved for future use.
*/
#define PCIE_DMA_CTRL_OFF_RSVDP_26(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CTRL_OFF_RSVDP_26_SHIFT)) & PCIE_DMA_CTRL_OFF_RSVDP_26_MASK)
/*! @} */
/*! @name DMA_WRITE_ENGINE_EN_OFF - DMA Write Engine Enable Register. */
/*! @{ */
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK (0x1U)
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT (0U)
/*! DMA_WRITE_ENGINE - DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal
* operation, you must initially set this bit to "1", before any other software setup actions. You
* do not need to toggle or rewrite to this bit during normal operation. You should set this bit
* to "0" when you want to "Soft Reset" the DMA controller write logic. There are three possible
* reasons for resetting the DMA controller write logic: - The "Abort Interrupt Status" bit is set
* (in the "DMA Write Interrupt Status Register" DMA_WRITE_INT_STATUS_OFF), and any of the bits
* is in the "DMA Write Error Status Register" (DMA_WRITE_ERR_STATUS_OFF) are set. Resetting the
* DMA controller write logic re-initializes the control logic, ensuring that the next DMA write
* transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit" ,
* after which, the "Abort Interrupt Status" bit is set and the Channel Status field (CS) of the
* DMA write "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped."
* Resetting the DMA controller write logic re-initializes the control logic ensuring that the
* next DMA write transfer is executed successfully. - During software development, when you
* incorrectly program the DMA write engine. To "Soft Reset" the DMA controller write logic, you must:
* - De-assert the DMA write engine enable bit. - Wait for the DMA to complete any in-progress
* TLP transfer, by waiting until a read on the DMA write engine enable bit returns a "0". - Assert
* the DMA write engine enable bit. This "Soft Reset" does not clear the DMA configuration
* registers. The DMA write transfer does not start until you write to the "DMA Write Doorbell
* Register" (DMA_WRITE_DOORBELL_OFF). Note: The access attributes of this field are as follows: - Dbi:
* R/W
*/
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_DMA_WRITE_ENGINE_MASK)
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MASK (0xFFFEU)
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_1_MASK)
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_ENGINE_EN_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_WRITE_DOORBELL_OFF - DMA Write Doorbell Register. */
/*! @{ */
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK (0x7U)
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT (0U)
/*! WR_DOORBELL_NUM - Doorbell Number. You must write the channel number to this register to start
* the DMA write transfer for that channel. The DMA detects a write to this register field even if
* the value of this field does not change. You do not need to toggle or write any other value
* to this register to start a new transfer. The range of this field is 0x0 to 0x7, and 0x0
* corresponds to channel 0. Also note that a write to this field triggers the controller to exit L1
* substates. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_WR_DOORBELL_NUM_MASK)
#define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MASK (0x7FFFFFF8U)
#define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SHIFT (3U)
/*! RSVDP_3 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_RSVDP_3_MASK)
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK (0x80000000U)
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT (31U)
/*! WR_STOP - Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops
* issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it
* is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the
* "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) to ensure that the write channel
* is "Running" (transferring data). For more information, see "Stopping the DMA Transfer
* (Software Stop)." Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_SHIFT)) & PCIE_DMA_WRITE_DOORBELL_OFF_WR_STOP_MASK)
/*! @} */
/*! @name DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Write Engine Channel Arbitration Weight Low Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK (0x1FU)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT (0U)
/*! WRITE_CHANNEL0_WEIGHT - Channel 0 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL0_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK (0x3E0U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT (5U)
/*! WRITE_CHANNEL1_WEIGHT - Channel 1 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL1_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK (0x7C00U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT (10U)
/*! WRITE_CHANNEL2_WEIGHT - Channel 2 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL2_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK (0xF8000U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT (15U)
/*! WRITE_CHANNEL3_WEIGHT - Channel 3 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_WRITE_CHANNEL3_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF - DMA Write Engine Channel Arbitration Weight High Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MASK (0x1FU)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SHIFT (0U)
/*! WRITE_CHANNEL4_WEIGHT - Channel 4 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL4_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MASK (0x3E0U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SHIFT (5U)
/*! WRITE_CHANNEL5_WEIGHT - Channel 5 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL5_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MASK (0x7C00U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SHIFT (10U)
/*! WRITE_CHANNEL6_WEIGHT - Channel 6 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL6_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MASK (0xF8000U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SHIFT (15U)
/*! WRITE_CHANNEL7_WEIGHT - Channel 7 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. A value of '0' means that one TLP is issued before moving to the next
* channel. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_WRITE_CHANNEL7_WEIGHT_MASK)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name DMA_READ_ENGINE_EN_OFF - DMA Read Engine Enable Register. */
/*! @{ */
#define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK (0x1U)
#define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT (0U)
/*! DMA_READ_ENGINE - DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal
* operation, you must initially set this bit to "1", before any other software setup actions. You do
* not need to toggle or rewrite to this bit during normal operation. You should set this field
* to "0" when you want to "Soft Reset" the DMA controller read logic. There are three possible
* reasons for resetting the DMA controller read logic: - The "Abort Interrupt Status" bit is set
* (in the "DMA Read Interrupt Status Register" (DMA_READ_INT_STATUS_OFF), and any of the bits in
* the "DMA Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) is set. Resetting the
* DMA controller read logic re-initializes the control logic, ensuring that the next DMA read
* transfer is executed successfully. - You have executed the procedure outlined in "Stop Bit",
* after which, the "Abort Interrupt Status" bit is set and the channel Status field (CS) of the DMA
* read "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_WRCH_0) is set to "Stopped".
* Resetting the DMA controller read logic re-initializes the control logic ensuring that the next DMA
* read transfer is executed successfully. - During software development, when you incorrectly
* program the DMA read engine. To "Soft Reset" the DMA controller read logic, you must: -
* De-assert the DMA read engine enable bit. - Wait for the DMA to complete any in-progress TLP
* transfer, by waiting until a read on the DMA read engine enable bit returns a "0". - Assert the DMA
* read engine enable bit. This "Soft Reset" does not clear the DMA configuration registers. The
* DMA read transfer does not start until you write to the "DMA Read Doorbell Register"
* (DMA_READ_DOORBELL_OFF). Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_DMA_READ_ENGINE_MASK)
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MASK (0xFFFEU)
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SHIFT (1U)
/*! RSVDP_1 - Reserved for future use.
*/
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_1_MASK)
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_ENGINE_EN_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_DOORBELL_OFF - DMA Read Doorbell Register. */
/*! @{ */
#define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK (0x7U)
#define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT (0U)
/*! RD_DOORBELL_NUM - Doorbell Number. You must write 0x0 to this register to start the DMA read
* transfer for that channel. The DMA detects a write to this register field even if the value of
* this field does not change. The range of this field is 0x0 to 0x7, and 0x0 corresponds to
* channel 0. Also note that a write to this field triggers the controller to exit L1 substates. Note:
* The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RD_DOORBELL_NUM_MASK)
#define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_MASK (0x7FFFFFF8U)
#define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_SHIFT (3U)
/*! RSVDP_3 - Reserved for future use.
*/
#define PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RSVDP_3_MASK)
#define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_MASK (0x80000000U)
#define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT (31U)
/*! RD_STOP - Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops
* issuing requests, sets the channel status to "Stopped", and asserts the "Abort" interrupt if it
* is enabled. Before setting the Stop bit, you must read the channel Status field (CS) of the
* "DMA Channel Control 1 Register " (DMA_CH_CONTROL1_OFF_RDCH_0) to ensure that the read channel
* is "Running" (transferring data). For more information, see "Stopping the DMA Transfer
* (Software Stop)". Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_DOORBELL_OFF_RD_STOP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_SHIFT)) & PCIE_DMA_READ_DOORBELL_OFF_RD_STOP_MASK)
/*! @} */
/*! @name DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF - DMA Read Engine Channel Arbitration Weight Low Register. */
/*! @{ */
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK (0x1FU)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT (0U)
/*! READ_CHANNEL0_WEIGHT - Channel 0 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL0_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK (0x3E0U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT (5U)
/*! READ_CHANNEL1_WEIGHT - Channel 1 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL1_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK (0x7C00U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT (10U)
/*! READ_CHANNEL2_WEIGHT - Channel 2 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL2_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK (0xF8000U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT (15U)
/*! READ_CHANNEL3_WEIGHT - Channel 3 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_READ_CHANNEL3_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF - DMA Read Engine Channel Arbitration Weight High Register. */
/*! @{ */
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MASK (0x1FU)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SHIFT (0U)
/*! READ_CHANNEL4_WEIGHT - Channel 4 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL4_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MASK (0x3E0U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SHIFT (5U)
/*! READ_CHANNEL5_WEIGHT - Channel 5 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL5_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MASK (0x7C00U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SHIFT (10U)
/*! READ_CHANNEL6_WEIGHT - Channel 6 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL6_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MASK (0xF8000U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SHIFT (15U)
/*! READ_CHANNEL7_WEIGHT - Channel 7 Weight. The weight is initialized by software before ringing
* the doorbell. The value is used by the channel weighted round robin arbiter to select the next
* channel read request. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_READ_CHANNEL7_WEIGHT_MASK)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK (0xFFF00000U)
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT (20U)
/*! RSVDP_20 - Reserved for future use.
*/
#define PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_SHIFT)) & PCIE_DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF_RSVDP_20_MASK)
/*! @} */
/*! @name DMA_WRITE_INT_STATUS_OFF - DMA Write Interrupt Status Register. */
/*! @{ */
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK (0xFFU)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT (0U)
/*! WR_DONE_INT_STATUS - Done Interrupt Status. The DMA write channel has successfully completed the
* DMA transfer. For more details, see "Interrupts and Error Handling". Each bit corresponds to
* a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and
* Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this
* register. - Clearing: You must write a 1'b1 to the corresponding channel bit in the DMA write
* interrupt Clear register to clear this interrupt bit. Note: You can write to this register to
* emulate interrupt generation, during software or hardware testing. A write to the address triggers
* an interrupt, but the DMA does not set the Done or Abort bits in this register. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_WR_DONE_INT_STATUS_MASK)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_8_MASK)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK (0xFF0000U)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT (16U)
/*! WR_ABORT_INT_STATUS - Abort Interrupt Status. The DMA write channel has detected an error, or
* you manually stopped the transfer as described in "Error Handling Assistance by Remote
* Software". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For
* details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt Mask register
* has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel
* bit in the DMA write interrupt Clear register to clear this interrupt bit. Note: You can write
* to this register to emulate interrupt generation, during software or hardware testing. A write
* to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in this
* register. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_WR_ABORT_INT_STATUS_MASK)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_STATUS_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_WRITE_INT_MASK_OFF - DMA Write Interrupt Mask Register. */
/*! @{ */
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK (0x1U)
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT (0U)
/*! WR_DONE_INT_MASK - Done Interrupt Mask. Prevents the Done interrupt status field in the DMA
* write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA
* channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_WR_DONE_INT_MASK_MASK)
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_8_MASK)
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK (0x10000U)
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT (16U)
/*! WR_ABORT_INT_MASK - Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA
* write interrupt status register from asserting the edma_int output. Each bit corresponds to a
* DMA channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_WR_ABORT_INT_MASK_MASK)
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_MASK_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_WRITE_INT_CLEAR_OFF - DMA Write Interrupt Clear Register. */
/*! @{ */
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK (0x1U)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT (0U)
/*! WR_DONE_INT_CLEAR - Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
* in the Done interrupt status field of the DMA write interrupt status register. Each bit
* corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this self-clearing
* register field always returns a "0".
*/
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_DONE_INT_CLEAR_MASK)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_8_MASK)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK (0x10000U)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT (16U)
/*! WR_ABORT_INT_CLEAR - Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
* in the Abort interrupt status field of the DMA write interrupt status register. Each bit
* corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this
* self-clearing register field always returns a "0".
*/
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_WR_ABORT_INT_CLEAR_MASK)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_INT_CLEAR_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_WRITE_ERR_STATUS_OFF - DMA Write Error Status Register */
/*! @{ */
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK (0xFFU)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT (0U)
/*! APP_READ_ERR_DETECT - Application Read Error Detected. The DMA write channel has received an
* error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while
* reading data from it. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
* Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA write interrupt
* Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
* corresponding channel bit in the Abort interrupt field of the "DMA Write Interrupt Clear Register"
* (DMA_WRITE_INT_CLEAR_OFF) to clear this error bit.
*/
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_APP_READ_ERR_DETECT_MASK)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_8_MASK)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U)
/*! LINKLIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. The DMA write
* channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is
* not used) while reading a linked list element from local memory. Each bit corresponds to a
* DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details, see "Interrupts and
* Error Handling". - Masking: The DMA write interrupt Mask register has no effect on this register.
* - Clearing: You must write a 1'b1 to the corresponding channel bit in the Abort interrupt
* field of the "DMA Write Interrupt Clear Register" (DMA_WRITE_INT_CLEAR_OFF) to clear this error
* bit.
*/
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_LINKLIST_ELEMENT_FETCH_ERR_DETECT_MASK)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_ERR_STATUS_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_WRITE_DONE_IMWR_LOW_OFF - DMA Write Done IMWr Address Low Register. */
/*! @{ */
#define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT (0U)
/*! DMA_WRITE_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
* for the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_SHIFT)) & PCIE_DMA_WRITE_DONE_IMWR_LOW_OFF_DMA_WRITE_DONE_LOW_REG_MASK)
/*! @} */
/*! @name DMA_WRITE_DONE_IMWR_HIGH_OFF - DMA Write Done IMWr Interrupt Address High Register. */
/*! @{ */
#define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT (0U)
/*! DMA_WRITE_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
* for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_WRITE_DONE_IMWR_HIGH_OFF_DMA_WRITE_DONE_HIGH_REG_MASK)
/*! @} */
/*! @name DMA_WRITE_ABORT_IMWR_LOW_OFF - DMA Write Abort IMWr Address Low Register. */
/*! @{ */
#define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT (0U)
/*! DMA_WRITE_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
* for the Abort IMWr TLP it generates. Bits [1:0] must be "00" as this address must be dword
* aligned. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_WRITE_ABORT_IMWR_LOW_OFF_DMA_WRITE_ABORT_LOW_REG_MASK)
/*! @} */
/*! @name DMA_WRITE_ABORT_IMWR_HIGH_OFF - DMA Write Abort IMWr Address High Register. */
/*! @{ */
#define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT (0U)
/*! DMA_WRITE_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
* for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_WRITE_ABORT_IMWR_HIGH_OFF_DMA_WRITE_ABORT_HIGH_REG_MASK)
/*! @} */
/*! @name DMA_WRITE_CH01_IMWR_DATA_OFF - DMA Write Channel 1 and 0 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK (0xFFFFU)
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT (0U)
/*! WR_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_0_DATA_MASK)
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT (16U)
/*! WR_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_WRITE_CH01_IMWR_DATA_OFF_WR_CHANNEL_1_DATA_MASK)
/*! @} */
/*! @name DMA_WRITE_CH23_IMWR_DATA_OFF - DMA Write Channel 3 and 2 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK (0xFFFFU)
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT (0U)
/*! WR_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_2_DATA_MASK)
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT (16U)
/*! WR_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_WRITE_CH23_IMWR_DATA_OFF_WR_CHANNEL_3_DATA_MASK)
/*! @} */
/*! @name DMA_WRITE_CH45_IMWR_DATA_OFF - DMA Write Channel 5 and 4 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MASK (0xFFFFU)
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SHIFT (0U)
/*! WR_CHANNEL_4_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_SHIFT)) & PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_4_DATA_MASK)
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SHIFT (16U)
/*! WR_CHANNEL_5_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_SHIFT)) & PCIE_DMA_WRITE_CH45_IMWR_DATA_OFF_WR_CHANNEL_5_DATA_MASK)
/*! @} */
/*! @name DMA_WRITE_CH67_IMWR_DATA_OFF - DMA Write Channel 7 and 6 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MASK (0xFFFFU)
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SHIFT (0U)
/*! WR_CHANNEL_6_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_SHIFT)) & PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_6_DATA_MASK)
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SHIFT (16U)
/*! WR_CHANNEL_7_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_SHIFT)) & PCIE_DMA_WRITE_CH67_IMWR_DATA_OFF_WR_CHANNEL_7_DATA_MASK)
/*! @} */
/*! @name DMA_WRITE_LINKED_LIST_ERR_EN_OFF - DMA Write Linked List Error Enable Register. */
/*! @{ */
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK (0x1U)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT (0U)
/*! WR_CHANNEL_LLRAIE - Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the
* write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element
* enable the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0]
* corresponds to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling".
* Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLRAIE_MASK)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK (0x10000U)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT (16U)
/*! WR_CHANNEL_LLLAIE - Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write
* channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable
* the write channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds
* to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling".
* Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_WR_CHANNEL_LLLAIE_MASK)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_WRITE_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_INT_STATUS_OFF - DMA Read Interrupt Status Register. */
/*! @{ */
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK (0xFFU)
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT (0U)
/*! RD_DONE_INT_STATUS - Done Interrupt Status. The DMA read channel has successfully completed the
* DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
* Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt
* Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
* corresponding channel bit in the DMA read interrupt Clear register to clear this interrupt bit. Note:
* You can write to this register to emulate interrupt generation, during software or hardware
* testing. A write to the address triggers an interrupt, but the DMA does not set the Done or
* Abort bits in this register. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RD_DONE_INT_STATUS_MASK)
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_8_MASK)
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK (0xFF0000U)
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT (16U)
/*! RD_ABORT_INT_STATUS - Abort Interrupt Status. The DMA read channel has detected an error, or you
* manually stopped the transfer as described in "Stopping the DMA Transfer (Software Stop)".
* Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. You can read the "DMA
* Read Error Status Low Register" (DMA_READ_ERR_STATUS_LOW_OFF) and "DMA Read Error Status High
* Register" (DMA_READ_ERR_STATUS_HIGH_OFF) to determine the source of the error. - Enabling: For
* details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask register
* has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding channel
* bit in the DMA read interrupt Clear register to clear this interrupt bit. Note: You can write
* to this register to emulate interrupt generation, during software or hardware testing. A
* write to the address triggers an interrupt, but the DMA does not set the Done or Abort bits in
* this register. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RD_ABORT_INT_STATUS_MASK)
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_STATUS_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_INT_MASK_OFF - DMA Read Interrupt Mask Register. */
/*! @{ */
#define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK (0x1U)
#define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT (0U)
/*! RD_DONE_INT_MASK - Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read
* interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA
* channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RD_DONE_INT_MASK_MASK)
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RSVDP_8_MASK)
#define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK (0x10000U)
#define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT (16U)
/*! RD_ABORT_INT_MASK - Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA
* read interrupt status register from asserting the edma_int output. Each bit corresponds to a
* DMA channel. Bit [0] corresponds to channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RD_ABORT_INT_MASK_MASK)
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_MASK_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_INT_CLEAR_OFF - DMA Read Interrupt Clear Register. */
/*! @{ */
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK (0xFFU)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT (0U)
/*! RD_DONE_INT_CLEAR - Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
* in the Done interrupt status field of the DMA read interrupt status register. Each bit
* corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this self-clearing
* register field always returns a "0".
*/
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RD_DONE_INT_CLEAR_MASK)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_8_MASK)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK (0xFF0000U)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT (16U)
/*! RD_ABORT_INT_CLEAR - Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit
* in the Abort interrupt status field of the DMA read interrupt status register. Each bit
* corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: Reading from this
* self-clearing register field always returns a "0".
*/
#define PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RD_ABORT_INT_CLEAR_MASK)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_INT_CLEAR_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_ERR_STATUS_LOW_OFF - DMA Read Error Status Low Register. */
/*! @{ */
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK (0xFFU)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT (0U)
/*! APP_WR_ERR_DETECT - Application Write Error Detected. The DMA read channel has received an error
* response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing
* data to it. This error is fatal. You must restart the transfer from the beginning, as the
* channel context is corrupted, and the transfer is not rolled back. For more details, see "Linked
* List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
* Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
* register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
* channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
* (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and also
* the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).
*/
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_APP_WR_ERR_DETECT_MASK)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_8_MASK)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK (0xFF0000U)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT (16U)
/*! LINK_LIST_ELEMENT_FETCH_ERR_DETECT - Linked List Element Fetch Error Detected. - The DMA read
* channel has received an error response from the AXI bus while reading a linked list element from
* local memory. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
* Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
* register has no effect on this register. - Clearing: You must write a 1'b1 to the
* corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
* (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this clears all bits in this register, and
* also the DMA Read Error Status High register (DMA_READ_ERR_STATUS_HIGH_OFF).
*/
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_LINK_LIST_ELEMENT_FETCH_ERR_DETECT_MASK)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_LOW_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_ERR_STATUS_HIGH_OFF - DMA Read Error Status High Register. */
/*! @{ */
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK (0xFFU)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT (0U)
/*! UNSUPPORTED_REQ - Unsupported Request. The DMA read channel has received a PCIe unsupported
* request completion status from the remote device in response to the MRd request. For more details,
* see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel
* 0. - Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read
* interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to the
* corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
* Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error
* bits for the same channel in this register and in the DMA Read Error Status Low register.
*/
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_UNSUPPORTED_REQ_MASK)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK (0xFF00U)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT (8U)
/*! CPL_ABORT - Completer Abort. The DMA read channel has received a PCIe completer abort completion
* status from the remote device in response to the MRd request. For more details, see "Linked
* List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. -
* Enabling: For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
* register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
* channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
* (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the
* same channel in this register and in the DMA Read Error Status Low register.
*/
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_ABORT_MASK)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK (0xFF0000U)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT (16U)
/*! CPL_TIMEOUT - Completion Time Out. The DMA read channel has timed-out while waiting for the
* remote device to respond to the MRd request, or a malformed CplD has been received. For more
* details, see "Linked List Mode". Each bit corresponds to a DMA channel. Bit [0] corresponds to
* channel 0. - Enabling: For details, see "Interrupts and Error Handling" . - Masking: The DMA read
* interrupt Mask register has no effect on this register. - Clearing: You must write a 1'b1 to
* the corresponding channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear
* Register" (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other
* error bits for the same channel in this register and in the DMA Read Error Status Low register.
*/
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_CPL_TIMEOUT_MASK)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK (0xFF000000U)
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT (24U)
/*! DATA_POISIONING - Data Poisoning. The DMA read channel has detected data poisoning in the
* completion from the remote device (in response to the MRd request). The DMA read channel will drop
* the completion and then be halted. The CX_FLT_MASK_UR_POIS filter rule does not affect this
* behavior. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling:
* For details, see "Interrupts and Error Handling". - Masking: The DMA read interrupt Mask
* register has no effect on this register. - Clearing: You must write a 1'b1 to the corresponding
* channel bit in the Abort interrupt field of the "DMA Read Interrupt Clear Register"
* (DMA_READ_INT_CLEAR_OFF) to clear this error bit. Note, this also clears the other error bits for the same
* channel in this register and in the DMA Read Error Status Low register.
*/
#define PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_SHIFT)) & PCIE_DMA_READ_ERR_STATUS_HIGH_OFF_DATA_POISIONING_MASK)
/*! @} */
/*! @name DMA_READ_LINKED_LIST_ERR_EN_OFF - DMA Read Linked List Error Enable Register. */
/*! @{ */
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK (0x1U)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT (0U)
/*! RD_CHANNEL_LLRAIE - Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read
* channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable
* the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds
* to channel 0. Used in linked list mode only. For more details, see "Interrupt Handling". Note:
* The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLRAIE_MASK)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK (0xFF00U)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT (8U)
/*! RSVDP_8 - Reserved for future use.
*/
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_8_MASK)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK (0x10000U)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT (16U)
/*! RD_CHANNEL_LLLAIE - Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read
* channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable
* the read channel done interrupts. Each bit corresponds to a DMA channel. Bit [0] corresponds to
* channel 0. Used in linked list mode only. For more details, see "Interrupt Handling". Note:
* The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RD_CHANNEL_LLLAIE_MASK)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK (0xFF000000U)
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT (24U)
/*! RSVDP_24 - Reserved for future use.
*/
#define PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_SHIFT)) & PCIE_DMA_READ_LINKED_LIST_ERR_EN_OFF_RSVDP_24_MASK)
/*! @} */
/*! @name DMA_READ_DONE_IMWR_LOW_OFF - DMA Read Done IMWr Address Low Register. */
/*! @{ */
#define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT (0U)
/*! DMA_READ_DONE_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field for
* the Done IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_SHIFT)) & PCIE_DMA_READ_DONE_IMWR_LOW_OFF_DMA_READ_DONE_LOW_REG_MASK)
/*! @} */
/*! @name DMA_READ_DONE_IMWR_HIGH_OFF - DMA Read Done IMWr Address High Register. */
/*! @{ */
#define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT (0U)
/*! DMA_READ_DONE_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
* for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_SHIFT)) & PCIE_DMA_READ_DONE_IMWR_HIGH_OFF_DMA_READ_DONE_HIGH_REG_MASK)
/*! @} */
/*! @name DMA_READ_ABORT_IMWR_LOW_OFF - DMA Read Abort IMWr Address Low Register. */
/*! @{ */
#define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT (0U)
/*! DMA_READ_ABORT_LOW_REG - The DMA uses this field to generate bits [31:0] of the address field
* for the Abort IMWr TLP. Bits [1:0] must be "00" as this address must be dword aligned. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_SHIFT)) & PCIE_DMA_READ_ABORT_IMWR_LOW_OFF_DMA_READ_ABORT_LOW_REG_MASK)
/*! @} */
/*! @name DMA_READ_ABORT_IMWR_HIGH_OFF - DMA Read Abort IMWr Address High Register. */
/*! @{ */
#define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK (0xFFFFFFFFU)
#define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT (0U)
/*! DMA_READ_ABORT_HIGH_REG - The DMA uses this field to generate bits [63:32] of the address field
* for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_SHIFT)) & PCIE_DMA_READ_ABORT_IMWR_HIGH_OFF_DMA_READ_ABORT_HIGH_REG_MASK)
/*! @} */
/*! @name DMA_READ_CH01_IMWR_DATA_OFF - DMA Read Channel 1 and 0 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK (0xFFFFU)
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT (0U)
/*! RD_CHANNEL_0_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_SHIFT)) & PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_0_DATA_MASK)
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT (16U)
/*! RD_CHANNEL_1_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_SHIFT)) & PCIE_DMA_READ_CH01_IMWR_DATA_OFF_RD_CHANNEL_1_DATA_MASK)
/*! @} */
/*! @name DMA_READ_CH23_IMWR_DATA_OFF - DMA Read Channel 3 and 2 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK (0xFFFFU)
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT (0U)
/*! RD_CHANNEL_2_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_SHIFT)) & PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_2_DATA_MASK)
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT (16U)
/*! RD_CHANNEL_3_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_SHIFT)) & PCIE_DMA_READ_CH23_IMWR_DATA_OFF_RD_CHANNEL_3_DATA_MASK)
/*! @} */
/*! @name DMA_READ_CH45_IMWR_DATA_OFF - DMA Read Channel 5 and 4 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MASK (0xFFFFU)
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SHIFT (0U)
/*! RD_CHANNEL_4_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_SHIFT)) & PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_4_DATA_MASK)
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SHIFT (16U)
/*! RD_CHANNEL_5_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_SHIFT)) & PCIE_DMA_READ_CH45_IMWR_DATA_OFF_RD_CHANNEL_5_DATA_MASK)
/*! @} */
/*! @name DMA_READ_CH67_IMWR_DATA_OFF - DMA Read Channel 7 and 6 IMWr Data Register. */
/*! @{ */
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MASK (0xFFFFU)
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SHIFT (0U)
/*! RD_CHANNEL_6_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_SHIFT)) & PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_6_DATA_MASK)
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MASK (0xFFFF0000U)
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SHIFT (16U)
/*! RD_CHANNEL_7_DATA - The DMA uses this field to generate the data field for the Done or Abort
* IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_SHIFT)) & PCIE_DMA_READ_CH67_IMWR_DATA_OFF_RD_CHANNEL_7_DATA_MASK)
/*! @} */
/*! @name DMA_CH_CONTROL1_OFF_WRCH_0 - DMA Write Channel Control 1 Register. */
/*! @{ */
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK (0x1U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT (0U)
/*! CB - Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer
* (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
* Synchronization". The DMA loads this field with the CB of the linked list element. Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CB_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK (0x2U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT (1U)
/*! TCB - Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used
* in linked list mode only. It is used to synchronize the producer (software) and the consumer
* (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads
* this field with the TCB of the linked list element. this field is not defined in a data LL
* element. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_TCB_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK (0x4U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT (2U)
/*! LLP - Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list
* element is a link element, and its LL element pointer dwords are pointing to the next
* (non-contiguous) element. The DMA loads this field with the LLP of the linked list element. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLP_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK (0x8U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT (3U)
/*! LIE - Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done
* or Abort Local interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
* the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only
* enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts. This
* field is not defined in a link LL element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LIE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK (0x10U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT (4U)
/*! RIE - Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done
* or Abort Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
* the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only
* enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.
* This field is not defined in a link LL element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_RIE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK (0x60U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT (5U)
/*! CS - Channel Status (CS). The channel status bits identify the current operational state of the
* DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved
* - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition
* has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has
* transferred all data for this channel, or you have prematurely stopped this channel by writing to the
* Stop field of the "DMA Write Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell
* Register" (DMA_READ_DOORBELL_OFF).
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CS_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK (0x80U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT (7U)
/*! DMA_RESERVED0 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED0_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK (0x100U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT (8U)
/*! CCS - Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the
* producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB
* Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked
* list operation. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_CCS_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK (0x200U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT (9U)
/*! LLE - Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list
* operation Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_LLE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK (0xC00U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT (10U)
/*! DMA_RESERVED1 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED1_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK (0x1F000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT (12U)
/*! DMA_FUNC_NUM - Function Number (FN). The controller uses this field when generating the
* requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you
* have set the VFE field in the "DMA Write Channel Control 2 Register"
* (DMA_CH_CONTROL2_OFF_WRCH_0). Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_FUNC_NUM_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MASK (0x7E0000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SHIFT (17U)
/*! DMA_RESERVED2 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED2_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK (0x800000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT (23U)
/*! DMA_NS_DST - Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header
* field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of
* this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_DST_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK (0x1000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT (24U)
/*! DMA_NS_SRC - Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field
* when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this
* field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_NS_SRC_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK (0x2000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT (25U)
/*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating
* MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RO_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK (0x4000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT (26U)
/*! DMA_RESERVED5 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_RESERVED5_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK (0x38000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT (27U)
/*! DMA_TC - Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating
* MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_TC_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK (0xC0000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT (30U)
/*! DMA_AT - Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when
* generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi:
* R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_WRCH_0_DMA_AT_MASK)
/*! @} */
/*! @name DMA_TRANSFER_SIZE_OFF_WRCH_0 - DMA Write Transfer Size Register. */
/*! @{ */
#define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU)
#define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT (0U)
/*! DMA_TRANSFER_SIZE - DMA Transfer Size. You program this register with the size of the DMA
* transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1).
* This field is automatically decremented by the DMA as the DMA write channel transfer progresses.
* This field indicates the number bytes remaining to be transferred. When all bytes are
* successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this
* register with the corresponding dword of the LL element. You can read this register to monitor the
* transfer progress, however in some scenarios this register is updated after a delay. For
* example, when less than 3 channels are doorbelled, this register is updated only after a descriptor
* finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_TRANSFER_SIZE_OFF_WRCH_0_DMA_TRANSFER_SIZE_MASK)
/*! @} */
/*! @name DMA_SAR_LOW_OFF_WRCH_0 - DMA Write SAR Low Register. */
/*! @{ */
#define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT (0U)
/*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). Indicates the next address to be
* read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of
* the remote memory. - DMA Write: The SAR is the address of the local memory. Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_SAR_LOW_OFF_WRCH_0_SRC_ADDR_REG_LOW_MASK)
/*! @} */
/*! @name DMA_SAR_HIGH_OFF_WRCH_0 - DMA Write SAR High Register. */
/*! @{ */
#define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U)
/*! SRC_ADDR_REG_HIGH - Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites
* this with the corresponding dword of the LL element. Note: The access attributes of this field
* are as follows: - Dbi: R/W
*/
#define PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_SAR_HIGH_OFF_WRCH_0_SRC_ADDR_REG_HIGH_MASK)
/*! @} */
/*! @name DMA_DAR_LOW_OFF_WRCH_0 - DMA Write DAR Low Register. */
/*! @{ */
#define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT (0U)
/*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). Indicates the next address to
* be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the
* address of the local memory. - DMA Write: The DAR is the address of the remote memory. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_DAR_LOW_OFF_WRCH_0_DST_ADDR_REG_LOW_MASK)
/*! @} */
/*! @name DMA_DAR_HIGH_OFF_WRCH_0 - DMA Write DAR High Register. */
/*! @{ */
#define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT (0U)
/*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. Note: The access attributes of this
* field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_DAR_HIGH_OFF_WRCH_0_DST_ADDR_REG_HIGH_MASK)
/*! @} */
/*! @name DMA_LLP_LOW_OFF_WRCH_0 - DMA Write Linked List Pointer Low Register. */
/*! @{ */
#define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT (0U)
/*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. Used in
* linked list mode only. Updated by the DMA to point to the next element in the transfer list
* after the previous element is consumed. - When the current element is a data element; this field
* is incremented by 6. - When the current element is a link element; this field is overwritten by
* the LL Element Pointer of the element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_LLP_LOW_OFF_WRCH_0_LLP_LOW_MASK)
/*! @} */
/*! @name DMA_LLP_HIGH_OFF_WRCH_0 - DMA Write Linked List Pointer High Register. */
/*! @{ */
#define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT (0U)
/*! LLP_HIGH - Upper 32 bits of the address of the linked list transfer list in local memory. Used
* in linked list mode only. Updated by the DMA to point to the next element in the transfer list
* as elements are consumed. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_LLP_HIGH_OFF_WRCH_0_LLP_HIGH_MASK)
/*! @} */
/*! @name DMA_CH_CONTROL1_OFF_RDCH_0 - DMA Read Channel Control 1 Register. */
/*! @{ */
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK (0x1U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT (0U)
/*! CB - Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer
* (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer
* Synchronization". The DMA loads this field with the CB of the linked list element. Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CB_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK (0x2U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT (1U)
/*! TCB - Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used
* in linked list mode only. It is used to synchronize the producer (software) and the consumer
* (DMA). For more details, see "PCS-CCS-CB-TCB Producer-Consumer Synchronization". The DMA loads
* this field with the TCB of the linked list element. this field is not defined in a data LL
* element. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_TCB_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK (0x4U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT (2U)
/*! LLP - Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list
* element is a link element, and its LL element pointer dwords are pointing to the next
* (non-contiguous) element. The DMA loads this field with the LLP of the linked list element. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLP_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK (0x8U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT (3U)
/*! LIE - Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done
* or Abort Local interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
* the DMA overwrites this with the LIE of the LL element. The LIE bit in a LL element only
* enables the Done interrupt. In non-LL mode, the LIE bit enables the Done and Abort interrupts. This
* field is not defined in a link LL element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LIE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK (0x10U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT (4U)
/*! RIE - Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done
* or Abort Remote interrupts. For more details, see "Interrupts and Error Handling". In LL mode,
* the DMA overwrites this with the RIE of the LL element. The RIE bit in a LL element only
* enables the Done interrupt. In non-LL mode, the RIE bit enables the Done and Abort interrupts.
* This field is not defined in a link LL element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_RIE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK (0x60U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT (5U)
/*! CS - Channel Status (CS). The channel status bits identify the current operational state of the
* DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved
* - 01: Running. This channel is active and transferring data. - 10: Halted. An error condition
* has been detected, and the DMA has stopped this channel. - 11: Stopped. The DMA has
* transferred all data for this channel, or you have prematurely stopped this channel by writing to the
* Stop field of the "DMA Read Doorbell Register" (DMA_WRITE_DOORBELL_OFF) or "DMA Read Doorbell
* Register" (DMA_READ_DOORBELL_OFF).
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CS_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK (0x80U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT (7U)
/*! DMA_RESERVED0 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED0_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK (0x100U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT (8U)
/*! CCS - Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the
* producer (software) and the consumer (DMA). For more details, see "PCS-CCS-CB-TCB
* Producer-Consumer Synchronization". You must initialize this bit. The DMA updates this bit during linked
* list operation. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_CCS_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK (0x200U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT (9U)
/*! LLE - Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list
* operation Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_LLE_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK (0xC00U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT (10U)
/*! DMA_RESERVED1 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED1_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK (0x1F000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT (12U)
/*! DMA_FUNC_NUM - Function Number (FN). The controller uses this field when generating the
* requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV, then this field is ignored if you
* have set the VFE field in the "DMA Read Channel Control 2 Register"
* (DMA_CH_CONTROL2_OFF_RDCH_0). Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_FUNC_NUM_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MASK (0x7E0000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SHIFT (17U)
/*! DMA_RESERVED2 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED2_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK (0x800000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT (23U)
/*! DMA_NS_DST - Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header
* field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of
* this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_DST_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK (0x1000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT (24U)
/*! DMA_NS_SRC - Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field
* when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this
* field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_NS_SRC_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK (0x2000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT (25U)
/*! DMA_RO - Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating
* MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RO_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK (0x4000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT (26U)
/*! DMA_RESERVED5 - Reserved. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_RESERVED5_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK (0x38000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT (27U)
/*! DMA_TC - Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating
* MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_TC_MASK)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK (0xC0000000U)
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT (30U)
/*! DMA_AT - Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when
* generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Dbi:
* R/W
*/
#define PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_SHIFT)) & PCIE_DMA_CH_CONTROL1_OFF_RDCH_0_DMA_AT_MASK)
/*! @} */
/*! @name DMA_TRANSFER_SIZE_OFF_RDCH_0 - DMA Read Transfer Size Register. */
/*! @{ */
#define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK (0xFFFFFFFFU)
#define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT (0U)
/*! DMA_TRANSFER_SIZE - DMA Transfer Size. You program this register with the size of the DMA
* transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1).
* This field is automatically decremented by the DMA as the DMA read channel transfer progresses.
* This field indicates the number bytes remaining to be transferred. When all bytes are
* successfully transferred the current transfer size is zero. In LL mode, the DMA overwrites this
* register with the corresponding dword of the LL element. You can read this register to monitor the
* transfer progress, however in some scenarios this register is updated after a delay. For
* example, when less than 3 channels are doorbelled, this register is updated only after a descriptor
* finishes(linked list mode), or the transfer ends (non-linked list mode). Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_SHIFT)) & PCIE_DMA_TRANSFER_SIZE_OFF_RDCH_0_DMA_TRANSFER_SIZE_MASK)
/*! @} */
/*! @name DMA_SAR_LOW_OFF_RDCH_0 - DMA Read SAR Low Register. */
/*! @{ */
#define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT (0U)
/*! SRC_ADDR_REG_LOW - Source Address Register (Lower 32 bits). Indicates the next address to be
* read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. - DMA Read: The SAR is the address of
* the remote memory. - DMA Read: The SAR is the address of the local memory. Note: The access
* attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_SAR_LOW_OFF_RDCH_0_SRC_ADDR_REG_LOW_MASK)
/*! @} */
/*! @name DMA_SAR_HIGH_OFF_RDCH_0 - DMA Read SAR High Register. */
/*! @{ */
#define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT (0U)
/*! SRC_ADDR_REG_HIGH - Source Address Register (Higher 32 bits). In LL mode, the DMA overwrites
* this with the corresponding dword of the LL element. Note: The access attributes of this field
* are as follows: - Dbi: R/W
*/
#define PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_SAR_HIGH_OFF_RDCH_0_SRC_ADDR_REG_HIGH_MASK)
/*! @} */
/*! @name DMA_DAR_LOW_OFF_RDCH_0 - DMA Read DAR Low Register. */
/*! @{ */
#define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT (0U)
/*! DST_ADDR_REG_LOW - Destination Address Register (Lower 32 bits). Indicates the next address to
* be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. - DMA Read: The DAR is the
* address of the local memory. - DMA Read: The DAR is the address of the remote memory. Note: The
* access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_SHIFT)) & PCIE_DMA_DAR_LOW_OFF_RDCH_0_DST_ADDR_REG_LOW_MASK)
/*! @} */
/*! @name DMA_DAR_HIGH_OFF_RDCH_0 - DMA Read DAR High Register. */
/*! @{ */
#define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT (0U)
/*! DST_ADDR_REG_HIGH - Destination Address Register (Higher 32 bits). In LL mode, the DMA
* overwrites this with the corresponding dword of the LL element. Note: The access attributes of this
* field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_SHIFT)) & PCIE_DMA_DAR_HIGH_OFF_RDCH_0_DST_ADDR_REG_HIGH_MASK)
/*! @} */
/*! @name DMA_LLP_LOW_OFF_RDCH_0 - DMA Read Linked List Pointer Low Register. */
/*! @{ */
#define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK (0xFFFFFFFFU)
#define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT (0U)
/*! LLP_LOW - Lower bits of the address of the linked list transfer list in local memory. Used in
* linked list mode only. Updated by the DMA to point to the next element in the transfer list
* after the previous element is consumed. - When the current element is a data element; this field
* is incremented by 6. - When the current element is a link element; this field is overwritten by
* the LL Element Pointer of the element. Note: The access attributes of this field are as
* follows: - Dbi: R/W
*/
#define PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_SHIFT)) & PCIE_DMA_LLP_LOW_OFF_RDCH_0_LLP_LOW_MASK)
/*! @} */
/*! @name DMA_LLP_HIGH_OFF_RDCH_0 - DMA Read Linked List Pointer High Register. */
/*! @{ */
#define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK (0xFFFFFFFFU)
#define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT (0U)
/*! LLP_HIGH - Upper 32 bits of the address of the linked list transfer list in local memory. Used
* in linked list mode only. Updated by the DMA to point to the next element in the transfer list
* as elements are consumed. Note: The access attributes of this field are as follows: - Dbi: R/W
*/
#define PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH(x) (((uint32_t)(((uint32_t)(x)) << PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_SHIFT)) & PCIE_DMA_LLP_HIGH_OFF_RDCH_0_LLP_HIGH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PCIE_Register_Masks */
/* PCIE - Peripheral instance base addresses */
/** Peripheral PCIE base address */
#define PCIE_BASE (0x33800000u)
/** Peripheral PCIE base pointer */
#define PCIE ((PCIE_Type *)PCIE_BASE)
/** Array initializer of PCIE peripheral base addresses */
#define PCIE_BASE_ADDRS { PCIE_BASE }
/** Array initializer of PCIE peripheral base pointers */
#define PCIE_BASE_PTRS { PCIE }
/*!
* @}
*/ /* end of group PCIE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PCIE_PHY Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCIE_PHY_Peripheral_Access_Layer PCIE_PHY Peripheral Access Layer
* @{
*/
/** PCIE_PHY - Register Layout Typedef */
typedef struct {
__IO uint8_t CMN_REG000; /**< , offset: 0x0 */
uint8_t RESERVED_0[3];
__IO uint8_t CMN_REG001; /**< , offset: 0x4 */
uint8_t RESERVED_1[3];
__IO uint8_t CMN_REG002; /**< , offset: 0x8 */
uint8_t RESERVED_2[3];
__IO uint8_t CMN_REG003; /**< , offset: 0xC */
uint8_t RESERVED_3[3];
__IO uint8_t CMN_REG004; /**< , offset: 0x10 */
uint8_t RESERVED_4[3];
__IO uint8_t CMN_REG005; /**< , offset: 0x14 */
uint8_t RESERVED_5[3];
__IO uint8_t CMN_REG006; /**< , offset: 0x18 */
uint8_t RESERVED_6[3];
__IO uint8_t CMN_REG007; /**< , offset: 0x1C */
uint8_t RESERVED_7[3];
__IO uint8_t CMN_REG008; /**< , offset: 0x20 */
uint8_t RESERVED_8[3];
__IO uint8_t CMN_REG009; /**< , offset: 0x24 */
uint8_t RESERVED_9[3];
__IO uint8_t CMN_REG00A; /**< , offset: 0x28 */
uint8_t RESERVED_10[3];
__IO uint8_t CMN_REG00B; /**< , offset: 0x2C */
uint8_t RESERVED_11[3];
__IO uint8_t CMN_REG00C; /**< , offset: 0x30 */
uint8_t RESERVED_12[3];
__IO uint8_t CMN_REG00D; /**< , offset: 0x34 */
uint8_t RESERVED_13[3];
__IO uint8_t CMN_REG00E; /**< , offset: 0x38 */
uint8_t RESERVED_14[3];
__IO uint8_t CMN_REG00F; /**< , offset: 0x3C */
uint8_t RESERVED_15[3];
__IO uint8_t CMN_REG010; /**< , offset: 0x40 */
uint8_t RESERVED_16[3];
__IO uint8_t CMN_REG011; /**< , offset: 0x44 */
uint8_t RESERVED_17[3];
__IO uint8_t CMN_REG012; /**< , offset: 0x48 */
uint8_t RESERVED_18[3];
__IO uint8_t CMN_REG013; /**< , offset: 0x4C */
uint8_t RESERVED_19[3];
__IO uint8_t CMN_REG014; /**< , offset: 0x50 */
uint8_t RESERVED_20[3];
__IO uint8_t CMN_REG015; /**< , offset: 0x54 */
uint8_t RESERVED_21[3];
__IO uint8_t CMN_REG016; /**< , offset: 0x58 */
uint8_t RESERVED_22[3];
__IO uint8_t CMN_REG017; /**< , offset: 0x5C */
uint8_t RESERVED_23[3];
__IO uint8_t CMN_REG018; /**< , offset: 0x60 */
uint8_t RESERVED_24[3];
__IO uint8_t CMN_REG019; /**< , offset: 0x64 */
uint8_t RESERVED_25[3];
__IO uint8_t CMN_REG01A; /**< , offset: 0x68 */
uint8_t RESERVED_26[3];
__IO uint8_t CMN_REG01B; /**< , offset: 0x6C */
uint8_t RESERVED_27[3];
__IO uint8_t CMN_REG01C; /**< , offset: 0x70 */
uint8_t RESERVED_28[3];
__IO uint8_t CMN_REG01D; /**< , offset: 0x74 */
uint8_t RESERVED_29[3];
__IO uint8_t CMN_REG01E; /**< , offset: 0x78 */
uint8_t RESERVED_30[3];
__IO uint8_t CMN_REG01F; /**< , offset: 0x7C */
uint8_t RESERVED_31[3];
__IO uint8_t CMN_REG020; /**< , offset: 0x80 */
uint8_t RESERVED_32[3];
__IO uint8_t CMN_REG021; /**< , offset: 0x84 */
uint8_t RESERVED_33[3];
__IO uint8_t CMN_REG022; /**< , offset: 0x88 */
uint8_t RESERVED_34[3];
__IO uint8_t CMN_REG023; /**< , offset: 0x8C */
uint8_t RESERVED_35[3];
__IO uint8_t CMN_REG024; /**< , offset: 0x90 */
uint8_t RESERVED_36[3];
__IO uint8_t CMN_REG025; /**< , offset: 0x94 */
uint8_t RESERVED_37[3];
__IO uint8_t CMN_REG026; /**< , offset: 0x98 */
uint8_t RESERVED_38[3];
__IO uint8_t CMN_REG027; /**< , offset: 0x9C */
uint8_t RESERVED_39[3];
__IO uint8_t CMN_REG028; /**< , offset: 0xA0 */
uint8_t RESERVED_40[3];
__IO uint8_t CMN_REG029; /**< , offset: 0xA4 */
uint8_t RESERVED_41[3];
__IO uint8_t CMN_REG02A; /**< , offset: 0xA8 */
uint8_t RESERVED_42[3];
__IO uint8_t CMN_REG02B; /**< , offset: 0xAC */
uint8_t RESERVED_43[3];
__IO uint8_t CMN_REG02C; /**< , offset: 0xB0 */
uint8_t RESERVED_44[3];
__IO uint8_t CMN_REG02D; /**< , offset: 0xB4 */
uint8_t RESERVED_45[3];
__IO uint8_t CMN_REG02E; /**< , offset: 0xB8 */
uint8_t RESERVED_46[3];
__IO uint8_t CMN_REG02F; /**< , offset: 0xBC */
uint8_t RESERVED_47[3];
__IO uint8_t CMN_REG030; /**< , offset: 0xC0 */
uint8_t RESERVED_48[3];
__IO uint8_t CMN_REG031; /**< , offset: 0xC4 */
uint8_t RESERVED_49[3];
__IO uint8_t CMN_REG032; /**< , offset: 0xC8 */
uint8_t RESERVED_50[3];
__IO uint8_t CMN_REG033; /**< , offset: 0xCC */
uint8_t RESERVED_51[3];
__IO uint8_t CMN_REG034; /**< , offset: 0xD0 */
uint8_t RESERVED_52[3];
__IO uint8_t CMN_REG035; /**< , offset: 0xD4 */
uint8_t RESERVED_53[3];
__IO uint8_t CMN_REG036; /**< , offset: 0xD8 */
uint8_t RESERVED_54[3];
__IO uint8_t CMN_REG037; /**< , offset: 0xDC */
uint8_t RESERVED_55[3];
__IO uint8_t CMN_REG038; /**< , offset: 0xE0 */
uint8_t RESERVED_56[3];
__IO uint8_t CMN_REG039; /**< , offset: 0xE4 */
uint8_t RESERVED_57[3];
__IO uint8_t CMN_REG03A; /**< , offset: 0xE8 */
uint8_t RESERVED_58[3];
__IO uint8_t CMN_REG03B; /**< , offset: 0xEC */
uint8_t RESERVED_59[3];
__IO uint8_t CMN_REG03C; /**< , offset: 0xF0 */
uint8_t RESERVED_60[3];
__IO uint8_t CMN_REG03D; /**< , offset: 0xF4 */
uint8_t RESERVED_61[3];
__IO uint8_t CMN_REG03E; /**< , offset: 0xF8 */
uint8_t RESERVED_62[3];
__IO uint8_t CMN_REG03F; /**< , offset: 0xFC */
uint8_t RESERVED_63[3];
__IO uint8_t CMN_REG040; /**< , offset: 0x100 */
uint8_t RESERVED_64[3];
__IO uint8_t CMN_REG041; /**< , offset: 0x104 */
uint8_t RESERVED_65[3];
__IO uint8_t CMN_REG042; /**< , offset: 0x108 */
uint8_t RESERVED_66[3];
__IO uint8_t CMN_REG043; /**< , offset: 0x10C */
uint8_t RESERVED_67[3];
__IO uint8_t CMN_REG044; /**< , offset: 0x110 */
uint8_t RESERVED_68[3];
__IO uint8_t CMN_REG045; /**< , offset: 0x114 */
uint8_t RESERVED_69[3];
__IO uint8_t CMN_REG046; /**< , offset: 0x118 */
uint8_t RESERVED_70[3];
__IO uint8_t CMN_REG047; /**< , offset: 0x11C */
uint8_t RESERVED_71[3];
__IO uint8_t CMN_REG048; /**< , offset: 0x120 */
uint8_t RESERVED_72[3];
__IO uint8_t CMN_REG049; /**< , offset: 0x124 */
uint8_t RESERVED_73[3];
__IO uint8_t CMN_REG04A; /**< , offset: 0x128 */
uint8_t RESERVED_74[3];
__IO uint8_t CMN_REG04B; /**< , offset: 0x12C */
uint8_t RESERVED_75[3];
__IO uint8_t CMN_REG04C; /**< , offset: 0x130 */
uint8_t RESERVED_76[3];
__IO uint8_t CMN_REG04D; /**< , offset: 0x134 */
uint8_t RESERVED_77[3];
__IO uint8_t CMN_REG04E; /**< , offset: 0x138 */
uint8_t RESERVED_78[3];
__IO uint8_t CMN_REG04F; /**< , offset: 0x13C */
uint8_t RESERVED_79[3];
__IO uint8_t CMN_REG050; /**< , offset: 0x140 */
uint8_t RESERVED_80[3];
__IO uint8_t CMN_REG051; /**< , offset: 0x144 */
uint8_t RESERVED_81[3];
__IO uint8_t CMN_REG052; /**< , offset: 0x148 */
uint8_t RESERVED_82[3];
__IO uint8_t CMN_REG053; /**< , offset: 0x14C */
uint8_t RESERVED_83[3];
__IO uint8_t CMN_REG054; /**< , offset: 0x150 */
uint8_t RESERVED_84[3];
__IO uint8_t CMN_REG055; /**< , offset: 0x154 */
uint8_t RESERVED_85[3];
__IO uint8_t CMN_REG056; /**< , offset: 0x158 */
uint8_t RESERVED_86[3];
__IO uint8_t CMN_REG057; /**< , offset: 0x15C */
uint8_t RESERVED_87[3];
__IO uint8_t CMN_REG058; /**< , offset: 0x160 */
uint8_t RESERVED_88[3];
__IO uint8_t CMN_REG059; /**< , offset: 0x164 */
uint8_t RESERVED_89[3];
__IO uint8_t CMN_REG05A; /**< , offset: 0x168 */
uint8_t RESERVED_90[3];
__IO uint8_t CMN_REG05B; /**< , offset: 0x16C */
uint8_t RESERVED_91[3];
__IO uint8_t CMN_REG05C; /**< , offset: 0x170 */
uint8_t RESERVED_92[3];
__IO uint8_t CMN_REG05D; /**< , offset: 0x174 */
uint8_t RESERVED_93[3];
__IO uint8_t CMN_REG05E; /**< , offset: 0x178 */
uint8_t RESERVED_94[3];
__IO uint8_t CMN_REG05F; /**< , offset: 0x17C */
uint8_t RESERVED_95[3];
__IO uint8_t CMN_REG060; /**< , offset: 0x180 */
uint8_t RESERVED_96[3];
__IO uint8_t CMN_REG061; /**< , offset: 0x184 */
uint8_t RESERVED_97[3];
__IO uint8_t CMN_REG062; /**< , offset: 0x188 */
uint8_t RESERVED_98[3];
__IO uint8_t CMN_REG063; /**< , offset: 0x18C */
uint8_t RESERVED_99[3];
__IO uint8_t CMN_REG064; /**< , offset: 0x190 */
uint8_t RESERVED_100[3];
__IO uint8_t CMN_REG065; /**< , offset: 0x194 */
uint8_t RESERVED_101[3];
__IO uint8_t CMN_REG066; /**< , offset: 0x198 */
uint8_t RESERVED_102[3];
__IO uint8_t CMN_REG067; /**< , offset: 0x19C */
uint8_t RESERVED_103[3];
__IO uint8_t CMN_REG068; /**< , offset: 0x1A0 */
uint8_t RESERVED_104[3];
__IO uint8_t CMN_REG069; /**< , offset: 0x1A4 */
uint8_t RESERVED_105[3];
__IO uint8_t CMN_REG06A; /**< , offset: 0x1A8 */
uint8_t RESERVED_106[3];
__IO uint8_t CMN_REG06B; /**< , offset: 0x1AC */
uint8_t RESERVED_107[3];
__IO uint8_t CMN_REG06C; /**< , offset: 0x1B0 */
uint8_t RESERVED_108[3];
__IO uint8_t CMN_REG06D; /**< , offset: 0x1B4 */
uint8_t RESERVED_109[3];
__IO uint8_t CMN_REG06E; /**< , offset: 0x1B8 */
uint8_t RESERVED_110[3];
__IO uint8_t CMN_REG06F; /**< , offset: 0x1BC */
uint8_t RESERVED_111[3];
__IO uint8_t CMN_REG070; /**< , offset: 0x1C0 */
uint8_t RESERVED_112[3];
__IO uint8_t CMN_REG071; /**< , offset: 0x1C4 */
uint8_t RESERVED_113[3];
__IO uint8_t CMN_REG072; /**< , offset: 0x1C8 */
uint8_t RESERVED_114[3];
__IO uint8_t CMN_REG073; /**< , offset: 0x1CC */
uint8_t RESERVED_115[3];
__IO uint8_t CMN_REG074; /**< , offset: 0x1D0 */
uint8_t RESERVED_116[3];
__IO uint8_t CMN_REG075; /**< , offset: 0x1D4 */
uint8_t RESERVED_117[43];
__IO uint8_t CMN_REG076; /**< , offset: 0x200 */
uint8_t RESERVED_118[3];
__IO uint8_t CMN_REG077; /**< , offset: 0x204 */
uint8_t RESERVED_119[3];
__IO uint8_t CMN_REG078; /**< , offset: 0x208 */
uint8_t RESERVED_120[3];
__IO uint8_t CMN_REG079; /**< , offset: 0x20C */
uint8_t RESERVED_121[3];
__IO uint8_t CMN_REG080; /**< , offset: 0x210 */
uint8_t RESERVED_122[3];
__IO uint8_t CMN_REG081; /**< , offset: 0x214 */
uint8_t RESERVED_123[3];
__IO uint8_t CMN_REG082; /**< , offset: 0x218 */
uint8_t RESERVED_124[487];
__IO uint8_t TRSV_REG000; /**< , offset: 0x400 */
uint8_t RESERVED_125[3];
__IO uint8_t TRSV_REG001; /**< , offset: 0x404 */
uint8_t RESERVED_126[3];
__IO uint8_t TRSV_REG002; /**< , offset: 0x408 */
uint8_t RESERVED_127[3];
__IO uint8_t TRSV_REG003; /**< , offset: 0x40C */
uint8_t RESERVED_128[3];
__IO uint8_t TRSV_REG004; /**< , offset: 0x410 */
uint8_t RESERVED_129[3];
__IO uint8_t TRSV_REG005; /**< , offset: 0x414 */
uint8_t RESERVED_130[3];
__IO uint8_t TRSV_REG006; /**< , offset: 0x418 */
uint8_t RESERVED_131[3];
__IO uint8_t TRSV_REG007; /**< , offset: 0x41C */
uint8_t RESERVED_132[3];
__IO uint8_t TRSV_REG008; /**< , offset: 0x420 */
uint8_t RESERVED_133[3];
__IO uint8_t TRSV_REG009; /**< , offset: 0x424 */
uint8_t RESERVED_134[3];
__IO uint8_t TRSV_REG00A; /**< , offset: 0x428 */
uint8_t RESERVED_135[3];
__IO uint8_t TRSV_REG00B; /**< , offset: 0x42C */
uint8_t RESERVED_136[3];
__IO uint8_t TRSV_REG00C; /**< , offset: 0x430 */
uint8_t RESERVED_137[3];
__IO uint8_t TRSV_REG00D; /**< , offset: 0x434 */
uint8_t RESERVED_138[3];
__IO uint8_t TRSV_REG00E; /**< , offset: 0x438 */
uint8_t RESERVED_139[3];
__IO uint8_t TRSV_REG00F; /**< , offset: 0x43C */
uint8_t RESERVED_140[3];
__IO uint8_t TRSV_REG010; /**< , offset: 0x440 */
uint8_t RESERVED_141[3];
__IO uint8_t TRSV_REG011; /**< , offset: 0x444 */
uint8_t RESERVED_142[3];
__IO uint8_t TRSV_REG012; /**< , offset: 0x448 */
uint8_t RESERVED_143[3];
__IO uint8_t TRSV_REG013; /**< , offset: 0x44C */
uint8_t RESERVED_144[3];
__IO uint8_t TRSV_REG014; /**< , offset: 0x450 */
uint8_t RESERVED_145[3];
__IO uint8_t TRSV_REG015; /**< , offset: 0x454 */
uint8_t RESERVED_146[3];
__IO uint8_t TRSV_REG016; /**< , offset: 0x458 */
uint8_t RESERVED_147[3];
__IO uint8_t TRSV_REG017; /**< , offset: 0x45C */
uint8_t RESERVED_148[3];
__IO uint8_t TRSV_REG018; /**< , offset: 0x460 */
uint8_t RESERVED_149[3];
__IO uint8_t TRSV_REG019; /**< , offset: 0x464 */
uint8_t RESERVED_150[3];
__IO uint8_t TRSV_REG01A; /**< , offset: 0x468 */
uint8_t RESERVED_151[3];
__IO uint8_t TRSV_REG01B; /**< , offset: 0x46C */
uint8_t RESERVED_152[3];
__IO uint8_t TRSV_REG01C; /**< , offset: 0x470 */
uint8_t RESERVED_153[3];
__IO uint8_t TRSV_REG01D; /**< , offset: 0x474 */
uint8_t RESERVED_154[3];
__IO uint8_t TRSV_REG01E; /**< , offset: 0x478 */
uint8_t RESERVED_155[3];
__IO uint8_t TRSV_REG01F; /**< , offset: 0x47C */
uint8_t RESERVED_156[3];
__IO uint8_t TRSV_REG020; /**< , offset: 0x480 */
uint8_t RESERVED_157[3];
__IO uint8_t TRSV_REG021; /**< , offset: 0x484 */
uint8_t RESERVED_158[3];
__IO uint8_t TRSV_REG022; /**< , offset: 0x488 */
uint8_t RESERVED_159[3];
__IO uint8_t TRSV_REG023; /**< , offset: 0x48C */
uint8_t RESERVED_160[3];
__IO uint8_t TRSV_REG024; /**< , offset: 0x490 */
uint8_t RESERVED_161[3];
__IO uint8_t TRSV_REG025; /**< , offset: 0x494 */
uint8_t RESERVED_162[3];
__IO uint8_t TRSV_REG026; /**< , offset: 0x498 */
uint8_t RESERVED_163[3];
__IO uint8_t TRSV_REG027; /**< , offset: 0x49C */
uint8_t RESERVED_164[3];
__IO uint8_t TRSV_REG028; /**< , offset: 0x4A0 */
uint8_t RESERVED_165[3];
__IO uint8_t TRSV_REG029; /**< , offset: 0x4A4 */
uint8_t RESERVED_166[3];
__IO uint8_t TRSV_REG02A; /**< , offset: 0x4A8 */
uint8_t RESERVED_167[3];
__IO uint8_t TRSV_REG02B; /**< , offset: 0x4AC */
uint8_t RESERVED_168[3];
__IO uint8_t TRSV_REG02C; /**< , offset: 0x4B0 */
uint8_t RESERVED_169[3];
__IO uint8_t TRSV_REG02D; /**< , offset: 0x4B4 */
uint8_t RESERVED_170[3];
__IO uint8_t TRSV_REG02E; /**< , offset: 0x4B8 */
uint8_t RESERVED_171[3];
__IO uint8_t TRSV_REG02F; /**< , offset: 0x4BC */
uint8_t RESERVED_172[3];
__IO uint8_t TRSV_REG030; /**< , offset: 0x4C0 */
uint8_t RESERVED_173[3];
__IO uint8_t TRSV_REG031; /**< , offset: 0x4C4 */
uint8_t RESERVED_174[3];
__IO uint8_t TRSV_REG032; /**< , offset: 0x4C8 */
uint8_t RESERVED_175[3];
__IO uint8_t TRSV_REG033; /**< , offset: 0x4CC */
uint8_t RESERVED_176[3];
__IO uint8_t TRSV_REG034; /**< , offset: 0x4D0 */
uint8_t RESERVED_177[3];
__IO uint8_t TRSV_REG035; /**< , offset: 0x4D4 */
uint8_t RESERVED_178[3];
__IO uint8_t TRSV_REG036; /**< , offset: 0x4D8 */
uint8_t RESERVED_179[3];
__IO uint8_t TRSV_REG037; /**< , offset: 0x4DC */
uint8_t RESERVED_180[3];
__IO uint8_t TRSV_REG038; /**< , offset: 0x4E0 */
uint8_t RESERVED_181[3];
__IO uint8_t TRSV_REG039; /**< , offset: 0x4E4 */
uint8_t RESERVED_182[3];
__IO uint8_t TRSV_REG03A; /**< , offset: 0x4E8 */
uint8_t RESERVED_183[3];
__IO uint8_t TRSV_REG03B; /**< , offset: 0x4EC */
uint8_t RESERVED_184[3];
__IO uint8_t TRSV_REG03C; /**< , offset: 0x4F0 */
uint8_t RESERVED_185[3];
__IO uint8_t TRSV_REG03D; /**< , offset: 0x4F4 */
uint8_t RESERVED_186[3];
__IO uint8_t TRSV_REG03E; /**< , offset: 0x4F8 */
uint8_t RESERVED_187[3];
__IO uint8_t TRSV_REG03F; /**< , offset: 0x4FC */
uint8_t RESERVED_188[3];
__IO uint8_t TRSV_REG040; /**< , offset: 0x500 */
uint8_t RESERVED_189[3];
__IO uint8_t TRSV_REG041; /**< , offset: 0x504 */
uint8_t RESERVED_190[3];
__IO uint8_t TRSV_REG042; /**< , offset: 0x508 */
uint8_t RESERVED_191[3];
__IO uint8_t TRSV_REG043; /**< , offset: 0x50C */
uint8_t RESERVED_192[3];
__IO uint8_t TRSV_REG044; /**< , offset: 0x510 */
uint8_t RESERVED_193[3];
__IO uint8_t TRSV_REG045; /**< , offset: 0x514 */
uint8_t RESERVED_194[3];
__IO uint8_t TRSV_REG046; /**< , offset: 0x518 */
uint8_t RESERVED_195[3];
__IO uint8_t TRSV_REG047; /**< , offset: 0x51C */
uint8_t RESERVED_196[3];
__IO uint8_t TRSV_REG048; /**< , offset: 0x520 */
uint8_t RESERVED_197[3];
__IO uint8_t TRSV_REG049; /**< , offset: 0x524 */
uint8_t RESERVED_198[3];
__IO uint8_t TRSV_REG04A; /**< , offset: 0x528 */
uint8_t RESERVED_199[3];
__IO uint8_t TRSV_REG04B; /**< , offset: 0x52C */
uint8_t RESERVED_200[3];
__IO uint8_t TRSV_REG04C; /**< , offset: 0x530 */
uint8_t RESERVED_201[3];
__IO uint8_t TRSV_REG04D; /**< , offset: 0x534 */
uint8_t RESERVED_202[3];
__IO uint8_t TRSV_REG04E; /**< , offset: 0x538 */
uint8_t RESERVED_203[3];
__IO uint8_t TRSV_REG04F; /**< , offset: 0x53C */
uint8_t RESERVED_204[3];
__IO uint8_t TRSV_REG050; /**< , offset: 0x540 */
uint8_t RESERVED_205[3];
__IO uint8_t TRSV_REG051; /**< , offset: 0x544 */
uint8_t RESERVED_206[3];
__IO uint8_t TRSV_REG052; /**< , offset: 0x548 */
uint8_t RESERVED_207[3];
__IO uint8_t TRSV_REG053; /**< , offset: 0x54C */
uint8_t RESERVED_208[3];
__IO uint8_t TRSV_REG054; /**< , offset: 0x550 */
uint8_t RESERVED_209[3];
__IO uint8_t TRSV_REG055; /**< , offset: 0x554 */
uint8_t RESERVED_210[3];
__IO uint8_t TRSV_REG056; /**< , offset: 0x558 */
uint8_t RESERVED_211[3];
__IO uint8_t TRSV_REG057; /**< , offset: 0x55C */
uint8_t RESERVED_212[3];
__IO uint8_t TRSV_REG058; /**< , offset: 0x560 */
uint8_t RESERVED_213[3];
__IO uint8_t TRSV_REG059; /**< , offset: 0x564 */
uint8_t RESERVED_214[3];
__IO uint8_t TRSV_REG05A; /**< , offset: 0x568 */
uint8_t RESERVED_215[3];
__IO uint8_t TRSV_REG05B; /**< , offset: 0x56C */
uint8_t RESERVED_216[3];
__IO uint8_t TRSV_REG05C; /**< , offset: 0x570 */
uint8_t RESERVED_217[3];
__IO uint8_t TRSV_REG05D; /**< , offset: 0x574 */
uint8_t RESERVED_218[3];
__IO uint8_t TRSV_REG05E; /**< , offset: 0x578 */
uint8_t RESERVED_219[3];
__IO uint8_t TRSV_REG05F; /**< , offset: 0x57C */
uint8_t RESERVED_220[3];
__IO uint8_t TRSV_REG060; /**< , offset: 0x580 */
uint8_t RESERVED_221[3];
__IO uint8_t TRSV_REG061; /**< , offset: 0x584 */
uint8_t RESERVED_222[3];
__IO uint8_t TRSV_REG062; /**< , offset: 0x588 */
uint8_t RESERVED_223[3];
__IO uint8_t TRSV_REG063; /**< , offset: 0x58C */
uint8_t RESERVED_224[3];
__IO uint8_t TRSV_REG064; /**< , offset: 0x590 */
uint8_t RESERVED_225[3];
__IO uint8_t TRSV_REG065; /**< , offset: 0x594 */
uint8_t RESERVED_226[3];
__IO uint8_t TRSV_REG066; /**< , offset: 0x598 */
uint8_t RESERVED_227[3];
__IO uint8_t TRSV_REG067; /**< , offset: 0x59C */
uint8_t RESERVED_228[3];
__IO uint8_t TRSV_REG068; /**< , offset: 0x5A0 */
uint8_t RESERVED_229[3];
__IO uint8_t TRSV_REG069; /**< , offset: 0x5A4 */
uint8_t RESERVED_230[3];
__IO uint8_t TRSV_REG06A; /**< , offset: 0x5A8 */
uint8_t RESERVED_231[3];
__IO uint8_t TRSV_REG06B; /**< , offset: 0x5AC */
uint8_t RESERVED_232[3];
__IO uint8_t TRSV_REG06C; /**< , offset: 0x5B0 */
uint8_t RESERVED_233[3];
__IO uint8_t TRSV_REG06D; /**< , offset: 0x5B4 */
uint8_t RESERVED_234[3];
__IO uint8_t TRSV_REG06E; /**< , offset: 0x5B8 */
uint8_t RESERVED_235[3];
__IO uint8_t TRSV_REG06F; /**< , offset: 0x5BC */
uint8_t RESERVED_236[3];
__IO uint8_t TRSV_REG070; /**< , offset: 0x5C0 */
uint8_t RESERVED_237[3];
__IO uint8_t TRSV_REG071; /**< , offset: 0x5C4 */
uint8_t RESERVED_238[3];
__IO uint8_t TRSV_REG072; /**< , offset: 0x5C8 */
uint8_t RESERVED_239[3];
__IO uint8_t TRSV_REG073; /**< , offset: 0x5CC */
uint8_t RESERVED_240[3];
__IO uint8_t TRSV_REG074; /**< , offset: 0x5D0 */
uint8_t RESERVED_241[3];
__IO uint8_t TRSV_REG075; /**< , offset: 0x5D4 */
uint8_t RESERVED_242[3];
__IO uint8_t TRSV_REG076; /**< , offset: 0x5D8 */
uint8_t RESERVED_243[3];
__IO uint8_t TRSV_REG077; /**< , offset: 0x5DC */
uint8_t RESERVED_244[3];
__IO uint8_t TRSV_REG078; /**< , offset: 0x5E0 */
uint8_t RESERVED_245[3];
__IO uint8_t TRSV_REG079; /**< , offset: 0x5E4 */
uint8_t RESERVED_246[3];
__IO uint8_t TRSV_REG07A; /**< , offset: 0x5E8 */
uint8_t RESERVED_247[3];
__IO uint8_t TRSV_REG07B; /**< , offset: 0x5EC */
uint8_t RESERVED_248[3];
__IO uint8_t TRSV_REG07C; /**< , offset: 0x5F0 */
uint8_t RESERVED_249[3];
__IO uint8_t TRSV_REG07D; /**< , offset: 0x5F4 */
uint8_t RESERVED_250[3];
__IO uint8_t TRSV_REG07E; /**< , offset: 0x5F8 */
uint8_t RESERVED_251[3];
__IO uint8_t TRSV_REG07F; /**< , offset: 0x5FC */
uint8_t RESERVED_252[3];
__IO uint8_t TRSV_REG080; /**< , offset: 0x600 */
uint8_t RESERVED_253[3];
__IO uint8_t TRSV_REG081; /**< , offset: 0x604 */
uint8_t RESERVED_254[3];
__IO uint8_t TRSV_REG082; /**< , offset: 0x608 */
uint8_t RESERVED_255[3];
__IO uint8_t TRSV_REG083; /**< , offset: 0x60C */
uint8_t RESERVED_256[3];
__IO uint8_t TRSV_REG084; /**< , offset: 0x610 */
uint8_t RESERVED_257[3];
__IO uint8_t TRSV_REG085; /**< , offset: 0x614 */
uint8_t RESERVED_258[3];
__IO uint8_t TRSV_REG086; /**< , offset: 0x618 */
uint8_t RESERVED_259[3];
__IO uint8_t TRSV_REG087; /**< , offset: 0x61C */
uint8_t RESERVED_260[3];
__IO uint8_t TRSV_REG088; /**< , offset: 0x620 */
uint8_t RESERVED_261[3];
__IO uint8_t TRSV_REG089; /**< , offset: 0x624 */
uint8_t RESERVED_262[3];
__IO uint8_t TRSV_REG08A; /**< , offset: 0x628 */
uint8_t RESERVED_263[3];
__IO uint8_t TRSV_REG08B; /**< , offset: 0x62C */
uint8_t RESERVED_264[3];
__IO uint8_t TRSV_REG08C; /**< , offset: 0x630 */
uint8_t RESERVED_265[3];
__IO uint8_t TRSV_REG08D; /**< , offset: 0x634 */
uint8_t RESERVED_266[3];
__IO uint8_t TRSV_REG08E; /**< , offset: 0x638 */
uint8_t RESERVED_267[3];
__IO uint8_t TRSV_REG08F; /**< , offset: 0x63C */
uint8_t RESERVED_268[3];
__IO uint8_t TRSV_REG090; /**< , offset: 0x640 */
uint8_t RESERVED_269[3];
__IO uint8_t TRSV_REG091; /**< , offset: 0x644 */
uint8_t RESERVED_270[3];
__IO uint8_t TRSV_REG092; /**< , offset: 0x648 */
uint8_t RESERVED_271[3];
__IO uint8_t TRSV_REG093; /**< , offset: 0x64C */
uint8_t RESERVED_272[3];
__IO uint8_t TRSV_REG094; /**< , offset: 0x650 */
uint8_t RESERVED_273[3];
__IO uint8_t TRSV_REG095; /**< , offset: 0x654 */
uint8_t RESERVED_274[3];
__IO uint8_t TRSV_REG096; /**< , offset: 0x658 */
uint8_t RESERVED_275[3];
__IO uint8_t TRSV_REG097; /**< , offset: 0x65C */
uint8_t RESERVED_276[3];
__IO uint8_t TRSV_REG098; /**< , offset: 0x660 */
uint8_t RESERVED_277[3];
__IO uint8_t TRSV_REG099; /**< , offset: 0x664 */
uint8_t RESERVED_278[3];
__IO uint8_t TRSV_REG09A; /**< , offset: 0x668 */
uint8_t RESERVED_279[3];
__IO uint8_t TRSV_REG09B; /**< , offset: 0x66C */
uint8_t RESERVED_280[3];
__IO uint8_t TRSV_REG09C; /**< , offset: 0x670 */
uint8_t RESERVED_281[3];
__IO uint8_t TRSV_REG09D; /**< , offset: 0x674 */
uint8_t RESERVED_282[3];
__IO uint8_t TRSV_REG09E; /**< , offset: 0x678 */
uint8_t RESERVED_283[3];
__IO uint8_t TRSV_REG09F; /**< , offset: 0x67C */
uint8_t RESERVED_284[3];
__IO uint8_t TRSV_REG0A0; /**< , offset: 0x680 */
uint8_t RESERVED_285[3];
__IO uint8_t TRSV_REG0A1; /**< , offset: 0x684 */
uint8_t RESERVED_286[3];
__IO uint8_t TRSV_REG0A2; /**< , offset: 0x688 */
uint8_t RESERVED_287[3];
__IO uint8_t TRSV_REG0A3; /**< , offset: 0x68C */
uint8_t RESERVED_288[3];
__IO uint8_t TRSV_REG0A4; /**< , offset: 0x690 */
uint8_t RESERVED_289[3];
__IO uint8_t TRSV_REG0A5; /**< , offset: 0x694 */
uint8_t RESERVED_290[3];
__IO uint8_t TRSV_REG0A6; /**< , offset: 0x698 */
uint8_t RESERVED_291[3];
__IO uint8_t TRSV_REG0A7; /**< , offset: 0x69C */
uint8_t RESERVED_292[3];
__IO uint8_t TRSV_REG0A8; /**< , offset: 0x6A0 */
uint8_t RESERVED_293[3];
__IO uint8_t TRSV_REG0A9; /**< , offset: 0x6A4 */
uint8_t RESERVED_294[3];
__IO uint8_t TRSV_REG0AA; /**< , offset: 0x6A8 */
uint8_t RESERVED_295[3];
__IO uint8_t TRSV_REG0AB; /**< , offset: 0x6AC */
uint8_t RESERVED_296[3];
__IO uint8_t TRSV_REG0AC; /**< , offset: 0x6B0 */
uint8_t RESERVED_297[3];
__IO uint8_t TRSV_REG0AD; /**< , offset: 0x6B4 */
uint8_t RESERVED_298[3];
__IO uint8_t TRSV_REG0AE; /**< , offset: 0x6B8 */
uint8_t RESERVED_299[3];
__IO uint8_t TRSV_REG0AF; /**< , offset: 0x6BC */
uint8_t RESERVED_300[3];
__IO uint8_t TRSV_REG0B0; /**< , offset: 0x6C0 */
uint8_t RESERVED_301[3];
__IO uint8_t TRSV_REG0B1; /**< , offset: 0x6C4 */
uint8_t RESERVED_302[3];
__IO uint8_t TRSV_REG0B2; /**< , offset: 0x6C8 */
uint8_t RESERVED_303[3];
__IO uint8_t TRSV_REG0B3; /**< , offset: 0x6CC */
uint8_t RESERVED_304[3];
__IO uint8_t TRSV_REG0B4; /**< , offset: 0x6D0 */
uint8_t RESERVED_305[3];
__IO uint8_t TRSV_REG0B5; /**< , offset: 0x6D4 */
uint8_t RESERVED_306[3];
__IO uint8_t TRSV_REG0B6; /**< , offset: 0x6D8 */
uint8_t RESERVED_307[3];
__IO uint8_t TRSV_REG0B7; /**< , offset: 0x6DC */
uint8_t RESERVED_308[3];
__IO uint8_t TRSV_REG0B8; /**< , offset: 0x6E0 */
uint8_t RESERVED_309[3];
__IO uint8_t TRSV_REG0B9; /**< , offset: 0x6E4 */
uint8_t RESERVED_310[3];
__IO uint8_t TRSV_REG0BA; /**< , offset: 0x6E8 */
uint8_t RESERVED_311[3];
__IO uint8_t TRSV_REG0BB; /**< , offset: 0x6EC */
uint8_t RESERVED_312[3];
__IO uint8_t TRSV_REG0BC; /**< , offset: 0x6F0 */
uint8_t RESERVED_313[3];
__IO uint8_t TRSV_REG0BD; /**< , offset: 0x6F4 */
uint8_t RESERVED_314[3];
__IO uint8_t TRSV_REG0BE; /**< , offset: 0x6F8 */
uint8_t RESERVED_315[3];
__IO uint8_t TRSV_REG0BF; /**< , offset: 0x6FC */
uint8_t RESERVED_316[3];
__IO uint8_t TRSV_REG0C0; /**< , offset: 0x700 */
uint8_t RESERVED_317[3];
__IO uint8_t TRSV_REG0C1; /**< , offset: 0x704 */
uint8_t RESERVED_318[3];
__IO uint8_t TRSV_REG0C2; /**< , offset: 0x708 */
uint8_t RESERVED_319[3];
__IO uint8_t TRSV_REG0C3; /**< , offset: 0x70C */
uint8_t RESERVED_320[3];
__IO uint8_t TRSV_REG0C4; /**< , offset: 0x710 */
uint8_t RESERVED_321[3];
__IO uint8_t TRSV_REG0C5; /**< , offset: 0x714 */
uint8_t RESERVED_322[3];
__IO uint8_t TRSV_REG0C6; /**< , offset: 0x718 */
uint8_t RESERVED_323[3];
__IO uint8_t TRSV_REG0C7; /**< , offset: 0x71C */
uint8_t RESERVED_324[3];
__IO uint8_t TRSV_REG0C8; /**< , offset: 0x720 */
uint8_t RESERVED_325[3];
__IO uint8_t TRSV_REG0C9; /**< , offset: 0x724 */
uint8_t RESERVED_326[3];
__IO uint8_t TRSV_REG0CA; /**< , offset: 0x728 */
uint8_t RESERVED_327[3];
__IO uint8_t TRSV_REG0CB; /**< , offset: 0x72C */
uint8_t RESERVED_328[3];
__IO uint8_t TRSV_REG0CC; /**< , offset: 0x730 */
uint8_t RESERVED_329[3];
__IO uint8_t TRSV_REG0CD; /**< , offset: 0x734 */
uint8_t RESERVED_330[3];
__IO uint8_t TRSV_REG0CE; /**< , offset: 0x738 */
uint8_t RESERVED_331[3];
__IO uint8_t TRSV_REG0CF; /**< , offset: 0x73C */
uint8_t RESERVED_332[3];
__IO uint8_t TRSV_REG0D0; /**< , offset: 0x740 */
uint8_t RESERVED_333[3];
__IO uint8_t TRSV_REG0D1; /**< , offset: 0x744 */
uint8_t RESERVED_334[3];
__IO uint8_t TRSV_REG0D2; /**< , offset: 0x748 */
uint8_t RESERVED_335[3];
__IO uint8_t TRSV_REG0D3; /**< , offset: 0x74C */
uint8_t RESERVED_336[3];
__IO uint8_t TRSV_REG0D4; /**< , offset: 0x750 */
uint8_t RESERVED_337[3];
__IO uint8_t TRSV_REG0D5; /**< , offset: 0x754 */
uint8_t RESERVED_338[3];
__IO uint8_t TRSV_REG0D6; /**< , offset: 0x758 */
uint8_t RESERVED_339[3];
__IO uint8_t TRSV_REG0D7; /**< , offset: 0x75C */
uint8_t RESERVED_340[3];
__IO uint8_t TRSV_REG0D8; /**< , offset: 0x760 */
uint8_t RESERVED_341[3];
__IO uint8_t TRSV_REG0D9; /**< , offset: 0x764 */
uint8_t RESERVED_342[3];
__IO uint8_t TRSV_REG0DA; /**< , offset: 0x768 */
uint8_t RESERVED_343[3];
__IO uint8_t TRSV_REG0DB; /**< , offset: 0x76C */
uint8_t RESERVED_344[3];
__IO uint8_t TRSV_REG0DC; /**< , offset: 0x770 */
uint8_t RESERVED_345[3];
__IO uint8_t TRSV_REG0DD; /**< , offset: 0x774 */
uint8_t RESERVED_346[3];
__IO uint8_t TRSV_REG0DE; /**< , offset: 0x778 */
uint8_t RESERVED_347[3];
__IO uint8_t TRSV_REG0DF; /**< , offset: 0x77C */
uint8_t RESERVED_348[3];
__IO uint8_t TRSV_REG0E0; /**< , offset: 0x780 */
uint8_t RESERVED_349[3];
__IO uint8_t TRSV_REG0E1; /**< , offset: 0x784 */
uint8_t RESERVED_350[3];
__IO uint8_t TRSV_REG0E2; /**< , offset: 0x788 */
uint8_t RESERVED_351[3];
__IO uint8_t TRSV_REG0E3; /**< , offset: 0x78C */
uint8_t RESERVED_352[3];
__IO uint8_t TRSV_REG0E4; /**< , offset: 0x790 */
uint8_t RESERVED_353[3];
__IO uint8_t TRSV_REG0E5; /**< , offset: 0x794 */
uint8_t RESERVED_354[3];
__IO uint8_t TRSV_REG0E6; /**< , offset: 0x798 */
uint8_t RESERVED_355[3];
__IO uint8_t TRSV_REG0E7; /**< , offset: 0x79C */
uint8_t RESERVED_356[3];
__IO uint8_t TRSV_REG0E8; /**< , offset: 0x7A0 */
uint8_t RESERVED_357[3];
__IO uint8_t TRSV_REG0E9; /**< , offset: 0x7A4 */
uint8_t RESERVED_358[3];
__IO uint8_t TRSV_REG0EA; /**< , offset: 0x7A8 */
uint8_t RESERVED_359[3];
__IO uint8_t TRSV_REG0EB; /**< , offset: 0x7AC */
uint8_t RESERVED_360[3];
__IO uint8_t TRSV_REG0EC; /**< , offset: 0x7B0 */
uint8_t RESERVED_361[3];
__IO uint8_t TRSV_REG0ED; /**< , offset: 0x7B4 */
uint8_t RESERVED_362[3];
__IO uint8_t TRSV_REG0EE; /**< , offset: 0x7B8 */
uint8_t RESERVED_363[3];
__IO uint8_t TRSV_REG0EF; /**< , offset: 0x7BC */
uint8_t RESERVED_364[3];
__IO uint8_t TRSV_REG0F0; /**< , offset: 0x7C0 */
uint8_t RESERVED_365[3];
__IO uint8_t TRSV_REG0F1; /**< , offset: 0x7C4 */
uint8_t RESERVED_366[3];
__IO uint8_t TRSV_REG0F2; /**< , offset: 0x7C8 */
uint8_t RESERVED_367[3];
__IO uint8_t TRSV_REG0F3; /**< , offset: 0x7CC */
uint8_t RESERVED_368[3];
__IO uint8_t TRSV_REG0F4; /**< , offset: 0x7D0 */
uint8_t RESERVED_369[3];
__IO uint8_t TRSV_REG0F5; /**< , offset: 0x7D4 */
uint8_t RESERVED_370[3];
__IO uint8_t TRSV_REG0F6; /**< , offset: 0x7D8 */
uint8_t RESERVED_371[3];
__IO uint8_t TRSV_REG0F7; /**< , offset: 0x7DC */
uint8_t RESERVED_372[3];
__IO uint8_t TRSV_REG0F8; /**< , offset: 0x7E0 */
uint8_t RESERVED_373[3];
__IO uint8_t TRSV_REG0F9; /**< , offset: 0x7E4 */
uint8_t RESERVED_374[3];
__IO uint8_t TRSV_REG0FA; /**< , offset: 0x7E8 */
uint8_t RESERVED_375[3];
__IO uint8_t TRSV_REG0FB; /**< , offset: 0x7EC */
uint8_t RESERVED_376[3];
__IO uint8_t TRSV_REG0FC; /**< , offset: 0x7F0 */
uint8_t RESERVED_377[3];
__IO uint8_t TRSV_REG0FD; /**< , offset: 0x7F4 */
uint8_t RESERVED_378[3];
__IO uint8_t TRSV_REG0FE; /**< , offset: 0x7F8 */
uint8_t RESERVED_379[3];
__IO uint8_t TRSV_REG0FF; /**< , offset: 0x7FC */
} PCIE_PHY_Type;
/* ----------------------------------------------------------------------------
-- PCIE_PHY Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PCIE_PHY_Register_Masks PCIE_PHY Register Masks
* @{
*/
/*! @name CMN_REG000 - */
/*! @{ */
#define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_MASK (0x1U)
#define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_SHIFT (0U)
/*! BGR_LPF_BYPASS - BGR LPF bypass to reduce BGR settle time
*/
#define PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG000_BGR_LPF_BYPASS_MASK)
#define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_MASK (0x2U)
#define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_SHIFT (1U)
/*! OVRD_BGR_LPF_BYPASS - Override enable for bgr_lpf_bypass
*/
#define PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG000_OVRD_BGR_LPF_BYPASS_MASK)
#define PCIE_PHY_CMN_REG000_BGR_EN_MASK (0x4U)
#define PCIE_PHY_CMN_REG000_BGR_EN_SHIFT (2U)
/*! BGR_EN - BGR enable
*/
#define PCIE_PHY_CMN_REG000_BGR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_BGR_EN_SHIFT)) & PCIE_PHY_CMN_REG000_BGR_EN_MASK)
#define PCIE_PHY_CMN_REG000_OVRD_BGR_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG000_OVRD_BGR_EN_SHIFT (3U)
/*! OVRD_BGR_EN - Override enable for bgr_en
*/
#define PCIE_PHY_CMN_REG000_OVRD_BGR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG000_OVRD_BGR_EN_SHIFT)) & PCIE_PHY_CMN_REG000_OVRD_BGR_EN_MASK)
/*! @} */
/*! @name CMN_REG001 - */
/*! @{ */
#define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_SHIFT (0U)
/*! ANA_BGR_LADDER_EN - BGR output voltage selection
*/
#define PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_LADDER_EN_MASK)
#define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_MASK (0x2U)
#define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_SHIFT (1U)
/*! ANA_BGR_CLK_EN - BGR chopper clock enable
*/
#define PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_CLK_EN_MASK)
#define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_MASK (0x7CU)
#define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_SHIFT (2U)
/*! ANA_BGR_820M_SEL - BGR 820mV selection ( for current bias )
*/
#define PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_SHIFT)) & PCIE_PHY_CMN_REG001_ANA_BGR_820M_SEL_MASK)
/*! @} */
/*! @name CMN_REG002 - */
/*! @{ */
#define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_SHIFT (0U)
/*! BIAS_RCAL_EN - RX RCAL bias current enable
*/
#define PCIE_PHY_CMN_REG002_BIAS_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_SHIFT)) & PCIE_PHY_CMN_REG002_BIAS_RCAL_EN_MASK)
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_MASK (0x2U)
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_SHIFT (1U)
/*! OVRD_BIAS_RCAL_EN - Override enable for bias_rcal_en
*/
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_SHIFT)) & PCIE_PHY_CMN_REG002_OVRD_BIAS_RCAL_EN_MASK)
#define PCIE_PHY_CMN_REG002_BIAS_EN_MASK (0x4U)
#define PCIE_PHY_CMN_REG002_BIAS_EN_SHIFT (2U)
/*! BIAS_EN - Bias current enable
*/
#define PCIE_PHY_CMN_REG002_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_BIAS_EN_SHIFT)) & PCIE_PHY_CMN_REG002_BIAS_EN_MASK)
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_SHIFT (3U)
/*! OVRD_BIAS_EN - Override enable for bias_en
*/
#define PCIE_PHY_CMN_REG002_OVRD_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_SHIFT)) & PCIE_PHY_CMN_REG002_OVRD_BIAS_EN_MASK)
#define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_MASK (0x10U)
#define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_SHIFT (4U)
/*! ANA_BGR_ATB_SEL - BGR ATB select
*/
#define PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_SHIFT)) & PCIE_PHY_CMN_REG002_ANA_BGR_ATB_SEL_MASK)
#define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_MASK (0xE0U)
#define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_SHIFT (5U)
/*! ANA_BGR_LADDER_SEL - Resistor ladder voltage selection
*/
#define PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_SHIFT)) & PCIE_PHY_CMN_REG002_ANA_BGR_LADDER_SEL_MASK)
/*! @} */
/*! @name CMN_REG003 - */
/*! @{ */
#define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_MASK (0x3U)
#define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_SHIFT (0U)
/*! ANA_BIAS_TX_RCAL_IREXT_CTRL - REXT-refered bias current control MSB for TX RCAL
*/
#define PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_TX_RCAL_IREXT_CTRL_MASK)
#define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_MASK (0xCU)
#define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_SHIFT (2U)
/*! ANA_BIAS_RX_RCAL_IREXT_CTRL - REXT-refered bias current controlI for RX RCAL
*/
#define PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_RX_RCAL_IREXT_CTRL_MASK)
#define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_MASK (0x30U)
#define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_SHIFT (4U)
/*! ANA_BIAS_IREXT_CTRL - REXT-refered bias current controlI for overall IP
*/
#define PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_SHIFT)) & PCIE_PHY_CMN_REG003_ANA_BIAS_IREXT_CTRL_MASK)
/*! @} */
/*! @name CMN_REG004 - */
/*! @{ */
#define PCIE_PHY_CMN_REG004_PLL_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG004_PLL_EN_SHIFT (0U)
/*! PLL_EN - PLL enable
*/
#define PCIE_PHY_CMN_REG004_PLL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG004_PLL_EN_SHIFT)) & PCIE_PHY_CMN_REG004_PLL_EN_MASK)
#define PCIE_PHY_CMN_REG004_OVRD_PLL_EN_MASK (0x2U)
#define PCIE_PHY_CMN_REG004_OVRD_PLL_EN_SHIFT (1U)
/*! OVRD_PLL_EN - Override enable for pll_en
*/
#define PCIE_PHY_CMN_REG004_OVRD_PLL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG004_OVRD_PLL_EN_SHIFT)) & PCIE_PHY_CMN_REG004_OVRD_PLL_EN_MASK)
/*! @} */
/*! @name CMN_REG005 - */
/*! @{ */
#define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_MASK (0x1U)
#define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_SHIFT (0U)
/*! PLL_AFC_RSTN - PLL AFC reset. When AFC reset is asserted, the previous AFC result is held. When
* AFC reset is released, AFC starts from the previous AFC code stored in internal memory.
*/
#define PCIE_PHY_CMN_REG005_PLL_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_AFC_RSTN_MASK)
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_SHIFT (1U)
/*! OVRD_PLL_AFC_RSTN - Override enable for pll_afc_rstn
*/
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_RSTN_MASK)
#define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_MASK (0x4U)
#define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_SHIFT (2U)
/*! PLL_AFC_INIT_RSTN - PLL AFC initial reset. When initial reset is asserted, the previous AFC
* result is reset. When initial reset is released, AFC starts from the initial AFC code given in
* i_rx_cdr_afc_sel_logic[3:0].
*/
#define PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_AFC_INIT_RSTN_MASK)
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_MASK (0x8U)
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_SHIFT (3U)
/*! OVRD_PLL_AFC_INIT_RSTN - Override enable for pll_afc_init_rstn
*/
#define PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_CMN_REG005_OVRD_PLL_AFC_INIT_RSTN_MASK)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_MASK (0x10U)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_SHIFT (4U)
/*! PLL_VCO_MODE_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G4_MASK)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_MASK (0x20U)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_SHIFT (5U)
/*! PLL_VCO_MODE_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G3_MASK)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_MASK (0x40U)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_SHIFT (6U)
/*! PLL_VCO_MODE_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G2_MASK)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_MASK (0x80U)
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_SHIFT (7U)
/*! PLL_VCO_MODE_G1 - [GEN1] PLL VCO selection
*/
#define PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_SHIFT)) & PCIE_PHY_CMN_REG005_PLL_VCO_MODE_G1_MASK)
/*! @} */
/*! @name CMN_REG006 - */
/*! @{ */
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_MASK (0x3U)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_SHIFT (0U)
/*! ANA_PLL_AFC_MAN_LC_CODE_SEL - Manual PLL AFC code selection (MSB)
*/
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_MAN_LC_CODE_SEL_MASK)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_MASK (0x4U)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_SHIFT (2U)
/*! ANA_PLL_AFC_FROM_PRE_CODE - PLL AFC option in restart case
*/
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_FROM_PRE_CODE_MASK)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_SHIFT (3U)
/*! ANA_PLL_AFC_EN - PLL AFC enable; if enabled, VCO frequency is automatically calibrated. If
* disabled, VCO starts to oscillate with fixed AFC code of i_pll_man_bsel_m and _l.
*/
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_EN_MASK)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_MASK (0x10U)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_SHIFT (4U)
/*! ANA_PLL_AFC_CODE_FORCE - PLL AFC code manual selection enable
*/
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CODE_FORCE_MASK)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_MASK (0x20U)
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_SHIFT (5U)
/*! ANA_PLL_AFC_CLK_DIV2_EN - PLL AFC clock frequency selection
*/
#define PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_SHIFT)) & PCIE_PHY_CMN_REG006_ANA_PLL_AFC_CLK_DIV2_EN_MASK)
/*! @} */
/*! @name CMN_REG007 - */
/*! @{ */
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_MASK (0xFU)
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_SHIFT (0U)
/*! ANA_PLL_AFC_STB_NUM - Number of reference clock cycle to check VCO stabilization during PLL AFC start
*/
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_SHIFT)) & PCIE_PHY_CMN_REG007_ANA_PLL_AFC_STB_NUM_MASK)
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_MASK (0xF0U)
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_SHIFT (4U)
/*! ANA_PLL_AFC_MAN_RING_CODE_SEL - Manual PLL AFC code selection (LSB)
*/
#define PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_SHIFT)) & PCIE_PHY_CMN_REG007_ANA_PLL_AFC_MAN_RING_CODE_SEL_MASK)
/*! @} */
/*! @name CMN_REG008 - */
/*! @{ */
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_MASK (0x1U)
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_SHIFT (0U)
/*! ANA_PLL_AFC_VCI_FORCE - PLL control voltage force for open-loop test purpose
*/
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_SHIFT)) & PCIE_PHY_CMN_REG008_ANA_PLL_AFC_VCI_FORCE_MASK)
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_MASK (0x1EU)
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_SHIFT (1U)
/*! ANA_PLL_AFC_TOL_NUM - PLL VCO stabilization tolerance; VCO is considered as settled-down if
* |counter difference|<i_pll_afc_tol during i_pll_afc_stb_num
*/
#define PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_SHIFT)) & PCIE_PHY_CMN_REG008_ANA_PLL_AFC_TOL_NUM_MASK)
/*! @} */
/*! @name CMN_REG009 - */
/*! @{ */
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_MASK (0x7U)
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_SHIFT (0U)
/*! ANA_PLL_AFC_VCO_CNT_WAIT_NUM - Number of reference clock cycle to count VCO clock during AFC
*/
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_SHIFT)) & PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_WAIT_NUM_MASK)
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_MASK (0xF8U)
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_SHIFT (3U)
/*! ANA_PLL_AFC_VCO_CNT_RUN_NUM - Number of reference clock cycle to wait VCO clock during AFC
*/
#define PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_SHIFT)) & PCIE_PHY_CMN_REG009_ANA_PLL_AFC_VCO_CNT_RUN_NUM_MASK)
/*! @} */
/*! @name CMN_REG00A - */
/*! @{ */
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_SHIFT (0U)
/*! ANA_PLL_AGMC_MAN_GM_SEL_EN - PLL LC VCO GM code selection
*/
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_MAN_GM_SEL_EN_MASK)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_MASK (0x6U)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_SHIFT (1U)
/*! ANA_PLL_AGMC_GM_ADD - Offset code to be added to final gm code
*/
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_GM_ADD_MASK)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_MASK (0x8U)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_SHIFT (3U)
/*! ANA_PLL_AGMC_FROM_MAX_GM - PLL LC VCO automatic gm search initial condition
*/
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_FROM_MAX_GM_MASK)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_MASK (0x10U)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_SHIFT (4U)
/*! ANA_PLL_AGMC_COMP_EN - Comparator enable for PLL LC VCO automatic gm search
*/
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AGMC_COMP_EN_MASK)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_MASK (0xE0U)
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_SHIFT (5U)
/*! ANA_PLL_AFC_VCO_START_CRITERION - Minimum PLL VCO counter value to start AFC (Criterion to suppose PLL VCO successfully start to oscillate)
*/
#define PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_SHIFT)) & PCIE_PHY_CMN_REG00A_ANA_PLL_AFC_VCO_START_CRITERION_MASK)
/*! @} */
/*! @name CMN_REG00B - */
/*! @{ */
#define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_MASK (0xFU)
#define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_SHIFT (0U)
/*! ANA_PLL_AGMC_MAN_GM_SEL - Manual GM code selection for LC VCO
*/
#define PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_SHIFT)) & PCIE_PHY_CMN_REG00B_ANA_PLL_AGMC_MAN_GM_SEL_MASK)
/*! @} */
/*! @name CMN_REG00C - */
/*! @{ */
#define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_MASK (0xFFU)
#define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_SHIFT (0U)
/*! PLL_AGMC_TG_CODE_G1 - [GEN1] Target counter value for automatic GM search of LC VCO
*/
#define PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_SHIFT)) & PCIE_PHY_CMN_REG00C_PLL_AGMC_TG_CODE_G1_MASK)
/*! @} */
/*! @name CMN_REG00D - */
/*! @{ */
#define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_MASK (0xFFU)
#define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_SHIFT (0U)
/*! PLL_AGMC_TG_CODE_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_SHIFT)) & PCIE_PHY_CMN_REG00D_PLL_AGMC_TG_CODE_G2_MASK)
/*! @} */
/*! @name CMN_REG00E - */
/*! @{ */
#define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_MASK (0xFFU)
#define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_SHIFT (0U)
/*! PLL_AGMC_TG_CODE_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_SHIFT)) & PCIE_PHY_CMN_REG00E_PLL_AGMC_TG_CODE_G3_MASK)
/*! @} */
/*! @name CMN_REG00F - */
/*! @{ */
#define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_MASK (0xFFU)
#define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_SHIFT (0U)
/*! PLL_AGMC_TG_CODE_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_SHIFT)) & PCIE_PHY_CMN_REG00F_PLL_AGMC_TG_CODE_G4_MASK)
/*! @} */
/*! @name CMN_REG010 - */
/*! @{ */
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_MASK (0x7U)
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_SHIFT (0U)
/*! PLL_ANA_CPI_CTRL_COARSE_G2 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G2_MASK)
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_MASK (0x38U)
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_SHIFT (3U)
/*! PLL_ANA_CPI_CTRL_COARSE_G1 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG010_PLL_ANA_CPI_CTRL_COARSE_G1_MASK)
/*! @} */
/*! @name CMN_REG011 - */
/*! @{ */
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_MASK (0x7U)
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_SHIFT (0U)
/*! PLL_ANA_CPI_CTRL_COARSE_G4 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G4_MASK)
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_MASK (0x38U)
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_SHIFT (3U)
/*! PLL_ANA_CPI_CTRL_COARSE_G3 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG011_PLL_ANA_CPI_CTRL_COARSE_G3_MASK)
/*! @} */
/*! @name CMN_REG012 - */
/*! @{ */
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_MASK (0x7U)
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_SHIFT (0U)
/*! PLL_ANA_CPI_CTRL_FINE_G2 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G2_MASK)
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_MASK (0x38U)
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_SHIFT (3U)
/*! PLL_ANA_CPI_CTRL_FINE_G1 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG012_PLL_ANA_CPI_CTRL_FINE_G1_MASK)
/*! @} */
/*! @name CMN_REG013 - */
/*! @{ */
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_MASK (0x7U)
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_SHIFT (0U)
/*! PLL_ANA_CPI_CTRL_FINE_G4 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G4_MASK)
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_MASK (0x38U)
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_SHIFT (3U)
/*! PLL_ANA_CPI_CTRL_FINE_G3 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG013_PLL_ANA_CPI_CTRL_FINE_G3_MASK)
/*! @} */
/*! @name CMN_REG014 - */
/*! @{ */
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_SHIFT (0U)
/*! PLL_ANA_CPP_CTRL_COARSE_G2 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G2_MASK)
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_SHIFT (4U)
/*! PLL_ANA_CPP_CTRL_COARSE_G1 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG014_PLL_ANA_CPP_CTRL_COARSE_G1_MASK)
/*! @} */
/*! @name CMN_REG015 - */
/*! @{ */
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_SHIFT (0U)
/*! PLL_ANA_CPP_CTRL_COARSE_G4 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G4_MASK)
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_SHIFT (4U)
/*! PLL_ANA_CPP_CTRL_COARSE_G3 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG015_PLL_ANA_CPP_CTRL_COARSE_G3_MASK)
/*! @} */
/*! @name CMN_REG016 - */
/*! @{ */
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_SHIFT (0U)
/*! PLL_ANA_CPP_CTRL_FINE_G2 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G2_MASK)
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_SHIFT (4U)
/*! PLL_ANA_CPP_CTRL_FINE_G1 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG016_PLL_ANA_CPP_CTRL_FINE_G1_MASK)
/*! @} */
/*! @name CMN_REG017 - */
/*! @{ */
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_SHIFT (0U)
/*! PLL_ANA_CPP_CTRL_FINE_G4 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G4_MASK)
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_SHIFT (4U)
/*! PLL_ANA_CPP_CTRL_FINE_G3 - [GEN1] PLL integral path charge-pump current contorl
*/
#define PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG017_PLL_ANA_CPP_CTRL_FINE_G3_MASK)
/*! @} */
/*! @name CMN_REG018 - */
/*! @{ */
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_MASK (0x7U)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_SHIFT (0U)
/*! ANA_PLL_ANA_LC_GM_COMP_VREF_SEL - PLL GM comparator reference voltage selection
*/
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_VREF_SEL_MASK)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_MASK (0x8U)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_SHIFT (3U)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_GM_COMP_CTRL_MASK)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_MASK (0x70U)
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_SHIFT (4U)
/*! ANA_PLL_ANA_LC_CAP_OFFSET_SEL - LC VCO varactor bias voltage selection
*/
#define PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_SHIFT)) & PCIE_PHY_CMN_REG018_ANA_PLL_ANA_LC_CAP_OFFSET_SEL_MASK)
/*! @} */
/*! @name CMN_REG019 - */
/*! @{ */
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_MASK (0x7U)
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_SHIFT (0U)
/*! ANA_PLL_ANA_LC_VREG_R_SEL - LC VCO voltage regulator output control
*/
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_R_SEL_MASK)
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_MASK (0x8U)
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_SHIFT (3U)
/*! ANA_PLL_ANA_LC_VREF_BYPASS - LPF on reference voltage for PLL LC VCO bypass
*/
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREF_BYPASS_MASK)
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_MASK (0x30U)
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_SHIFT (4U)
/*! ANA_PLL_ANA_LC_VREG_I_CTRL - LC VCO Vreg current branch enable (1+1/20 or 1+ 1/33)
*/
#define PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_SHIFT)) & PCIE_PHY_CMN_REG019_ANA_PLL_ANA_LC_VREG_I_CTRL_MASK)
/*! @} */
/*! @name CMN_REG01A - */
/*! @{ */
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_MASK (0x7U)
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_SHIFT (0U)
/*! PLL_ANA_LPF_C_SEL_COARSE_G2 - [GEN2] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G2_MASK)
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_MASK (0x38U)
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_SHIFT (3U)
/*! PLL_ANA_LPF_C_SEL_COARSE_G1 - [GEN1] [Coarse Mode] PLL loop filter capacitor control
*/
#define PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG01A_PLL_ANA_LPF_C_SEL_COARSE_G1_MASK)
/*! @} */
/*! @name CMN_REG01B - */
/*! @{ */
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_MASK (0x7U)
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_SHIFT (0U)
/*! PLL_ANA_LPF_C_SEL_COARSE_G4 - [GEN4] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G4_MASK)
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_MASK (0x38U)
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_SHIFT (3U)
/*! PLL_ANA_LPF_C_SEL_COARSE_G3 - [GEN3] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG01B_PLL_ANA_LPF_C_SEL_COARSE_G3_MASK)
/*! @} */
/*! @name CMN_REG01C - */
/*! @{ */
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_MASK (0x7U)
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_SHIFT (0U)
/*! PLL_ANA_LPF_C_SEL_FINE_G2 - [GEN2] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G2_MASK)
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_MASK (0x38U)
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_SHIFT (3U)
/*! PLL_ANA_LPF_C_SEL_FINE_G1 - [GEN1] [Fine Mode] PLL loop filter capacitor control
*/
#define PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG01C_PLL_ANA_LPF_C_SEL_FINE_G1_MASK)
/*! @} */
/*! @name CMN_REG01D - */
/*! @{ */
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_MASK (0x7U)
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_SHIFT (0U)
/*! PLL_ANA_LPF_C_SEL_FINE_G4 - [GEN4] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G4_MASK)
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_MASK (0x38U)
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_SHIFT (3U)
/*! PLL_ANA_LPF_C_SEL_FINE_G3 - [GEN3] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG01D_PLL_ANA_LPF_C_SEL_FINE_G3_MASK)
/*! @} */
/*! @name CMN_REG01E - */
/*! @{ */
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_SHIFT (0U)
/*! PLL_ANA_LPF_R_SEL_COARSE_G2 - [GEN2] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_SHIFT)) & PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G2_MASK)
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_SHIFT (4U)
/*! PLL_ANA_LPF_R_SEL_COARSE_G1 - [GEN1] [Coarse Mode] PLL loop filter resistor control
*/
#define PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_SHIFT)) & PCIE_PHY_CMN_REG01E_PLL_ANA_LPF_R_SEL_COARSE_G1_MASK)
/*! @} */
/*! @name CMN_REG01F - */
/*! @{ */
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_SHIFT (0U)
/*! PLL_ANA_LPF_R_SEL_COARSE_G4 - [GEN4] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_SHIFT)) & PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G4_MASK)
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_SHIFT (4U)
/*! PLL_ANA_LPF_R_SEL_COARSE_G3 - [GEN3] [Coarse Mode]
*/
#define PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_SHIFT)) & PCIE_PHY_CMN_REG01F_PLL_ANA_LPF_R_SEL_COARSE_G3_MASK)
/*! @} */
/*! @name CMN_REG020 - */
/*! @{ */
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_SHIFT (0U)
/*! PLL_ANA_LPF_R_SEL_FINE_G2 - [GEN2] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_SHIFT)) & PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G2_MASK)
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_SHIFT (4U)
/*! PLL_ANA_LPF_R_SEL_FINE_G1 - [GEN1] [Fine Mode] PLL loop filter resistor control
*/
#define PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_SHIFT)) & PCIE_PHY_CMN_REG020_PLL_ANA_LPF_R_SEL_FINE_G1_MASK)
/*! @} */
/*! @name CMN_REG021 - */
/*! @{ */
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_SHIFT (0U)
/*! PLL_ANA_LPF_R_SEL_FINE_G4 - [GEN4] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_SHIFT)) & PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G4_MASK)
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_SHIFT (4U)
/*! PLL_ANA_LPF_R_SEL_FINE_G3 - [GEN3] [Fine Mode]
*/
#define PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_SHIFT)) & PCIE_PHY_CMN_REG021_PLL_ANA_LPF_R_SEL_FINE_G3_MASK)
/*! @} */
/*! @name CMN_REG022 - */
/*! @{ */
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_SHIFT (0U)
/*! ANA_PLL_ANA_RING_IQ_DIV_EN - I/Q divider enable for PLL ring VCO clock
*/
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_SHIFT)) & PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_IQ_DIV_EN_MASK)
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_MASK (0x1EU)
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_SHIFT (1U)
/*! ANA_PLL_ANA_RING_DCC_EN - PLL ring VCO DCC enable for each phase
*/
#define PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_SHIFT)) & PCIE_PHY_CMN_REG022_ANA_PLL_ANA_RING_DCC_EN_MASK)
/*! @} */
/*! @name CMN_REG023 - */
/*! @{ */
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_SHIFT (0U)
/*! ANA_PLL_ANA_VCI_TEST_EN - PLL VCO test mode enable
*/
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_SHIFT)) & PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_TEST_EN_MASK)
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_MASK (0xEU)
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_SHIFT (1U)
/*! ANA_PLL_ANA_VCI_SEL - PLL control voltage selection in AFC or open-loop test
*/
#define PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_SHIFT)) & PCIE_PHY_CMN_REG023_ANA_PLL_ANA_VCI_SEL_MASK)
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_MASK (0x30U)
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_SHIFT (4U)
/*! PLL_ANA_RING_PI_RATIO_CTRL_FINE - Ratio between proportional and integral path gain
*/
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_SHIFT)) & PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_FINE_MASK)
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_MASK (0xC0U)
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_SHIFT (6U)
/*! PLL_ANA_RING_PI_RATIO_CTRL_COARSE - Ratio between proportional and integral path gain
*/
#define PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_SHIFT)) & PCIE_PHY_CMN_REG023_PLL_ANA_RING_PI_RATIO_CTRL_COARSE_MASK)
/*! @} */
/*! @name CMN_REG024 - */
/*! @{ */
#define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_MASK (0x1U)
#define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_SHIFT (0U)
/*! ANA_PLL_EOM_PH_FINE_STEP - EOM phase resolution enhancement
*/
#define PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_SHIFT)) & PCIE_PHY_CMN_REG024_ANA_PLL_EOM_PH_FINE_STEP_MASK)
#define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_MASK (0xFEU)
#define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_SHIFT (1U)
/*! ANA_PLL_ATB_SEL - Select PLL ATB
*/
#define PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_SHIFT)) & PCIE_PHY_CMN_REG024_ANA_PLL_ATB_SEL_MASK)
/*! @} */
/*! @name CMN_REG025 - */
/*! @{ */
#define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_MASK (0x1U)
#define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_SHIFT (0U)
/*! ANA_PLL_FLD_FAST_BYPASS - PLL fast frequency lock detection bypass
*/
#define PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_FLD_FAST_BYPASS_MASK)
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_MASK (0x1EU)
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_SHIFT (1U)
/*! ANA_PLL_EOM_PH_SEL - EOM phase selection
*/
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_SEL_MASK)
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_MASK (0x20U)
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_SHIFT (5U)
/*! ANA_PLL_EOM_PH_FIX - Phase shift enable for EOM
*/
#define PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_SHIFT)) & PCIE_PHY_CMN_REG025_ANA_PLL_EOM_PH_FIX_MASK)
/*! @} */
/*! @name CMN_REG026 - */
/*! @{ */
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_MASK (0x1FU)
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_SHIFT (0U)
/*! ANA_PLL_FLD_LOCK_TOL_NUM - FLD lock tolerance setting
*/
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_SHIFT)) & PCIE_PHY_CMN_REG026_ANA_PLL_FLD_LOCK_TOL_NUM_MASK)
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_MASK (0xE0U)
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_SHIFT (5U)
/*! ANA_PLL_FLD_FAST_SETTLE_NUM - Number of reference clock cycle to check VCO stabilization in fast FLD
*/
#define PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_SHIFT)) & PCIE_PHY_CMN_REG026_ANA_PLL_FLD_FAST_SETTLE_NUM_MASK)
/*! @} */
/*! @name CMN_REG027 - */
/*! @{ */
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_MASK (0x1U)
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_SHIFT (0U)
/*! ANA_PLL_FLD_SLOW_BYPASS - PLL slow frequency lock detection bypass
*/
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG027_ANA_PLL_FLD_SLOW_BYPASS_MASK)
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_MASK (0x2U)
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_SHIFT (1U)
/*! ANA_PLL_FLD_NON_CONTINUOUS_MODE - Check frequency lock detection of PLL
*/
#define PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_SHIFT)) & PCIE_PHY_CMN_REG027_ANA_PLL_FLD_NON_CONTINUOUS_MODE_MASK)
/*! @} */
/*! @name CMN_REG028 - */
/*! @{ */
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_MASK (0x1U)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_SHIFT (0U)
/*! PLL_PI_EN_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G4_MASK)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_MASK (0x2U)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_SHIFT (1U)
/*! PLL_PI_EN_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G3_MASK)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_MASK (0x4U)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_SHIFT (2U)
/*! PLL_PI_EN_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G2_MASK)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_MASK (0x8U)
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_SHIFT (3U)
/*! PLL_PI_EN_G1 - [GEN1] PLL phase interpolator enable
*/
#define PCIE_PHY_CMN_REG028_PLL_PI_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG028_PLL_PI_EN_G1_MASK)
/*! @} */
/*! @name CMN_REG029 - */
/*! @{ */
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_SHIFT (0U)
/*! PLL_PI_STR_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_SHIFT)) & PCIE_PHY_CMN_REG029_PLL_PI_STR_G2_MASK)
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_SHIFT (4U)
/*! PLL_PI_STR_G1 - [GEN1] PLL phase interpolator input buffer strength control for Gen3 and Gen4 ( for 8GHz VCO )
*/
#define PCIE_PHY_CMN_REG029_PLL_PI_STR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_SHIFT)) & PCIE_PHY_CMN_REG029_PLL_PI_STR_G1_MASK)
/*! @} */
/*! @name CMN_REG02A - */
/*! @{ */
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_SHIFT (0U)
/*! PLL_PI_STR_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_SHIFT)) & PCIE_PHY_CMN_REG02A_PLL_PI_STR_G4_MASK)
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_SHIFT (4U)
/*! PLL_PI_STR_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_SHIFT)) & PCIE_PHY_CMN_REG02A_PLL_PI_STR_G3_MASK)
/*! @} */
/*! @name CMN_REG02B - */
/*! @{ */
#define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_MASK (0x1U)
#define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_SHIFT (0U)
/*! PLL_PMS_PDIV_RSTN - PLL pre-divider reset
*/
#define PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_PLL_PMS_PDIV_RSTN_MASK)
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_SHIFT (1U)
/*! OVRD_PLL_PMS_PDIV_RSTN - Override enable for pll_pms_pdiv_rstn
*/
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_PDIV_RSTN_MASK)
#define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_MASK (0x4U)
#define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_SHIFT (2U)
/*! PLL_PMS_MDIV_RSTN - PLL main divider reset
*/
#define PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_PLL_PMS_MDIV_RSTN_MASK)
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_MASK (0x8U)
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_SHIFT (3U)
/*! OVRD_PLL_PMS_MDIV_RSTN - Override enable for pll_pms_mdiv_rstn
*/
#define PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG02B_OVRD_PLL_PMS_MDIV_RSTN_MASK)
/*! @} */
/*! @name CMN_REG02C - */
/*! @{ */
#define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_MASK (0xFFU)
#define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_SHIFT (0U)
/*! PLL_PMS_MDIV_AFC_G1 - [GEN1] PLL AFC target value (fVCO/fREF) setting
*/
#define PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_SHIFT)) & PCIE_PHY_CMN_REG02C_PLL_PMS_MDIV_AFC_G1_MASK)
/*! @} */
/*! @name CMN_REG02D - */
/*! @{ */
#define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_MASK (0xFFU)
#define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_SHIFT (0U)
/*! PLL_PMS_MDIV_AFC_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_SHIFT)) & PCIE_PHY_CMN_REG02D_PLL_PMS_MDIV_AFC_G2_MASK)
/*! @} */
/*! @name CMN_REG02E - */
/*! @{ */
#define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_MASK (0xFFU)
#define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_SHIFT (0U)
/*! PLL_PMS_MDIV_AFC_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_SHIFT)) & PCIE_PHY_CMN_REG02E_PLL_PMS_MDIV_AFC_G3_MASK)
/*! @} */
/*! @name CMN_REG02F - */
/*! @{ */
#define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_MASK (0xFFU)
#define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_SHIFT (0U)
/*! PLL_PMS_MDIV_AFC_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_SHIFT)) & PCIE_PHY_CMN_REG02F_PLL_PMS_MDIV_AFC_G4_MASK)
/*! @} */
/*! @name CMN_REG030 - */
/*! @{ */
#define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_MASK (0xFFU)
#define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_SHIFT (0U)
/*! PLL_PMS_MDIV_G1 - [GEN1] PLL main divider setting
*/
#define PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_SHIFT)) & PCIE_PHY_CMN_REG030_PLL_PMS_MDIV_G1_MASK)
/*! @} */
/*! @name CMN_REG031 - */
/*! @{ */
#define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_MASK (0xFFU)
#define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_SHIFT (0U)
/*! PLL_PMS_MDIV_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_SHIFT)) & PCIE_PHY_CMN_REG031_PLL_PMS_MDIV_G2_MASK)
/*! @} */
/*! @name CMN_REG032 - */
/*! @{ */
#define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_MASK (0xFFU)
#define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_SHIFT (0U)
/*! PLL_PMS_MDIV_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_SHIFT)) & PCIE_PHY_CMN_REG032_PLL_PMS_MDIV_G3_MASK)
/*! @} */
/*! @name CMN_REG033 - */
/*! @{ */
#define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_MASK (0xFFU)
#define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_SHIFT (0U)
/*! PLL_PMS_MDIV_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_SHIFT)) & PCIE_PHY_CMN_REG033_PLL_PMS_MDIV_G4_MASK)
/*! @} */
/*! @name CMN_REG034 - */
/*! @{ */
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_MASK (0xFU)
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_SHIFT (0U)
/*! ANA_PLL_PMS_PDIV - PLL pre-divider setting
*/
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_SHIFT)) & PCIE_PHY_CMN_REG034_ANA_PLL_PMS_PDIV_MASK)
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_MASK (0x10U)
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_SHIFT (4U)
/*! ANA_PLL_PMS_MDIV_X2_EN - PLL main divider extra X2 enable
*/
#define PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_SHIFT)) & PCIE_PHY_CMN_REG034_ANA_PLL_PMS_MDIV_X2_EN_MASK)
/*! @} */
/*! @name CMN_REG035 - */
/*! @{ */
#define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_MASK (0xFU)
#define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_SHIFT (0U)
/*! ANA_PLL_PMS_REFDIV - PLL reference clock divider setting
*/
#define PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_SHIFT)) & PCIE_PHY_CMN_REG035_ANA_PLL_PMS_REFDIV_MASK)
/*! @} */
/*! @name CMN_REG036 - */
/*! @{ */
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_SHIFT (0U)
/*! PLL_PMS_SDIV_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_SHIFT)) & PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G2_MASK)
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_SHIFT (4U)
/*! PLL_PMS_SDIV_G1 - [GEN1] PLL post divider setting
*/
#define PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_SHIFT)) & PCIE_PHY_CMN_REG036_PLL_PMS_SDIV_G1_MASK)
/*! @} */
/*! @name CMN_REG037 - */
/*! @{ */
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_SHIFT (0U)
/*! PLL_PMS_SDIV_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_SHIFT)) & PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G4_MASK)
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_SHIFT (4U)
/*! PLL_PMS_SDIV_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_SHIFT)) & PCIE_PHY_CMN_REG037_PLL_PMS_SDIV_G3_MASK)
/*! @} */
/*! @name CMN_REG038 - */
/*! @{ */
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_SHIFT (0U)
/*! ANA_PLL_REF_CHOPPER_CLK_EN - Chopper clk enable
*/
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_EN_MASK)
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_MASK (0x6U)
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_SHIFT (1U)
/*! ANA_PLL_REF_CHOPPER_CLK_DIV_SEL - Chopper clk divider value
*/
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_CHOPPER_CLK_DIV_SEL_MASK)
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_MASK (0x18U)
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_SHIFT (3U)
/*! ANA_PLL_REF_BYPASS_CLK_SEL - PLL Bypass clock selection
*/
#define PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG038_ANA_PLL_REF_BYPASS_CLK_SEL_MASK)
#define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK (0x20U)
#define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT (5U)
/*! PLL_REF_CHOPPER_CLK_DIV_RSTN - Chopper clk divider reset
*/
#define PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG038_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK)
#define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK (0x40U)
#define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT (6U)
/*! OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN - Override enable for pll_ref_chopper_clk_div_rstn
*/
#define PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_SHIFT)) & PCIE_PHY_CMN_REG038_OVRD_PLL_REF_CHOPPER_CLK_DIV_RSTN_MASK)
/*! @} */
/*! @name CMN_REG039 - */
/*! @{ */
#define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_MASK (0x1U)
#define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_SHIFT (0U)
#define PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_ANA_PLL_REF_DIG_CLK_SEL_MASK)
#define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_MASK (0x6U)
#define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_SHIFT (1U)
/*! PLL_REF_CLK_SEL - PLL reference clock selection
*/
#define PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_PLL_REF_CLK_SEL_MASK)
#define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_MASK (0x8U)
#define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_SHIFT (3U)
/*! OVRD_PLL_REF_CLK_SEL - Override enable for pll_ref_clk_sel
*/
#define PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG039_OVRD_PLL_REF_CLK_SEL_MASK)
/*! @} */
/*! @name CMN_REG03A - */
/*! @{ */
#define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_MASK (0x1U)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_SHIFT (0U)
/*! PLL_SDM_RSTN - PLL SDM reset
*/
#define PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_RSTN_MASK)
#define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_SHIFT (1U)
/*! OVRD_PLL_SDM_RSTN - Override enable for pll_sdm_rstn
*/
#define PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03A_OVRD_PLL_SDM_RSTN_MASK)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_MASK (0x4U)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_SHIFT (2U)
/*! PLL_SDM_EN_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G4_MASK)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_MASK (0x8U)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_SHIFT (3U)
/*! PLL_SDM_EN_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G3_MASK)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_MASK (0x10U)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_SHIFT (4U)
/*! PLL_SDM_EN_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G2_MASK)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_MASK (0x20U)
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_SHIFT (5U)
/*! PLL_SDM_EN_G1 - [GEN1] PLL SDM enable
*/
#define PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG03A_PLL_SDM_EN_G1_MASK)
/*! @} */
/*! @name CMN_REG03B - */
/*! @{ */
#define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_MASK (0x1U)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_SHIFT (0U)
/*! PLL_SDC_RSTN - PLL SDM clock generation (SDC) reset
*/
#define PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_RSTN_MASK)
#define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_SHIFT (1U)
/*! OVRD_PLL_SDC_RSTN - Override enable for pll_sdc_rstn
*/
#define PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG03B_OVRD_PLL_SDC_RSTN_MASK)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_MASK (0x4U)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_SHIFT (2U)
/*! PLL_SDC_FRACTIONAL_EN_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G4_MASK)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_MASK (0x8U)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_SHIFT (3U)
/*! PLL_SDC_FRACTIONAL_EN_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G3_MASK)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_MASK (0x10U)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_SHIFT (4U)
/*! PLL_SDC_FRACTIONAL_EN_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G2_MASK)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_MASK (0x20U)
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_SHIFT (5U)
/*! PLL_SDC_FRACTIONAL_EN_G1 - [GEN1] Fractional clock divide in SDM clock generation
*/
#define PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_SHIFT)) & PCIE_PHY_CMN_REG03B_PLL_SDC_FRACTIONAL_EN_G1_MASK)
/*! @} */
/*! @name CMN_REG03C - */
/*! @{ */
#define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_MASK (0xFFU)
#define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_SHIFT (0U)
/*! PLL_SDM_DENOMINATOR_G1 - [GEN1] Denominator of SDM (Max. 255)
*/
#define PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG03C_PLL_SDM_DENOMINATOR_G1_MASK)
/*! @} */
/*! @name CMN_REG03D - */
/*! @{ */
#define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_MASK (0xFFU)
#define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_SHIFT (0U)
/*! PLL_SDM_DENOMINATOR_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG03D_PLL_SDM_DENOMINATOR_G2_MASK)
/*! @} */
/*! @name CMN_REG03E - */
/*! @{ */
#define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_MASK (0xFFU)
#define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_SHIFT (0U)
/*! PLL_SDM_DENOMINATOR_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG03E_PLL_SDM_DENOMINATOR_G3_MASK)
/*! @} */
/*! @name CMN_REG03F - */
/*! @{ */
#define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_MASK (0xFFU)
#define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_SHIFT (0U)
/*! PLL_SDM_DENOMINATOR_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG03F_PLL_SDM_DENOMINATOR_G4_MASK)
/*! @} */
/*! @name CMN_REG040 - */
/*! @{ */
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_MASK (0x1U)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_SHIFT (0U)
/*! PLL_SDM_NUMERATOR_SIGN_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G4_MASK)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_MASK (0x2U)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_SHIFT (1U)
/*! PLL_SDM_NUMERATOR_SIGN_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G3_MASK)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_MASK (0x4U)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_SHIFT (2U)
/*! PLL_SDM_NUMERATOR_SIGN_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G2_MASK)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_MASK (0x8U)
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_SHIFT (3U)
/*! PLL_SDM_NUMERATOR_SIGN_G1 - [GEN1] Sign of SDM numerator
*/
#define PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_SHIFT)) & PCIE_PHY_CMN_REG040_PLL_SDM_NUMERATOR_SIGN_G1_MASK)
/*! @} */
/*! @name CMN_REG041 - */
/*! @{ */
#define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_MASK (0xFFU)
#define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_SHIFT (0U)
/*! PLL_SDM_NUMERATOR_G1 - [GEN1] Numerator of SDM with i_pll_sdm_k_sign (-255~255)
*/
#define PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG041_PLL_SDM_NUMERATOR_G1_MASK)
/*! @} */
/*! @name CMN_REG042 - */
/*! @{ */
#define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_MASK (0xFFU)
#define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_SHIFT (0U)
/*! PLL_SDM_NUMERATOR_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG042_PLL_SDM_NUMERATOR_G2_MASK)
/*! @} */
/*! @name CMN_REG043 - */
/*! @{ */
#define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_MASK (0xFFU)
#define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_SHIFT (0U)
/*! PLL_SDM_NUMERATOR_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG043_PLL_SDM_NUMERATOR_G3_MASK)
/*! @} */
/*! @name CMN_REG044 - */
/*! @{ */
#define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_MASK (0xFFU)
#define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_SHIFT (0U)
/*! PLL_SDM_NUMERATOR_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG044_PLL_SDM_NUMERATOR_G4_MASK)
/*! @} */
/*! @name CMN_REG045 - */
/*! @{ */
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_MASK (0x1U)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_SHIFT (0U)
/*! PLL_SDM_PH_NUM_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G4_MASK)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_MASK (0x2U)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_SHIFT (1U)
/*! PLL_SDM_PH_NUM_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G3_MASK)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_MASK (0x4U)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_SHIFT (2U)
/*! PLL_SDM_PH_NUM_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G2_MASK)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_MASK (0x8U)
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_SHIFT (3U)
/*! PLL_SDM_PH_NUM_SEL_G1 - [GEN1] PLL PI input clock phase number
*/
#define PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_SHIFT)) & PCIE_PHY_CMN_REG045_PLL_SDM_PH_NUM_SEL_G1_MASK)
/*! @} */
/*! @name CMN_REG046 - */
/*! @{ */
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_MASK (0x3U)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_SHIFT (0U)
/*! PLL_SDM_PI_STEP_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G4_MASK)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_MASK (0xCU)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_SHIFT (2U)
/*! PLL_SDM_PI_STEP_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G3_MASK)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_MASK (0x30U)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_SHIFT (4U)
/*! PLL_SDM_PI_STEP_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G2_MASK)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_MASK (0xC0U)
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_SHIFT (6U)
/*! PLL_SDM_PI_STEP_G1 - [GEN1] PLL phase interpolstor step
*/
#define PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_SHIFT)) & PCIE_PHY_CMN_REG046_PLL_SDM_PI_STEP_G1_MASK)
/*! @} */
/*! @name CMN_REG047 - */
/*! @{ */
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_MASK (0x7U)
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_SHIFT (0U)
/*! PLL_SDC_N_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_SHIFT)) & PCIE_PHY_CMN_REG047_PLL_SDC_N_G2_MASK)
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_MASK (0x38U)
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_SHIFT (3U)
/*! PLL_SDC_N_G1 - [GEN1] PLL SDC divide-ratio selection
*/
#define PCIE_PHY_CMN_REG047_PLL_SDC_N_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_SHIFT)) & PCIE_PHY_CMN_REG047_PLL_SDC_N_G1_MASK)
/*! @} */
/*! @name CMN_REG048 - */
/*! @{ */
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_MASK (0x7U)
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_SHIFT (0U)
/*! PLL_SDC_N_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_SHIFT)) & PCIE_PHY_CMN_REG048_PLL_SDC_N_G4_MASK)
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_MASK (0x38U)
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_SHIFT (3U)
/*! PLL_SDC_N_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG048_PLL_SDC_N_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_SHIFT)) & PCIE_PHY_CMN_REG048_PLL_SDC_N_G3_MASK)
/*! @} */
/*! @name CMN_REG049 - */
/*! @{ */
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_MASK (0x1U)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_SHIFT (0U)
/*! PLL_SDC_N2_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G4_MASK)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_MASK (0x2U)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_SHIFT (1U)
/*! PLL_SDC_N2_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G3_MASK)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_MASK (0x4U)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_SHIFT (2U)
/*! PLL_SDC_N2_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G2_MASK)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_MASK (0x8U)
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_SHIFT (3U)
/*! PLL_SDC_N2_G1 - [GEN1] PLL SDC divide-ratio selection
*/
#define PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_SHIFT)) & PCIE_PHY_CMN_REG049_PLL_SDC_N2_G1_MASK)
/*! @} */
/*! @name CMN_REG04A - */
/*! @{ */
#define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_SHIFT (0U)
/*! PLL_SDC_NUMERATOR_G1 - [GEN1] Numerator of SDC (Max 65)
*/
#define PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG04A_PLL_SDC_NUMERATOR_G1_MASK)
/*! @} */
/*! @name CMN_REG04B - */
/*! @{ */
#define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_SHIFT (0U)
/*! PLL_SDC_NUMERATOR_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG04B_PLL_SDC_NUMERATOR_G2_MASK)
/*! @} */
/*! @name CMN_REG04C - */
/*! @{ */
#define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_SHIFT (0U)
/*! PLL_SDC_NUMERATOR_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG04C_PLL_SDC_NUMERATOR_G3_MASK)
/*! @} */
/*! @name CMN_REG04D - */
/*! @{ */
#define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_SHIFT (0U)
/*! PLL_SDC_NUMERATOR_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG04D_PLL_SDC_NUMERATOR_G4_MASK)
/*! @} */
/*! @name CMN_REG04E - */
/*! @{ */
#define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_SHIFT (0U)
/*! PLL_SDC_DENOMINATOR_G1 - [GEN1] Denominator of SDC (Max 65)
*/
#define PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_SHIFT)) & PCIE_PHY_CMN_REG04E_PLL_SDC_DENOMINATOR_G1_MASK)
/*! @} */
/*! @name CMN_REG04F - */
/*! @{ */
#define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_MASK (0x3FU)
#define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_SHIFT (0U)
/*! PLL_SDC_DENOMINATOR_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_SHIFT)) & PCIE_PHY_CMN_REG04F_PLL_SDC_DENOMINATOR_G2_MASK)
/*! @} */
/*! @name CMN_REG050 - */
/*! @{ */
#define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_MASK (0x3FU)
#define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_SHIFT (0U)
/*! PLL_SDC_DENOMINATOR_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_SHIFT)) & PCIE_PHY_CMN_REG050_PLL_SDC_DENOMINATOR_G3_MASK)
/*! @} */
/*! @name CMN_REG051 - */
/*! @{ */
#define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_MASK (0x1U)
#define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_SHIFT (0U)
/*! ANA_PLL_SDC_MC_VALUE_SEL - PLL SDC value force
*/
#define PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_SHIFT)) & PCIE_PHY_CMN_REG051_ANA_PLL_SDC_MC_VALUE_SEL_MASK)
#define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_MASK (0x7EU)
#define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_SHIFT (1U)
/*! PLL_SDC_DENOMINATOR_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_SHIFT)) & PCIE_PHY_CMN_REG051_PLL_SDC_DENOMINATOR_G4_MASK)
/*! @} */
/*! @name CMN_REG052 - */
/*! @{ */
#define PCIE_PHY_CMN_REG052_PLL_SSC_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG052_PLL_SSC_EN_SHIFT (0U)
/*! PLL_SSC_EN - PLL SSC enable
*/
#define PCIE_PHY_CMN_REG052_PLL_SSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG052_PLL_SSC_EN_SHIFT)) & PCIE_PHY_CMN_REG052_PLL_SSC_EN_MASK)
#define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_MASK (0x2U)
#define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_SHIFT (1U)
/*! OVRD_PLL_SSC_EN - Override enable for pll_ssc_en
*/
#define PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_SHIFT)) & PCIE_PHY_CMN_REG052_OVRD_PLL_SSC_EN_MASK)
/*! @} */
/*! @name CMN_REG053 - */
/*! @{ */
#define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_MASK (0x3FU)
#define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_SHIFT (0U)
/*! PLL_SSC_FM_DEVIATION_G1 - [GEN1] PLL SSC modulation deviation
*/
#define PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_SHIFT)) & PCIE_PHY_CMN_REG053_PLL_SSC_FM_DEVIATION_G1_MASK)
/*! @} */
/*! @name CMN_REG054 - */
/*! @{ */
#define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_MASK (0x3FU)
#define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_SHIFT (0U)
/*! PLL_SSC_FM_DEVIATION_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_SHIFT)) & PCIE_PHY_CMN_REG054_PLL_SSC_FM_DEVIATION_G2_MASK)
/*! @} */
/*! @name CMN_REG055 - */
/*! @{ */
#define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_MASK (0x3FU)
#define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_SHIFT (0U)
/*! PLL_SSC_FM_DEVIATION_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_SHIFT)) & PCIE_PHY_CMN_REG055_PLL_SSC_FM_DEVIATION_G3_MASK)
/*! @} */
/*! @name CMN_REG056 - */
/*! @{ */
#define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_MASK (0x3FU)
#define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_SHIFT (0U)
/*! PLL_SSC_FM_DEVIATION_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_SHIFT)) & PCIE_PHY_CMN_REG056_PLL_SSC_FM_DEVIATION_G4_MASK)
/*! @} */
/*! @name CMN_REG057 - */
/*! @{ */
#define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_MASK (0x1FU)
#define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_SHIFT (0U)
/*! PLL_SSC_FM_FREQ_G1 - [GEN1] PLL SSC modulation frequency
*/
#define PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_SHIFT)) & PCIE_PHY_CMN_REG057_PLL_SSC_FM_FREQ_G1_MASK)
/*! @} */
/*! @name CMN_REG058 - */
/*! @{ */
#define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_MASK (0x1FU)
#define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_SHIFT (0U)
/*! PLL_SSC_FM_FREQ_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_SHIFT)) & PCIE_PHY_CMN_REG058_PLL_SSC_FM_FREQ_G2_MASK)
/*! @} */
/*! @name CMN_REG059 - */
/*! @{ */
#define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_MASK (0x1FU)
#define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_SHIFT (0U)
/*! PLL_SSC_FM_FREQ_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_SHIFT)) & PCIE_PHY_CMN_REG059_PLL_SSC_FM_FREQ_G3_MASK)
/*! @} */
/*! @name CMN_REG05A - */
/*! @{ */
#define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_MASK (0x1FU)
#define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_SHIFT (0U)
/*! PLL_SSC_FM_FREQ_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_SHIFT)) & PCIE_PHY_CMN_REG05A_PLL_SSC_FM_FREQ_G4_MASK)
/*! @} */
/*! @name CMN_REG05B - */
/*! @{ */
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_MASK (0x3U)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_SHIFT (0U)
/*! PLL_SSC_PROFILE_OPT_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G4_MASK)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_MASK (0xCU)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_SHIFT (2U)
/*! PLL_SSC_PROFILE_OPT_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G3_MASK)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_MASK (0x30U)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_SHIFT (4U)
/*! PLL_SSC_PROFILE_OPT_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G2_MASK)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_MASK (0xC0U)
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_SHIFT (6U)
/*! PLL_SSC_PROFILE_OPT_G1 - [GEN1] PLL SSC modulation profile shape control
*/
#define PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_SHIFT)) & PCIE_PHY_CMN_REG05B_PLL_SSC_PROFILE_OPT_G1_MASK)
/*! @} */
/*! @name CMN_REG05C - */
/*! @{ */
#define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_MASK (0x1U)
#define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_SHIFT (0U)
/*! PLL_CD_TX_SER_RSTN - TX_SER resetn
*/
#define PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_SHIFT)) & PCIE_PHY_CMN_REG05C_PLL_CD_TX_SER_RSTN_MASK)
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_SHIFT (1U)
/*! OVRD_PLL_CD_TX_SER_RSTN - Override enable for pll_cd_tx_ser_rstn
*/
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_SHIFT)) & PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_TX_SER_RSTN_MASK)
#define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_MASK (0x4U)
#define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_SHIFT (2U)
/*! PLL_CD_CLK_EN - CD enable
*/
#define PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG05C_PLL_CD_CLK_EN_MASK)
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_SHIFT (3U)
/*! OVRD_PLL_CD_CLK_EN - Override enable for pll_cd_clk_en
*/
#define PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_SHIFT)) & PCIE_PHY_CMN_REG05C_OVRD_PLL_CD_CLK_EN_MASK)
#define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_MASK (0xF0U)
#define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_SHIFT (4U)
/*! ANA_PLL_SSC_CLK_DIV_SEL - PLL SSC clock divide ratio
*/
#define PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_SHIFT)) & PCIE_PHY_CMN_REG05C_ANA_PLL_SSC_CLK_DIV_SEL_MASK)
/*! @} */
/*! @name CMN_REG05D - */
/*! @{ */
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_SHIFT (0U)
/*! ANA_PLL_CD_HSCLK_EAST_EN - CD driver pmos strength control
*/
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_EAST_EN_MASK)
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_MASK (0x2U)
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_SHIFT (1U)
/*! ANA_PLL_CD_HSCLK_WEST_EN - CD driver nmos strength control
*/
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_WEST_EN_MASK)
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_MASK (0x4U)
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_SHIFT (2U)
/*! ANA_PLL_CD_HSCLK_INV - CD output clock polarity inversion
*/
#define PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_SHIFT)) & PCIE_PHY_CMN_REG05D_ANA_PLL_CD_HSCLK_INV_MASK)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_MASK (0x8U)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_SHIFT (3U)
/*! PLL_CD_TX_SER_RATE_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G4_MASK)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_MASK (0x10U)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_SHIFT (4U)
/*! PLL_CD_TX_SER_RATE_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G3_MASK)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_MASK (0x20U)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_SHIFT (5U)
/*! PLL_CD_TX_SER_RATE_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G2_MASK)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_MASK (0x40U)
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_SHIFT (6U)
/*! PLL_CD_TX_SER_RATE_SEL_G1 - [GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit)
*/
#define PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_SHIFT)) & PCIE_PHY_CMN_REG05D_PLL_CD_TX_SER_RATE_SEL_G1_MASK)
/*! @} */
/*! @name CMN_REG05E - */
/*! @{ */
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_MASK (0x3U)
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_SHIFT (0U)
/*! ANA_PLL_MISC_CLK_SEL - PLL low-frequency clock output source selection
*/
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SEL_MASK)
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_MASK (0x4U)
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_SHIFT (2U)
/*! ANA_PLL_MISC_CLK_SYNC_EN - PLL miscellaneous clock synchronization enable
*/
#define PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_ANA_PLL_MISC_CLK_SYNC_EN_MASK)
#define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_SHIFT (3U)
/*! PLL_BEACON_LFPS_OUT_EN - TX beacon clock enable
*/
#define PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_PLL_BEACON_LFPS_OUT_EN_MASK)
#define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_MASK (0x10U)
#define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_SHIFT (4U)
/*! OVRD_PLL_BEACON_LFPS_OUT_EN - Override enable for pll_beacon_lfps_out_en
*/
#define PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_CMN_REG05E_OVRD_PLL_BEACON_LFPS_OUT_EN_MASK)
/*! @} */
/*! @name CMN_REG05F - */
/*! @{ */
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_MASK (0xFU)
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_SHIFT (0U)
/*! PLL_MISC_CLK_DIV_G2 - [GEN2]
*/
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_SHIFT)) & PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G2_MASK)
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_MASK (0xF0U)
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_SHIFT (4U)
/*! PLL_MISC_CLK_DIV_G1 - [GEN1] PLL miscellaneous clock divider ratio
*/
#define PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_SHIFT)) & PCIE_PHY_CMN_REG05F_PLL_MISC_CLK_DIV_G1_MASK)
/*! @} */
/*! @name CMN_REG060 - */
/*! @{ */
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_MASK (0xFU)
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_SHIFT (0U)
/*! PLL_MISC_CLK_DIV_G4 - [GEN4]
*/
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_SHIFT)) & PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G4_MASK)
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_MASK (0xF0U)
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_SHIFT (4U)
/*! PLL_MISC_CLK_DIV_G3 - [GEN3]
*/
#define PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_SHIFT)) & PCIE_PHY_CMN_REG060_PLL_MISC_CLK_DIV_G3_MASK)
/*! @} */
/*! @name CMN_REG061 - */
/*! @{ */
#define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_MASK (0x1U)
#define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_SHIFT (0U)
/*! ANA_PLL_CLK_OUT_TO_EXT_IO_EN - PLL low-frequency clock output to external I/O enable
*/
#define PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_SHIFT)) & PCIE_PHY_CMN_REG061_ANA_PLL_CLK_OUT_TO_EXT_IO_EN_MASK)
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_MASK (0x2U)
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_SHIFT (1U)
/*! PLL_MISC_OSC_RSTN - PLL miscellaneous clock oscillator reset
*/
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG061_PLL_MISC_OSC_RSTN_MASK)
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_MASK (0x4U)
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_SHIFT (2U)
/*! OVRD_PLL_MISC_OSC_RSTN - Override enable for pll_misc_osc_rstn
*/
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_SHIFT)) & PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_RSTN_MASK)
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_MASK (0x78U)
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_SHIFT (3U)
/*! PLL_MISC_OSC_FREQ_SEL - PLL miscellaneous clock frequency selection
*/
#define PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_SHIFT)) & PCIE_PHY_CMN_REG061_PLL_MISC_OSC_FREQ_SEL_MASK)
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_MASK (0x80U)
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_SHIFT (7U)
/*! OVRD_PLL_MISC_OSC_FREQ_SEL - Override enable for pll_misc_osc_freq_sel
*/
#define PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_SHIFT)) & PCIE_PHY_CMN_REG061_OVRD_PLL_MISC_OSC_FREQ_SEL_MASK)
/*! @} */
/*! @name CMN_REG062 - */
/*! @{ */
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_MASK (0x3U)
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_SHIFT (0U)
/*! ANA_PLL_REF_CLK_MON_SEL - PLL reference clock selection for monitor
*/
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_SEL_MASK)
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_MASK (0x4U)
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_SHIFT (2U)
/*! ANA_PLL_REF_CLK_MON_EN - PLL reference clock monitor enable
*/
#define PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_REF_CLK_MON_EN_MASK)
#define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_MASK (0x8U)
#define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_SHIFT (3U)
/*! ANA_PLL_CLK_OUT_TO_EXT_IO_SEL - PLL low-frequency clock output to external I/O source selection
*/
#define PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_SHIFT)) & PCIE_PHY_CMN_REG062_ANA_PLL_CLK_OUT_TO_EXT_IO_SEL_MASK)
/*! @} */
/*! @name CMN_REG063 - */
/*! @{ */
#define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_MASK (0x3FU)
#define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_SHIFT (0U)
/*! ANA_PLL_RESERVED - PLL Reserved pins
*/
#define PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_SHIFT)) & PCIE_PHY_CMN_REG063_ANA_PLL_RESERVED_MASK)
#define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_MASK (0xC0U)
#define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_SHIFT (6U)
/*! AUX_PLL_REFCLK_SEL - 0X: AUX_IN (PLL clock)
*/
#define PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_SHIFT)) & PCIE_PHY_CMN_REG063_AUX_PLL_REFCLK_SEL_MASK)
/*! @} */
/*! @name CMN_REG064 - */
/*! @{ */
#define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_MASK (0x7U)
#define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_SHIFT (0U)
/*! ANA_AUX_TX_TERM - TX termination resistor control. Default code : 010, 50.7Ω
*/
#define PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_TX_TERM_MASK)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_MASK (0x8U)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_SHIFT (3U)
/*! ANA_AUX_RX_TERM_GND_EN - External reference clock I/O termination to ground
*/
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_TERM_GND_EN_MASK)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_MASK (0x10U)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_SHIFT (4U)
/*! ANA_AUX_RX_CAP_BYPASS - External reference clock I/O AC-coupling capacitor bypass enable
*/
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_CAP_BYPASS_MASK)
#define PCIE_PHY_CMN_REG064_AUX_EN_MASK (0x20U)
#define PCIE_PHY_CMN_REG064_AUX_EN_SHIFT (5U)
/*! AUX_EN - AUX Enable
*/
#define PCIE_PHY_CMN_REG064_AUX_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_AUX_EN_SHIFT)) & PCIE_PHY_CMN_REG064_AUX_EN_MASK)
#define PCIE_PHY_CMN_REG064_OVRD_AUX_EN_MASK (0x40U)
#define PCIE_PHY_CMN_REG064_OVRD_AUX_EN_SHIFT (6U)
/*! OVRD_AUX_EN - Override enable for aux_en
*/
#define PCIE_PHY_CMN_REG064_OVRD_AUX_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_OVRD_AUX_EN_SHIFT)) & PCIE_PHY_CMN_REG064_OVRD_AUX_EN_MASK)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_MASK (0x80U)
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_SHIFT (7U)
/*! ANA_AUX_RX_TX_SEL - Select mode (TX or RX)
*/
#define PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_SHIFT)) & PCIE_PHY_CMN_REG064_ANA_AUX_RX_TX_SEL_MASK)
/*! @} */
/*! @name CMN_REG065 - */
/*! @{ */
#define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_MASK (0xFU)
#define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_SHIFT (0U)
/*! ANA_AUX_TX_LVL_CTRL - TX Amplitude resistor control. Default code : 101, 375mVpp
*/
#define PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_SHIFT)) & PCIE_PHY_CMN_REG065_ANA_AUX_TX_LVL_CTRL_MASK)
#define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_MASK (0xF0U)
#define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_SHIFT (4U)
/*! ANA_AUX_RX_TERM - RX termination resistor control. Default code : 1001, 99.6Ω
*/
#define PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_SHIFT)) & PCIE_PHY_CMN_REG065_ANA_AUX_RX_TERM_MASK)
/*! @} */
/*! @name CMN_REG066 - */
/*! @{ */
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_MASK (0x7U)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_SHIFT (0U)
/*! ANA_AUX_RX_HYS_CTRL - Hysteresis for RX noise blocking control.
*/
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_HYS_CTRL_MASK)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_MASK (0x18U)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_SHIFT (3U)
/*! ANA_AUX_RX_VCM_FINE_CTRL - VCM of RX control. 171mV ~ 680mV at typical condition.
*/
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_FINE_CTRL_MASK)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_MASK (0x60U)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_SHIFT (5U)
/*! ANA_AUX_RX_VCM_COARSE_CTRL - VCM of RX control. 171mV ~ 680mV at typical condition.
*/
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_COARSE_CTRL_MASK)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_MASK (0x80U)
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_SHIFT (7U)
/*! ANA_AUX_RX_VCM_SEL - Input common mode voltage control.
*/
#define PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_SHIFT)) & PCIE_PHY_CMN_REG066_ANA_AUX_RX_VCM_SEL_MASK)
/*! @} */
/*! @name CMN_REG067 - */
/*! @{ */
#define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_MASK (0xFFU)
#define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_SHIFT (0U)
/*! ANA_AUX_RESERVED - Reserved port
*/
#define PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_SHIFT)) & PCIE_PHY_CMN_REG067_ANA_AUX_RESERVED_MASK)
/*! @} */
/*! @name CMN_REG068 - */
/*! @{ */
#define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_MASK (0x1U)
#define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_SHIFT (0U)
/*! PLL_LOCK_DONE - PLL lock done overide value
*/
#define PCIE_PHY_CMN_REG068_PLL_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_PLL_LOCK_DONE_MASK)
#define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_MASK (0x2U)
#define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_SHIFT (1U)
/*! OVRD_PLL_LOCK_DONE - Override enable for pll_lock_done
*/
#define PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_PLL_LOCK_DONE_MASK)
#define PCIE_PHY_CMN_REG068_PLL_AFC_DONE_MASK (0x4U)
#define PCIE_PHY_CMN_REG068_PLL_AFC_DONE_SHIFT (2U)
/*! PLL_AFC_DONE - PLL AFC done overide value
*/
#define PCIE_PHY_CMN_REG068_PLL_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_PLL_AFC_DONE_MASK)
#define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_MASK (0x8U)
#define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_SHIFT (3U)
/*! OVRD_PLL_AFC_DONE - Override enable for pll_afc_done
*/
#define PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_PLL_AFC_DONE_MASK)
#define PCIE_PHY_CMN_REG068_BGR_SET_DONE_MASK (0x10U)
#define PCIE_PHY_CMN_REG068_BGR_SET_DONE_SHIFT (4U)
/*! BGR_SET_DONE - BGR set done
*/
#define PCIE_PHY_CMN_REG068_BGR_SET_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_BGR_SET_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_BGR_SET_DONE_MASK)
#define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_MASK (0x20U)
#define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_SHIFT (5U)
/*! OVRD_BGR_SET_DONE - Override enable for bgr_set_done
*/
#define PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_SHIFT)) & PCIE_PHY_CMN_REG068_OVRD_BGR_SET_DONE_MASK)
/*! @} */
/*! @name CMN_REG069 - */
/*! @{ */
#define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_MASK (0x1U)
#define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_SHIFT (0U)
#define PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_SHIFT)) & PCIE_PHY_CMN_REG069_PLL_FINE_TUNE_START_MASK)
#define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_MASK (0x2U)
#define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_SHIFT (1U)
/*! OVRD_PLL_FINE_TUNE_START - Override enable for pll_fine_tune_start
*/
#define PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_PLL_FINE_TUNE_START_MASK)
#define PCIE_PHY_CMN_REG069_HIGH_SPEED_MASK (0x4U)
#define PCIE_PHY_CMN_REG069_HIGH_SPEED_SHIFT (2U)
/*! HIGH_SPEED - HIGH SPEED indicator by operating LC VCO
*/
#define PCIE_PHY_CMN_REG069_HIGH_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_HIGH_SPEED_SHIFT)) & PCIE_PHY_CMN_REG069_HIGH_SPEED_MASK)
#define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_MASK (0x8U)
#define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_SHIFT (3U)
/*! OVRD_HIGH_SPEED - Override enable for high_speed
*/
#define PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_HIGH_SPEED_MASK)
#define PCIE_PHY_CMN_REG069_PHY_MODE_MASK (0x30U)
#define PCIE_PHY_CMN_REG069_PHY_MODE_SHIFT (4U)
#define PCIE_PHY_CMN_REG069_PHY_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_PHY_MODE_SHIFT)) & PCIE_PHY_CMN_REG069_PHY_MODE_MASK)
#define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_MASK (0x40U)
#define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_SHIFT (6U)
/*! OVRD_PHY_MODE - Override enable for phy_mode
*/
#define PCIE_PHY_CMN_REG069_OVRD_PHY_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_SHIFT)) & PCIE_PHY_CMN_REG069_OVRD_PHY_MODE_MASK)
/*! @} */
/*! @name CMN_REG06A - */
/*! @{ */
#define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_MASK (0xFU)
#define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_SHIFT (0U)
/*! TG_BGR_FAST_PULSE_TIME - BGR LPF bypass duration after BGR_EN = 1
*/
#define PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_SHIFT)) & PCIE_PHY_CMN_REG06A_TG_BGR_FAST_PULSE_TIME_MASK)
#define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_MASK (0x10U)
#define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_SHIFT (4U)
#define PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_SHIFT)) & PCIE_PHY_CMN_REG06A_CMN_TIMER_SEL_MASK)
#define PCIE_PHY_CMN_REG06A_CMN_RATE_MASK (0x60U)
#define PCIE_PHY_CMN_REG06A_CMN_RATE_SHIFT (5U)
/*! CMN_RATE - TX Data Rate manual setting
*/
#define PCIE_PHY_CMN_REG06A_CMN_RATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_CMN_RATE_SHIFT)) & PCIE_PHY_CMN_REG06A_CMN_RATE_MASK)
#define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_MASK (0x80U)
#define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_SHIFT (7U)
/*! OVRD_CMN_RATE - Override enable for cmn_rate
*/
#define PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_SHIFT)) & PCIE_PHY_CMN_REG06A_OVRD_CMN_RATE_MASK)
/*! @} */
/*! @name CMN_REG06B - */
/*! @{ */
#define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_MASK (0x7U)
#define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_SHIFT (0U)
/*! TG_PLL_SDM_RSTN_DELAY_TIME - PLL SDM start delay after PLL integer-mode lock(PLL lock)
*/
#define PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06B_TG_PLL_SDM_RSTN_DELAY_TIME_MASK)
#define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_MASK (0x38U)
#define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_SHIFT (3U)
#define PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06B_TG_BGR_SET_DELAY_TIME_MASK)
/*! @} */
/*! @name CMN_REG06C - */
/*! @{ */
#define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_MASK (0x7U)
#define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_SHIFT (0U)
/*! TG_PLL_FINE_LOCK_DELAY_TIME - PLL Fine LOCK DLY CODE
*/
#define PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06C_TG_PLL_FINE_LOCK_DELAY_TIME_MASK)
#define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_MASK (0x38U)
#define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_SHIFT (3U)
/*! TG_PLL_AFC_RSTN_DELAY_TIME - PLL AFC reset delay time after bypassing BGR LPF
*/
#define PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06C_TG_PLL_AFC_RSTN_DELAY_TIME_MASK)
/*! @} */
/*! @name CMN_REG06D - */
/*! @{ */
#define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_MASK (0x7U)
#define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_SHIFT (0U)
/*! TG_PLL_SDC_RSTN_DELAY_TIME - PLL SDM RESET STABLE DLY CODE
*/
#define PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06D_TG_PLL_SDC_RSTN_DELAY_TIME_MASK)
#define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_MASK (0x38U)
#define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_SHIFT (3U)
/*! TG_PLL_SSC_EN_DELAY_TIME - PLL SSC start delay time after
*/
#define PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06D_TG_PLL_SSC_EN_DELAY_TIME_MASK)
/*! @} */
/*! @name CMN_REG06E - */
/*! @{ */
#define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_MASK (0x7U)
#define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_SHIFT (0U)
#define PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_CMN_REG06E_TG_PLL_CD_TX_SER_RSTN_DELAY_TIME_MASK)
/*! @} */
/*! @name CMN_REG06F - */
/*! @{ */
#define PCIE_PHY_CMN_REG06F_DTB_SEL_MASK (0xFFU)
#define PCIE_PHY_CMN_REG06F_DTB_SEL_SHIFT (0U)
/*! DTB_SEL - Digital Test Bus (DTB) selection
*/
#define PCIE_PHY_CMN_REG06F_DTB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG06F_DTB_SEL_SHIFT)) & PCIE_PHY_CMN_REG06F_DTB_SEL_MASK)
/*! @} */
/*! @name CMN_REG070 - */
/*! @{ */
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_MASK (0xFU)
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_SHIFT (0U)
/*! ANA_PLL_AFC_RING_CODE_MON - LC AFC code MSB monitor
*/
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG070_ANA_PLL_AFC_RING_CODE_MON_MASK)
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_MASK (0x30U)
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_SHIFT (4U)
/*! ANA_PLL_AFC_LC_CODE_MON - LC AFC code MSB monitor
*/
#define PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG070_ANA_PLL_AFC_LC_CODE_MON_MASK)
/*! @} */
/*! @name CMN_REG071 - */
/*! @{ */
#define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_MASK (0xFU)
#define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_SHIFT (0U)
/*! ANA_PLL_AGMC_CODE_MON - LC VCO GM code monitor
*/
#define PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_SHIFT)) & PCIE_PHY_CMN_REG071_ANA_PLL_AGMC_CODE_MON_MASK)
/*! @} */
/*! @name CMN_REG072 - */
/*! @{ */
#define PCIE_PHY_CMN_REG072_MON_CMN_STATE_MASK (0x1FU)
#define PCIE_PHY_CMN_REG072_MON_CMN_STATE_SHIFT (0U)
/*! MON_CMN_STATE - CMN state monitor
*/
#define PCIE_PHY_CMN_REG072_MON_CMN_STATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG072_MON_CMN_STATE_SHIFT)) & PCIE_PHY_CMN_REG072_MON_CMN_STATE_MASK)
/*! @} */
/*! @name CMN_REG073 - */
/*! @{ */
#define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_MASK (0x7FU)
#define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_SHIFT (0U)
/*! MON_CMN_TIME__14_8 - CMN timer monitor
*/
#define PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_SHIFT)) & PCIE_PHY_CMN_REG073_MON_CMN_TIME__14_8_MASK)
/*! @} */
/*! @name CMN_REG074 - */
/*! @{ */
#define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_MASK (0xFFU)
#define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_SHIFT (0U)
/*! MON_CMN_TIME__7_0 - CMN timer monitor
*/
#define PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_SHIFT)) & PCIE_PHY_CMN_REG074_MON_CMN_TIME__7_0_MASK)
/*! @} */
/*! @name CMN_REG075 - */
/*! @{ */
#define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_MASK (0x1U)
#define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_SHIFT (0U)
/*! ANA_PLL_AFC_DONE - PLL AFC Done
*/
#define PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_SHIFT)) & PCIE_PHY_CMN_REG075_ANA_PLL_AFC_DONE_MASK)
#define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_MASK (0x2U)
#define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_SHIFT (1U)
/*! ANA_PLL_LOCK_DONE - PLL Lock Done
*/
#define PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_SHIFT)) & PCIE_PHY_CMN_REG075_ANA_PLL_LOCK_DONE_MASK)
/*! @} */
/*! @name CMN_REG076 - */
/*! @{ */
#define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_MASK (0x3U)
#define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_SHIFT (0U)
/*! LANE0_RESET_MUX_SEL - 0x0 : Lane0 reset signal from Port 0
*/
#define PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE0_RESET_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_MASK (0xCU)
#define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_SHIFT (2U)
/*! LANE1_RESET_MUX_SEL - 0x0 : Lane1 reset signal from Port 0
*/
#define PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE1_RESET_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_MASK (0x30U)
#define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_SHIFT (4U)
/*! LANE2_RESET_MUX_SEL - 0x0 : Lane2 reset signal from Port 0
*/
#define PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE2_RESET_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_MASK (0xC0U)
#define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_SHIFT (6U)
/*! LANE3_RESET_MUX_SEL - 0x0 : Lane3 reset signal from Port 0
*/
#define PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG076_LANE3_RESET_MUX_SEL_MASK)
/*! @} */
/*! @name CMN_REG077 - */
/*! @{ */
#define PCIE_PHY_CMN_REG077_LANE0_SW_RESET_MASK (0x1U)
#define PCIE_PHY_CMN_REG077_LANE0_SW_RESET_SHIFT (0U)
/*! LANE0_SW_RESET - 0x0 : Lane0 reset
*/
#define PCIE_PHY_CMN_REG077_LANE0_SW_RESET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE0_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE0_SW_RESET_MASK)
#define PCIE_PHY_CMN_REG077_LANE1_SW_RESET_MASK (0x2U)
#define PCIE_PHY_CMN_REG077_LANE1_SW_RESET_SHIFT (1U)
/*! LANE1_SW_RESET - 0x0 : Lane1 reset
*/
#define PCIE_PHY_CMN_REG077_LANE1_SW_RESET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE1_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE1_SW_RESET_MASK)
#define PCIE_PHY_CMN_REG077_LANE2_SW_RESET_MASK (0x4U)
#define PCIE_PHY_CMN_REG077_LANE2_SW_RESET_SHIFT (2U)
/*! LANE2_SW_RESET - 0x0 : Lane2 reset
*/
#define PCIE_PHY_CMN_REG077_LANE2_SW_RESET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE2_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE2_SW_RESET_MASK)
#define PCIE_PHY_CMN_REG077_LANE3_SW_RESET_MASK (0x8U)
#define PCIE_PHY_CMN_REG077_LANE3_SW_RESET_SHIFT (3U)
/*! LANE3_SW_RESET - 0x0 : Lane3 reset
*/
#define PCIE_PHY_CMN_REG077_LANE3_SW_RESET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_LANE3_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_LANE3_SW_RESET_MASK)
#define PCIE_PHY_CMN_REG077_CMN_SW_RESET_MASK (0x10U)
#define PCIE_PHY_CMN_REG077_CMN_SW_RESET_SHIFT (4U)
/*! CMN_SW_RESET - 0x0 : cmn reset
*/
#define PCIE_PHY_CMN_REG077_CMN_SW_RESET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG077_CMN_SW_RESET_SHIFT)) & PCIE_PHY_CMN_REG077_CMN_SW_RESET_MASK)
/*! @} */
/*! @name CMN_REG078 - */
/*! @{ */
#define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_MASK (0x3U)
#define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_SHIFT (0U)
#define PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE0_TX_DATA_CLK_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_MASK (0xCU)
#define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_SHIFT (2U)
#define PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE1_TX_DATA_CLK_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_MASK (0x30U)
#define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_SHIFT (4U)
#define PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE2_TX_DATA_CLK_MUX_SEL_MASK)
#define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_MASK (0xC0U)
#define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_SHIFT (6U)
/*! LANE3_TX_DATA_CLK_MUX_SEL - 0x0 : tx data clock from lane0
*/
#define PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_SHIFT)) & PCIE_PHY_CMN_REG078_LANE3_TX_DATA_CLK_MUX_SEL_MASK)
/*! @} */
/*! @name CMN_REG079 - */
/*! @{ */
#define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_MASK (0x1U)
#define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_SHIFT (0U)
#define PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_SHIFT)) & PCIE_PHY_CMN_REG079_CMN_RESET_CONTROL_MASK)
/*! @} */
/*! @name CMN_REG080 - */
/*! @{ */
#define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_MASK (0xFFU)
#define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_SHIFT (0U)
#define PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_SHIFT)) & PCIE_PHY_CMN_REG080_RATE_CHANGE_DELAY_MASK)
/*! @} */
/*! @name CMN_REG081 - */
/*! @{ */
#define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_MASK (0xFFU)
#define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_SHIFT (0U)
#define PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_SHIFT)) & PCIE_PHY_CMN_REG081_RX_EFOM_ERROR_TH_7_0_MASK)
/*! @} */
/*! @name CMN_REG082 - */
/*! @{ */
#define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_MASK (0x3U)
#define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_SHIFT (0U)
#define PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_SHIFT)) & PCIE_PHY_CMN_REG082_RX_EFOM_ERROR_TH_9_8_MASK)
/*! @} */
/*! @name TRSV_REG000 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_SHIFT (0U)
/*! LN0_TX_DRV_EI_EN - TX driver electrical-idle state enable
*/
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EI_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_SHIFT (1U)
/*! LN0_OVRD_TX_DRV_EI_EN - Override enable for tx_drv_ei_en
*/
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EI_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_SHIFT (2U)
/*! LN0_TX_DRV_CM_KEEPER_EN - TX driver common-mode keep enable
*/
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_CM_KEEPER_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_SHIFT (3U)
/*! LN0_OVRD_TX_DRV_CM_KEEPER_EN - Override enable for tx_drv_cm_keeper_en
*/
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_CM_KEEPER_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT (4U)
/*! LN0_TX_DRV_BEACON_LFPS_OUT_EN - TX beacon or LFPS enable
*/
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_BEACON_LFPS_OUT_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT (5U)
/*! LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN - Override enable for tx_drv_beacon_lfps_out_en
*/
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_BEACON_LFPS_OUT_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_SHIFT (6U)
/*! LN0_TX_DRV_EN - TX driver enable
*/
#define PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_TX_DRV_EN_MASK)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_SHIFT (7U)
/*! LN0_OVRD_TX_DRV_EN - Override enable for tx_drv_en
*/
#define PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG000_LN0_OVRD_TX_DRV_EN_MASK)
/*! @} */
/*! @name TRSV_REG001 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_SHIFT (0U)
/*! LN0_TX_DRV_LVL_CTRL_G1 - [GEN1] TX driver main-tap level
*/
#define PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG001_LN0_TX_DRV_LVL_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_SHIFT (5U)
/*! LN0_OVRD_TX_DRV_LVL_CTRL - Override enable for tx_drv_lvl_ctrl_g1
*/
#define PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG001_LN0_OVRD_TX_DRV_LVL_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG002 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_SHIFT (0U)
/*! LN0_TX_DRV_LVL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG002_LN0_TX_DRV_LVL_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG003 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_SHIFT (0U)
/*! LN0_TX_DRV_LVL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG003_LN0_TX_DRV_LVL_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG004 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_SHIFT (0U)
/*! LN0_TX_DRV_LVL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG004_LN0_TX_DRV_LVL_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG005 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_SHIFT (0U)
/*! LN0_TX_DRV_POST_LVL_CTRL_G1 - [GEN1] TX driver de-emphasis level
*/
#define PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG005_LN0_TX_DRV_POST_LVL_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_SHIFT (5U)
/*! LN0_OVRD_TX_DRV_POST_LVL_CTRL - Override enable for tx_drv_post_lvl_ctrl_g1
*/
#define PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG005_LN0_OVRD_TX_DRV_POST_LVL_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG006 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_SHIFT (0U)
/*! LN0_TX_DRV_POST_LVL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG006_LN0_TX_DRV_POST_LVL_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG007 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_SHIFT (0U)
/*! LN0_TX_DRV_POST_LVL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG007_LN0_TX_DRV_POST_LVL_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG008 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_SHIFT (0U)
/*! LN0_TX_DRV_POST_LVL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG008_LN0_TX_DRV_POST_LVL_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG009 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_MASK (0xFU)
#define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_SHIFT (0U)
/*! LN0_TX_DRV_PRE_LVL_CTRL_G1 - [GEN1] TX driver pre-shoot level
*/
#define PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG009_LN0_TX_DRV_PRE_LVL_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_SHIFT (4U)
/*! LN0_OVRD_TX_DRV_PRE_LVL_CTRL - Override enable for tx_drv_pre_lvl_ctrl_g1
*/
#define PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG009_LN0_OVRD_TX_DRV_PRE_LVL_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG00A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_MASK (0xFU)
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_SHIFT (0U)
/*! LN0_TX_DRV_PRE_LVL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_SHIFT (4U)
/*! LN0_TX_DRV_PRE_LVL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG00A_LN0_TX_DRV_PRE_LVL_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG00B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_SHIFT (0U)
/*! LN0_TX_DRV_IDRV_EN - TX current-driver enable
*/
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_IDRV_EN_MASK)
#define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_SHIFT (1U)
/*! LN0_OVRD_TX_DRV_IDRV_EN - Override enable for tx_drv_idrv_en
*/
#define PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_OVRD_TX_DRV_IDRV_EN_MASK)
#define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SHIFT (2U)
/*! LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN - TX LFPS/BEACON synchronization enable
*/
#define PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_ANA_TX_DRV_BEACON_LFPS_SYNC_EN_MASK)
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_MASK (0x78U)
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_SHIFT (3U)
/*! LN0_TX_DRV_PRE_LVL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG00B_LN0_TX_DRV_PRE_LVL_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG00C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_SHIFT (0U)
/*! LN0_ANA_TX_DRV_ACCDRV_EN - Enable of Cap. Peaking block.
*/
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_ACCDRV_EN_MASK)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_MASK (0x2U)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_SHIFT (1U)
/*! LN0_ANA_TX_DRV_IDRV_VREF_SEL - TX current driver reference selection
*/
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_VREF_SEL_MASK)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_SHIFT (2U)
/*! LN0_ANA_TX_DRV_IDRV_IUP_CTRL - TX current driver pmos current control
*/
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_MASK)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_SHIFT (5U)
/*! LN0_ANA_TX_DRV_IDRV_IDN_CTRL - TX current driver pmos current control
*/
#define PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG00C_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG00D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_SHIFT (0U)
#define PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_SHIFT)) & PCIE_PHY_TRSV_REG00D_LN0_RX_VALID_RSTN_DELAY_MASK)
/*! @} */
/*! @name TRSV_REG00E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_MASK (0x3U)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_SHIFT (0U)
/*! LN0_TX_DRV_EI_EN_DELAY_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_MASK (0xCU)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_SHIFT (2U)
/*! LN0_TX_DRV_EI_EN_DELAY_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G3_MASK)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_MASK (0x30U)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_SHIFT (4U)
/*! LN0_TX_DRV_EI_EN_DELAY_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_SHIFT (6U)
/*! LN0_TX_DRV_EI_EN_DELAY_SEL_G1 - [GEN1] TX EI enable latency control
*/
#define PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG00E_LN0_TX_DRV_EI_EN_DELAY_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG00F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_SHIFT (0U)
/*! LN0_ANA_TX_DRV_PLL_REF_MON_EN - Enable of PLL reference clock monitor through Tx driver
*/
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_PLL_REF_MON_EN_MASK)
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_SHIFT (1U)
/*! LN0_ANA_TX_DRV_HSCLK_MON_EN - Enable of high-speed clock monitor through Tx driver
*/
#define PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG00F_LN0_ANA_TX_DRV_HSCLK_MON_EN_MASK)
/*! @} */
/*! @name TRSV_REG010 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_SHIFT (0U)
/*! LN0_TX_JEQ_CAP_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_SHIFT (4U)
/*! LN0_TX_JEQ_CAP_CTRL_G1 - [GEN1] TX jitter EQ loding capacitance control in thermomether
*/
#define PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG010_LN0_TX_JEQ_CAP_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG011 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_SHIFT (0U)
/*! LN0_TX_JEQ_CAP_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_SHIFT (4U)
/*! LN0_TX_JEQ_CAP_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG011_LN0_TX_JEQ_CAP_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG012 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_SHIFT (0U)
/*! LN0_ANA_TX_JEQ_EN - TX jitter EQ enable
*/
#define PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_SHIFT)) & PCIE_PHY_TRSV_REG012_LN0_ANA_TX_JEQ_EN_MASK)
/*! @} */
/*! @name TRSV_REG013 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_SHIFT (0U)
/*! LN0_TX_JEQ_EVEN_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_SHIFT (4U)
/*! LN0_TX_JEQ_EVEN_CTRL_G1 - [GEN1] TX jitter EQ driver (even) strength control
*/
#define PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG013_LN0_TX_JEQ_EVEN_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG014 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_SHIFT (0U)
/*! LN0_TX_JEQ_EVEN_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_SHIFT (4U)
/*! LN0_TX_JEQ_EVEN_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG014_LN0_TX_JEQ_EVEN_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG015 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_SHIFT (0U)
/*! LN0_TX_JEQ_ODD_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_SHIFT (4U)
/*! LN0_TX_JEQ_ODD_CTRL_G1 - [GEN1] TX jitter EQ driver (odd) strength control
*/
#define PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG015_LN0_TX_JEQ_ODD_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG016 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_SHIFT (0U)
/*! LN0_TX_JEQ_ODD_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_SHIFT (4U)
/*! LN0_TX_JEQ_ODD_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG016_LN0_TX_JEQ_ODD_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG017 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_SHIFT (0U)
/*! LN0_ANA_TX_RCAL_IRMRES_CTRL - TX RCAL rmres bias current control
*/
#define PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_ANA_TX_RCAL_IRMRES_CTRL_MASK)
#define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_SHIFT (2U)
/*! LN0_TX_RCAL_EN - TX RCAL enable
*/
#define PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_TX_RCAL_EN_MASK)
#define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_SHIFT (3U)
/*! LN0_OVRD_TX_RCAL_EN - Override enable for tx_rcal_en
*/
#define PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG017_LN0_OVRD_TX_RCAL_EN_MASK)
/*! @} */
/*! @name TRSV_REG018 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_SHIFT (0U)
/*! LN0_TX_RXD_EN - TX receiver detector enable. Drives a transition on the serial data and measures
* the charge time of the line in order to determine whether a receiver is connected.
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RXD_EN_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_SHIFT (1U)
/*! LN0_OVRD_TX_RXD_EN - Override enable for tx_rxd_en
*/
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_EN_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_SHIFT (2U)
/*! LN0_TX_RXD_COMP_EN - TX receiver detector comparator enable
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RXD_COMP_EN_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_SHIFT (3U)
/*! LN0_OVRD_TX_RXD_COMP_EN - Override enable for tx_rxd_comp_en
*/
#define PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_OVRD_TX_RXD_COMP_EN_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_MASK (0x10U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_SHIFT (4U)
/*! LN0_TX_RTERM_42P5_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_MASK (0x20U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_SHIFT (5U)
/*! LN0_TX_RTERM_42P5_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_MASK (0x40U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_SHIFT (6U)
/*! LN0_TX_RTERM_42P5_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_MASK (0x80U)
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_SHIFT (7U)
/*! LN0_TX_RTERM_42P5_EN_G1 - [GEN1]
*/
#define PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG018_LN0_TX_RTERM_42P5_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG019 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_SHIFT (0U)
/*! LN0_ANA_TX_RXD_COMP_I_CTRL - TX receiver detector comparator bias control
*/
#define PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG019_LN0_ANA_TX_RXD_COMP_I_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG01A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_SHIFT (0U)
/*! LN0_TX_SER_DATA_RSTN - TX serializer data-path resetn
*/
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_DATA_RSTN_MASK)
#define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_SHIFT (1U)
/*! LN0_OVRD_TX_SER_DATA_RSTN - Override enable for tx_ser_data_rstn
*/
#define PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_OVRD_TX_SER_DATA_RSTN_MASK)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_MASK (0x4U)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_SHIFT (2U)
/*! LN0_TX_SER_40BIT_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_MASK (0x8U)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_SHIFT (3U)
/*! LN0_TX_SER_40BIT_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_MASK (0x10U)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_SHIFT (4U)
/*! LN0_TX_SER_40BIT_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_MASK (0x20U)
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_SHIFT (5U)
/*! LN0_TX_SER_40BIT_EN_G1 - [GEN1] TX serializer data width selection
*/
#define PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG01A_LN0_TX_SER_40BIT_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG01B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_MASK (0x1U)
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_SHIFT (0U)
/*! LN0_ANA_TX_SER_TXCLK_INV - TX byte clock polarity inversion
*/
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_SER_TXCLK_INV_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_SHIFT (1U)
/*! LN0_ANA_TX_CDR_CLK_MON_EN - TX serializer clock selection
*/
#define PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_ANA_TX_CDR_CLK_MON_EN_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_SHIFT (2U)
/*! LN0_TX_SER_CLK_RSTN - TX serializer clock-path resetn
*/
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_CLK_RSTN_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_SHIFT (3U)
/*! LN0_OVRD_TX_SER_CLK_RSTN - Override enable for tx_ser_clk_rstn
*/
#define PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_OVRD_TX_SER_CLK_RSTN_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_MASK (0x10U)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_SHIFT (4U)
/*! LN0_TX_SER_RATE_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_MASK (0x20U)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_SHIFT (5U)
/*! LN0_TX_SER_RATE_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G3_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_MASK (0x40U)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_SHIFT (6U)
/*! LN0_TX_SER_RATE_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_MASK (0x80U)
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_SHIFT (7U)
/*! LN0_TX_SER_RATE_SEL_G1 - [GEN1] TX serializer data rate selection for Gen4 (Need to be controlled with i_tx_en_40bit)
*/
#define PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG01B_LN0_TX_SER_RATE_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG01C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_SHIFT (0U)
/*! LN0_ANA_TX_ATB_EN - TX ATB enable
*/
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_EN_MASK)
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_MASK (0x3EU)
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_SHIFT (1U)
/*! LN0_ANA_TX_ATB_SEL - 0000: Serailizer VDD, 0001: Pre Driver VDD, 0010: Driver VDD, 0011: Driver VDDH,
*/
#define PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_SHIFT)) & PCIE_PHY_TRSV_REG01C_LN0_ANA_TX_ATB_SEL_MASK)
/*! @} */
/*! @name TRSV_REG01D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_SHIFT (0U)
/*! LN0_ANA_TX_SRLB_EN - Serial retimed loopback enable
*/
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SRLB_EN_MASK)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_SHIFT (1U)
/*! LN0_ANA_TX_LLB_EN - Line loopback enalble
*/
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_LLB_EN_MASK)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_SHIFT (2U)
/*! LN0_ANA_TX_SLB_EN - Serial loopback enable
*/
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_SLB_EN_MASK)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_MASK (0x38U)
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_SHIFT (3U)
/*! LN0_ANA_TX_BIAS_RMRES_CTRL - RX RMRES bias current control
*/
#define PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01D_LN0_ANA_TX_BIAS_RMRES_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG01E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_MASK (0xFU)
#define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_SHIFT (0U)
/*! LN0_ANA_TX_RESERVED - Reserved port
*/
#define PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_ANA_TX_RESERVED_MASK)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_MASK (0x10U)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_SHIFT (4U)
/*! LN0_TX_EQ_2UI_DELAY_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_MASK (0x20U)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_SHIFT (5U)
/*! LN0_TX_EQ_2UI_DELAY_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_MASK (0x40U)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_SHIFT (6U)
/*! LN0_TX_EQ_2UI_DELAY_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_MASK (0x80U)
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_SHIFT (7U)
/*! LN0_TX_EQ_2UI_DELAY_EN_G1 - [GEN1] TX FIR filter delay control when bit-duplication
*/
#define PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG01E_LN0_TX_EQ_2UI_DELAY_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG01F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_SHIFT (0U)
/*! LN0_RX_CDR_MODE_CTRL - RX CDR mode select
*/
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_MODE_CTRL_MASK)
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_MASK (0x4U)
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_SHIFT (2U)
/*! LN0_OVRD_RX_CDR_MODE_CTRL - Override enable for rx_cdr_mode_ctrl
*/
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_MODE_CTRL_MASK)
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_SHIFT (3U)
/*! LN0_RX_CDR_EN - RX CDR enable
*/
#define PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_RX_CDR_EN_MASK)
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_SHIFT (4U)
/*! LN0_OVRD_RX_CDR_EN - Override enable for rx_cdr_en
*/
#define PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_SHIFT)) & PCIE_PHY_TRSV_REG01F_LN0_OVRD_RX_CDR_EN_MASK)
/*! @} */
/*! @name TRSV_REG020 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_SHIFT (0U)
/*! LN0_RX_CDR_REFDIV_SEL_PLL_G2 - [GEN2] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_SHIFT)) & PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G2_MASK)
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_SHIFT (4U)
/*! LN0_RX_CDR_REFDIV_SEL_PLL_G1 - [GEN1] [PLL mode] Decision of CDR ref. clock dividing-rate
*/
#define PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_SHIFT)) & PCIE_PHY_TRSV_REG020_LN0_RX_CDR_REFDIV_SEL_PLL_G1_MASK)
/*! @} */
/*! @name TRSV_REG021 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_SHIFT (0U)
/*! LN0_RX_CDR_REFDIV_SEL_PLL_G4 - [GEN4] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_SHIFT)) & PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G4_MASK)
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_SHIFT (4U)
/*! LN0_RX_CDR_REFDIV_SEL_PLL_G3 - [GEN3] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_SHIFT)) & PCIE_PHY_TRSV_REG021_LN0_RX_CDR_REFDIV_SEL_PLL_G3_MASK)
/*! @} */
/*! @name TRSV_REG022 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_SHIFT (0U)
/*! LN0_RX_CDR_REFDIV_SEL_DATA_G2 - [GEN2] [Data mode]
*/
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_SHIFT)) & PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G2_MASK)
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_SHIFT (4U)
/*! LN0_RX_CDR_REFDIV_SEL_DATA_G1 - [GEN1] [Data mode] Decision of CDR ref. divider ratio
*/
#define PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_SHIFT)) & PCIE_PHY_TRSV_REG022_LN0_RX_CDR_REFDIV_SEL_DATA_G1_MASK)
/*! @} */
/*! @name TRSV_REG023 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_SHIFT (0U)
/*! LN0_RX_CDR_REFDIV_SEL_DATA_G4 - [GEN4] [Data mode]
*/
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_SHIFT)) & PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G4_MASK)
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_SHIFT (4U)
/*! LN0_RX_CDR_REFDIV_SEL_DATA_G3 - [GEN3] [Data mode]
*/
#define PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_SHIFT)) & PCIE_PHY_TRSV_REG023_LN0_RX_CDR_REFDIV_SEL_DATA_G3_MASK)
/*! @} */
/*! @name TRSV_REG024 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_SHIFT (0U)
/*! LN0_RX_CDR_MDIV_SEL_PLL_G2 - [GEN2] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_SHIFT)) & PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G2_MASK)
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_SHIFT (4U)
/*! LN0_RX_CDR_MDIV_SEL_PLL_G1 - [GEN1] [PLL mode] Decision of CDR main-divider ratio
*/
#define PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_SHIFT)) & PCIE_PHY_TRSV_REG024_LN0_RX_CDR_MDIV_SEL_PLL_G1_MASK)
/*! @} */
/*! @name TRSV_REG025 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_SHIFT (0U)
/*! LN0_RX_CDR_MDIV_SEL_PLL_G4 - [GEN4] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_SHIFT)) & PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G4_MASK)
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_SHIFT (4U)
/*! LN0_RX_CDR_MDIV_SEL_PLL_G3 - [GEN3] [PLL mode]
*/
#define PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_SHIFT)) & PCIE_PHY_TRSV_REG025_LN0_RX_CDR_MDIV_SEL_PLL_G3_MASK)
/*! @} */
/*! @name TRSV_REG026 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_SHIFT (0U)
/*! LN0_RX_CDR_MDIV_SEL_DATA_G2 - [GEN2] [Data mode]
*/
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_SHIFT)) & PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G2_MASK)
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_SHIFT (4U)
/*! LN0_RX_CDR_MDIV_SEL_DATA_G1 - [GEN1] [Data mode] Decision of CDR main-divider ratio
*/
#define PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_SHIFT)) & PCIE_PHY_TRSV_REG026_LN0_RX_CDR_MDIV_SEL_DATA_G1_MASK)
/*! @} */
/*! @name TRSV_REG027 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_SHIFT (0U)
/*! LN0_RX_CDR_MDIV_SEL_DATA_G4 - [GEN4] [Data mode]
*/
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_SHIFT)) & PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G4_MASK)
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_SHIFT (4U)
/*! LN0_RX_CDR_MDIV_SEL_DATA_G3 - [GEN3] [Data mode]
*/
#define PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_SHIFT)) & PCIE_PHY_TRSV_REG027_LN0_RX_CDR_MDIV_SEL_DATA_G3_MASK)
/*! @} */
/*! @name TRSV_REG028 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_SHIFT (0U)
/*! LN0_ANA_RX_CDR_AFC_VCI_FORCE - RX CDR control voltage force
*/
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_VCI_FORCE_MASK)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_SHIFT (1U)
/*! LN0_ANA_RX_CDR_AFC_TEST_EN - RX CDR test mode enable
*/
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_TEST_EN_MASK)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_SHIFT (2U)
/*! LN0_ANA_RX_CDR_AFC_EN - RX CDR AFC enable
*/
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_AFC_EN_MASK)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_MASK (0x8U)
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_SHIFT (3U)
/*! LN0_ANA_RX_CDR_DES_RXCLK_INV - RX byte clock polarity inversion
*/
#define PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_ANA_RX_CDR_DES_RXCLK_INV_MASK)
#define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_SHIFT (4U)
/*! LN0_RX_CDR_BW_CTRL - RX CDR bandwidth control
*/
#define PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_RX_CDR_BW_CTRL_MASK)
#define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_SHIFT (5U)
/*! LN0_OVRD_RX_CDR_BW_CTRL - Override enable for rx_cdr_bw_ctrl
*/
#define PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG028_LN0_OVRD_RX_CDR_BW_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG029 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_SHIFT (0U)
/*! LN0_ANA_RX_CDR_CP_E_EN - RX CDR even charge-pump enable
*/
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_E_EN_MASK)
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_MASK (0xEU)
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_SHIFT (1U)
/*! LN0_ANA_RX_CDR_CP_CTRL - RX CDR charge pump current control (Ieven + Iodd)
*/
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_CP_CTRL_MASK)
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SHIFT (4U)
/*! LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL - RX CDR VCI reference voltage selection
*/
#define PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG029_LN0_ANA_RX_CDR_AFC_VCI_SUPPLY_SEL_MASK)
/*! @} */
/*! @name TRSV_REG02A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_MASK (0x1U)
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_SHIFT (0U)
/*! LN0_RX_CDR_VCO_STARTUP - RX CDR VCO startup signal, low to high transition
*/
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_VCO_STARTUP_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_MASK (0x2U)
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_SHIFT (1U)
/*! LN0_OVRD_RX_CDR_VCO_STARTUP - Override enable for rx_cdr_vco_startup
*/
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_VCO_STARTUP_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_SHIFT (2U)
/*! LN0_RX_CDR_FBB_CAL_EN - RX CDR FBB calibration enable
*/
#define PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_RX_CDR_FBB_CAL_EN_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_SHIFT (3U)
/*! LN0_OVRD_RX_CDR_FBB_CAL_EN - Override enable for rx_cdr_fbb_cal_en
*/
#define PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_OVRD_RX_CDR_FBB_CAL_EN_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_SHIFT (4U)
/*! LN0_ANA_RX_CDR_CP_VREG_LPF_EN - LPF enable for RX CDR charge pump regualtor
*/
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_LPF_EN_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_SHIFT (5U)
/*! LN0_ANA_RX_CDR_CP_VREG_IN_SEL - RX CDR charge pump regulator reference voltage selection
*/
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_VREG_IN_SEL_MASK)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_SHIFT (6U)
/*! LN0_ANA_RX_CDR_CP_O_EN - RX CDR odd charge-pump enable
*/
#define PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_SHIFT)) & PCIE_PHY_TRSV_REG02A_LN0_ANA_RX_CDR_CP_O_EN_MASK)
/*! @} */
/*! @name TRSV_REG02B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL - RX CDR BBVCO dummy cap control to decrease frequency
*/
#define PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG02B_LN0_ANA_RX_CDR_VCO_BBCAP_DN_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG02C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_MASK (0x1U)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_SHIFT (0U)
/*! LN0_RX_CDR_VCO_FREQ_BOOST_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G4_MASK)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_MASK (0x2U)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_SHIFT (1U)
/*! LN0_RX_CDR_VCO_FREQ_BOOST_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G3_MASK)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_MASK (0x4U)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_SHIFT (2U)
/*! LN0_RX_CDR_VCO_FREQ_BOOST_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G2_MASK)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_MASK (0x8U)
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_SHIFT (3U)
/*! LN0_RX_CDR_VCO_FREQ_BOOST_G1 - [GEN1] RX CDR VCO frequency boost enable
*/
#define PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_SHIFT)) & PCIE_PHY_TRSV_REG02C_LN0_RX_CDR_VCO_FREQ_BOOST_G1_MASK)
/*! @} */
/*! @name TRSV_REG02D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_MASK (0x7U)
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_SHIFT (0U)
/*! LN0_RX_CDR_VCO_VREG_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_MASK (0x38U)
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_SHIFT (3U)
/*! LN0_RX_CDR_VCO_VREG_SEL_G1 - [GEN1] RX CDR voltage regualtor selection
*/
#define PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG02D_LN0_RX_CDR_VCO_VREG_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG02E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_SHIFT (0U)
/*! LN0_RX_CTLE_EN - RX CTLE enable
*/
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CTLE_EN_MASK)
#define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_SHIFT (1U)
/*! LN0_OVRD_RX_CTLE_EN - Override enable for rx_ctle_en
*/
#define PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_OVRD_RX_CTLE_EN_MASK)
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_SHIFT (2U)
/*! LN0_RX_CDR_VCO_VREG_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_SHIFT (5U)
/*! LN0_RX_CDR_VCO_VREG_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG02E_LN0_RX_CDR_VCO_VREG_SEL_G3_MASK)
/*! @} */
/*! @name TRSV_REG02F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_MASK (0x1U)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_SHIFT (0U)
/*! LN0_RX_CTLE_HIGH_BW_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_MASK (0x2U)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_SHIFT (1U)
/*! LN0_RX_CTLE_HIGH_BW_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_MASK (0x4U)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_SHIFT (2U)
/*! LN0_RX_CTLE_HIGH_BW_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_MASK (0x8U)
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_SHIFT (3U)
/*! LN0_RX_CTLE_HIGH_BW_EN_G1 - [GEN1] RX CTLE bandwidth enhancement by boosting up current
*/
#define PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG02F_LN0_RX_CTLE_HIGH_BW_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG030 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_SHIFT (0U)
/*! LN0_RX_CTLE_ITAIL_CTRL_G1 - [GEN1] RX CTLE main tail current
*/
#define PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG030_LN0_RX_CTLE_ITAIL_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG031 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CTLE_ITAIL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG031_LN0_RX_CTLE_ITAIL_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG032 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_SHIFT (0U)
/*! LN0_RX_CTLE_ITAIL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG032_LN0_RX_CTLE_ITAIL_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG033 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_ITAIL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG033_LN0_RX_CTLE_ITAIL_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG034 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_SHIFT (0U)
/*! LN0_RX_CTLE_OC_CODE - RX CTLE manual offset code
*/
#define PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG034_LN0_RX_CTLE_OC_CODE_MASK)
#define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_CTLE_OC_CODE - Override enable for rx_ctle_oc_code
*/
#define PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG034_LN0_OVRD_RX_CTLE_OC_CODE_MASK)
/*! @} */
/*! @name TRSV_REG035 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_SHIFT (0U)
/*! LN0_RX_CTLE_OC_EN - RX CTLE offset calibration enable
*/
#define PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG035_LN0_RX_CTLE_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_SHIFT (1U)
/*! LN0_OVRD_RX_CTLE_OC_EN - Override enable for rx_ctle_oc_en
*/
#define PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG035_LN0_OVRD_RX_CTLE_OC_EN_MASK)
/*! @} */
/*! @name TRSV_REG036 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_MASK (0x1U)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_OC_VCM_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_MASK (0x2U)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_SHIFT (1U)
/*! LN0_RX_CTLE_OC_VCM_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G3_MASK)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_MASK (0x4U)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_SHIFT (2U)
/*! LN0_RX_CTLE_OC_VCM_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_MASK (0x8U)
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_SHIFT (3U)
/*! LN0_RX_CTLE_OC_VCM_SEL_G1 - [GEN1] RX CTLE input common-mode selection in offset calibration
*/
#define PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG036_LN0_RX_CTLE_OC_VCM_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG037 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_SHIFT (0U)
/*! LN0_RX_CTLE_RL_CTRL_G1 - [GEN1] RX CTLE load resistance control for Gen1
*/
#define PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG037_LN0_RX_CTLE_RL_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG038 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CTLE_RL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG038_LN0_RX_CTLE_RL_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG039 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_SHIFT (0U)
/*! LN0_RX_CTLE_RL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG039_LN0_RX_CTLE_RL_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG03A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_RL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG03A_LN0_RX_CTLE_RL_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG03B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_MASK (0xFU)
#define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_SHIFT (0U)
/*! LN0_RX_CTLE_RS1_CTRL_G1 - [GEN1] RX CTLE 1st stage source series resistance control
*/
#define PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG03B_LN0_RX_CTLE_RS1_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_SHIFT (4U)
/*! LN0_OVRD_RX_CTLE_RS1_CTRL - Override enable for rx_ctle_rs1_ctrl_g1
*/
#define PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG03B_LN0_OVRD_RX_CTLE_RS1_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG03C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_MASK (0xFU)
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_SHIFT (0U)
/*! LN0_RX_CTLE_RS1_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_SHIFT (4U)
/*! LN0_RX_CTLE_RS1_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG03C_LN0_RX_CTLE_RS1_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG03D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_RS1_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG03D_LN0_RX_CTLE_RS1_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG03E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_MASK (0xFU)
#define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_SHIFT (0U)
/*! LN0_RX_CTLE_RS2_CTRL_G1 - [GEN1] RX CTLE 2nd stage source series resistance control
*/
#define PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG03E_LN0_RX_CTLE_RS2_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_SHIFT (4U)
/*! LN0_OVRD_RX_CTLE_RS2_CTRL - Override enable for rx_ctle_rs2_ctrl_g1
*/
#define PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG03E_LN0_OVRD_RX_CTLE_RS2_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG03F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_MASK (0xFU)
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_SHIFT (0U)
/*! LN0_RX_CTLE_RS2_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_SHIFT (4U)
/*! LN0_RX_CTLE_RS2_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG03F_LN0_RX_CTLE_RS2_CTRL_G2_MASK)
/*! @} */
/*! @name TRSV_REG040 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_RS2_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG040_LN0_RX_CTLE_RS2_CTRL_G4_MASK)
/*! @} */
/*! @name TRSV_REG041 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_MASK (0x1U)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_SHIFT (0U)
/*! LN0_RX_CTLE_CHFB_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_MASK (0x2U)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_SHIFT (1U)
/*! LN0_RX_CTLE_CHFB_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_MASK (0x4U)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_SHIFT (2U)
/*! LN0_RX_CTLE_CHFB_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_MASK (0x8U)
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_SHIFT (3U)
/*! LN0_RX_CTLE_CHFB_EN_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier enable
*/
#define PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG041_LN0_RX_CTLE_CHFB_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG042 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CTLE_CS_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_SHIFT (4U)
/*! LN0_RX_CTLE_CS_CTRL_G1 - [GEN1] CTLE capacitance control. 4'h0=Gen4,3 4'h3=Gen2 4'h7=Gen1
*/
#define PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG042_LN0_RX_CTLE_CS_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG043 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_CS_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_SHIFT (4U)
/*! LN0_RX_CTLE_CS_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG043_LN0_RX_CTLE_CS_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG044 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_MASK (0x3U)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_SHIFT (0U)
/*! LN0_RX_CTLE_PEAKING_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_MASK (0xCU)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_SHIFT (2U)
/*! LN0_RX_CTLE_PEAKING_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_MASK (0x30U)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_SHIFT (4U)
/*! LN0_RX_CTLE_PEAKING_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_SHIFT (6U)
/*! LN0_RX_CTLE_PEAKING_EN_G1 - [GEN1] RX CTLE stage enable for Gen1
*/
#define PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG044_LN0_RX_CTLE_PEAKING_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG045 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_MASK (0x7U)
#define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_CTLE_IBLEED_CTRL - RX CTLE bleeder current control
*/
#define PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG045_LN0_ANA_RX_CTLE_IBLEED_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG046 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_SHIFT (0U)
/*! LN0_RX_CTLE_NEGC_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_SHIFT (4U)
/*! LN0_RX_CTLE_NEGC_EN_G1 - [GEN1] RX CTLE negative-C enable
*/
#define PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG046_LN0_RX_CTLE_NEGC_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG047 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_SHIFT (0U)
/*! LN0_RX_CTLE_NEGC_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_SHIFT (4U)
/*! LN0_RX_CTLE_NEGC_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG047_LN0_RX_CTLE_NEGC_EN_G3_MASK)
/*! @} */
/*! @name TRSV_REG048 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_SHIFT (4U)
/*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1 - [GEN1] RX CTLE negative-C tail current control
*/
#define PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG048_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG049 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_SHIFT (4U)
/*! LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG049_LN0_RX_CTLE_NEGC_ITAIL_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG04A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_SHIFT (0U)
/*! LN0_ANA_RX_CTLE_VCM_SEL - RX AFE (CTLE output) common-mode voltage selection
*/
#define PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_SHIFT)) & PCIE_PHY_TRSV_REG04A_LN0_ANA_RX_CTLE_VCM_SEL_MASK)
/*! @} */
/*! @name TRSV_REG04B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_MASK (0x3U)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_CHFB_BW_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_MASK (0xCU)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_SHIFT (2U)
/*! LN0_RX_CTLE_CHFB_BW_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_MASK (0x30U)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_SHIFT (4U)
/*! LN0_RX_CTLE_CHFB_BW_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_SHIFT (6U)
/*! LN0_RX_CTLE_CHFB_BW_CTRL_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier bandwidth control
*/
#define PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04B_LN0_RX_CTLE_CHFB_BW_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG04C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_MASK (0x7U)
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_MASK (0x38U)
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_SHIFT (3U)
/*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G1 - [GEN1] RX CTLE Cherry-Hooper feedback amplifier gain control
*/
#define PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04C_LN0_RX_CTLE_CHFB_GAIN_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG04D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_MASK (0x7U)
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_MASK (0x38U)
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_SHIFT (3U)
/*! LN0_RX_CTLE_CHFB_GAIN_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04D_LN0_RX_CTLE_CHFB_GAIN_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG04E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_MASK (0x3U)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_MASK (0xCU)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_SHIFT (2U)
/*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_MASK (0x30U)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_SHIFT (4U)
/*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_SHIFT (6U)
/*! LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1 - [GEN1] RX CTLE active load control
*/
#define PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG04E_LN0_RX_CTLE_ACTIVE_LOAD_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG04F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_SHIFT (0U)
/*! LN0_ANA_RX_CTLE_PTAT_EN - RX CTLE PTAT current enable
*/
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_PTAT_EN_MASK)
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_SHIFT (1U)
/*! LN0_ANA_RX_CTLE_VREG_SEL - RX CTLE voltage regulator output voltage
*/
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VREG_SEL_MASK)
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_SHIFT (5U)
/*! LN0_ANA_RX_CTLE_VGA_CTRL - RX CTLE stage3 gain control
*/
#define PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG04F_LN0_ANA_RX_CTLE_VGA_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG050 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_MASK (0x1U)
#define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_SHIFT (0U)
/*! LN0_RX_DES_DATA_CLEAR - RX deserializer data clear to prevent garbage data
*/
#define PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_RX_DES_DATA_CLEAR_MASK)
#define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_MASK (0x2U)
#define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_SHIFT (1U)
/*! LN0_OVRD_RX_DES_DATA_CLEAR - Override enable for rx_des_data_clear
*/
#define PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_OVRD_RX_DES_DATA_CLEAR_MASK)
#define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_SHIFT (2U)
/*! LN0_ANA_RX_CTLE_RESERVED - Reserved port
*/
#define PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG050_LN0_ANA_RX_CTLE_RESERVED_MASK)
/*! @} */
/*! @name TRSV_REG051 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_MASK (0x3U)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_SHIFT (0U)
/*! LN0_RX_DES_DATA_WIDTH_SEL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_MASK (0xCU)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_SHIFT (2U)
/*! LN0_RX_DES_DATA_WIDTH_SEL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G3_MASK)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_MASK (0x30U)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_SHIFT (4U)
/*! LN0_RX_DES_DATA_WIDTH_SEL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_SHIFT (6U)
/*! LN0_RX_DES_DATA_WIDTH_SEL_G1 - [GEN1] RX deserializer data width selection
*/
#define PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG051_LN0_RX_DES_DATA_WIDTH_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG052 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_ANA_RX_DES_DATA_CLEAR_DELAY_SEL_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_SHIFT (2U)
/*! LN0_RX_DES_RSTN - RX deserializer reset
*/
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_RSTN_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_SHIFT (3U)
/*! LN0_OVRD_RX_DES_RSTN - Override enable for rx_des_rstn
*/
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_RSTN_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_MASK (0x10U)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_SHIFT (4U)
/*! LN0_RX_DES_NON_DATA_SEL - RX deserializer non-data selection for edge/error sampler calibration
*/
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_NON_DATA_SEL_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_SHIFT (5U)
/*! LN0_OVRD_RX_DES_NON_DATA_SEL - Override enable for rx_des_non_data_sel
*/
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_NON_DATA_SEL_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_SHIFT (6U)
/*! LN0_RX_DES_EN - RX deserializer enable
*/
#define PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_RX_DES_EN_MASK)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_SHIFT (7U)
/*! LN0_OVRD_RX_DES_EN - Override enable for rx_des_en
*/
#define PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_SHIFT)) & PCIE_PHY_TRSV_REG052_LN0_OVRD_RX_DES_EN_MASK)
/*! @} */
/*! @name TRSV_REG053 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_MASK (0x7U)
#define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_SHIFT (0U)
/*! LN0_ANA_RX_DFE_EOM_PI_DIV_SEL - Clock divider control before RX EOM phase interpolator
*/
#define PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_ANA_RX_DFE_EOM_PI_DIV_SEL_MASK)
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_SHIFT (3U)
/*! LN0_RX_DFE_EOM_EN - RX EOM enable
*/
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_RX_DFE_EOM_EN_MASK)
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_SHIFT (4U)
/*! LN0_OVRD_RX_DFE_EOM_EN - Override enable for rx_dfe_eom_en
*/
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_EOM_EN_MASK)
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_SHIFT (5U)
/*! LN0_RX_DFE_ADAP_EN - RX DFE adaptation path enable. Only one of i_rx_dfe_adap_en and i_rx_eom_en should be "1".
*/
#define PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_RX_DFE_ADAP_EN_MASK)
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_SHIFT (6U)
/*! LN0_OVRD_RX_DFE_ADAP_EN - Override enable for rx_dfe_adap_en
*/
#define PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG053_LN0_OVRD_RX_DFE_ADAP_EN_MASK)
/*! @} */
/*! @name TRSV_REG054 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_DFE_EOM_PI_STR_CTRL - RX EOM PI drive strengh in pre-buffer stage
*/
#define PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG054_LN0_ANA_RX_DFE_EOM_PI_STR_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG055 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT (0U)
/*! LN0_RX_DFE_OC_ADDER_EVEN_CODE - RX DFE even data path offset calibration code
*/
#define PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG055_LN0_RX_DFE_OC_ADDER_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE - Override enable for rx_dfe_oc_adder_even_code
*/
#define PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG055_LN0_OVRD_RX_DFE_OC_ADDER_EVEN_CODE_MASK)
/*! @} */
/*! @name TRSV_REG056 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_SHIFT (0U)
/*! LN0_RX_DFE_OC_ADDER_ODD_CODE - RX DFE odd data path offset calibration code
*/
#define PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG056_LN0_RX_DFE_OC_ADDER_ODD_CODE_MASK)
#define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE - Override enable for rx_dfe_oc_adder_odd_code
*/
#define PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG056_LN0_OVRD_RX_DFE_OC_ADDER_ODD_CODE_MASK)
/*! @} */
/*! @name TRSV_REG057 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK (0x7U)
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT (0U)
/*! LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even edge path offset calibration
*/
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT (3U)
/*! LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE - Override enable for rx_dfe_oc_dac_edge_even_code
*/
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_EDGE_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK (0x10U)
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT (4U)
/*! LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd adder offset calibration
*/
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT (5U)
/*! LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE - Override enable for rx_dfe_oc_dac_adder_odd_code
*/
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_ODD_CODE_MASK)
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK (0x40U)
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT (6U)
/*! LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even adder offset calibration
*/
#define PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE - Override enable for rx_dfe_oc_dac_adder_even_code
*/
#define PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG057_LN0_OVRD_RX_DFE_OC_DAC_ADDER_EVEN_CODE_MASK)
/*! @} */
/*! @name TRSV_REG058 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK (0x7U)
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT (0U)
/*! LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE - Fine control of zero-crossing in RX DFE DAC for even error path offset calibration
*/
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT (3U)
/*! LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE - Override enable for rx_dfe_oc_dac_err_even_code
*/
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_ERR_EVEN_CODE_MASK)
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK (0x70U)
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT (4U)
/*! LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd edge path offset calibration
*/
#define PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK)
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE - Override enable for rx_dfe_oc_dac_edge_odd_code
*/
#define PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG058_LN0_OVRD_RX_DFE_OC_DAC_EDGE_ODD_CODE_MASK)
/*! @} */
/*! @name TRSV_REG059 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_SHIFT (0U)
/*! LN0_RX_DFE_OC_EN - RX DFE offset calibration progress enable
*/
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_OC_EN - Override enable for rx_dfe_oc_en
*/
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT (2U)
/*! LN0_RX_DFE_OC_DAC_ERR_ODD_CODE - Fine control of zero-crossing in RX DFE DAC for odd error path offset calibration
*/
#define PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK)
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT (5U)
/*! LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE - Override enable for rx_dfe_oc_dac_err_odd_code
*/
#define PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG059_LN0_OVRD_RX_DFE_OC_DAC_ERR_ODD_CODE_MASK)
/*! @} */
/*! @name TRSV_REG05A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8 - RX DFE even edge path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05A_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__8_MASK)
#define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE - Override enable for rx_dfe_oc_sa_edge_even_code
*/
#define PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05A_LN0_OVRD_RX_DFE_OC_SA_EDGE_EVEN_CODE_MASK)
/*! @} */
/*! @name TRSV_REG05B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0 - RX DFE even edge path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05B_LN0_RX_DFE_OC_SA_EDGE_EVEN_CODE__7_0_MASK)
/*! @} */
/*! @name TRSV_REG05C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8 - RX DFE odd edge path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05C_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__8_MASK)
#define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE - Override enable for rx_dfe_oc_sa_edge_odd_code
*/
#define PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05C_LN0_OVRD_RX_DFE_OC_SA_EDGE_ODD_CODE_MASK)
/*! @} */
/*! @name TRSV_REG05D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0 - RX DFE odd edge path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05D_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE__7_0_MASK)
/*! @} */
/*! @name TRSV_REG05E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8 - RX DFE even error path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG05E_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__8_MASK)
#define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE - Override enable for rx_dfe_oc_sa_err_even_code
*/
#define PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG05E_LN0_OVRD_RX_DFE_OC_SA_ERR_EVEN_CODE_MASK)
/*! @} */
/*! @name TRSV_REG05F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0 - RX DFE even error path offset calibration code
*/
#define PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG05F_LN0_RX_DFE_OC_SA_ERR_EVEN_CODE__7_0_MASK)
/*! @} */
/*! @name TRSV_REG060 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8 - RX DFE odd error path offset calibration code
*/
#define PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_SHIFT)) & PCIE_PHY_TRSV_REG060_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__8_MASK)
#define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE - Override enable for rx_dfe_oc_sa_err_odd_code
*/
#define PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_SHIFT)) & PCIE_PHY_TRSV_REG060_LN0_OVRD_RX_DFE_OC_SA_ERR_ODD_CODE_MASK)
/*! @} */
/*! @name TRSV_REG061 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SHIFT (0U)
/*! LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0 - RX DFE odd error path offset calibration code
*/
#define PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG061_LN0_RX_DFE_OC_SA_ERR_ODD_CODE__7_0_MASK)
/*! @} */
/*! @name TRSV_REG062 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_SHIFT (0U)
/*! LN0_RX_DFE_SA_ERR_OC_EN - RX DFE error path enable in offset calibration (If all of
* rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
*/
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_ERR_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_SA_ERR_OC_EN - Override enable for rx_dfe_sa_err_oc_en
*/
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_ERR_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_SHIFT (2U)
/*! LN0_RX_DFE_SA_EDGE_OC_EN - RX DFE edge path enable in offset calibration (If all of
* rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
*/
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_EDGE_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_SHIFT (3U)
/*! LN0_OVRD_RX_DFE_SA_EDGE_OC_EN - Override enable for rx_dfe_sa_edge_oc_en
*/
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_EDGE_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT (4U)
/*! LN0_RX_DFE_SA_DATA_ODD_OC_EN - RX DFE data even path enable in offset calibration (If all of
* rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
*/
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_ODD_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT (5U)
/*! LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN - Override enable for rx_dfe_sa_data_odd_oc_en
*/
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_ODD_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT (6U)
/*! LN0_RX_DFE_SA_DATA_EVEN_OC_EN - RX DFE data odd path enable in offset calibration (If all of
* rx_dfe_sa_*_oc_en are 0, all path are autimatically activated as normal mode)
*/
#define PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_RX_DFE_SA_DATA_EVEN_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT (7U)
/*! LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN - Override enable for rx_dfe_sa_data_even_oc_en
*/
#define PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG062_LN0_OVRD_RX_DFE_SA_DATA_EVEN_OC_EN_MASK)
/*! @} */
/*! @name TRSV_REG063 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_SHIFT (0U)
/*! LN0_RX_DFE_VREF_CTRL__8 - RX DFE Vref control
*/
#define PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_SHIFT)) & PCIE_PHY_TRSV_REG063_LN0_RX_DFE_VREF_CTRL__8_MASK)
#define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_MASK (0x2U)
#define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_SHIFT (1U)
/*! LN0_OVRD_RX_DFE_VREF_CTRL - Override enable for rx_dfe_vref_ctrl
*/
#define PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG063_LN0_OVRD_RX_DFE_VREF_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG064 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_SHIFT (0U)
/*! LN0_RX_DFE_VREF_CTRL__7_0 - RX DFE Vref control
*/
#define PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_SHIFT)) & PCIE_PHY_TRSV_REG064_LN0_RX_DFE_VREF_CTRL__7_0_MASK)
/*! @} */
/*! @name TRSV_REG065 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_SHIFT (0U)
/*! LN0_ANA_RX_DFE_VREG_SEL - N/A, DFE bias current control [3:2]: DFE adder bias current, [1:0]: OC DAC bias current.
*/
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_SHIFT)) & PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_VREG_SEL_MASK)
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_SHIFT (4U)
#define PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG065_LN0_ANA_RX_DFE_ADDER_BLEED_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG066 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_SHIFT (0U)
/*! LN0_RX_RCAL_EN - RX RCAL enable
*/
#define PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_RX_RCAL_EN_MASK)
#define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_SHIFT (1U)
/*! LN0_OVRD_RX_RCAL_EN - Override enable for rx_rcal_en
*/
#define PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_OVRD_RX_RCAL_EN_MASK)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_MASK (0x4U)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_SHIFT (2U)
/*! LN0_ANA_RX_DFE_EOM_CLK_SEL - RX EOM clock selection
*/
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_EOM_CLK_SEL_MASK)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_MASK (0x38U)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_SHIFT (3U)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_VCM_CTRL_MASK)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_MASK (0x40U)
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_SHIFT (6U)
/*! LN0_ANA_RX_DFE_DAC_OUT_PULLUP - Pull-up all DAC output in RX DFE to disable all offset code effect
*/
#define PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_SHIFT)) & PCIE_PHY_TRSV_REG066_LN0_ANA_RX_DFE_DAC_OUT_PULLUP_MASK)
/*! @} */
/*! @name TRSV_REG067 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_SHIFT (0U)
/*! LN0_RX_RTERM_EN - RX RTERM enable
*/
#define PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_RX_RTERM_EN_MASK)
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_SHIFT (1U)
/*! LN0_OVRD_RX_RTERM_EN - Override enable for rx_rterm_en
*/
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RTERM_EN_MASK)
#define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_MASK (0xCU)
#define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_SHIFT (2U)
#define PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_ANA_RX_RCAL_IRMRES_CTRL_MASK)
#define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_SHIFT (4U)
/*! LN0_RX_RCAL_BIAS_EN - RX RCAL bias current enable
*/
#define PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_RX_RCAL_BIAS_EN_MASK)
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_SHIFT (5U)
/*! LN0_OVRD_RX_RCAL_BIAS_EN - Override enable for rx_rcal_bias_en
*/
#define PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG067_LN0_OVRD_RX_RCAL_BIAS_EN_MASK)
/*! @} */
/*! @name TRSV_REG068 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_RTERM_INCM_SW_CTRL - RX RTERM single-ended impedance control by switch control
*/
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_SW_CTRL_MASK)
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_MASK (0xCU)
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_SHIFT (2U)
/*! LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL - RX RTERM single-ended impedance control by current control
*/
#define PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_MASK)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_MASK (0x10U)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_SHIFT (4U)
/*! LN0_RX_RTERM_42P5_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_MASK (0x20U)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_SHIFT (5U)
/*! LN0_RX_RTERM_42P5_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_MASK (0x40U)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_SHIFT (6U)
/*! LN0_RX_RTERM_42P5_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_MASK (0x80U)
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_SHIFT (7U)
/*! LN0_RX_RTERM_42P5_EN_G1 - [GEN1] RX RTERM resistance shift
*/
#define PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG068_LN0_RX_RTERM_42P5_EN_G1_MASK)
/*! @} */
/*! @name TRSV_REG069 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_RTERM_OFSP_CTRL - Offset code for RX RTERM P node
*/
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSP_CTRL_MASK)
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_MASK (0x2U)
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_SHIFT (1U)
/*! LN0_ANA_RX_RTERM_OFSN_CTRL - Offset code for RX RTERM N node
*/
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_OFSN_CTRL_MASK)
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MASK (0xCU)
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SHIFT (2U)
/*! LN0_ANA_RX_RTERM_INCM_VCM_CTRL - RX RTERM output common-mode voltage control
*/
#define PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG069_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG06A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_SHIFT (0U)
/*! LN0_RX_RTERM_CM_PULLDN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G4_MASK)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_MASK (0x2U)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_SHIFT (1U)
/*! LN0_RX_RTERM_CM_PULLDN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G3_MASK)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_MASK (0x4U)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_SHIFT (2U)
/*! LN0_RX_RTERM_CM_PULLDN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G2_MASK)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_MASK (0x8U)
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_SHIFT (3U)
/*! LN0_RX_RTERM_CM_PULLDN_G1 - [GEN1] RX RTERM termination voltage pull-down
*/
#define PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_RX_RTERM_CM_PULLDN_G1_MASK)
#define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_SHIFT (4U)
/*! LN0_OVRD_RX_RTERM_CM_PULLDN - Override enable for rx_rterm_cm_pulldn_g1
*/
#define PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_SHIFT)) & PCIE_PHY_TRSV_REG06A_LN0_OVRD_RX_RTERM_CM_PULLDN_MASK)
/*! @} */
/*! @name TRSV_REG06B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_SHIFT (0U)
#define PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_SHIFT (1U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_SQ_BMR_EN_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_SHIFT (2U)
/*! LN0_OVRD_RX_SQ_BMR_EN - Override enable for rx_sq_bmr_en
*/
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_SQ_BMR_EN_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_MASK (0x8U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_SHIFT (3U)
/*! LN0_RX_RTERM_VCM_EN_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G4_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_MASK (0x10U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_SHIFT (4U)
/*! LN0_RX_RTERM_VCM_EN_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G3_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_MASK (0x20U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_SHIFT (5U)
/*! LN0_RX_RTERM_VCM_EN_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G2_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_MASK (0x40U)
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_SHIFT (6U)
/*! LN0_RX_RTERM_VCM_EN_G1 - [GEN1]
*/
#define PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_RX_RTERM_VCM_EN_G1_MASK)
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_SHIFT (7U)
/*! LN0_OVRD_RX_RTERM_VCM_EN - Override enable for rx_rterm_vcm_en_g1
*/
#define PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_SHIFT)) & PCIE_PHY_TRSV_REG06B_LN0_OVRD_RX_RTERM_VCM_EN_MASK)
/*! @} */
/*! @name TRSV_REG06C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_SHIFT (0U)
/*! LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN - RX high-squelch diff-N offset sign
*/
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN_MASK)
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_SHIFT (1U)
/*! LN0_RX_SQHS_DIFN_OC_EN - RX high-squelch diff-N offset calibration enable
*/
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_DIFN_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_SHIFT (2U)
/*! LN0_OVRD_RX_SQHS_DIFN_OC_EN - Override enable for rx_sqhs_difn_oc_en
*/
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_DIFN_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_SHIFT (3U)
/*! LN0_RX_SQHS_EN - RX high-speed squelch enable
*/
#define PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_RX_SQHS_EN_MASK)
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_SHIFT (4U)
/*! LN0_OVRD_RX_SQHS_EN - Override enable for rx_sqhs_en
*/
#define PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_OVRD_RX_SQHS_EN_MASK)
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_MASK (0x60U)
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_SHIFT (5U)
#define PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_SHIFT)) & PCIE_PHY_TRSV_REG06C_LN0_ANA_RX_SQ_VREF_820M_SEL_MASK)
/*! @} */
/*! @name TRSV_REG06D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_SHIFT (0U)
/*! LN0_RX_SQHS_DIFP_OC_EN - RX high-squelch diff-P offset calibration enable
*/
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFP_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_SHIFT (1U)
/*! LN0_OVRD_RX_SQHS_DIFP_OC_EN - Override enable for rx_sqhs_difp_oc_en
*/
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFP_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_ANA_RX_SQHS_DIFN_SKEWBUF_EN_MASK)
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_MASK (0x78U)
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_SHIFT (3U)
/*! LN0_RX_SQHS_DIFN_OC_CODE - RX high-squelch diff-N manual offset code
*/
#define PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_RX_SQHS_DIFN_OC_CODE_MASK)
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_MASK (0x80U)
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_SHIFT (7U)
/*! LN0_OVRD_RX_SQHS_DIFN_OC_CODE - Override enable for rx_sqhs_difn_oc_code
*/
#define PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06D_LN0_OVRD_RX_SQHS_DIFN_OC_CODE_MASK)
/*! @} */
/*! @name TRSV_REG06E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_SHIFT (0U)
/*! LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN - Fixed skew for PCIe/SATA Squelch
*/
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_SKEW_DEFAULT_EN_MASK)
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SHIFT (1U)
/*! LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN - Enable the high speed Squelch DIFP SKEW BUFFER
*/
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_SKEWBUF_EN_MASK)
#define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_MASK (0x3CU)
#define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_SHIFT (2U)
/*! LN0_RX_SQHS_DIFP_OC_CODE - RX squelch diff-P manual offset code
*/
#define PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_RX_SQHS_DIFP_OC_CODE_MASK)
#define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_MASK (0x40U)
#define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_SHIFT (6U)
/*! LN0_OVRD_RX_SQHS_DIFP_OC_CODE - Override enable for rx_sqhs_difp_oc_code
*/
#define PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_OVRD_RX_SQHS_DIFP_OC_CODE_MASK)
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_SHIFT (7U)
/*! LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN - RX high-squelch diff-P offset sign
*/
#define PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_SHIFT)) & PCIE_PHY_TRSV_REG06E_LN0_ANA_RX_SQHS_DIFP_OC_CODE_SIGN_MASK)
/*! @} */
/*! @name TRSV_REG06F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_SHIFT (0U)
/*! LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL - Selection of supply voltage of reference voltage for threshold calibration of HS SQ
*/
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_VREF_SUPPLY_SEL_MASK)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_MASK (0x6U)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_SHIFT (1U)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_BW_CTRL_MASK)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_SHIFT (3U)
/*! LN0_ANA_RX_SQHS_FILTER_EN - SQHS loss detector enable
*/
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_FILTER_EN_MASK)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_SHIFT (4U)
/*! LN0_ANA_RX_SQHS_TH_CTRL - RX squelch threshold voltage selection
*/
#define PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG06F_LN0_ANA_RX_SQHS_TH_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG070 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_MASK (0x7U)
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_SQLS_DIFN_TH_CTRL - DIFN in MPHY, LFPS in USB:
*/
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFN_TH_CTRL_MASK)
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_MASK (0x8U)
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_SHIFT (3U)
/*! LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL - RX DIFP detect signal selection for PRE_DATA_VALID and DATA_VALID signal
*/
#define PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_ANA_RX_SQLS_DIFP_FAST_ANA_SEL_MASK)
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_SHIFT (4U)
/*! LN0_RX_SQLS_DIFP_DET_EN - RX low-speed DIFP squelch enable
*/
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFP_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_SHIFT (5U)
/*! LN0_OVRD_RX_SQLS_DIFP_DET_EN - Override enable for rx_sqls_difp_det_en
*/
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFP_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_SHIFT (6U)
/*! LN0_RX_SQLS_DIFN_DET_EN - RX low-speed DIFN squelch enable
*/
#define PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_RX_SQLS_DIFN_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_SHIFT (7U)
/*! LN0_OVRD_RX_SQLS_DIFN_DET_EN - Override enable for rx_sqls_difn_det_en
*/
#define PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG070_LN0_OVRD_RX_SQLS_DIFN_DET_EN_MASK)
/*! @} */
/*! @name TRSV_REG071 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL - Current controls for low-speed Squelch comparator current source
*/
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_SCL2CMOS_I_CTRL_MASK)
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_SHIFT (2U)
/*! LN0_ANA_RX_SQLS_IN_LPF_CTRL - Low pass filter resistor control for Squelch input : 00:30MHz,01:60MHz,, 10:100MHz, 11: 150MHz
*/
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_IN_LPF_CTRL_MASK)
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_SHIFT (5U)
/*! LN0_ANA_RX_SQLS_DIFP_TH_CTRL - DIFP in MPHY
*/
#define PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG071_LN0_ANA_RX_SQLS_DIFP_TH_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG072 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_SHIFT (0U)
/*! LN0_RX_PWM_AFC_RSTN - RX MPHY PWM AFC reset
*/
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_AFC_RSTN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_SHIFT (1U)
/*! LN0_OVRD_RX_PWM_AFC_RSTN - Override enable for rx_pwm_afc_rstn
*/
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_AFC_RSTN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_SHIFT (2U)
/*! LN0_RX_PWM_RSTN - RX MPHY PWM reset
*/
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_RSTN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_SHIFT (3U)
/*! LN0_OVRD_RX_PWM_RSTN - Override enable for rx_pwm_rstn
*/
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_RSTN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_SHIFT (4U)
/*! LN0_RX_PWM_CNT_EN - Enalbe counter clock for PWM over sampling
*/
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_CNT_EN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_SHIFT (5U)
/*! LN0_OVRD_RX_PWM_CNT_EN - Override enable for rx_pwm_cnt_en
*/
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_CNT_EN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_SHIFT (6U)
/*! LN0_RX_PWM_OSC_EN - RX MPHY PWM oscillator enable which is used in analog RX block in order to oversample
*/
#define PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_RX_PWM_OSC_EN_MASK)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_SHIFT (7U)
/*! LN0_OVRD_RX_PWM_OSC_EN - Override enable for rx_pwm_osc_en
*/
#define PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_SHIFT)) & PCIE_PHY_TRSV_REG072_LN0_OVRD_RX_PWM_OSC_EN_MASK)
/*! @} */
/*! @name TRSV_REG073 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_MASK (0x7U)
#define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_SHIFT (0U)
/*! LN0_ANA_RX_PWM_DIV_RATIO - RX MPHY PWM oversampling clock divide ratio from PWM oscillator
*/
#define PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_ANA_RX_PWM_DIV_RATIO_MASK)
#define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_SHIFT (3U)
/*! LN0_RX_PWM_AFC_DONE - RX MPHY PWM AFC done signal
*/
#define PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_RX_PWM_AFC_DONE_MASK)
#define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_MASK (0x10U)
#define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_SHIFT (4U)
/*! LN0_OVRD_RX_PWM_AFC_DONE - Override enable for rx_pwm_afc_done
*/
#define PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG073_LN0_OVRD_RX_PWM_AFC_DONE_MASK)
/*! @} */
/*! @name TRSV_REG074 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_ANA_RX_PWM_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_SHIFT (1U)
/*! LN0_RX_PWM_OSC_CODE - RX MPHY PWM AFC code for oscillator
*/
#define PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_RX_PWM_OSC_CODE_MASK)
#define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_SHIFT (5U)
/*! LN0_OVRD_RX_PWM_OSC_CODE - Override enable for rx_pwm_osc_code
*/
#define PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG074_LN0_OVRD_RX_PWM_OSC_CODE_MASK)
/*! @} */
/*! @name TRSV_REG075 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_SHIFT (0U)
/*! LN0_ANA_RX_LFPS_LOSS_DET_EN - LFPS loss detector enable
*/
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_ANA_RX_LFPS_LOSS_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_SHIFT (1U)
/*! LN0_RX_LFPS_DET_EN - LFPS detector enable
*/
#define PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_RX_LFPS_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_SHIFT (2U)
/*! LN0_OVRD_RX_LFPS_DET_EN - Override enable for rx_lfps_det_en
*/
#define PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_OVRD_RX_LFPS_DET_EN_MASK)
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_MASK (0x78U)
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_SHIFT (3U)
/*! LN0_ANA_RX_PWM_OC_CODE - min(-7 or 0_111){maximum negative offset} - max(+7 or 1_111) {maximum positive offset}
*/
#define PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG075_LN0_ANA_RX_PWM_OC_CODE_MASK)
/*! @} */
/*! @name TRSV_REG076 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_SHIFT (0U)
/*! LN0_ANA_RX_SRLB_EN - Serial retimed loopback enable
*/
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SRLB_EN_MASK)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_SHIFT (1U)
/*! LN0_ANA_RX_LLB_EN - Line loopback enalble
*/
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_LLB_EN_MASK)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_SHIFT (2U)
/*! LN0_ANA_RX_SLB_EN - Serial loopback enable
*/
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_SLB_EN_MASK)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_MASK (0x38U)
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_SHIFT (3U)
/*! LN0_ANA_RX_BIAS_RMRES_CTRL - RX RMRES bias current control
*/
#define PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_ANA_RX_BIAS_RMRES_CTRL_MASK)
#define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_SHIFT (6U)
/*! LN0_RX_BIAS_EN - RX bias current enable
*/
#define PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_RX_BIAS_EN_MASK)
#define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_SHIFT (7U)
/*! LN0_OVRD_RX_BIAS_EN - Override enable for rx_bias_en
*/
#define PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_SHIFT)) & PCIE_PHY_TRSV_REG076_LN0_OVRD_RX_BIAS_EN_MASK)
/*! @} */
/*! @name TRSV_REG077 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_SHIFT (0U)
/*! LN0_ANA_RX_LLB_ITAIL_CTRL - Line loopback tail-current control
*/
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ITAIL_CTRL_MASK)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_SHIFT (2U)
/*! LN0_ANA_RX_LLB_DUTY_CTRL - Line loopback duty-ratio control
*/
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_DUTY_CTRL_MASK)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_SHIFT (5U)
/*! LN0_ANA_RX_LLB_ACCAP_EN - Line loopback path selection
*/
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_LLB_ACCAP_EN_MASK)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_MASK (0x40U)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_SHIFT (6U)
/*! LN0_ANA_RX_SRLB_DATA_EDGE_SEL - Serial retimed loopback path selection
*/
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_DATA_EDGE_SEL_MASK)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_MASK (0x80U)
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_SHIFT (7U)
/*! LN0_ANA_RX_SRLB_EVEN_ODD_SEL - Serial retimed loopback path selection
*/
#define PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_SHIFT)) & PCIE_PHY_TRSV_REG077_LN0_ANA_RX_SRLB_EVEN_ODD_SEL_MASK)
/*! @} */
/*! @name TRSV_REG078 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_SHIFT (0U)
/*! LN0_ANA_RX_ATB_EN - RX ATB enable
*/
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_ATB_EN_MASK)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_SHIFT (1U)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_CDR_CLK_MON_EN_MASK)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_MASK (0x4U)
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_SHIFT (2U)
/*! LN0_ANA_RX_LLB_RLOAD_CTRL - Line loopback load resistance control
*/
#define PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG078_LN0_ANA_RX_LLB_RLOAD_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG079 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_MASK (0x3FU)
#define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_SHIFT (0U)
/*! LN0_ANA_RX_ATB_SEL - When i_sfr_rx_atb_en=1 and i_sfr_rx_atb_sel<5>=0, RX AFE nodes are under monitoring.
*/
#define PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_SHIFT)) & PCIE_PHY_TRSV_REG079_LN0_ANA_RX_ATB_SEL_MASK)
/*! @} */
/*! @name TRSV_REG07A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_SHIFT (0U)
/*! LN0_ANA_RX_RESERVED - Reserved port
*/
#define PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_SHIFT)) & PCIE_PHY_TRSV_REG07A_LN0_ANA_RX_RESERVED_MASK)
/*! @} */
/*! @name TRSV_REG07B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_SHIFT (0U)
/*! LN0_RX_OC_EN - RX offset calibration tolerance for average value
*/
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_EN_MASK)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_MASK (0x6U)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_SHIFT (1U)
/*! LN0_RX_OC_TOL - RX offset calibration enable
*/
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TOL_MASK)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_MASK (0x18U)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_SHIFT (3U)
/*! LN0_RX_OC_CNT_SEL - RX SQ offset calibraiton counter selection for waiting time
*/
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_CNT_SEL_MASK)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_SHIFT (5U)
/*! LN0_RX_OC_TRIAL_CNT - RX offset calibration trial number selection
*/
#define PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_SHIFT)) & PCIE_PHY_TRSV_REG07B_LN0_RX_OC_TRIAL_CNT_MASK)
/*! @} */
/*! @name TRSV_REG07C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_FINAL_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_MASK (0x2U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_SHIFT (1U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_ADDER_ODD_FINAL_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_EVEN_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MASK (0x8U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SHIFT (3U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_EDGE_ODD_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_EVEN_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_MASK (0x20U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_SHIFT (5U)
/*! LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD - Bypass
*/
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_BYPASS_DFE_SA_ERR_ODD_MASK)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_SHIFT (6U)
/*! LN0_RX_OC_UPD_CNT_SEL - RX offset calibration code wating time selection for SA & CTLE only
*/
#define PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG07C_LN0_RX_OC_UPD_CNT_SEL_MASK)
/*! @} */
/*! @name TRSV_REG07D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_SHIFT (0U)
/*! LN0_RX_OC_DONE - RX offset calibration overide value
*/
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_DONE_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_SHIFT (1U)
/*! LN0_OVRD_RX_OC_DONE - Override enable for rx_oc_done
*/
#define PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_OVRD_RX_OC_DONE_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_MASK (0x4U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_SHIFT (2U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_ALL_RATE_MODE_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_SHIFT (3U)
/*! LN0_RX_OC_BYPASS_CTLE - Bypass offset calibration for CTLE
*/
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_CTLE_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_MASK (0x10U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_SHIFT (4U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFP_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_SHIFT (5U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_RX_SQ_DIFN_MASK)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_MASK (0x40U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_SHIFT (6U)
#define PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07D_LN0_RX_OC_BYPASS_DFE_ADDER_EVEN_INIT_MASK)
/*! @} */
/*! @name TRSV_REG07E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07E_LN0_RX_SSLMS_C0_INIT_MASK)
/*! @} */
/*! @name TRSV_REG07F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C2_SGN_INIT_MASK)
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_MASK (0x7EU)
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_SHIFT)) & PCIE_PHY_TRSV_REG07F_LN0_RX_SSLMS_C1_INIT_MASK)
/*! @} */
/*! @name TRSV_REG080 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C3_SGN_INIT_MASK)
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_MASK (0x3EU)
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_SHIFT)) & PCIE_PHY_TRSV_REG080_LN0_RX_SSLMS_C2_INIT_MASK)
/*! @} */
/*! @name TRSV_REG081 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C4_SGN_INIT_MASK)
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_MASK (0x3EU)
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_SHIFT)) & PCIE_PHY_TRSV_REG081_LN0_RX_SSLMS_C3_INIT_MASK)
/*! @} */
/*! @name TRSV_REG082 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_SHIFT)) & PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C5_SGN_INIT_MASK)
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_SHIFT)) & PCIE_PHY_TRSV_REG082_LN0_RX_SSLMS_C4_INIT_MASK)
/*! @} */
/*! @name TRSV_REG083 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_MASK (0x3U)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_SHIFT (0U)
/*! LN0_RX_SSLMS_C1_ADAP_SPEED - RX DFE SSLMS c1 adaptation speed selection
*/
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C1_ADAP_SPEED_MASK)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_MASK (0xCU)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_SHIFT (2U)
/*! LN0_RX_SSLMS_C0_ADAP_SPEED - RX DFE SSLMS c0 adaptation speed selection
*/
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C0_ADAP_SPEED_MASK)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_SHIFT (4U)
#define PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_SHIFT)) & PCIE_PHY_TRSV_REG083_LN0_RX_SSLMS_C5_INIT_MASK)
/*! @} */
/*! @name TRSV_REG084 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_MASK (0x3U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_GAIN_MASK)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_MASK (0xCU)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C1_ADAP_GAIN_MASK)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_MASK (0x30U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C0_ADAP_GAIN_MASK)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_SHIFT (6U)
/*! LN0_RX_SSLMS_C2_ADAP_SPEED - RX DFE SSLMS c2 adaptation speed selection
*/
#define PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_SHIFT)) & PCIE_PHY_TRSV_REG084_LN0_RX_SSLMS_C2_ADAP_SPEED_MASK)
/*! @} */
/*! @name TRSV_REG085 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_TOL_MASK)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_MASK (0xCU)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_SHIFT (2U)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_ADAP_STAB_MASK)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_MASK (0x10U)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_SHIFT (4U)
#define PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_SHIFT)) & PCIE_PHY_TRSV_REG085_LN0_RX_SSLMS_STAB_CONT_MASK)
/*! @} */
/*! @name TRSV_REG086 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_CONT_MASK)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_MASK (0x2U)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_SHIFT (1U)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_CHK_MASK)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_MASK (0xFCU)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_SHIFT (2U)
#define PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_SHIFT)) & PCIE_PHY_TRSV_REG086_LN0_RX_SSLMS_ADAP_COEF_SEL_MASK)
/*! @} */
/*! @name TRSV_REG087 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_MASK (0x1U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_SHIFT (0U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_HOLD_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_MASK (0x2U)
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SHIFT (1U)
/*! LN0_OVRD_RX_SSLMS_ADAP_HOLD - Override enable for rx_sslms_adap_hold
*/
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_HOLD_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_EN_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_SHIFT (3U)
/*! LN0_OVRD_RX_SSLMS_ADAP_EN - Override enable for rx_sslms_adap_en
*/
#define PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_OVRD_RX_SSLMS_ADAP_EN_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_RSTN_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_SHIFT (5U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_EN_MASK)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_MASK (0xC0U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_SHIFT (6U)
#define PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_SHIFT)) & PCIE_PHY_TRSV_REG087_LN0_RX_SSLMS_ADAP_TIMEOUT_SEL_MASK)
/*! @} */
/*! @name TRSV_REG088 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_SHIFT)) & PCIE_PHY_TRSV_REG088_LN0_RX_CDR_PMS_M_G1__8_MASK)
/*! @} */
/*! @name TRSV_REG089 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_SHIFT)) & PCIE_PHY_TRSV_REG089_LN0_RX_CDR_PMS_M_G1__7_0_MASK)
/*! @} */
/*! @name TRSV_REG08A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_SHIFT)) & PCIE_PHY_TRSV_REG08A_LN0_RX_CDR_PMS_M_G2__8_MASK)
/*! @} */
/*! @name TRSV_REG08B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08B_LN0_RX_CDR_PMS_M_G2__7_0_MASK)
/*! @} */
/*! @name TRSV_REG08C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_SHIFT)) & PCIE_PHY_TRSV_REG08C_LN0_RX_CDR_PMS_M_G3__8_MASK)
/*! @} */
/*! @name TRSV_REG08D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08D_LN0_RX_CDR_PMS_M_G3__7_0_MASK)
/*! @} */
/*! @name TRSV_REG08E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_SHIFT)) & PCIE_PHY_TRSV_REG08E_LN0_RX_CDR_PMS_M_G4__8_MASK)
/*! @} */
/*! @name TRSV_REG08F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_SHIFT)) & PCIE_PHY_TRSV_REG08F_LN0_RX_CDR_PMS_M_G4__7_0_MASK)
/*! @} */
/*! @name TRSV_REG090 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_MASK (0xFU)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_SHIFT (0U)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_STB_NUM_MASK)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_INIT_RSTN_MASK)
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_SHIFT (5U)
/*! LN0_OVRD_RX_CDR_AFC_INIT_RSTN - Override enable for rx_cdr_afc_init_rstn
*/
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_INIT_RSTN_MASK)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_SHIFT (6U)
#define PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_RX_CDR_AFC_RSTN_MASK)
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_SHIFT (7U)
/*! LN0_OVRD_RX_CDR_AFC_RSTN - Override enable for rx_cdr_afc_rstn
*/
#define PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG090_LN0_OVRD_RX_CDR_AFC_RSTN_MASK)
/*! @} */
/*! @name TRSV_REG091 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG091_LN0_RX_CDR_AFC_TOL_MASK)
/*! @} */
/*! @name TRSV_REG092 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG092_LN0_RX_CDR_AFC_VCO_CNT_RUN_NO_MASK)
/*! @} */
/*! @name TRSV_REG093 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_SHIFT)) & PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_FIX_CODE_MASK)
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_SHIFT)) & PCIE_PHY_TRSV_REG093_LN0_RX_CDR_AFC_VCO_CNT_WAIT_MASK)
/*! @} */
/*! @name TRSV_REG094 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_MASK (0x1U)
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_SHIFT (0U)
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_SHIFT)) & PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_MAN_BSEL_TIME_MASK)
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_SHIFT (1U)
#define PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_SHIFT)) & PCIE_PHY_TRSV_REG094_LN0_RX_CDR_AFC_PRESET_VCO_CNT_MASK)
/*! @} */
/*! @name TRSV_REG095 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_SHIFT)) & PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_BSEL_MASK)
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_SHIFT (1U)
#define PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_SHIFT)) & PCIE_PHY_TRSV_REG095_LN0_RX_CDR_AFC_MAN_BSEL_MASK)
/*! @} */
/*! @name TRSV_REG096 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_MASK (0x3FU)
#define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG096_LN0_RX_CDR_FBB_VCO_CNT_RUN_NO_MASK)
/*! @} */
/*! @name TRSV_REG097 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_SHIFT)) & PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_MAN_SEL_MASK)
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SHIFT (1U)
#define PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG097_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_MASK)
/*! @} */
/*! @name TRSV_REG098 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_MASK (0xFU)
#define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SHIFT (0U)
#define PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_SHIFT)) & PCIE_PHY_TRSV_REG098_LN0_RX_CDR_FBB_MAN_CODE_UPDC_MASK)
/*! @} */
/*! @name TRSV_REG099 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_MASK (0x3FU)
#define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_SHIFT (0U)
/*! LN0_RX_CDR_FBB_DELTA_CNT - Target delta number in VCO counter in CDR FBB cal mode
*/
#define PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_SHIFT)) & PCIE_PHY_TRSV_REG099_LN0_RX_CDR_FBB_DELTA_CNT_MASK)
/*! @} */
/*! @name TRSV_REG09A - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in PLL mode
*/
#define PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09A_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG09B - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09B_LN0_RX_CDR_FBB_PLL_MODE_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG09C - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_COARSE_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_COARSE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in coarse mode (high bandwidth)
*/
#define PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09C_LN0_RX_CDR_FBB_COARSE_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG09D - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_COARSE_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_COARSE_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09D_LN0_RX_CDR_FBB_COARSE_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG09E - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_FINE_CTRL_G2 - [GEN2]
*/
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_FINE_CTRL_G1 - [GEN1] RX CDR BBVCO FBB gain control in fine mode (low bandwidth)
*/
#define PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG09E_LN0_RX_CDR_FBB_FINE_CTRL_G1_MASK)
/*! @} */
/*! @name TRSV_REG09F - */
/*! @{ */
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_FINE_CTRL_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_FINE_CTRL_G3 - [GEN3]
*/
#define PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG09F_LN0_RX_CDR_FBB_FINE_CTRL_G3_MASK)
/*! @} */
/*! @name TRSV_REG0A0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G2 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G2_MASK)
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G1 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A0_LN0_RX_CDR_FBB_PLL_BW_DIFF_G1_MASK)
/*! @} */
/*! @name TRSV_REG0A1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G4_MASK)
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_PLL_BW_DIFF_G3 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A1_LN0_RX_CDR_FBB_PLL_BW_DIFF_G3_MASK)
/*! @} */
/*! @name TRSV_REG0A2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_HI_BW_DIFF_G2 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G2_MASK)
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_HI_BW_DIFF_G1 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A2_LN0_RX_CDR_FBB_HI_BW_DIFF_G1_MASK)
/*! @} */
/*! @name TRSV_REG0A3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_HI_BW_DIFF_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G4_MASK)
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_HI_BW_DIFF_G3 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A3_LN0_RX_CDR_FBB_HI_BW_DIFF_G3_MASK)
/*! @} */
/*! @name TRSV_REG0A4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_SHIFT (0U)
/*! LN0_RX_CDR_FBB_LO_BW_DIFF_G2 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_SHIFT)) & PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G2_MASK)
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_SHIFT (4U)
/*! LN0_RX_CDR_FBB_LO_BW_DIFF_G1 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_SHIFT)) & PCIE_PHY_TRSV_REG0A4_LN0_RX_CDR_FBB_LO_BW_DIFF_G1_MASK)
/*! @} */
/*! @name TRSV_REG0A5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_SHIFT (0U)
/*! LN0_RX_CDR_FBB_LO_BW_DIFF_G4 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_SHIFT)) & PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G4_MASK)
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_SHIFT (4U)
/*! LN0_RX_CDR_FBB_LO_BW_DIFF_G3 - [GEN4]
*/
#define PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_SHIFT)) & PCIE_PHY_TRSV_REG0A5_LN0_RX_CDR_FBB_LO_BW_DIFF_G3_MASK)
/*! @} */
/*! @name TRSV_REG0A6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A6_LN0_RX_CDR_PLL_VCO_CNT_RUN_NO_MASK)
/*! @} */
/*! @name TRSV_REG0A7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A7_LN0_RX_CDR_PLL_VCO_CNT_WAIT_NO_MASK)
/*! @} */
/*! @name TRSV_REG0A8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_RESTART_MASK)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_MODE_ENTRY_SRC_MASK)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_MASK (0x7CU)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_SHIFT)) & PCIE_PHY_TRSV_REG0A8_LN0_RX_CDR_PLL_LOCK_PPM_SET_MASK)
/*! @} */
/*! @name TRSV_REG0A9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_MASK (0x1FU)
#define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_SHIFT)) & PCIE_PHY_TRSV_REG0A9_LN0_RX_CDR_CK_VCO_CNT_RUN_NO_MASK)
/*! @} */
/*! @name TRSV_REG0AA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_SHIFT)) & PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_LOCK_SETTLE_NO_MASK)
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_MASK (0x78U)
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_SHIFT)) & PCIE_PHY_TRSV_REG0AA_LN0_RX_CDR_CK_VCO_CNT_WAIT_NO_MASK)
/*! @} */
/*! @name TRSV_REG0AB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_SHIFT (1U)
/*! LN0_OVRD_RX_CDR_CAL_DONE - Override enable for rx_cdr_cal_done
*/
#define PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_OVRD_RX_CDR_CAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_MASK (0x7CU)
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_SHIFT)) & PCIE_PHY_TRSV_REG0AB_LN0_RX_CDR_CK_LOCK_PPM_SET_MASK)
/*! @} */
/*! @name TRSV_REG0AC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_SHIFT)) & PCIE_PHY_TRSV_REG0AC_LN0_RX_PWM_TG_OSC_CNT_MIN_MASK)
/*! @} */
/*! @name TRSV_REG0AD - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_SHIFT)) & PCIE_PHY_TRSV_REG0AD_LN0_RX_PWM_TG_OSC_CNT_MAX_MASK)
/*! @} */
/*! @name TRSV_REG0AE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_STB_NUM_MASK)
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_SHIFT)) & PCIE_PHY_TRSV_REG0AE_LN0_RX_PWM_AFC_TOL_MASK)
/*! @} */
/*! @name TRSV_REG0AF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_SHIFT)) & PCIE_PHY_TRSV_REG0AF_LN0_RX_PWM_AFC_EN_MASK)
/*! @} */
/*! @name TRSV_REG0B0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_SHIFT (0U)
/*! LN0_OVRD_RX_EFOM_FEEDBACK - Override enable for
*/
#define PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_SHIFT)) & PCIE_PHY_TRSV_REG0B0_LN0_OVRD_RX_EFOM_FEEDBACK_MASK)
/*! @} */
/*! @name TRSV_REG0B1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0B1_LN0_RX_EFOM_FEEDBACK__15_8_MASK)
/*! @} */
/*! @name TRSV_REG0B2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0B2_LN0_RX_EFOM_FEEDBACK__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0B3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_START_MASK)
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_SHIFT (1U)
/*! LN0_OVRD_RX_EFOM_START - Override enable for rx_efom_start
*/
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_START_MASK)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_MODE_MASK)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_RX_EFOM_DONE_MASK)
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_SHIFT (6U)
/*! LN0_OVRD_RX_EFOM_DONE - Override enable for rx_efom_done
*/
#define PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0B3_LN0_OVRD_RX_EFOM_DONE_MASK)
/*! @} */
/*! @name TRSV_REG0B4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_V_WEIGHT_MASK)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_MASK (0xCU)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_H_WEIGHT_MASK)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_START_SSM_DISABLE_MASK)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_MASK (0xE0U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_SHIFT)) & PCIE_PHY_TRSV_REG0B4_LN0_RX_EFOM_VREF_RESOL_MASK)
/*! @} */
/*! @name TRSV_REG0B5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_EN_MASK)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_MASK (0xCU)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_BIT_WIDTH_SEL_MASK)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0B5_LN0_RX_EFOM_SETTLE_TIME_MASK)
/*! @} */
/*! @name TRSV_REG0B6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_MASK (0x3FU)
#define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_SHIFT)) & PCIE_PHY_TRSV_REG0B6_LN0_RX_EFOM_NUM_OF_SAMPLE__13_8_MASK)
/*! @} */
/*! @name TRSV_REG0B7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0B7_LN0_RX_EFOM_NUM_OF_SAMPLE__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0B8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_OUT_WIDTH_SEL_MASK)
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_MASK (0xEU)
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0B8_LN0_RX_EFOM_TRIAL_NUM_MASK)
/*! @} */
/*! @name TRSV_REG0B9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0B9_LN0_RX_EFOM_DFE_VREF_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG0BA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0BA_LN0_RX_EFOM_EOM_PH_SEL_MASK)
/*! @} */
/*! @name TRSV_REG0BB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_RETIMEDLB_EN_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_NEARLB_EN_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DB_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_FIX_DA_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_BYPASS_ERR_CHK_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_TXD_DESKEW_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_SHIFT (7U)
/*! LN0_OVRD_TXD_DESKEW_RSTN - Override enable for txd_deskew_rstn
*/
#define PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BB_LN0_OVRD_TXD_DESKEW_RSTN_MASK)
/*! @} */
/*! @name TRSV_REG0BC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_FLIP_BYTE_MASK)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_LOCK_NUM_MASK)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_WORD_MASK)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_HOLD_MASK)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_SHIFT)) & PCIE_PHY_TRSV_REG0BC_LN0_RXD_ALIGN_EN_MASK)
/*! @} */
/*! @name TRSV_REG0BD - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_DN_OPT_CODE_MASK)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_MASK (0xCU)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_UP_OPT_CODE_MASK)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_TX_RCAL_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_SHIFT (5U)
/*! LN0_OVRD_TX_RCAL_RSTN - Override enable for tx_rcal_rstn
*/
#define PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_OVRD_TX_RCAL_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_RXD_POLARITY_MASK)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_SHIFT)) & PCIE_PHY_TRSV_REG0BD_LN0_RXD_FLIP_BIT_MASK)
/*! @} */
/*! @name TRSV_REG0BE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_SHIFT (0U)
/*! LN0_TX_RCAL_DN_CODE - Termination down control bits. <3>bit is reserved bit., Default code= 011,Min code =000 and Max code is 111
*/
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_DN_CODE_MASK)
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_SHIFT (4U)
/*! LN0_TX_RCAL_UP_CODE - Termination up control bits. <3> bit is reserved bit., Default code = 011,Min code =000 and Max code is 111
*/
#define PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BE_LN0_TX_RCAL_UP_CODE_MASK)
/*! @} */
/*! @name TRSV_REG0BF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_OPT_CODE_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_RX_RCAL_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_SHIFT (3U)
/*! LN0_OVRD_RX_RCAL_RSTN - Override enable for rx_rcal_rstn
*/
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_RX_RCAL_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_SHIFT (4U)
/*! LN0_TX_RCAL_DONE - Monitoring for TX RCAL done
*/
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_SHIFT (5U)
/*! LN0_OVRD_TX_RCAL_DONE - Override enable for tx_rcal_done
*/
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_TX_RCAL_COMP_OUT_MASK)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_SHIFT (7U)
/*! LN0_OVRD_TX_RCAL_COMP_OUT - Override enable for tx_rcal_comp_out
*/
#define PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0BF_LN0_OVRD_TX_RCAL_COMP_OUT_MASK)
/*! @} */
/*! @name TRSV_REG0C0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_SHIFT (0U)
/*! LN0_RX_RCAL_DONE - RX RCAL done
*/
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_SHIFT (1U)
/*! LN0_OVRD_RX_RCAL_DONE - Override enable for rx_rcal_done
*/
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RCAL_COMP_OUT_MASK)
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_SHIFT (3U)
/*! LN0_OVRD_RX_RCAL_COMP_OUT - Override enable for rx_rcal_comp_out
*/
#define PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_OVRD_RX_RCAL_COMP_OUT_MASK)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_SHIFT (4U)
/*! LN0_RX_RTERM_CTRL - Termination Calibration will send control signals to make 42.5 ohms. MSB<4>=>1'b0=50,1'b1=42.5(default).
*/
#define PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0C0_LN0_RX_RTERM_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG0C1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_PRBS_MODE_MASK)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_MASK (0x1CU)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_SEED_SEL_MASK)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_MASK (0x60U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_COMDET_NUM_MASK)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_SHIFT)) & PCIE_PHY_TRSV_REG0C1_LN0_BIST_AUTO_RUN_MASK)
/*! @} */
/*! @name TRSV_REG0C2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_START_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_ERRINJ_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_TX_EN_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_START_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_HOLD_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_RX_EN_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_DATA_EN_MASK)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C2_LN0_BIST_EN_MASK)
/*! @} */
/*! @name TRSV_REG0C3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_SHIFT)) & PCIE_PHY_TRSV_REG0C3_LN0_BIST_USER_PAT_EN_MASK)
/*! @} */
/*! @name TRSV_REG0C4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_SHIFT)) & PCIE_PHY_TRSV_REG0C4_LN0_BIST_USER_PAT__79_72_MASK)
/*! @} */
/*! @name TRSV_REG0C5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_SHIFT)) & PCIE_PHY_TRSV_REG0C5_LN0_BIST_USER_PAT__71_64_MASK)
/*! @} */
/*! @name TRSV_REG0C6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_SHIFT)) & PCIE_PHY_TRSV_REG0C6_LN0_BIST_USER_PAT__63_56_MASK)
/*! @} */
/*! @name TRSV_REG0C7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_SHIFT)) & PCIE_PHY_TRSV_REG0C7_LN0_BIST_USER_PAT__55_48_MASK)
/*! @} */
/*! @name TRSV_REG0C8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_SHIFT)) & PCIE_PHY_TRSV_REG0C8_LN0_BIST_USER_PAT__47_40_MASK)
/*! @} */
/*! @name TRSV_REG0C9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_SHIFT)) & PCIE_PHY_TRSV_REG0C9_LN0_BIST_USER_PAT__39_32_MASK)
/*! @} */
/*! @name TRSV_REG0CA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_SHIFT)) & PCIE_PHY_TRSV_REG0CA_LN0_BIST_USER_PAT__31_24_MASK)
/*! @} */
/*! @name TRSV_REG0CB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_SHIFT)) & PCIE_PHY_TRSV_REG0CB_LN0_BIST_USER_PAT__23_16_MASK)
/*! @} */
/*! @name TRSV_REG0CC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0CC_LN0_BIST_USER_PAT__15_8_MASK)
/*! @} */
/*! @name TRSV_REG0CD - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0CD_LN0_BIST_USER_PAT__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0CE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_SHIFT (0U)
/*! LN0_LANE_MODE - Lane operation mode
*/
#define PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_LANE_MODE_MASK)
#define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_MASK (0xEU)
#define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_MASK)
#define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_MASK (0x30U)
#define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_SHIFT)) & PCIE_PHY_TRSV_REG0CE_LN0_RX_SIGVAL_LPF_BYPASS_MASK)
/*! @} */
/*! @name TRSV_REG0CF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_INV_MASK)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_RX_CLK_SRC_MASK)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_MISC_TX_CLK_SRC_MASK)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_LANE_TIMER_SEL_MASK)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_MASK (0x30U)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_LANE_RATE_MASK)
#define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_SHIFT (6U)
/*! LN0_OVRD_LANE_RATE - Override enable for lane_rate
*/
#define PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_SHIFT)) & PCIE_PHY_TRSV_REG0CF_LN0_OVRD_LANE_RATE_MASK)
/*! @} */
/*! @name TRSV_REG0D0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_TX_RXD_DETECTED_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_SHIFT (1U)
/*! LN0_OVRD_MISC_TX_RXD_DETECTED - Override enable for misc_tx_rxd_detected
*/
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_TX_RXD_DETECTED_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_LFPS_DET_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_SHIFT (3U)
/*! LN0_OVRD_MISC_RX_LFPS_DET - Override enable for misc_rx_lfps_det
*/
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_LFPS_DET_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_DATA_CLEAR_SRC_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_MISC_RX_SQHS_SIGVAL_MASK)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_SHIFT (6U)
/*! LN0_OVRD_MISC_RX_SQHS_SIGVAL - Override enable for misc_rx_sqhs_sigval
*/
#define PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_SHIFT)) & PCIE_PHY_TRSV_REG0D0_LN0_OVRD_MISC_RX_SQHS_SIGVAL_MASK)
/*! @} */
/*! @name TRSV_REG0D1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_SHIFT (0U)
/*! LN0_TG_RCAL_RSTN_DELAY_TIME - Rx Rcal reset delay time after PLL AFC done
*/
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_TG_RCAL_RSTN_DELAY_TIME_MASK)
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_MASK (0x38U)
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_SHIFT (3U)
/*! LN0_TG_CDR_BW_CTRL_DELAY_TIME - RX CDR bandwidth change time control
*/
#define PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_TG_CDR_BW_CTRL_DELAY_TIME_MASK)
#define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_MISC_RX_VALID_RSTN_MASK)
#define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_SHIFT (7U)
/*! LN0_OVRD_MISC_RX_VALID_RSTN - Override enable for misc_rx_valid_rstn
*/
#define PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_SHIFT)) & PCIE_PHY_TRSV_REG0D1_LN0_OVRD_MISC_RX_VALID_RSTN_MASK)
/*! @} */
/*! @name TRSV_REG0D2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_SHIFT)) & PCIE_PHY_TRSV_REG0D2_LN0_TG_RXD_COMP_DELAY_TIME_MASK)
/*! @} */
/*! @name TRSV_REG0D3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_MON_LANE_STATE_MASK)
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_SHIFT (4U)
/*! LN0_ANA_RX_SQLS_DIFP_DET - DIFP Detection signal
*/
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFP_DET_MASK)
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_SHIFT (5U)
/*! LN0_ANA_RX_SQLS_DIFN_DET - DIFN Detection signal
*/
#define PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_SHIFT)) & PCIE_PHY_TRSV_REG0D3_LN0_ANA_RX_SQLS_DIFN_DET_MASK)
/*! @} */
/*! @name TRSV_REG0D4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_SHIFT)) & PCIE_PHY_TRSV_REG0D4_LN0_MON_CDR_STATE_MASK)
/*! @} */
/*! @name TRSV_REG0D5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_SHIFT)) & PCIE_PHY_TRSV_REG0D5_LN0_MON_LANE_TIME__14_8_MASK)
/*! @} */
/*! @name TRSV_REG0D6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0D6_LN0_MON_LANE_TIME__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0D7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_FBB_FINE_CTRL_MASK)
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_SHIFT)) & PCIE_PHY_TRSV_REG0D7_LN0_MON_RX_CDR_AFC_SEL_LOGIC_MASK)
/*! @} */
/*! @name TRSV_REG0D8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_PLL_MODE_CTRL_MASK)
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D8_LN0_MON_RX_CDR_FBB_COARSE_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG0D9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_SHIFT)) & PCIE_PHY_TRSV_REG0D9_LN0_MON_RX_CDR_MODE_CTRL_MASK)
/*! @} */
/*! @name TRSV_REG0DA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0DA_LN0_MON_RX_OC_DFE_ADDER_EVEN_MASK)
/*! @} */
/*! @name TRSV_REG0DB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_DAC_ADDER_EVEN_MASK)
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_MASK (0xFEU)
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0DB_LN0_MON_RX_OC_DFE_ADDER_ODD_MASK)
/*! @} */
/*! @name TRSV_REG0DC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0DC_LN0_MON_RX_OC_DFE_DAC_ADDER_ODD_MASK)
/*! @} */
/*! @name TRSV_REG0DD - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_SHIFT)) & PCIE_PHY_TRSV_REG0DD_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__8_MASK)
/*! @} */
/*! @name TRSV_REG0DE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0DE_LN0_MON_RX_OC_DFE_SA_EDGE_EVEN__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0DF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_SHIFT)) & PCIE_PHY_TRSV_REG0DF_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__8_MASK)
/*! @} */
/*! @name TRSV_REG0E0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E0_LN0_MON_RX_OC_DFE_SA_EDGE_ODD__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0E1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_EVEN_MASK)
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_MASK (0x38U)
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0E1_LN0_MON_RX_OC_DFE_DAC_EDGE_ODD_MASK)
/*! @} */
/*! @name TRSV_REG0E2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_SHIFT)) & PCIE_PHY_TRSV_REG0E2_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__8_MASK)
/*! @} */
/*! @name TRSV_REG0E3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E3_LN0_MON_RX_OC_DFE_SA_ERR_EVEN__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0E4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_SHIFT)) & PCIE_PHY_TRSV_REG0E4_LN0_MON_RX_OC_DFE_SA_ERR_ODD__8_MASK)
/*! @} */
/*! @name TRSV_REG0E5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0E5_LN0_MON_RX_OC_DFE_SA_ERR_ODD__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0E6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_SHIFT)) & PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_ODD_MASK)
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_MASK (0x38U)
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_SHIFT)) & PCIE_PHY_TRSV_REG0E6_LN0_MON_RX_OC_DFE_DAC_ERR_EVEN_MASK)
/*! @} */
/*! @name TRSV_REG0E7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_MASK (0x7FU)
#define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_SHIFT)) & PCIE_PHY_TRSV_REG0E7_LN0_MON_RX_OC_CTLE_MASK)
/*! @} */
/*! @name TRSV_REG0E8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_SHIFT)) & PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFP_MASK)
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_SHIFT)) & PCIE_PHY_TRSV_REG0E8_LN0_MON_RX_OC_SQ_DIFN_MASK)
/*! @} */
/*! @name TRSV_REG0E9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0E9_LN0_MON_RX_OC_CAL_DONE_MASK)
/*! @} */
/*! @name TRSV_REG0EA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_MASK (0x3U)
#define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_SHIFT)) & PCIE_PHY_TRSV_REG0EA_LN0_MON_RX_OC_FAIL__9_8_MASK)
/*! @} */
/*! @name TRSV_REG0EB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0EB_LN0_MON_RX_OC_FAIL__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0EC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_SHIFT)) & PCIE_PHY_TRSV_REG0EC_LN0_MON_RX_SSLMS_C0__8_MASK)
/*! @} */
/*! @name TRSV_REG0ED - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0ED_LN0_MON_RX_SSLMS_C0__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0EE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C2_SGN_MASK)
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_MASK (0xFEU)
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_SHIFT)) & PCIE_PHY_TRSV_REG0EE_LN0_MON_RX_SSLMS_C1_MASK)
/*! @} */
/*! @name TRSV_REG0EF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C3_SGN_MASK)
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_MASK (0x3EU)
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_SHIFT)) & PCIE_PHY_TRSV_REG0EF_LN0_MON_RX_SSLMS_C2_MASK)
/*! @} */
/*! @name TRSV_REG0F0 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C4_SGN_MASK)
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_MASK (0x3EU)
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_SHIFT)) & PCIE_PHY_TRSV_REG0F0_LN0_MON_RX_SSLMS_C3_MASK)
/*! @} */
/*! @name TRSV_REG0F1 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_SHIFT)) & PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C5_SGN_MASK)
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_SHIFT)) & PCIE_PHY_TRSV_REG0F1_LN0_MON_RX_SSLMS_C4_MASK)
/*! @} */
/*! @name TRSV_REG0F2 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_EFOM_DONE_MASK)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_ADAP_DONE_MASK)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_MASK (0x3CU)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_SHIFT)) & PCIE_PHY_TRSV_REG0F2_LN0_MON_RX_SSLMS_C5_MASK)
/*! @} */
/*! @name TRSV_REG0F3 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_MASK (0x3FU)
#define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_SHIFT)) & PCIE_PHY_TRSV_REG0F3_LN0_MON_RX_EFOM_ERR_CNT__13_8_MASK)
/*! @} */
/*! @name TRSV_REG0F4 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0F4_LN0_MON_RX_EFOM_ERR_CNT__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0F5 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_SHIFT)) & PCIE_PHY_TRSV_REG0F5_LN0_MON_RX_EFOM_FEEDBACK__15_8_MASK)
/*! @} */
/*! @name TRSV_REG0F6 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_SHIFT)) & PCIE_PHY_TRSV_REG0F6_LN0_MON_RX_EFOM_FEEDBACK__7_0_MASK)
/*! @} */
/*! @name TRSV_REG0F7 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_MASK (0x1EU)
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F7_LN0_MON_TX_RCAL_TUNE_CODE_MASK)
/*! @} */
/*! @name TRSV_REG0F8 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_REPEAT_MASK)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_FAIL_MASK)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_PWM_AFC_DONE_MASK)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_MASK (0xF0U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F8_LN0_MON_RX_RCAL_TUNE_CODE_MASK)
/*! @} */
/*! @name TRSV_REG0F9 - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_MASK (0xFU)
#define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_SHIFT)) & PCIE_PHY_TRSV_REG0F9_LN0_MON_RX_PWM_AFC_CODE_MASK)
/*! @} */
/*! @name TRSV_REG0FA - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_MASK (0x1U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_START_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_MASK (0x2U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_SHIFT (1U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_ERRINJ_TEST_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_MASK (0x4U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_SHIFT (2U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_BIST_COMP_TEST_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_LOCK_DONE_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_MASK (0x10U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_MASK (0x20U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_SHIFT (5U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_CAL_DONE_MASK)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_MASK (0x40U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_SHIFT (6U)
#define PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_SHIFT)) & PCIE_PHY_TRSV_REG0FA_LN0_MON_RX_CDR_AFC_DONE_MASK)
/*! @} */
/*! @name TRSV_REG0FB - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_MASK (0xFFU)
#define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_SHIFT)) & PCIE_PHY_TRSV_REG0FB_LN0_MON_BIST_EOUT_MASK)
/*! @} */
/*! @name TRSV_REG0FC - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G2_MASK)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_MASK (0x70U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_CTRL_G1_MASK)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FC_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG0FD - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G4_MASK)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_MASK (0x8U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_SHIFT (3U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_MASK (0x70U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_CTRL_G3_MASK)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_MASK (0x80U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_SHIFT (7U)
#define PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FD_LN0_ANA_TX_DRV_ACCDRV_POL_SEL_G3_MASK)
/*! @} */
/*! @name TRSV_REG0FE - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_SHIFT)) & PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G2_MASK)
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_MASK (0x70U)
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_SHIFT)) & PCIE_PHY_TRSV_REG0FE_LN0_ANA_RX_CDR_AFC_VCI_SEL_G1_MASK)
/*! @} */
/*! @name TRSV_REG0FF - */
/*! @{ */
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_MASK (0x7U)
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_SHIFT (0U)
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_SHIFT)) & PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G4_MASK)
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_MASK (0x70U)
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_SHIFT (4U)
#define PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3(x) (((uint8_t)(((uint8_t)(x)) << PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_SHIFT)) & PCIE_PHY_TRSV_REG0FF_LN0_ANA_RX_CDR_AFC_VCI_SEL_G3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PCIE_PHY_Register_Masks */
/* PCIE_PHY - Peripheral instance base addresses */
/** Peripheral PCIE_PHY base address */
#define PCIE_PHY_BASE (0x32F00000u)
/** Peripheral PCIE_PHY base pointer */
#define PCIE_PHY ((PCIE_PHY_Type *)PCIE_PHY_BASE)
/** Array initializer of PCIE_PHY peripheral base addresses */
#define PCIE_PHY_BASE_ADDRS { PCIE_PHY_BASE }
/** Array initializer of PCIE_PHY peripheral base pointers */
#define PCIE_PHY_BASE_PTRS { PCIE_PHY }
/*!
* @}
*/ /* end of group PCIE_PHY_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PDM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
* @{
*/
/** PDM - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL_1; /**< MICFIL Control register 1, offset: 0x0 */
__IO uint32_t CTRL_2; /**< MICFIL Control register 2, offset: 0x4 */
__IO uint32_t STAT; /**< MICFIL Status register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control register, offset: 0x10 */
__IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status register, offset: 0x14 */
uint8_t RESERVED_1[12];
__I uint32_t DATACH[8]; /**< MICFIL Output Result Register, array offset: 0x24, array step: 0x4 */
uint8_t RESERVED_2[32];
__IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control register, offset: 0x64 */
uint8_t RESERVED_3[12];
__IO uint32_t RANGE_CTRL; /**< MICFIL Range Control register, offset: 0x74 */
uint8_t RESERVED_4[4];
__IO uint32_t RANGE_STAT; /**< MICFIL Range Status register, offset: 0x7C */
uint8_t RESERVED_5[16];
__IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector Control register, offset: 0x90 */
__IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector Control register, offset: 0x94 */
__IO uint32_t VAD0_STAT; /**< Voice Activity Detector Status register, offset: 0x98 */
__IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector Signal Configuration, offset: 0x9C */
__IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector Noise Configuration, offset: 0xA0 */
__I uint32_t VAD0_NDATA; /**< Voice Activity Detector Noise Data, offset: 0xA4 */
__IO uint32_t VAD0_ZCD; /**< Voice Activity Detector Zero-Crossing Detector, offset: 0xA8 */
} PDM_Type;
/* ----------------------------------------------------------------------------
-- PDM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDM_Register_Masks PDM Register Masks
* @{
*/
/*! @name CTRL_1 - MICFIL Control register 1 */
/*! @{ */
#define PDM_CTRL_1_CH0EN_MASK (0x1U)
#define PDM_CTRL_1_CH0EN_SHIFT (0U)
/*! CH0EN - Channel 0 Enable
*/
#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
#define PDM_CTRL_1_CH1EN_MASK (0x2U)
#define PDM_CTRL_1_CH1EN_SHIFT (1U)
/*! CH1EN - Channel 1 Enable
*/
#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
#define PDM_CTRL_1_CH2EN_MASK (0x4U)
#define PDM_CTRL_1_CH2EN_SHIFT (2U)
/*! CH2EN - Channel 2 Enable
*/
#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
#define PDM_CTRL_1_CH3EN_MASK (0x8U)
#define PDM_CTRL_1_CH3EN_SHIFT (3U)
/*! CH3EN - Channel 3 Enable
*/
#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
#define PDM_CTRL_1_CH4EN_MASK (0x10U)
#define PDM_CTRL_1_CH4EN_SHIFT (4U)
/*! CH4EN - Channel 4 Enable
*/
#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
#define PDM_CTRL_1_CH5EN_MASK (0x20U)
#define PDM_CTRL_1_CH5EN_SHIFT (5U)
/*! CH5EN - Channel 5 Enable
*/
#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
#define PDM_CTRL_1_CH6EN_MASK (0x40U)
#define PDM_CTRL_1_CH6EN_SHIFT (6U)
/*! CH6EN - Channel 6 Enable
*/
#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
#define PDM_CTRL_1_CH7EN_MASK (0x80U)
#define PDM_CTRL_1_CH7EN_SHIFT (7U)
/*! CH7EN - Channel 7 Enable
*/
#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
#define PDM_CTRL_1_ERREN_MASK (0x800000U)
#define PDM_CTRL_1_ERREN_SHIFT (23U)
/*! ERREN - Error Interruption Enable
* 0b0..Error Interrupts disabled
* 0b1..Error Interrupts enabled
*/
#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
#define PDM_CTRL_1_DISEL_MASK (0x3000000U)
#define PDM_CTRL_1_DISEL_SHIFT (24U)
/*! DISEL - DMA Interrupt Selection
* 0b00..DMA and interrupt requests disabled
* 0b01..DMA requests enabled
* 0b10..Interrupt requests enabled
* 0b11..Reserved
*/
#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
#define PDM_CTRL_1_DBGE_MASK (0x4000000U)
#define PDM_CTRL_1_DBGE_SHIFT (26U)
/*! DBGE - Module Enable in Debug
* 0b0..PDM Interface is disabled in debug mode, after completing the current frame.
* 0b1..PDM Interface is enabled in debug mode.
*/
#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
#define PDM_CTRL_1_SRES_MASK (0x8000000U)
#define PDM_CTRL_1_SRES_SHIFT (27U)
/*! SRES - Software-reset bit
* 0b0..No action
* 0b1..Software reset
*/
#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
#define PDM_CTRL_1_DBG_MASK (0x10000000U)
#define PDM_CTRL_1_DBG_SHIFT (28U)
/*! DBG - Debug Mode
* 0b0..PDM Interface is in Normal Mode.
* 0b1..PDM Interface is in Debug Mode.
*/
#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U)
#define PDM_CTRL_1_PDMIEN_SHIFT (29U)
/*! PDMIEN - PDM Inteface Enable
* 0b0..PDM Interface disabled
* 0b1..PDM Interface enabled.
*/
#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
#define PDM_CTRL_1_DOZEN_MASK (0x40000000U)
#define PDM_CTRL_1_DOZEN_SHIFT (30U)
/*! DOZEN - DOZE enable
* 0b0..DOZE enable bit is not asserted
* 0b1..DOZE enable bit is asserted
*/
#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
#define PDM_CTRL_1_MDIS_MASK (0x80000000U)
#define PDM_CTRL_1_MDIS_SHIFT (31U)
/*! MDIS - Module Disable
* 0b0..Normal Mode
* 0b1..Disable/Low Leakage Mode
*/
#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
/*! @} */
/*! @name CTRL_2 - MICFIL Control register 2 */
/*! @{ */
#define PDM_CTRL_2_CLKDIV_MASK (0xFFU)
#define PDM_CTRL_2_CLKDIV_SHIFT (0U)
/*! CLKDIV - Clock Divider
*/
#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
#define PDM_CTRL_2_CICOSR_MASK (0xF0000U)
#define PDM_CTRL_2_CICOSR_SHIFT (16U)
/*! CICOSR - CIC Oversampling Rate
*/
#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
#define PDM_CTRL_2_QSEL_MASK (0xE000000U)
#define PDM_CTRL_2_QSEL_SHIFT (25U)
/*! QSEL - Quality Select
* 0b001..High quality mode.
* 0b000..Medium quality mode.
* 0b111..Low quality mode.
* 0b110..Very low quality 0 mode.
* 0b101..Very low quality 1 mode.
* 0b100..Very low quality 2 mode.
*/
#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
/*! @} */
/*! @name STAT - MICFIL Status register */
/*! @{ */
#define PDM_STAT_CH0F_MASK (0x1U)
#define PDM_STAT_CH0F_SHIFT (0U)
/*! CH0F - Channel 0 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
#define PDM_STAT_CH1F_MASK (0x2U)
#define PDM_STAT_CH1F_SHIFT (1U)
/*! CH1F - Channel 1 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
#define PDM_STAT_CH2F_MASK (0x4U)
#define PDM_STAT_CH2F_SHIFT (2U)
/*! CH2F - Channel 2 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
#define PDM_STAT_CH3F_MASK (0x8U)
#define PDM_STAT_CH3F_SHIFT (3U)
/*! CH3F - Channel 3 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
#define PDM_STAT_CH4F_MASK (0x10U)
#define PDM_STAT_CH4F_SHIFT (4U)
/*! CH4F - Channel 4 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
#define PDM_STAT_CH5F_MASK (0x20U)
#define PDM_STAT_CH5F_SHIFT (5U)
/*! CH5F - Channel 5 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
#define PDM_STAT_CH6F_MASK (0x40U)
#define PDM_STAT_CH6F_SHIFT (6U)
/*! CH6F - Channel 6 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
#define PDM_STAT_CH7F_MASK (0x80U)
#define PDM_STAT_CH7F_SHIFT (7U)
/*! CH7F - Channel 7 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
*/
#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
#define PDM_STAT_LOWFREQF_MASK (0x20000000U)
#define PDM_STAT_LOWFREQF_SHIFT (29U)
/*! LOWFREQF - Low Frequency Flag
* 0b0..CLKDIV value is OK.
* 0b1..CLKDIV value is too low.
*/
#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
#define PDM_STAT_FIR_RDY_MASK (0x40000000U)
#define PDM_STAT_FIR_RDY_SHIFT (30U)
/*! FIR_RDY - FIR Filter Data Ready
* 0b0..FIR Filter data not reliable.
* 0b1..FIR Filter data reliable.
*/
#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
#define PDM_STAT_BSY_FIL_MASK (0x80000000U)
#define PDM_STAT_BSY_FIL_SHIFT (31U)
/*! BSY_FIL - Decimation Filter Busy Flag
* 0b1..At least one Decimation Filter channel is running.
* 0b0..All Decimation Filters are stopped.
*/
#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
/*! @} */
/*! @name FIFO_CTRL - MICFIL FIFO Control register */
/*! @{ */
#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x1FU)
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U)
/*! FIFOWMK - FIFO Watermark Control
*/
#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/*! @} */
/*! @name FIFO_STAT - MICFIL FIFO Status register */
/*! @{ */
#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U)
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U)
/*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U)
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U)
/*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U)
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U)
/*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U)
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U)
/*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U)
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U)
/*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U)
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U)
/*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U)
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U)
/*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U)
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U)
/*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U)
#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U)
/*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U)
#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U)
/*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U)
#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U)
/*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U)
#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U)
/*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U)
#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U)
/*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U)
#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U)
/*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U)
#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U)
/*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U)
#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U)
/*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
/*! @} */
/*! @name DATACH - MICFIL Output Result Register */
/*! @{ */
#define PDM_DATACH_DATA_MASK (0xFFFFFFFFU)
#define PDM_DATACH_DATA_SHIFT (0U)
/*! DATA - Channel n Data
*/
#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
/*! @} */
/* The count of PDM_DATACH */
#define PDM_DATACH_COUNT (8U)
/*! @name DC_CTRL - MICFIL DC Remover Control register */
/*! @{ */
#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U)
#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU)
#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U)
#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U)
#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U)
#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U)
#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U)
#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U)
#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
* 0b11..DC Remover is bypassed.
* 0b00..DC Remover cut-off at 21Hz.
* 0b01..DC Remover cut-off at 83Hz.
* 0b10..DC Remover cut-off at 152Hz.
*/
#define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
/*! @} */
/*! @name RANGE_CTRL - MICFIL Range Control register */
/*! @{ */
#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU)
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U)
/*! RANGEADJ0 - Channel 0 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U)
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U)
/*! RANGEADJ1 - Channel 1 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U)
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U)
/*! RANGEADJ2 - Channel 2 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U)
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U)
/*! RANGEADJ3 - Channel 3 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
#define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U)
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U)
/*! RANGEADJ4 - Channel 4 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
#define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U)
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U)
/*! RANGEADJ5 - Channel 5 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
#define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U)
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U)
/*! RANGEADJ6 - Channel 6 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
#define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U)
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U)
/*! RANGEADJ7 - Channel 7 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
/*! @} */
/*! @name RANGE_STAT - MICFIL Range Status register */
/*! @{ */
#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U)
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U)
/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U)
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U)
/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U)
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U)
/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U)
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U)
/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
#define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U)
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U)
/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
#define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U)
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U)
/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
#define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U)
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U)
/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
#define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U)
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U)
/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
* 0b0..No exception by range overflow.
* 0b1..Exception by range overflow.
*/
#define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U)
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U)
/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U)
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U)
/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U)
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U)
/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U)
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U)
/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
#define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U)
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U)
/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
#define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U)
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U)
/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
#define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U)
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U)
/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
#define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U)
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U)
/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
* 0b0..No exception by range underflow.
* 0b1..Exception by range underflow.
*/
#define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
/*! @} */
/*! @name VAD0_CTRL_1 - Voice Activity Detector Control register */
/*! @{ */
#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U)
#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U)
/*! VADEN - Voice Activity Detector Enable
* 0b0..The HWVAD is disabled.
* 0b1..The HWVAD is enabled.
*/
#define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U)
#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U)
/*! VADRST - Voice Activity Detector Reset
*/
#define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U)
#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U)
/*! VADIE - Voice Activity Detector Interruption Enable
* 0b0..HWVAD Interrupts disabled
* 0b1..HWVAD Interrupts enabled
*/
#define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U)
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U)
/*! VADERIE - Voice Activity Detector Error Interruption Enable
* 0b0..HWVAD Error Interrupts disabled
* 0b1..HWVAD Error Interrupts enabled
*/
#define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U)
#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U)
/*! VADST10 - Voice Activity Detector Internal Filters Initialization
* 0b0..Normal operation.
* 0b1..Filters are initialized.
*/
#define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U)
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U)
/*! VADINITT - Voice Activity Detector Initialization Time
*/
#define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U)
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U)
/*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate
*/
#define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U)
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U)
/*! VADCHSEL - Voice Activity Detector Channel Selector
*/
#define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
/*! @} */
/*! @name VAD0_CTRL_2 - Voice Activity Detector Control register */
/*! @{ */
#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U)
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U)
/*! VADHPF - Voice Activity Detector High-Pass Filter
* 0b00..Filter bypassed.
* 0b01..Cut-off frequency at 1750Hz.
* 0b10..Cut-off frequency at 215Hz.
* 0b11..Cut-off frequency at 102Hz.
*/
#define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U)
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U)
/*! VADINPGAIN - Voice Activity Detector Input Gain
*/
#define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U)
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U)
/*! VADFRAMET - Voice Activity Detector Frame Time
*/
#define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U)
/*! VADFOUTDIS - Voice Activity Detector Force Output Disable
* 0b0..Output is enabled.
* 0b1..Output is disabled.
*/
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U)
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U)
/*! VADPREFEN - Voice Activity Detector Pre Filter Enable
* 0b0..Pre-filter is bypassed.
* 0b1..Pre-filter is enabled.
*/
#define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U)
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U)
/*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
* 0b1..Frame energy calculus disabled.
* 0b0..Frame energy calculus enabled.
*/
#define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
/*! @} */
/*! @name VAD0_STAT - Voice Activity Detector Status register */
/*! @{ */
#define PDM_VAD0_STAT_VADIF_MASK (0x1U)
#define PDM_VAD0_STAT_VADIF_SHIFT (0U)
/*! VADIF - Voice Activity Detector Interrupt Flag
* 0b0..Voice activity has not been detected by the HWVAD.
* 0b1..Voice activity has been detected by the HWVAD.
*/
#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
#define PDM_VAD0_STAT_VADEF_MASK (0x8000U)
#define PDM_VAD0_STAT_VADEF_SHIFT (15U)
/*! VADEF - Voice Activity Detector Event Flag
* 0b0..Voice activity has not been detected by the HWVAD.
* 0b1..Voice activity has been detected by the HWVAD.
*/
#define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U)
#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U)
/*! VADINSATF - Voice Activity Detector Input Saturation Flag
* 0b0..No exception by HWVAD input saturation.
* 0b1..Exception by HWVAD input saturation.
*/
#define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U)
#define PDM_VAD0_STAT_VADINITF_SHIFT (31U)
/*! VADINITF - Voice Activity Detector Initialization Flag
* 0b0..HWVAD is not being initialized.
* 0b1..HWVAD is being initialized.
*/
#define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
/*! @} */
/*! @name VAD0_SCONFIG - Voice Activity Detector Signal Configuration */
/*! @{ */
#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU)
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U)
/*! VADSGAIN - Voice Activity Detector Signal Gain
*/
#define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U)
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U)
/*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
* 0b0..Maximum block is bypassed.
* 0b1..Maximum block is enabled.
*/
#define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U)
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U)
/*! VADSFILEN - Voice Activity Detector Signal Filter Enable
* 0b0..Signal filter is disabled.
* 0b1..Signal filter is enabled.
*/
#define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/*! @} */
/*! @name VAD0_NCONFIG - Voice Activity Detector Noise Configuration */
/*! @{ */
#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU)
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U)
/*! VADNGAIN - Voice Activity Detector Noise Gain
*/
#define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U)
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U)
/*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment
*/
#define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U)
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U)
/*! VADNOREN - Voice Activity Detector Noise OR Enable
* 0b0..Noise input is not decimated.
* 0b1..Noise input is decimated.
*/
#define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U)
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U)
/*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
* 0b0..Noise input is not decimated.
* 0b1..Noise input is decimated.
*/
#define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U)
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U)
/*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
* 0b0..Minimum block is bypassed.
* 0b1..Minimum block is enabled.
*/
#define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U)
/*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
* 0b0..Noise filter is always enabled.
* 0b1..Noise filter is enabled/disabled based on voice activity information.
*/
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
/*! @} */
/*! @name VAD0_NDATA - Voice Activity Detector Noise Data */
/*! @{ */
#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU)
#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U)
/*! VADNDATA - Voice Activity Detector Noise Data
*/
#define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
/*! @} */
/*! @name VAD0_ZCD - Voice Activity Detector Zero-Crossing Detector */
/*! @{ */
#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U)
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U)
/*! VADZCDEN - Zero-Crossing Detector Enable
* 0b0..The ZCD is disabled.
* 0b1..The ZCD is enabled.
*/
#define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U)
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U)
/*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
* 0b0..The ZCD threshold is not estimated automatically,
* 0b1..The ZCD threshold is estimated automatically.
*/
#define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U)
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U)
/*! VADZCDAND - Zero-Crossing Detector AND Behavior
* 0b0..The ZCD result is OR'ed with the energy-based detection.
* 0b1..The ZCD result is AND'ed with the energy-based detection.
*/
#define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U)
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U)
/*! VADZCDADJ - Zero-Crossing Detector Adjustment
*/
#define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U)
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U)
/*! VADZCDTH - Zero-Crossing Detector Threshold
*/
#define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PDM_Register_Masks */
/* PDM - Peripheral instance base addresses */
/** Peripheral PDM base address */
#define PDM_BASE (0x30CA0000u)
/** Peripheral PDM base pointer */
#define PDM ((PDM_Type *)PDM_BASE)
/** Array initializer of PDM peripheral base addresses */
#define PDM_BASE_ADDRS { PDM_BASE }
/** Array initializer of PDM peripheral base pointers */
#define PDM_BASE_PTRS { PDM }
/*!
* @}
*/ /* end of group PDM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PHYCONFIGURATION Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PHYCONFIGURATION_Peripheral_Access_Layer PHYCONFIGURATION Peripheral Access Layer
* @{
*/
/** PHYCONFIGURATION - Register Layout Typedef */
typedef struct {
__IO uint8_t PHY_CONF0; /**< PHY Configuration Register This register holds the power down, data enable polarity, and interface control of the HDMI Source PHY control., offset: 0x0 */
__IO uint8_t PHY_TST0; /**< PHY Test Interface Register 0 PHY TX mapped test interface (control)., offset: 0x1 */
__IO uint8_t PHY_TST1; /**< PHY Test Interface Register 1 PHY TX mapped text interface (data in)., offset: 0x2 */
__I uint8_t PHY_TST2; /**< PHY Test Interface Register 2 PHY TX mapped text interface (data out)., offset: 0x3 */
__I uint8_t PHY_STAT0; /**< PHY RXSENSE, PLL Lock, and HPD Status Register This register contains the following active high packet sent status indications., offset: 0x4 */
__I uint8_t PHY_INT0; /**< PHY RXSENSE, PLL Lock, and HPD Interrupt Register This register contains the interrupt indication of the PHY_STAT0 status interrupts., offset: 0x5 */
__IO uint8_t PHY_MASK0; /**< PHY RXSENSE, PLL Lock, and HPD Mask Register Mask register for generation of PHY_INT0 interrupts., offset: 0x6 */
__IO uint8_t PHY_POL0; /**< PHY RXSENSE, PLL Lock, and HPD Polarity Register Polarity register for generation of PHY_INT0 interrupts., offset: 0x7 */
uint8_t RESERVED_0[24];
__IO uint8_t PHY_I2CM_SLAVE; /**< PHY I2C Slave Address Configuration Register, offset: 0x20 */
__IO uint8_t PHY_I2CM_ADDRESS; /**< PHY I2C Address Configuration Register This register writes the address for read and write operations., offset: 0x21 */
__IO uint8_t PHY_I2CM_DATAO_1; /**< PHY I2C Data Write Register 1, offset: 0x22 */
__IO uint8_t PHY_I2CM_DATAO_0; /**< PHY I2C Data Write Register 0, offset: 0x23 */
__I uint8_t PHY_I2CM_DATAI_1; /**< PHY I2C Data Read Register 1, offset: 0x24 */
__I uint8_t PHY_I2CM_DATAI_0; /**< PHY I2C Data Read Register 0, offset: 0x25 */
__O uint8_t PHY_I2CM_OPERATION; /**< PHY I2C RD/RD_EXT/WR Operation Register This register requests read and write operations from the I2C Master PHY., offset: 0x26 */
__IO uint8_t PHY_I2CM_INT; /**< PHY I2C Done Interrupt Register This register contains and configures I2C master PHY done interrupt., offset: 0x27 */
__IO uint8_t PHY_I2CM_CTLINT; /**< PHY I2C error Interrupt Register This register contains and configures the I2C master PHY error interrupts., offset: 0x28 */
__IO uint8_t PHY_I2CM_DIV; /**< PHY I2C Speed control Register This register wets the I2C Master PHY to work in either Fast or Standard mode., offset: 0x29 */
__IO uint8_t PHY_I2CM_SOFTRSTZ; /**< PHY I2C SW reset control register This register sets the I2C Master PHY software reset., offset: 0x2A */
__IO uint8_t PHY_I2CM_SS_SCL_HCNT_1_ADDR; /**< PHY I2C Slow Speed SCL High Level Control Register 1, offset: 0x2B */
__IO uint8_t PHY_I2CM_SS_SCL_HCNT_0_ADDR; /**< PHY I2C Slow Speed SCL High Level Control Register 0, offset: 0x2C */
__IO uint8_t PHY_I2CM_SS_SCL_LCNT_1_ADDR; /**< PHY I2C Slow Speed SCL Low Level Control Register 1, offset: 0x2D */
__IO uint8_t PHY_I2CM_SS_SCL_LCNT_0_ADDR; /**< PHY I2C Slow Speed SCL Low Level Control Register 0, offset: 0x2E */
__IO uint8_t PHY_I2CM_FS_SCL_HCNT_1_ADDR; /**< PHY I2C Fast Speed SCL High Level Control Register 1, offset: 0x2F */
__IO uint8_t PHY_I2CM_FS_SCL_HCNT_0_ADDR; /**< PHY I2C Fast Speed SCL High Level Control Register 0, offset: 0x30 */
__IO uint8_t PHY_I2CM_FS_SCL_LCNT_1_ADDR; /**< PHY I2C Fast Speed SCL Low Level Control Register 1, offset: 0x31 */
__IO uint8_t PHY_I2CM_FS_SCL_LCNT_0_ADDR; /**< PHY I2C Fast Speed SCL Low Level Control Register 0, offset: 0x32 */
__IO uint8_t PHY_I2CM_SDA_HOLD; /**< PHY I2C SDA HOLD Control Register, offset: 0x33 */
__IO uint8_t JTAG_PHY_CONFIG; /**< PHY I2C/JTAG I/O Configuration Control Register, offset: 0x34 */
__IO uint8_t JTAG_PHY_TAP_TCK; /**< PHY JTAG Clock Control Register, offset: 0x35 */
__IO uint8_t JTAG_PHY_TAP_IN; /**< PHY JTAG TAP In Control Register, offset: 0x36 */
__I uint8_t JTAG_PHY_TAP_OUT; /**< PHY JTAG TAP Out Control Register, offset: 0x37 */
__IO uint8_t JTAG_PHY_ADDR; /**< PHY JTAG Address Control Register, offset: 0x38 */
} PHYCONFIGURATION_Type;
/* ----------------------------------------------------------------------------
-- PHYCONFIGURATION Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PHYCONFIGURATION_Register_Masks PHYCONFIGURATION Register Masks
* @{
*/
/*! @name PHY_CONF0 - PHY Configuration Register This register holds the power down, data enable polarity, and interface control of the HDMI Source PHY control. */
/*! @{ */
#define PHYCONFIGURATION_PHY_CONF0_SELDIPIF_MASK (0x1U)
#define PHYCONFIGURATION_PHY_CONF0_SELDIPIF_SHIFT (0U)
/*! seldipif - Select interface control.
*/
#define PHYCONFIGURATION_PHY_CONF0_SELDIPIF(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SELDIPIF_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SELDIPIF_MASK)
#define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_MASK (0x2U)
#define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_SHIFT (1U)
/*! seldataenpol - Select data enable polarity.
*/
#define PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SELDATAENPOL_MASK)
#define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_MASK (0x4U)
#define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_SHIFT (2U)
/*! enhpdrxsense - PHY ENHPDRXSENSE signal.
*/
#define PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_ENHPDRXSENSE_MASK)
#define PHYCONFIGURATION_PHY_CONF0_TXPWRON_MASK (0x8U)
#define PHYCONFIGURATION_PHY_CONF0_TXPWRON_SHIFT (3U)
/*! txpwron - PHY TXPWRON signal.
*/
#define PHYCONFIGURATION_PHY_CONF0_TXPWRON(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_TXPWRON_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_TXPWRON_MASK)
#define PHYCONFIGURATION_PHY_CONF0_PDDQ_MASK (0x10U)
#define PHYCONFIGURATION_PHY_CONF0_PDDQ_SHIFT (4U)
/*! pddq - PHY PDDQ signal.
*/
#define PHYCONFIGURATION_PHY_CONF0_PDDQ(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_PDDQ_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_PDDQ_MASK)
#define PHYCONFIGURATION_PHY_CONF0_SPARECTRL_MASK (0x20U)
#define PHYCONFIGURATION_PHY_CONF0_SPARECTRL_SHIFT (5U)
/*! sparectrl - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_CONF0_SPARECTRL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARECTRL_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARECTRL_MASK)
#define PHYCONFIGURATION_PHY_CONF0_SPARES_1_MASK (0x40U)
#define PHYCONFIGURATION_PHY_CONF0_SPARES_1_SHIFT (6U)
/*! spares_1 - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_CONF0_SPARES_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARES_1_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARES_1_MASK)
#define PHYCONFIGURATION_PHY_CONF0_SPARES_2_MASK (0x80U)
#define PHYCONFIGURATION_PHY_CONF0_SPARES_2_SHIFT (7U)
/*! spares_2 - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_CONF0_SPARES_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_CONF0_SPARES_2_SHIFT)) & PHYCONFIGURATION_PHY_CONF0_SPARES_2_MASK)
/*! @} */
/*! @name PHY_TST0 - PHY Test Interface Register 0 PHY TX mapped test interface (control). */
/*! @{ */
#define PHYCONFIGURATION_PHY_TST0_SPARE_0_MASK (0x1U)
#define PHYCONFIGURATION_PHY_TST0_SPARE_0_SHIFT (0U)
/*! spare_0 - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST0_SPARE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_0_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_0_MASK)
#define PHYCONFIGURATION_PHY_TST0_SPARE_1_MASK (0xEU)
#define PHYCONFIGURATION_PHY_TST0_SPARE_1_SHIFT (1U)
/*! spare_1 - Reserved as "spare" bit with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST0_SPARE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_1_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_1_MASK)
#define PHYCONFIGURATION_PHY_TST0_SPARE_3_MASK (0x10U)
#define PHYCONFIGURATION_PHY_TST0_SPARE_3_SHIFT (4U)
/*! spare_3 - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST0_SPARE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_3_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_3_MASK)
#define PHYCONFIGURATION_PHY_TST0_SPARE_4_MASK (0x20U)
#define PHYCONFIGURATION_PHY_TST0_SPARE_4_SHIFT (5U)
/*! spare_4 - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST0_SPARE_4(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_4_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_4_MASK)
#define PHYCONFIGURATION_PHY_TST0_SPARE_2_MASK (0xC0U)
#define PHYCONFIGURATION_PHY_TST0_SPARE_2_SHIFT (6U)
/*! spare_2 - Reserved as "spare" bit with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST0_SPARE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST0_SPARE_2_SHIFT)) & PHYCONFIGURATION_PHY_TST0_SPARE_2_MASK)
/*! @} */
/*! @name PHY_TST1 - PHY Test Interface Register 1 PHY TX mapped text interface (data in). */
/*! @{ */
#define PHYCONFIGURATION_PHY_TST1_SPARE_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_TST1_SPARE_SHIFT (0U)
/*! spare - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST1_SPARE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST1_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_TST1_SPARE_MASK)
/*! @} */
/*! @name PHY_TST2 - PHY Test Interface Register 2 PHY TX mapped text interface (data out). */
/*! @{ */
#define PHYCONFIGURATION_PHY_TST2_SPARE_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_TST2_SPARE_SHIFT (0U)
/*! spare - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_TST2_SPARE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_TST2_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_TST2_SPARE_MASK)
/*! @} */
/*! @name PHY_STAT0 - PHY RXSENSE, PLL Lock, and HPD Status Register This register contains the following active high packet sent status indications. */
/*! @{ */
#define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_MASK (0x1U)
#define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_SHIFT (0U)
/*! TX_PHY_LOCK - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_TX_PHY_LOCK_MASK)
#define PHYCONFIGURATION_PHY_STAT0_HPD_MASK (0x2U)
#define PHYCONFIGURATION_PHY_STAT0_HPD_SHIFT (1U)
/*! HPD - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_HPD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_HPD_MASK)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_MASK (0x10U)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_SHIFT (4U)
/*! RX_SENSE_0 - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_0_MASK)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_MASK (0x20U)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_SHIFT (5U)
/*! RX_SENSE_1 - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_1_MASK)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_MASK (0x40U)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_SHIFT (6U)
/*! RX_SENSE_2 - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_2_MASK)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_MASK (0x80U)
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_SHIFT (7U)
/*! RX_SENSE_3 - Status bit.
*/
#define PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_STAT0_RX_SENSE_3_MASK)
/*! @} */
/*! @name PHY_INT0 - PHY RXSENSE, PLL Lock, and HPD Interrupt Register This register contains the interrupt indication of the PHY_STAT0 status interrupts. */
/*! @{ */
#define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_MASK (0x1U)
#define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_SHIFT (0U)
/*! TX_PHY_LOCK - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_INT0_TX_PHY_LOCK_MASK)
#define PHYCONFIGURATION_PHY_INT0_HPD_MASK (0x2U)
#define PHYCONFIGURATION_PHY_INT0_HPD_SHIFT (1U)
/*! HPD - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_HPD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_INT0_HPD_MASK)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_MASK (0x10U)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_SHIFT (4U)
/*! RX_SENSE_0 - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_0_MASK)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_MASK (0x20U)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_SHIFT (5U)
/*! RX_SENSE_1 - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_1_MASK)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_MASK (0x40U)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_SHIFT (6U)
/*! RX_SENSE_2 - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_2_MASK)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_MASK (0x80U)
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_SHIFT (7U)
/*! RX_SENSE_3 - Interrupt indication bit.
*/
#define PHYCONFIGURATION_PHY_INT0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_INT0_RX_SENSE_3_MASK)
/*! @} */
/*! @name PHY_MASK0 - PHY RXSENSE, PLL Lock, and HPD Mask Register Mask register for generation of PHY_INT0 interrupts. */
/*! @{ */
#define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_MASK (0x1U)
#define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_SHIFT (0U)
/*! TX_PHY_LOCK - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_TX_PHY_LOCK_MASK)
#define PHYCONFIGURATION_PHY_MASK0_HPD_MASK (0x2U)
#define PHYCONFIGURATION_PHY_MASK0_HPD_SHIFT (1U)
/*! HPD - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_HPD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_HPD_MASK)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_MASK (0x10U)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_SHIFT (4U)
/*! RX_SENSE_0 - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_0_MASK)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_MASK (0x20U)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_SHIFT (5U)
/*! RX_SENSE_1 - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_1_MASK)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_MASK (0x40U)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_SHIFT (6U)
/*! RX_SENSE_2 - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_2_MASK)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_MASK (0x80U)
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_SHIFT (7U)
/*! RX_SENSE_3 - Mask bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_MASK0_RX_SENSE_3_MASK)
/*! @} */
/*! @name PHY_POL0 - PHY RXSENSE, PLL Lock, and HPD Polarity Register Polarity register for generation of PHY_INT0 interrupts. */
/*! @{ */
#define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_MASK (0x1U)
#define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_SHIFT (0U)
/*! TX_PHY_LOCK - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_SHIFT)) & PHYCONFIGURATION_PHY_POL0_TX_PHY_LOCK_MASK)
#define PHYCONFIGURATION_PHY_POL0_HPD_MASK (0x2U)
#define PHYCONFIGURATION_PHY_POL0_HPD_SHIFT (1U)
/*! HPD - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_HPD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_HPD_SHIFT)) & PHYCONFIGURATION_PHY_POL0_HPD_MASK)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_MASK (0x10U)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_SHIFT (4U)
/*! RX_SENSE_0 - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_0_MASK)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_MASK (0x20U)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_SHIFT (5U)
/*! RX_SENSE_1 - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_1_MASK)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_MASK (0x40U)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_SHIFT (6U)
/*! RX_SENSE_2 - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_2(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_2_MASK)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_MASK (0x80U)
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_SHIFT (7U)
/*! RX_SENSE_3 - Polarity bit for PHY_INT0.
*/
#define PHYCONFIGURATION_PHY_POL0_RX_SENSE_3(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_SHIFT)) & PHYCONFIGURATION_PHY_POL0_RX_SENSE_3_MASK)
/*! @} */
/*! @name PHY_I2CM_SLAVE - PHY I2C Slave Address Configuration Register */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_MASK (0x7FU)
#define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_SHIFT (0U)
/*! slaveaddr - Slave address to be sent during read and write operations.
*/
#define PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SLAVE_SLAVEADDR_MASK)
/*! @} */
/*! @name PHY_I2CM_ADDRESS - PHY I2C Address Configuration Register This register writes the address for read and write operations. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_SHIFT (0U)
/*! address - Register address for read and write operations
*/
#define PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_ADDRESS_ADDRESS_MASK)
/*! @} */
/*! @name PHY_I2CM_DATAO_1 - PHY I2C Data Write Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_SHIFT (0U)
/*! datao - Data MSB (datao[15:8]) to be written on register pointed by phy_i2cm_address [7:0].
*/
#define PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAO_1_DATAO_MASK)
/*! @} */
/*! @name PHY_I2CM_DATAO_0 - PHY I2C Data Write Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_SHIFT (0U)
/*! datao - Data LSB (datao[7:0]) to be written on register pointed by phy_i2cm_address [7:0].
*/
#define PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAO_0_DATAO_MASK)
/*! @} */
/*! @name PHY_I2CM_DATAI_1 - PHY I2C Data Read Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_SHIFT (0U)
/*! datai - Data MSB (datai[15:8]) read from register pointed by phy_i2cm_address[7:0].
*/
#define PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAI_1_DATAI_MASK)
/*! @} */
/*! @name PHY_I2CM_DATAI_0 - PHY I2C Data Read Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_SHIFT (0U)
/*! datai - Data LSB (datai[7:0]) read from register pointed by phy_i2cm_address[7:0].
*/
#define PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DATAI_0_DATAI_MASK)
/*! @} */
/*! @name PHY_I2CM_OPERATION - PHY I2C RD/RD_EXT/WR Operation Register This register requests read and write operations from the I2C Master PHY. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_MASK (0x1U)
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_SHIFT (0U)
/*! rd - Read operation request
*/
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_RD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_OPERATION_RD_MASK)
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_MASK (0x10U)
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_SHIFT (4U)
/*! wr - Write operation request
*/
#define PHYCONFIGURATION_PHY_I2CM_OPERATION_WR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_OPERATION_WR_MASK)
/*! @} */
/*! @name PHY_I2CM_INT - PHY I2C Done Interrupt Register This register contains and configures I2C master PHY done interrupt. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_MASK (0x1U)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_SHIFT (0U)
/*! done_status - Operation done status bit.
*/
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_STATUS_MASK)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_MASK (0x2U)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_SHIFT (1U)
/*! done_interrupt - Operation done interrupt bit.
*/
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_INTERRUPT_MASK)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_MASK (0x4U)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_SHIFT (2U)
/*! done_mask - Done interrupt mask signal
*/
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_MASK_MASK)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_MASK (0x8U)
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_SHIFT (3U)
/*! done_pol - Done interrupt polarity configuration
*/
#define PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_INT_DONE_POL_MASK)
/*! @} */
/*! @name PHY_I2CM_CTLINT - PHY I2C error Interrupt Register This register contains and configures the I2C master PHY error interrupts. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_MASK (0x1U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_SHIFT (0U)
/*! arbitration_status - Arbitration error status bit.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_STATUS_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_MASK (0x2U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_SHIFT (1U)
/*! arbitration_interrupt - Arbitration error interrupt bit {arbitration_interrupt =
* (arbitration_mask==0b) && (arbitration_status==arbitration_pol)} Note: This bit field is read by the sticky
* bits present on the ih_i2cmphy_stat0 register.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_INTERRUPT_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_MASK (0x4U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_SHIFT (2U)
/*! arbitration_mask - Arbitration error interrupt mask signal.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_MASK_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_MASK (0x8U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_SHIFT (3U)
/*! arbitration_pol - Arbitration error interrupt polarity configuration.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_ARBITRATION_POL_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_MASK (0x10U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_SHIFT (4U)
/*! nack_status - Not acknowledge error status bit.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_STATUS_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_MASK (0x20U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_SHIFT (5U)
/*! nack_interrupt - Not acknowledge error interrupt bit.
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_INTERRUPT_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_MASK (0x40U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_SHIFT (6U)
/*! nack_mask - Not acknowledge error interrupt mask signal
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_MASK_MASK)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_MASK (0x80U)
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_SHIFT (7U)
/*! nack_pol - Not acknowledge error interrupt polarity configuration
*/
#define PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_CTLINT_NACK_POL_MASK)
/*! @} */
/*! @name PHY_I2CM_DIV - PHY I2C Speed control Register This register wets the I2C Master PHY to work in either Fast or Standard mode. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_MASK (0x7U)
#define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_SHIFT (0U)
/*! spare - Reserved as "spare" register with no associated functionality.
*/
#define PHYCONFIGURATION_PHY_I2CM_DIV_SPARE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DIV_SPARE_MASK)
#define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_MASK (0x8U)
#define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_SHIFT (3U)
/*! fast_std_mode - Sets the I2C Master to work in Fast Mode or Standard Mode: 1: Fast Mode 0: Standard Mode
*/
#define PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_DIV_FAST_STD_MODE_MASK)
/*! @} */
/*! @name PHY_I2CM_SOFTRSTZ - PHY I2C SW reset control register This register sets the I2C Master PHY software reset. */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK (0x1U)
#define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT (0U)
/*! i2c_softrstz - I2C Master Software Reset.
*/
#define PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SOFTRSTZ_I2C_SOFTRSTZ_MASK)
/*! @} */
/*! @name PHY_I2CM_SS_SCL_HCNT_1_ADDR - PHY I2C Slow Speed SCL High Level Control Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT (0U)
/*! i2cmp_ss_scl_hcnt1 - PHY I2C Slow Speed SCL High Level Control Register 1
*/
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_1_ADDR_I2CMP_SS_SCL_HCNT1_MASK)
/*! @} */
/*! @name PHY_I2CM_SS_SCL_HCNT_0_ADDR - PHY I2C Slow Speed SCL High Level Control Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT (0U)
/*! i2cmp_ss_scl_hcnt0 - PHY I2C Slow Speed SCL High Level Control Register 0
*/
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_HCNT_0_ADDR_I2CMP_SS_SCL_HCNT0_MASK)
/*! @} */
/*! @name PHY_I2CM_SS_SCL_LCNT_1_ADDR - PHY I2C Slow Speed SCL Low Level Control Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT (0U)
/*! i2cmp_ss_scl_lcnt1 - PHY I2C Slow Speed SCL Low Level Control Register 1
*/
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_1_ADDR_I2CMP_SS_SCL_LCNT1_MASK)
/*! @} */
/*! @name PHY_I2CM_SS_SCL_LCNT_0_ADDR - PHY I2C Slow Speed SCL Low Level Control Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT (0U)
/*! i2cmp_ss_scl_lcnt0 - PHY I2C Slow Speed SCL Low Level Control Register 0
*/
#define PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SS_SCL_LCNT_0_ADDR_I2CMP_SS_SCL_LCNT0_MASK)
/*! @} */
/*! @name PHY_I2CM_FS_SCL_HCNT_1_ADDR - PHY I2C Fast Speed SCL High Level Control Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT (0U)
/*! i2cmp_fs_scl_hcnt1 - PHY I2C Fast Speed SCL High Level Control Register 1
*/
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_1_ADDR_I2CMP_FS_SCL_HCNT1_MASK)
/*! @} */
/*! @name PHY_I2CM_FS_SCL_HCNT_0_ADDR - PHY I2C Fast Speed SCL High Level Control Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT (0U)
/*! i2cmp_fs_scl_hcnt0 - PHY I2C Fast Speed SCL High Level Control Register 0
*/
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_HCNT_0_ADDR_I2CMP_FS_SCL_HCNT0_MASK)
/*! @} */
/*! @name PHY_I2CM_FS_SCL_LCNT_1_ADDR - PHY I2C Fast Speed SCL Low Level Control Register 1 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT (0U)
/*! i2cmp_fs_scl_lcnt1 - PHY I2C Fast Speed SCL Low Level Control Register 1
*/
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_1_ADDR_I2CMP_FS_SCL_LCNT1_MASK)
/*! @} */
/*! @name PHY_I2CM_FS_SCL_LCNT_0_ADDR - PHY I2C Fast Speed SCL Low Level Control Register 0 */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT (0U)
/*! i2cmp_fs_scl_lcnt0 - PHY I2C Fast Speed SCL Low Level Control Register 0
*/
#define PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_FS_SCL_LCNT_0_ADDR_I2CMP_FS_SCL_LCNT0_MASK)
/*! @} */
/*! @name PHY_I2CM_SDA_HOLD - PHY I2C SDA HOLD Control Register */
/*! @{ */
#define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_MASK (0xFFU)
#define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT (0U)
/*! osda_hold - Defines the number of SFR clock cycles to meet tHD:DAT (300 ns) osda_hold =
* round_to_high_integer (300 ns / (1/isfrclk_frequency))
*/
#define PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_SHIFT)) & PHYCONFIGURATION_PHY_I2CM_SDA_HOLD_OSDA_HOLD_MASK)
/*! @} */
/*! @name JTAG_PHY_CONFIG - PHY I2C/JTAG I/O Configuration Control Register */
/*! @{ */
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_MASK (0x1U)
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_SHIFT (0U)
/*! jtag_trst_n - Configures the JTAG PHY interface output pin JTAG_TRST_N when in internal control
* mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_trst_n when PHY_EXTERNAL=1.
*/
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_CONFIG_JTAG_TRST_N_MASK)
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_MASK (0x10U)
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_SHIFT (4U)
/*! i2c_jtagz - Configures the JTAG PHY interface output pin I2C_JTAGZ to select the PHY
* configuration interface when in internal control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_i2c_jtagz when
* PHY_EXTERNAL=1.
*/
#define PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_CONFIG_I2C_JTAGZ_MASK)
/*! @} */
/*! @name JTAG_PHY_TAP_TCK - PHY JTAG Clock Control Register */
/*! @{ */
#define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_MASK (0x1U)
#define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_SHIFT (0U)
/*! jtag_tck - Configures the JTAG PHY interface pin JTAG_TCK when in internal control mode
* (iphy_ext_ctrl=1'b0) or ophyext_jtag_tck when PHY_EXTERNAL=1.
*/
#define PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_TCK_JTAG_TCK_MASK)
/*! @} */
/*! @name JTAG_PHY_TAP_IN - PHY JTAG TAP In Control Register */
/*! @{ */
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_MASK (0x1U)
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_SHIFT (0U)
/*! jtag_tdi - Configures the JTAG PHY interface pin JTAG_TDI when in internal control mode
* (iphy_ext_ctrl=1'b0) or ophyext_jtag_tdi when PHY_EXTERNAL=1.
*/
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TDI_MASK)
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_MASK (0x10U)
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_SHIFT (4U)
/*! jtag_tms - Configures the JTAG PHY interface pin JTAG_TMS when in internal control mode
* (iphy_ext_ctrl=1'b0) or ophyext_jtag_tms when PHY_EXTERNAL=1.
*/
#define PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_IN_JTAG_TMS_MASK)
/*! @} */
/*! @name JTAG_PHY_TAP_OUT - PHY JTAG TAP Out Control Register */
/*! @{ */
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_MASK (0x1U)
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_SHIFT (0U)
/*! jtag_tdo - Read JTAG PHY interface input pin JTAG_TDO when in internal control mode
* (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo when PHY_EXTERNAL=1
*/
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_MASK)
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_MASK (0x10U)
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_SHIFT (4U)
/*! jtag_tdo_en - Read JTAG PHY interface input pin JTAG_TDO_EN when in internal control mode
* (iphy_ext_ctrl=1'b0) or iphyext_jtag_tdo_en when PHY_EXTERNAL=1
*/
#define PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_TAP_OUT_JTAG_TDO_EN_MASK)
/*! @} */
/*! @name JTAG_PHY_ADDR - PHY JTAG Address Control Register */
/*! @{ */
#define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_MASK (0xFFU)
#define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_SHIFT (0U)
/*! jtag_addr - Configures the JTAG PHY interface pin JTAG_ADDR[7:0] when in internal control mode
* (iphy_ext_ctrl=1'b0) or iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1
*/
#define PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR(x) (((uint8_t)(((uint8_t)(x)) << PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_SHIFT)) & PHYCONFIGURATION_JTAG_PHY_ADDR_JTAG_ADDR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PHYCONFIGURATION_Register_Masks */
/* PHYCONFIGURATION - Peripheral instance base addresses */
/** Peripheral PHYCONFIGURATION base address */
#define PHYCONFIGURATION_BASE (0x32FDB000u)
/** Peripheral PHYCONFIGURATION base pointer */
#define PHYCONFIGURATION ((PHYCONFIGURATION_Type *)PHYCONFIGURATION_BASE)
/** Array initializer of PHYCONFIGURATION peripheral base addresses */
#define PHYCONFIGURATION_BASE_ADDRS { PHYCONFIGURATION_BASE }
/** Array initializer of PHYCONFIGURATION peripheral base pointers */
#define PHYCONFIGURATION_BASE_PTRS { PHYCONFIGURATION }
/*!
* @}
*/ /* end of group PHYCONFIGURATION_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
* @{
*/
/** PWM - Register Layout Typedef */
typedef struct {
__IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */
__IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */
__IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */
__IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */
__IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */
__I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */
} PWM_Type;
/* ----------------------------------------------------------------------------
-- PWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Register_Masks PWM Register Masks
* @{
*/
/*! @name PWMCR - PWM Control Register */
/*! @{ */
#define PWM_PWMCR_EN_MASK (0x1U)
#define PWM_PWMCR_EN_SHIFT (0U)
/*! EN
* 0b0..PWM disabled
* 0b1..PWM enabled
*/
#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
#define PWM_PWMCR_REPEAT_MASK (0x6U)
#define PWM_PWMCR_REPEAT_SHIFT (1U)
/*! REPEAT
* 0b00..Use each sample once
* 0b01..Use each sample twice
* 0b10..Use each sample four times
* 0b11..Use each sample eight times
*/
#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
#define PWM_PWMCR_SWR_MASK (0x8U)
#define PWM_PWMCR_SWR_SHIFT (3U)
/*! SWR
* 0b0..PWM is out of reset
* 0b1..PWM is undergoing reset
*/
#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U)
#define PWM_PWMCR_PRESCALER_SHIFT (4U)
/*! PRESCALER
* 0b000000000000..Divide by 1
* 0b000000000001..Divide by 2
* 0b111111111111..Divide by 4096
*/
#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
#define PWM_PWMCR_CLKSRC_MASK (0x30000U)
#define PWM_PWMCR_CLKSRC_SHIFT (16U)
/*! CLKSRC
* 0b00..Clock is off
* 0b01..ipg_clk
* 0b10..ipg_clk_highfreq
* 0b11..ipg_clk_32k
*/
#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
#define PWM_PWMCR_POUTC_MASK (0xC0000U)
#define PWM_PWMCR_POUTC_SHIFT (18U)
/*! POUTC
* 0b00..Output pin is set at rollover and cleared at comparison
* 0b01..Output pin is cleared at rollover and set at comparison
* 0b10..PWM output is disconnected
* 0b11..PWM output is disconnected
*/
#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
#define PWM_PWMCR_HCTR_MASK (0x100000U)
#define PWM_PWMCR_HCTR_SHIFT (20U)
/*! HCTR
* 0b0..Half word swapping does not take place
* 0b1..Half words from write data bus are swapped
*/
#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
#define PWM_PWMCR_BCTR_MASK (0x200000U)
#define PWM_PWMCR_BCTR_SHIFT (21U)
/*! BCTR
* 0b0..byte ordering remains the same
* 0b1..byte ordering is reversed
*/
#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
#define PWM_PWMCR_DBGEN_MASK (0x400000U)
#define PWM_PWMCR_DBGEN_SHIFT (22U)
/*! DBGEN
* 0b0..Inactive in debug mode
* 0b1..Active in debug mode
*/
#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK)
#define PWM_PWMCR_WAITEN_MASK (0x800000U)
#define PWM_PWMCR_WAITEN_SHIFT (23U)
/*! WAITEN
* 0b0..Inactive in wait mode
* 0b1..Active in wait mode
*/
#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
#define PWM_PWMCR_DOZEN_MASK (0x1000000U)
#define PWM_PWMCR_DOZEN_SHIFT (24U)
/*! DOZEN
* 0b0..Inactive in doze mode
* 0b1..Active in doze mode
*/
#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
#define PWM_PWMCR_STOPEN_MASK (0x2000000U)
#define PWM_PWMCR_STOPEN_SHIFT (25U)
/*! STOPEN
* 0b0..Inactive in stop mode
* 0b1..Active in stop mode
*/
#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
#define PWM_PWMCR_FWM_MASK (0xC000000U)
#define PWM_PWMCR_FWM_SHIFT (26U)
/*! FWM
* 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
* 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
* 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
* 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
*/
#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
/*! @} */
/*! @name PWMSR - PWM Status Register */
/*! @{ */
#define PWM_PWMSR_FIFOAV_MASK (0x7U)
#define PWM_PWMSR_FIFOAV_SHIFT (0U)
/*! FIFOAV
* 0b000..No data available
* 0b001..1 word of data in FIFO
* 0b010..2 words of data in FIFO
* 0b011..3 words of data in FIFO
* 0b100..4 words of data in FIFO
* 0b101..unused
* 0b110..unused
* 0b111..unused
*/
#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
#define PWM_PWMSR_FE_MASK (0x8U)
#define PWM_PWMSR_FE_SHIFT (3U)
/*! FE
* 0b0..Data level is above water mark
* 0b1..When the data level falls below the mark set by FWM field
*/
#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
#define PWM_PWMSR_ROV_MASK (0x10U)
#define PWM_PWMSR_ROV_SHIFT (4U)
/*! ROV
* 0b0..Roll-over event not occurred
* 0b1..Roll-over event occurred
*/
#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
#define PWM_PWMSR_CMP_MASK (0x20U)
#define PWM_PWMSR_CMP_SHIFT (5U)
/*! CMP
* 0b0..Compare event not occurred
* 0b1..Compare event occurred
*/
#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
#define PWM_PWMSR_FWE_MASK (0x40U)
#define PWM_PWMSR_FWE_SHIFT (6U)
/*! FWE
* 0b0..FIFO write error not occurred
* 0b1..FIFO write error occurred
*/
#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
/*! @} */
/*! @name PWMIR - PWM Interrupt Register */
/*! @{ */
#define PWM_PWMIR_FIE_MASK (0x1U)
#define PWM_PWMIR_FIE_SHIFT (0U)
/*! FIE
* 0b0..FIFO Empty interrupt disabled
* 0b1..FIFO Empty interrupt enabled
*/
#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
#define PWM_PWMIR_RIE_MASK (0x2U)
#define PWM_PWMIR_RIE_SHIFT (1U)
/*! RIE
* 0b0..Roll-over interrupt not enabled
* 0b1..Roll-over Interrupt enabled
*/
#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
#define PWM_PWMIR_CIE_MASK (0x4U)
#define PWM_PWMIR_CIE_SHIFT (2U)
/*! CIE
* 0b0..Compare Interrupt not enabled
* 0b1..Compare Interrupt enabled
*/
#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
/*! @} */
/*! @name PWMSAR - PWM Sample Register */
/*! @{ */
#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU)
#define PWM_PWMSAR_SAMPLE_SHIFT (0U)
#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
/*! @} */
/*! @name PWMPR - PWM Period Register */
/*! @{ */
#define PWM_PWMPR_PERIOD_MASK (0xFFFFU)
#define PWM_PWMPR_PERIOD_SHIFT (0U)
#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
/*! @} */
/*! @name PWMCNR - PWM Counter Register */
/*! @{ */
#define PWM_PWMCNR_COUNT_MASK (0xFFFFU)
#define PWM_PWMCNR_COUNT_SHIFT (0U)
#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PWM_Register_Masks */
/* PWM - Peripheral instance base addresses */
/** Peripheral PWM1 base address */
#define PWM1_BASE (0x30660000u)
/** Peripheral PWM1 base pointer */
#define PWM1 ((PWM_Type *)PWM1_BASE)
/** Peripheral PWM2 base address */
#define PWM2_BASE (0x30670000u)
/** Peripheral PWM2 base pointer */
#define PWM2 ((PWM_Type *)PWM2_BASE)
/** Peripheral PWM3 base address */
#define PWM3_BASE (0x30680000u)
/** Peripheral PWM3 base pointer */
#define PWM3 ((PWM_Type *)PWM3_BASE)
/** Peripheral PWM4 base address */
#define PWM4_BASE (0x30690000u)
/** Peripheral PWM4 base pointer */
#define PWM4 ((PWM_Type *)PWM4_BASE)
/** Array initializer of PWM peripheral base addresses */
#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
/** Array initializer of PWM peripheral base pointers */
#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
/** Interrupt vectors for the PWM peripheral type */
#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn }
/*!
* @}
*/ /* end of group PWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
* @{
*/
/** RDC - Register Layout Typedef */
typedef struct {
__I uint32_t VIR; /**< Version Information, offset: 0x0 */
uint8_t RESERVED_0[32];
__IO uint32_t STAT; /**< Status, offset: 0x24 */
__IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */
__IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */
uint8_t RESERVED_1[464];
__IO uint32_t MDA[40]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_2[352];
__IO uint32_t PDAP[112]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_3[576];
struct { /* offset: 0x800, array step: 0x10 */
__IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
__IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
__IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
} MR[77];
} RDC_Type;
/* ----------------------------------------------------------------------------
-- RDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_Register_Masks RDC Register Masks
* @{
*/
/*! @name VIR - Version Information */
/*! @{ */
#define RDC_VIR_NDID_MASK (0xFU)
#define RDC_VIR_NDID_SHIFT (0U)
/*! NDID - Number of Domains
*/
#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
#define RDC_VIR_NMSTR_MASK (0xFF0U)
#define RDC_VIR_NMSTR_SHIFT (4U)
/*! NMSTR - Number of Masters
*/
#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
#define RDC_VIR_NPER_MASK (0xFF000U)
#define RDC_VIR_NPER_SHIFT (12U)
/*! NPER - Number of Peripherals
*/
#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
#define RDC_VIR_NRGN_MASK (0xFF00000U)
#define RDC_VIR_NRGN_SHIFT (20U)
/*! NRGN - Number of Memory Regions
*/
#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
/*! @} */
/*! @name STAT - Status */
/*! @{ */
#define RDC_STAT_DID_MASK (0xFU)
#define RDC_STAT_DID_SHIFT (0U)
/*! DID - Domain ID
*/
#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
#define RDC_STAT_PDS_MASK (0x100U)
#define RDC_STAT_PDS_SHIFT (8U)
/*! PDS - Power Domain Status
* 0b0..Power Down Domain is OFF
* 0b1..Power Down Domain is ON
*/
#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
/*! @} */
/*! @name INTCTRL - Interrupt and Control */
/*! @{ */
#define RDC_INTCTRL_RCI_EN_MASK (0x1U)
#define RDC_INTCTRL_RCI_EN_SHIFT (0U)
/*! RCI_EN - Restoration Complete Interrupt
* 0b0..Interrupt Disabled
* 0b1..Interrupt Enabled
*/
#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt Status */
/*! @{ */
#define RDC_INTSTAT_INT_MASK (0x1U)
#define RDC_INTSTAT_INT_SHIFT (0U)
/*! INT - Interrupt Status
* 0b0..No Interrupt Pending
* 0b1..Interrupt Pending
*/
#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
/*! @} */
/*! @name MDA - Master Domain Assignment */
/*! @{ */
#define RDC_MDA_DID_MASK (0x3U)
#define RDC_MDA_DID_SHIFT (0U)
/*! DID - Domain ID
* 0b00..Master assigned to Processing Domain 0
* 0b01..Master assigned to Processing Domain 1
* 0b10..Master assigned to Processing Domain 2
* 0b11..Master assigned to Processing Domain 3
*/
#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
#define RDC_MDA_LCK_MASK (0x80000000U)
#define RDC_MDA_LCK_SHIFT (31U)
/*! LCK - Assignment Lock
* 0b0..Not Locked
* 0b1..Locked
*/
#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
/*! @} */
/* The count of RDC_MDA */
#define RDC_MDA_COUNT (40U)
/*! @name PDAP - Peripheral Domain Access Permissions */
/*! @{ */
#define RDC_PDAP_D0W_MASK (0x1U)
#define RDC_PDAP_D0W_SHIFT (0U)
/*! D0W - Domain 0 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
#define RDC_PDAP_D0R_MASK (0x2U)
#define RDC_PDAP_D0R_SHIFT (1U)
/*! D0R - Domain 0 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
#define RDC_PDAP_D1W_MASK (0x4U)
#define RDC_PDAP_D1W_SHIFT (2U)
/*! D1W - Domain 1 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
#define RDC_PDAP_D1R_MASK (0x8U)
#define RDC_PDAP_D1R_SHIFT (3U)
/*! D1R - Domain 1 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
#define RDC_PDAP_D2W_MASK (0x10U)
#define RDC_PDAP_D2W_SHIFT (4U)
/*! D2W - Domain 2 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK)
#define RDC_PDAP_D2R_MASK (0x20U)
#define RDC_PDAP_D2R_SHIFT (5U)
/*! D2R - Domain 2 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK)
#define RDC_PDAP_D3W_MASK (0x40U)
#define RDC_PDAP_D3W_SHIFT (6U)
/*! D3W - Domain 3 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK)
#define RDC_PDAP_D3R_MASK (0x80U)
#define RDC_PDAP_D3R_SHIFT (7U)
/*! D3R - Domain 3 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK)
#define RDC_PDAP_SREQ_MASK (0x40000000U)
#define RDC_PDAP_SREQ_SHIFT (30U)
/*! SREQ - Semaphore Required
* 0b0..Semaphores have no effect
* 0b1..Semaphores are enforced
*/
#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
#define RDC_PDAP_LCK_MASK (0x80000000U)
#define RDC_PDAP_LCK_SHIFT (31U)
/*! LCK - Peripheral Permissions Lock
* 0b0..Not Locked
* 0b1..Locked
*/
#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
/*! @} */
/* The count of RDC_PDAP */
#define RDC_PDAP_COUNT (112U)
/*! @name MRSA - Memory Region Start Address */
/*! @{ */
#define RDC_MRSA_SADR_MASK (0xFFFFFF80U)
#define RDC_MRSA_SADR_SHIFT (7U)
/*! SADR - Start address for memory region
*/
#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
/*! @} */
/* The count of RDC_MRSA */
#define RDC_MRSA_COUNT (77U)
/*! @name MREA - Memory Region End Address */
/*! @{ */
#define RDC_MREA_EADR_MASK (0xFFFFFF80U)
#define RDC_MREA_EADR_SHIFT (7U)
/*! EADR - Upper bound for memory region
*/
#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
/*! @} */
/* The count of RDC_MREA */
#define RDC_MREA_COUNT (77U)
/*! @name MRC - Memory Region Control */
/*! @{ */
#define RDC_MRC_D0W_MASK (0x1U)
#define RDC_MRC_D0W_SHIFT (0U)
/*! D0W - Domain 0 Write Access to Region
* 0b0..Processing Domain 0 does not have Write access to the memory region
* 0b1..Processing Domain 0 has Write access to the memory region
*/
#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
#define RDC_MRC_D0R_MASK (0x2U)
#define RDC_MRC_D0R_SHIFT (1U)
/*! D0R - Domain 0 Read Access to Region
* 0b0..Processing Domain 0 does not have Read access to the memory region
* 0b1..Processing Domain 0 has Read access to the memory region
*/
#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
#define RDC_MRC_D1W_MASK (0x4U)
#define RDC_MRC_D1W_SHIFT (2U)
/*! D1W - Domain 1 Write Access to Region
* 0b0..Processing Domain 1 does not have Write access to the memory region
* 0b1..Processing Domain 1 has Write access to the memory region
*/
#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
#define RDC_MRC_D1R_MASK (0x8U)
#define RDC_MRC_D1R_SHIFT (3U)
/*! D1R - Domain 1 Read Access to Region
* 0b0..Processing Domain 1 does not have Read access to the memory region
* 0b1..Processing Domain 1 has Read access to the memory region
*/
#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
#define RDC_MRC_D2W_MASK (0x10U)
#define RDC_MRC_D2W_SHIFT (4U)
/*! D2W - Domain 2 Write Access to Region
* 0b0..Processing Domain 2 does not have Write access to the memory region
* 0b1..Processing Domain 2 has Write access to the memory region
*/
#define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK)
#define RDC_MRC_D2R_MASK (0x20U)
#define RDC_MRC_D2R_SHIFT (5U)
/*! D2R - Domain 2 Read Access to Region
* 0b0..Processing Domain 2 does not have Read access to the memory region
* 0b1..Processing Domain 2 has Read access to the memory region
*/
#define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK)
#define RDC_MRC_D3W_MASK (0x40U)
#define RDC_MRC_D3W_SHIFT (6U)
/*! D3W - Domain 3 Write Access to Region
* 0b0..Processing Domain 3 does not have Write access to the memory region
* 0b1..Processing Domain 3 has Read access to the memory region
*/
#define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK)
#define RDC_MRC_D3R_MASK (0x80U)
#define RDC_MRC_D3R_SHIFT (7U)
/*! D3R - Domain 3 Read Access to Region
* 0b0..Processing Domain 3 does not have Read access to the memory region
* 0b1..Processing Domain 3 has Read access to the memory region
*/
#define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK)
#define RDC_MRC_ENA_MASK (0x40000000U)
#define RDC_MRC_ENA_SHIFT (30U)
/*! ENA - Region Enable
* 0b0..Memory region is not defined or restricted.
* 0b1..Memory boundaries, domain permissions and controls are in effect.
*/
#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
#define RDC_MRC_LCK_MASK (0x80000000U)
#define RDC_MRC_LCK_SHIFT (31U)
/*! LCK - Region Lock
* 0b0..No Lock. All fields in this register may be modified.
* 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
*/
#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
/*! @} */
/* The count of RDC_MRC */
#define RDC_MRC_COUNT (77U)
/*! @name MRVS - Memory Region Violation Status */
/*! @{ */
#define RDC_MRVS_VDID_MASK (0x3U)
#define RDC_MRVS_VDID_SHIFT (0U)
/*! VDID - Violating Domain ID
* 0b00..Processing Domain 0
* 0b01..Processing Domain 1
* 0b10..Processing Domain 2
* 0b11..Processing Domain 3
*/
#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
#define RDC_MRVS_AD_MASK (0x10U)
#define RDC_MRVS_AD_SHIFT (4U)
/*! AD - Access Denied
*/
#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U)
#define RDC_MRVS_VADR_SHIFT (5U)
/*! VADR - Violating Address
*/
#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
/*! @} */
/* The count of RDC_MRVS */
#define RDC_MRVS_COUNT (77U)
/*!
* @}
*/ /* end of group RDC_Register_Masks */
/* RDC - Peripheral instance base addresses */
/** Peripheral RDC base address */
#define RDC_BASE (0x303D0000u)
/** Peripheral RDC base pointer */
#define RDC ((RDC_Type *)RDC_BASE)
/** Array initializer of RDC peripheral base addresses */
#define RDC_BASE_ADDRS { RDC_BASE }
/** Array initializer of RDC peripheral base pointers */
#define RDC_BASE_PTRS { RDC }
/** Interrupt vectors for the RDC peripheral type */
#define RDC_IRQS { RDC_IRQn }
/*!
* @}
*/ /* end of group RDC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RDC_SEMAPHORE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
* @{
*/
/** RDC_SEMAPHORE - Register Layout Typedef */
typedef struct {
__IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */
__IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */
__IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */
__IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */
__IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */
__IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */
__IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */
__IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */
__IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */
__IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */
__IO uint8_t GATE10; /**< Gate Register, offset: 0xA */
__IO uint8_t GATE11; /**< Gate Register, offset: 0xB */
__IO uint8_t GATE12; /**< Gate Register, offset: 0xC */
__IO uint8_t GATE13; /**< Gate Register, offset: 0xD */
__IO uint8_t GATE14; /**< Gate Register, offset: 0xE */
__IO uint8_t GATE15; /**< Gate Register, offset: 0xF */
__IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */
__IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */
__IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */
__IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */
__IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */
__IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */
__IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */
__IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */
__IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */
__IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */
__IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */
__IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */
__IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */
__IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */
__IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */
__IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */
__IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */
__IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */
__IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */
__IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */
__IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */
__IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */
__IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */
__IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */
__IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */
__IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */
__IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */
__IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */
__IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */
__IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */
__IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */
__IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */
__IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */
__IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */
__IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */
__IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */
__IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */
__IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */
__IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */
__IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */
__IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */
__IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */
__IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */
__IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */
__IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */
__IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */
__IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */
__IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */
uint8_t RESERVED_0[2];
union { /* offset: 0x42 */
__IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */
__IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */
};
} RDC_SEMAPHORE_Type;
/* ----------------------------------------------------------------------------
-- RDC_SEMAPHORE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
* @{
*/
/*! @name GATE0 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE0_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE0_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK)
/*! @} */
/*! @name GATE1 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE1_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE1_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK)
/*! @} */
/*! @name GATE2 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE2_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE2_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK)
/*! @} */
/*! @name GATE3 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE3_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE3_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK)
/*! @} */
/*! @name GATE4 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE4_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE4_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK)
/*! @} */
/*! @name GATE5 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE5_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE5_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK)
/*! @} */
/*! @name GATE6 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE6_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE6_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK)
/*! @} */
/*! @name GATE7 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE7_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE7_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK)
/*! @} */
/*! @name GATE8 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE8_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE8_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK)
/*! @} */
/*! @name GATE9 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE9_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE9_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK)
/*! @} */
/*! @name GATE10 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE10_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK)
/*! @} */
/*! @name GATE11 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE11_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK)
/*! @} */
/*! @name GATE12 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE12_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK)
/*! @} */
/*! @name GATE13 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE13_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK)
/*! @} */
/*! @name GATE14 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE14_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK)
/*! @} */
/*! @name GATE15 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE15_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK)
/*! @} */
/*! @name GATE16 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE16_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE16_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK)
/*! @} */
/*! @name GATE17 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE17_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE17_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK)
/*! @} */
/*! @name GATE18 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE18_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE18_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK)
/*! @} */
/*! @name GATE19 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE19_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE19_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK)
/*! @} */
/*! @name GATE20 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE20_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE20_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK)
/*! @} */
/*! @name GATE21 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE21_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE21_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK)
/*! @} */
/*! @name GATE22 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE22_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE22_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK)
/*! @} */
/*! @name GATE23 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE23_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE23_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK)
/*! @} */
/*! @name GATE24 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE24_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE24_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK)
/*! @} */
/*! @name GATE25 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE25_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE25_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK)
/*! @} */
/*! @name GATE26 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE26_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE26_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK)
/*! @} */
/*! @name GATE27 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE27_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE27_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK)
/*! @} */
/*! @name GATE28 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE28_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE28_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK)
/*! @} */
/*! @name GATE29 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE29_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE29_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK)
/*! @} */
/*! @name GATE30 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE30_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE30_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK)
/*! @} */
/*! @name GATE31 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE31_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE31_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK)
/*! @} */
/*! @name GATE32 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE32_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE32_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK)
/*! @} */
/*! @name GATE33 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE33_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE33_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK)
/*! @} */
/*! @name GATE34 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE34_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE34_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK)
/*! @} */
/*! @name GATE35 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE35_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE35_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK)
/*! @} */
/*! @name GATE36 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE36_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE36_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK)
/*! @} */
/*! @name GATE37 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE37_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE37_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK)
/*! @} */
/*! @name GATE38 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE38_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE38_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK)
/*! @} */
/*! @name GATE39 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE39_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE39_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK)
/*! @} */
/*! @name GATE40 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE40_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE40_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK)
/*! @} */
/*! @name GATE41 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE41_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE41_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK)
/*! @} */
/*! @name GATE42 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE42_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE42_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK)
/*! @} */
/*! @name GATE43 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE43_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE43_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK)
/*! @} */
/*! @name GATE44 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE44_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE44_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK)
/*! @} */
/*! @name GATE45 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE45_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE45_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK)
/*! @} */
/*! @name GATE46 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE46_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE46_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK)
/*! @} */
/*! @name GATE47 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE47_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE47_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK)
/*! @} */
/*! @name GATE48 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE48_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE48_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK)
/*! @} */
/*! @name GATE49 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE49_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE49_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK)
/*! @} */
/*! @name GATE50 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE50_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE50_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK)
/*! @} */
/*! @name GATE51 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE51_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE51_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK)
/*! @} */
/*! @name GATE52 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE52_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE52_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK)
/*! @} */
/*! @name GATE53 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE53_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE53_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK)
/*! @} */
/*! @name GATE54 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE54_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE54_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK)
/*! @} */
/*! @name GATE55 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE55_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE55_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK)
/*! @} */
/*! @name GATE56 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE56_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE56_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK)
/*! @} */
/*! @name GATE57 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE57_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE57_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK)
/*! @} */
/*! @name GATE58 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE58_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE58_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK)
/*! @} */
/*! @name GATE59 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE59_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE59_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK)
/*! @} */
/*! @name GATE60 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE60_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE60_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK)
/*! @} */
/*! @name GATE61 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE61_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE61_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK)
/*! @} */
/*! @name GATE62 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE62_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE62_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK)
/*! @} */
/*! @name GATE63 - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE63_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..The gate has been locked by domain 2.
* 0b11..The gate has been locked by domain 3.
*/
#define RDC_SEMAPHORE_GATE63_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK)
/*! @} */
/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)
/*! RSTGSM
* 0b00..Idle, waiting for the first data pattern write.
* 0b01..Waiting for the second data pattern write.
* 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
* this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
* for only one clock cycle. Software will never be able to observe this state.
* 0b11..This state encoding is never used and therefore reserved.
*/
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
/*! @} */
/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group RDC_SEMAPHORE_Register_Masks */
/* RDC_SEMAPHORE - Peripheral instance base addresses */
/** Peripheral RDC_SEMAPHORE1 base address */
#define RDC_SEMAPHORE1_BASE (0x303B0000u)
/** Peripheral RDC_SEMAPHORE1 base pointer */
#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
/** Peripheral RDC_SEMAPHORE2 base address */
#define RDC_SEMAPHORE2_BASE (0x303C0000u)
/** Peripheral RDC_SEMAPHORE2 base pointer */
#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
/** Array initializer of RDC_SEMAPHORE peripheral base addresses */
#define RDC_SEMAPHORE_BASE_ADDRS { 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/** Array initializer of RDC_SEMAPHORE peripheral base pointers */
#define RDC_SEMAPHORE_BASE_PTRS { (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
/*!
* @}
*/ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SDMAARM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
* @{
*/
/** SDMAARM - Register Layout Typedef */
typedef struct {
__IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */
__IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */
__IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */
__IO uint32_t HSTART; /**< Channel Start, offset: 0xC */
__IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */
__IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */
__IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */
__IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */
uint8_t RESERVED_0[4];
__I uint32_t RESET; /**< Reset Register, offset: 0x24 */
__I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */
__IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */
__I uint32_t PSW; /**< Schedule Status, offset: 0x30 */
__I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */
__IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */
__IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */
__IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */
__IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */
__IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */
__I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */
__IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */
uint8_t RESERVED_1[4];
__IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */
__IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */
__I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */
__I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */
uint8_t RESERVED_2[8];
__IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
__IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
uint8_t RESERVED_3[136];
__IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_4[128];
__IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_5[3392];
__IO uint32_t DONE0_CONFIG; /**< SDMA DONE0 Configuration, offset: 0x1000 */
__IO uint32_t DONE1_CONFIG; /**< SDMA DONE1 Configuration, offset: 0x1004 */
} SDMAARM_Type;
/* ----------------------------------------------------------------------------
-- SDMAARM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
* @{
*/
/*! @name MC0PTR - Arm platform Channel 0 Pointer */
/*! @{ */
#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU)
#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U)
#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK)
/*! @} */
/*! @name INTR - Channel Interrupts */
/*! @{ */
#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU)
#define SDMAARM_INTR_HI_SHIFT (0U)
#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK)
/*! @} */
/*! @name STOP_STAT - Channel Stop/Channel Status */
/*! @{ */
#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU)
#define SDMAARM_STOP_STAT_HE_SHIFT (0U)
#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK)
/*! @} */
/*! @name HSTART - Channel Start */
/*! @{ */
#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU)
#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U)
#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK)
/*! @} */
/*! @name EVTOVR - Channel Event Override */
/*! @{ */
#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU)
#define SDMAARM_EVTOVR_EO_SHIFT (0U)
#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK)
/*! @} */
/*! @name DSPOVR - Channel BP Override */
/*! @{ */
#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU)
#define SDMAARM_DSPOVR_DO_SHIFT (0U)
/*! DO
* 0b00000000000000000000000000000000..- Reserved
* 0b00000000000000000000000000000001..- Reset value.
*/
#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK)
/*! @} */
/*! @name HOSTOVR - Channel Arm platform Override */
/*! @{ */
#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU)
#define SDMAARM_HOSTOVR_HO_SHIFT (0U)
#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK)
/*! @} */
/*! @name EVTPEND - Channel Event Pending */
/*! @{ */
#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU)
#define SDMAARM_EVTPEND_EP_SHIFT (0U)
#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK)
/*! @} */
/*! @name RESET - Reset Register */
/*! @{ */
#define SDMAARM_RESET_RESET_MASK (0x1U)
#define SDMAARM_RESET_RESET_SHIFT (0U)
#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK)
#define SDMAARM_RESET_RESCHED_MASK (0x2U)
#define SDMAARM_RESET_RESCHED_SHIFT (1U)
#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK)
/*! @} */
/*! @name EVTERR - DMA Request Error Register */
/*! @{ */
#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU)
#define SDMAARM_EVTERR_CHNERR_SHIFT (0U)
#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK)
/*! @} */
/*! @name INTRMASK - Channel Arm platform Interrupt Mask */
/*! @{ */
#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU)
#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U)
#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK)
/*! @} */
/*! @name PSW - Schedule Status */
/*! @{ */
#define SDMAARM_PSW_CCR_MASK (0xFU)
#define SDMAARM_PSW_CCR_SHIFT (0U)
#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK)
#define SDMAARM_PSW_CCP_MASK (0xF0U)
#define SDMAARM_PSW_CCP_SHIFT (4U)
/*! CCP
* 0b0000..No running channel
* 0b0001..Active channel priority
*/
#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK)
#define SDMAARM_PSW_NCR_MASK (0x1F00U)
#define SDMAARM_PSW_NCR_SHIFT (8U)
#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK)
#define SDMAARM_PSW_NCP_MASK (0xE000U)
#define SDMAARM_PSW_NCP_SHIFT (13U)
/*! NCP
* 0b000..No running channel
* 0b001..Active channel priority
*/
#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK)
/*! @} */
/*! @name EVTERRDBG - DMA Request Error Register */
/*! @{ */
#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU)
#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U)
#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK)
/*! @} */
/*! @name CONFIG - Configuration Register */
/*! @{ */
#define SDMAARM_CONFIG_CSM_MASK (0x3U)
#define SDMAARM_CONFIG_CSM_SHIFT (0U)
/*! CSM
* 0b00..static
* 0b01..dynamic low power
* 0b10..dynamic with no loop
* 0b11..dynamic
*/
#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK)
#define SDMAARM_CONFIG_ACR_MASK (0x10U)
#define SDMAARM_CONFIG_ACR_SHIFT (4U)
/*! ACR
* 0b0..Arm platform DMA interface frequency equals twice core frequency
* 0b1..Arm platform DMA interface frequency equals core frequency
*/
#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK)
#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U)
#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U)
/*! RTDOBS
* 0b0..RTD pins disabled
* 0b1..RTD pins enabled
*/
#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK)
#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U)
#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U)
/*! DSPDMA
* 0b0..- Reset Value
* 0b1..- Reserved
*/
#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK)
/*! @} */
/*! @name SDMA_LOCK - SDMA LOCK */
/*! @{ */
#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U)
#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U)
/*! LOCK
* 0b0..LOCK disengaged.
* 0b1..LOCK enabled.
*/
#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK)
#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U)
#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U)
/*! SRESET_LOCK_CLR
* 0b0..Software Reset does not clear the LOCK bit.
* 0b1..Software Reset clears the LOCK bit.
*/
#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK)
/*! @} */
/*! @name ONCE_ENB - OnCE Enable */
/*! @{ */
#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U)
#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U)
#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK)
/*! @} */
/*! @name ONCE_DATA - OnCE Data Register */
/*! @{ */
#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU)
#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U)
#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK)
/*! @} */
/*! @name ONCE_INSTR - OnCE Instruction Register */
/*! @{ */
#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU)
#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U)
#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK)
/*! @} */
/*! @name ONCE_STAT - OnCE Status Register */
/*! @{ */
#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U)
#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U)
/*! ECDR
* 0b000..1 matched addra_cond
* 0b001..1 matched addrb_cond
* 0b010..1 matched data_cond
*/
#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK)
#define SDMAARM_ONCE_STAT_MST_MASK (0x80U)
#define SDMAARM_ONCE_STAT_MST_SHIFT (7U)
/*! MST
* 0b0..The JTAG interface controls the OnCE.
* 0b1..The Arm platform peripheral interface controls the OnCE.
*/
#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK)
#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U)
#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U)
#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK)
#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U)
#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U)
#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK)
#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U)
#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U)
#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK)
#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U)
#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U)
#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK)
#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U)
#define SDMAARM_ONCE_STAT_PST_SHIFT (12U)
/*! PST
* 0b0000..Program
* 0b0001..Data
* 0b0010..Change of Flow
* 0b0011..Change of Flow in Loop
* 0b0100..Debug
* 0b0101..Functional Unit
* 0b0110..Sleep
* 0b0111..Save
* 0b1000..Program in Sleep
* 0b1001..Data in Sleep
* 0b0010..Change of Flow in Sleep
* 0b0011..Change Flow in Loop in Sleep
* 0b1100..Debug in Sleep
* 0b1101..Functional Unit in Sleep
* 0b1110..Sleep after Reset
* 0b1111..Restore
*/
#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK)
/*! @} */
/*! @name ONCE_CMD - OnCE Command Register */
/*! @{ */
#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU)
#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U)
/*! CMD
* 0b0000..rstatus
* 0b0001..dmov
* 0b0010..exec_once
* 0b0011..run_core
* 0b0100..exec_core
* 0b0101..debug_rqst
* 0b0110..rbuffer
*/
#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK)
/*! @} */
/*! @name ILLINSTADDR - Illegal Instruction Trap Address */
/*! @{ */
#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU)
#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U)
#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
/*! @} */
/*! @name CHN0ADDR - Channel 0 Boot Address */
/*! @{ */
#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU)
#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U)
#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U)
#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U)
/*! SMSZ
* 0b0..24 words per context
* 0b1..32 words per context
*/
#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK)
/*! @} */
/*! @name EVT_MIRROR - DMA Requests */
/*! @{ */
#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU)
#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U)
/*! EVENTS
* 0b00000000000000000000000000000000..DMA request event not pending
* 0b00000000000000000000000000000001..DMA request event pending
*/
#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK)
/*! @} */
/*! @name EVT_MIRROR2 - DMA Requests 2 */
/*! @{ */
#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU)
#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U)
/*! EVENTS
* 0b0000000000000000..- DMA request event not pending
*/
#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK)
/*! @} */
/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */
/*! @{ */
#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU)
#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U)
#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK)
#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U)
#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U)
/*! CNF0
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK)
#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U)
#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U)
#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK)
#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U)
#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U)
/*! CNF1
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK)
#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U)
#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U)
#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK)
#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U)
#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U)
/*! CNF2
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK)
#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U)
#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U)
#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK)
#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U)
#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U)
/*! CNF3
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK)
/*! @} */
/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */
/*! @{ */
#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU)
#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U)
#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK)
#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U)
#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U)
/*! CNF4
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK)
#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U)
#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U)
#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK)
#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U)
#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U)
/*! CNF5
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK)
#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U)
#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U)
#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK)
#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U)
#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U)
/*! CNF6
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK)
#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U)
#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U)
#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK)
#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U)
#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U)
/*! CNF7
* 0b0..channel
* 0b1..DMA request
*/
#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK)
/*! @} */
/*! @name SDMA_CHNPRI - Channel Priority Registers */
/*! @{ */
#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U)
#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U)
#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
/*! @} */
/* The count of SDMAARM_SDMA_CHNPRI */
#define SDMAARM_SDMA_CHNPRI_COUNT (32U)
/*! @name CHNENBL - Channel Enable RAM */
/*! @{ */
#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU)
#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U)
#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK)
/*! @} */
/* The count of SDMAARM_CHNENBL */
#define SDMAARM_CHNENBL_COUNT (48U)
/*! @name DONE0_CONFIG - SDMA DONE0 Configuration */
/*! @{ */
#define SDMAARM_DONE0_CONFIG_CH_SEL0_MASK (0x1FU)
#define SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT (0U)
#define SDMAARM_DONE0_CONFIG_CH_SEL0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL0_MASK)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK (0x40U)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT (6U)
/*! SW_DONE_DIS0
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK)
#define SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK (0x80U)
#define SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT (7U)
/*! DONE_SEL0
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE0_CONFIG_DONE_SEL0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK)
#define SDMAARM_DONE0_CONFIG_CH_SEL1_MASK (0x1F00U)
#define SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT (8U)
#define SDMAARM_DONE0_CONFIG_CH_SEL1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL1_MASK)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK (0x4000U)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT (14U)
/*! SW_DONE_DIS1
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK)
#define SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK (0x8000U)
#define SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT (15U)
/*! DONE_SEL1
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE0_CONFIG_DONE_SEL1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK)
#define SDMAARM_DONE0_CONFIG_CH_SEL2_MASK (0x1F0000U)
#define SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT (16U)
#define SDMAARM_DONE0_CONFIG_CH_SEL2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL2_MASK)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK (0x400000U)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT (22U)
/*! SW_DONE_DIS2
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK)
#define SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK (0x800000U)
#define SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT (23U)
/*! DONE_SEL2
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE0_CONFIG_DONE_SEL2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK)
#define SDMAARM_DONE0_CONFIG_CH_SEL3_MASK (0x1F000000U)
#define SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT (24U)
#define SDMAARM_DONE0_CONFIG_CH_SEL3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL3_MASK)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK (0x40000000U)
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT (30U)
/*! SW_DONE_DIS3
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK)
#define SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK (0x80000000U)
#define SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT (31U)
/*! DONE_SEL3
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE0_CONFIG_DONE_SEL3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK)
/*! @} */
/*! @name DONE1_CONFIG - SDMA DONE1 Configuration */
/*! @{ */
#define SDMAARM_DONE1_CONFIG_CH_SEL4_MASK (0x1FU)
#define SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT (0U)
#define SDMAARM_DONE1_CONFIG_CH_SEL4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL4_MASK)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK (0x40U)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT (6U)
/*! SW_DONE_DIS4
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK)
#define SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK (0x80U)
#define SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT (7U)
/*! DONE_SEL4
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE1_CONFIG_DONE_SEL4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK)
#define SDMAARM_DONE1_CONFIG_CH_SEL5_MASK (0x1F00U)
#define SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT (8U)
#define SDMAARM_DONE1_CONFIG_CH_SEL5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL5_MASK)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK (0x4000U)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT (14U)
/*! SW_DONE_DIS5
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK)
#define SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK (0x8000U)
#define SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT (15U)
/*! DONE_SEL5
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE1_CONFIG_DONE_SEL5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK)
#define SDMAARM_DONE1_CONFIG_CH_SEL6_MASK (0x1F0000U)
#define SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT (16U)
#define SDMAARM_DONE1_CONFIG_CH_SEL6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL6_MASK)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK (0x400000U)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT (22U)
/*! SW_DONE_DIS6
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK)
#define SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK (0x800000U)
#define SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT (23U)
/*! DONE_SEL6
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE1_CONFIG_DONE_SEL6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK)
#define SDMAARM_DONE1_CONFIG_CH_SEL7_MASK (0x1F000000U)
#define SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT (24U)
#define SDMAARM_DONE1_CONFIG_CH_SEL7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL7_MASK)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK (0x40000000U)
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT (30U)
/*! SW_DONE_DIS7
* 0b0..Enable
* 0b1..Disable
*/
#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK)
#define SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK (0x80000000U)
#define SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT (31U)
/*! DONE_SEL7
* 0b0..HW
* 0b1..SW
*/
#define SDMAARM_DONE1_CONFIG_DONE_SEL7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SDMAARM_Register_Masks */
/* SDMAARM - Peripheral instance base addresses */
/** Peripheral SDMAARM1 base address */
#define SDMAARM1_BASE (0x30BD0000u)
/** Peripheral SDMAARM1 base pointer */
#define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE)
/** Peripheral SDMAARM2 base address */
#define SDMAARM2_BASE (0x30E10000u)
/** Peripheral SDMAARM2 base pointer */
#define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE)
/** Peripheral SDMAARM3 base address */
#define SDMAARM3_BASE (0x30E00000u)
/** Peripheral SDMAARM3 base pointer */
#define SDMAARM3 ((SDMAARM_Type *)SDMAARM3_BASE)
/** Array initializer of SDMAARM peripheral base addresses */
#define SDMAARM_BASE_ADDRS { SDMAARM1_BASE, SDMAARM2_BASE, SDMAARM3_BASE }
/** Array initializer of SDMAARM peripheral base pointers */
#define SDMAARM_BASE_PTRS { SDMAARM1, SDMAARM2, SDMAARM3 }
/** Interrupt vectors for the SDMAARM peripheral type */
#define SDMAARM_IRQS { SDMA1_IRQn, SDMA2_IRQn, SDMA3_IRQn }
/*!
* @}
*/ /* end of group SDMAARM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SEMA4 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
* @{
*/
/** SEMA4 - Register Layout Typedef */
typedef struct {
__IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */
__IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */
__IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */
__IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */
__IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */
__IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */
__IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */
__IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */
__IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */
__IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */
__IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */
__IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */
__IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */
__IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */
__IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */
__IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */
uint8_t RESERVED_0[48];
struct { /* offset: 0x40, array step: 0x8 */
__IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
uint8_t RESERVED_0[6];
} CPINE[2];
uint8_t RESERVED_1[48];
struct { /* offset: 0x80, array step: 0x8 */
__I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
uint8_t RESERVED_0[6];
} CPNTF[2];
uint8_t RESERVED_2[112];
__IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
uint8_t RESERVED_3[2];
__IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
} SEMA4_Type;
/* ----------------------------------------------------------------------------
-- SEMA4 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
* @{
*/
/*! @name Gate00 - Semaphores Gate 0 Register */
/*! @{ */
#define SEMA4_Gate00_GTFSM_MASK (0x3U)
#define SEMA4_Gate00_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK)
/*! @} */
/*! @name Gate01 - Semaphores Gate 1 Register */
/*! @{ */
#define SEMA4_Gate01_GTFSM_MASK (0x3U)
#define SEMA4_Gate01_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK)
/*! @} */
/*! @name Gate02 - Semaphores Gate 2 Register */
/*! @{ */
#define SEMA4_Gate02_GTFSM_MASK (0x3U)
#define SEMA4_Gate02_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK)
/*! @} */
/*! @name Gate03 - Semaphores Gate 3 Register */
/*! @{ */
#define SEMA4_Gate03_GTFSM_MASK (0x3U)
#define SEMA4_Gate03_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK)
/*! @} */
/*! @name Gate04 - Semaphores Gate 4 Register */
/*! @{ */
#define SEMA4_Gate04_GTFSM_MASK (0x3U)
#define SEMA4_Gate04_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK)
/*! @} */
/*! @name Gate05 - Semaphores Gate 5 Register */
/*! @{ */
#define SEMA4_Gate05_GTFSM_MASK (0x3U)
#define SEMA4_Gate05_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK)
/*! @} */
/*! @name Gate06 - Semaphores Gate 6 Register */
/*! @{ */
#define SEMA4_Gate06_GTFSM_MASK (0x3U)
#define SEMA4_Gate06_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK)
/*! @} */
/*! @name Gate07 - Semaphores Gate 7 Register */
/*! @{ */
#define SEMA4_Gate07_GTFSM_MASK (0x3U)
#define SEMA4_Gate07_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK)
/*! @} */
/*! @name Gate08 - Semaphores Gate 8 Register */
/*! @{ */
#define SEMA4_Gate08_GTFSM_MASK (0x3U)
#define SEMA4_Gate08_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK)
/*! @} */
/*! @name Gate09 - Semaphores Gate 9 Register */
/*! @{ */
#define SEMA4_Gate09_GTFSM_MASK (0x3U)
#define SEMA4_Gate09_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK)
/*! @} */
/*! @name Gate10 - Semaphores Gate 10 Register */
/*! @{ */
#define SEMA4_Gate10_GTFSM_MASK (0x3U)
#define SEMA4_Gate10_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK)
/*! @} */
/*! @name Gate11 - Semaphores Gate 11 Register */
/*! @{ */
#define SEMA4_Gate11_GTFSM_MASK (0x3U)
#define SEMA4_Gate11_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK)
/*! @} */
/*! @name Gate12 - Semaphores Gate 12 Register */
/*! @{ */
#define SEMA4_Gate12_GTFSM_MASK (0x3U)
#define SEMA4_Gate12_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK)
/*! @} */
/*! @name Gate13 - Semaphores Gate 13 Register */
/*! @{ */
#define SEMA4_Gate13_GTFSM_MASK (0x3U)
#define SEMA4_Gate13_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK)
/*! @} */
/*! @name Gate14 - Semaphores Gate 14 Register */
/*! @{ */
#define SEMA4_Gate14_GTFSM_MASK (0x3U)
#define SEMA4_Gate14_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK)
/*! @} */
/*! @name Gate15 - Semaphores Gate 15 Register */
/*! @{ */
#define SEMA4_Gate15_GTFSM_MASK (0x3U)
#define SEMA4_Gate15_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK)
/*! @} */
/*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
/*! @{ */
#define SEMA4_CPINE_INE7_MASK (0x1U)
#define SEMA4_CPINE_INE7_SHIFT (0U)
/*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 7.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
#define SEMA4_CPINE_INE6_MASK (0x2U)
#define SEMA4_CPINE_INE6_SHIFT (1U)
/*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 6.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
#define SEMA4_CPINE_INE5_MASK (0x4U)
#define SEMA4_CPINE_INE5_SHIFT (2U)
/*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 5.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
#define SEMA4_CPINE_INE4_MASK (0x8U)
#define SEMA4_CPINE_INE4_SHIFT (3U)
/*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 4.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
#define SEMA4_CPINE_INE3_MASK (0x10U)
#define SEMA4_CPINE_INE3_SHIFT (4U)
/*! INE3
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
#define SEMA4_CPINE_INE2_MASK (0x20U)
#define SEMA4_CPINE_INE2_SHIFT (5U)
/*! INE2
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
#define SEMA4_CPINE_INE1_MASK (0x40U)
#define SEMA4_CPINE_INE1_SHIFT (6U)
/*! INE1
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
#define SEMA4_CPINE_INE0_MASK (0x80U)
#define SEMA4_CPINE_INE0_SHIFT (7U)
/*! INE0
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
#define SEMA4_CPINE_INE15_MASK (0x100U)
#define SEMA4_CPINE_INE15_SHIFT (8U)
/*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 15.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
#define SEMA4_CPINE_INE14_MASK (0x200U)
#define SEMA4_CPINE_INE14_SHIFT (9U)
/*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 14.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
#define SEMA4_CPINE_INE13_MASK (0x400U)
#define SEMA4_CPINE_INE13_SHIFT (10U)
/*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 13.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
#define SEMA4_CPINE_INE12_MASK (0x800U)
#define SEMA4_CPINE_INE12_SHIFT (11U)
/*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 12.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
#define SEMA4_CPINE_INE11_MASK (0x1000U)
#define SEMA4_CPINE_INE11_SHIFT (12U)
/*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 11.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
#define SEMA4_CPINE_INE10_MASK (0x2000U)
#define SEMA4_CPINE_INE10_SHIFT (13U)
/*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 10.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
#define SEMA4_CPINE_INE9_MASK (0x4000U)
#define SEMA4_CPINE_INE9_SHIFT (14U)
/*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 9.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
#define SEMA4_CPINE_INE8_MASK (0x8000U)
#define SEMA4_CPINE_INE8_SHIFT (15U)
/*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 8.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
/*! @} */
/* The count of SEMA4_CPINE */
#define SEMA4_CPINE_COUNT (2U)
/*! @name CPNTF - Semaphores Processor n IRQ Notification */
/*! @{ */
#define SEMA4_CPNTF_GN7_MASK (0x1U)
#define SEMA4_CPNTF_GN7_SHIFT (0U)
#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
#define SEMA4_CPNTF_GN6_MASK (0x2U)
#define SEMA4_CPNTF_GN6_SHIFT (1U)
#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
#define SEMA4_CPNTF_GN5_MASK (0x4U)
#define SEMA4_CPNTF_GN5_SHIFT (2U)
#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
#define SEMA4_CPNTF_GN4_MASK (0x8U)
#define SEMA4_CPNTF_GN4_SHIFT (3U)
#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
#define SEMA4_CPNTF_GN3_MASK (0x10U)
#define SEMA4_CPNTF_GN3_SHIFT (4U)
#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
#define SEMA4_CPNTF_GN2_MASK (0x20U)
#define SEMA4_CPNTF_GN2_SHIFT (5U)
#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
#define SEMA4_CPNTF_GN1_MASK (0x40U)
#define SEMA4_CPNTF_GN1_SHIFT (6U)
#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
#define SEMA4_CPNTF_GN0_MASK (0x80U)
#define SEMA4_CPNTF_GN0_SHIFT (7U)
#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
#define SEMA4_CPNTF_GN15_MASK (0x100U)
#define SEMA4_CPNTF_GN15_SHIFT (8U)
#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
#define SEMA4_CPNTF_GN14_MASK (0x200U)
#define SEMA4_CPNTF_GN14_SHIFT (9U)
#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
#define SEMA4_CPNTF_GN13_MASK (0x400U)
#define SEMA4_CPNTF_GN13_SHIFT (10U)
#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
#define SEMA4_CPNTF_GN12_MASK (0x800U)
#define SEMA4_CPNTF_GN12_SHIFT (11U)
#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
#define SEMA4_CPNTF_GN11_MASK (0x1000U)
#define SEMA4_CPNTF_GN11_SHIFT (12U)
#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
#define SEMA4_CPNTF_GN10_MASK (0x2000U)
#define SEMA4_CPNTF_GN10_SHIFT (13U)
#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
#define SEMA4_CPNTF_GN9_MASK (0x4000U)
#define SEMA4_CPNTF_GN9_SHIFT (14U)
#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
#define SEMA4_CPNTF_GN8_MASK (0x8000U)
#define SEMA4_CPNTF_GN8_SHIFT (15U)
#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
/*! @} */
/* The count of SEMA4_CPNTF */
#define SEMA4_CPNTF_COUNT (2U)
/*! @name RSTGT - Semaphores (Secure) Reset Gate n */
/*! @{ */
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)
#define SEMA4_RSTGT_RSTGTN_SHIFT (8U)
#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
/*! @} */
/*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
/*! @{ */
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)
#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U)
#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SEMA4_Register_Masks */
/* SEMA4 - Peripheral instance base addresses */
/** Peripheral SEMA4 base address */
#define SEMA4_BASE (0x30AC0000u)
/** Peripheral SEMA4 base pointer */
#define SEMA4 ((SEMA4_Type *)SEMA4_BASE)
/** Array initializer of SEMA4 peripheral base addresses */
#define SEMA4_BASE_ADDRS { SEMA4_BASE }
/** Array initializer of SEMA4 peripheral base pointers */
#define SEMA4_BASE_PTRS { SEMA4 }
/*!
* @}
*/ /* end of group SEMA4_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
* @{
*/
/** SNVS - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
__IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
uint8_t RESERVED_1[8];
__IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
uint8_t RESERVED_2[12];
__IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
__IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
__IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
__IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
__IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
__IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
uint8_t RESERVED_3[16];
__IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
uint8_t RESERVED_4[12];
__IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
__IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
__IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
__IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
uint8_t RESERVED_5[36];
__IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
uint8_t RESERVED_6[96];
__IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_7[2792];
__I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
__I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
} SNVS_Type;
/* ----------------------------------------------------------------------------
-- SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Register_Masks SNVS Register Masks
* @{
*/
/*! @name HPCOMR - SNVS_HP Command Register */
/*! @{ */
#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
/*! LP_SWR
* 0b0..No Action
* 0b1..Reset LP section
*/
#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
/*! LP_SWR_DIS
* 0b0..LP software reset is enabled
* 0b1..LP software reset is disabled
*/
#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
/*! @} */
/*! @name HPCR - SNVS_HP Control Register */
/*! @{ */
#define SNVS_HPCR_RTC_EN_MASK (0x1U)
#define SNVS_HPCR_RTC_EN_SHIFT (0U)
/*! RTC_EN
* 0b0..RTC is disabled
* 0b1..RTC is enabled
*/
#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
/*! HPTA_EN
* 0b0..HP Time Alarm Interrupt is disabled
* 0b1..HP Time Alarm Interrupt is enabled
*/
#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
/*! HPCALB_EN
* 0b0..HP Timer calibration disabled
* 0b1..HP Timer calibration enabled
*/
#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
/*! HPCALB_VAL
* 0b00000..+0 counts per each 32768 ticks of the counter
* 0b00001..+1 counts per each 32768 ticks of the counter
* 0b00010..+2 counts per each 32768 ticks of the counter
* 0b01111..+15 counts per each 32768 ticks of the counter
* 0b10000..-16 counts per each 32768 ticks of the counter
* 0b10001..-15 counts per each 32768 ticks of the counter
* 0b11110..-2 counts per each 32768 ticks of the counter
* 0b11111..-1 counts per each 32768 ticks of the counter
*/
#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
/*! @} */
/*! @name HPSR - SNVS_HP Status Register */
/*! @{ */
#define SNVS_HPSR_HPTA_MASK (0x1U)
#define SNVS_HPSR_HPTA_SHIFT (0U)
/*! HPTA
* 0b0..No time alarm interrupt occurred.
* 0b1..A time alarm interrupt occurred.
*/
#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
#define SNVS_HPSR_LPDIS_MASK (0x10U)
#define SNVS_HPSR_LPDIS_SHIFT (4U)
#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
#define SNVS_HPSR_BTN_MASK (0x40U)
#define SNVS_HPSR_BTN_SHIFT (6U)
#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
#define SNVS_HPSR_BI_MASK (0x80U)
#define SNVS_HPSR_BI_SHIFT (7U)
#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
/*! @} */
/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
/*! @{ */
#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
#define SNVS_HPRTCMR_RTC_SHIFT (0U)
#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
/*! @} */
/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
/*! @{ */
#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
#define SNVS_HPRTCLR_RTC_SHIFT (0U)
#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
/*! @} */
/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
/*! @{ */
#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
/*! @} */
/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
/*! @{ */
#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
/*! @} */
/*! @name LPLR - SNVS_LP Lock Register */
/*! @{ */
#define SNVS_LPLR_MC_HL_MASK (0x10U)
#define SNVS_LPLR_MC_HL_SHIFT (4U)
/*! MC_HL
* 0b0..Write access (increment) is allowed.
* 0b1..Write access (increment) is not allowed.
*/
#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
#define SNVS_LPLR_GPR_HL_MASK (0x20U)
#define SNVS_LPLR_GPR_HL_SHIFT (5U)
/*! GPR_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
/*! @} */
/*! @name LPCR - SNVS_LP Control Register */
/*! @{ */
#define SNVS_LPCR_MC_ENV_MASK (0x4U)
#define SNVS_LPCR_MC_ENV_SHIFT (2U)
/*! MC_ENV
* 0b0..MC is disabled or invalid.
* 0b1..MC is enabled and valid.
*/
#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
#define SNVS_LPCR_DP_EN_MASK (0x20U)
#define SNVS_LPCR_DP_EN_SHIFT (5U)
/*! DP_EN
* 0b0..Smart PMIC enabled.
* 0b1..Dumb PMIC enabled.
*/
#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
#define SNVS_LPCR_TOP_MASK (0x40U)
#define SNVS_LPCR_TOP_SHIFT (6U)
/*! TOP
* 0b0..Leave system power on.
* 0b1..Turn off system power.
*/
#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
#define SNVS_LPCR_ON_TIME_SHIFT (20U)
#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
#define SNVS_LPCR_PK_EN_MASK (0x400000U)
#define SNVS_LPCR_PK_EN_SHIFT (22U)
#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
/*! @} */
/*! @name LPSR - SNVS_LP Status Register */
/*! @{ */
#define SNVS_LPSR_MCR_MASK (0x4U)
#define SNVS_LPSR_MCR_SHIFT (2U)
/*! MCR
* 0b0..MC has not reached its maximum value.
* 0b1..MC has reached its maximum value.
*/
#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
#define SNVS_LPSR_EO_MASK (0x20000U)
#define SNVS_LPSR_EO_SHIFT (17U)
/*! EO
* 0b0..Emergency off was not detected.
* 0b1..Emergency off was detected.
*/
#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
#define SNVS_LPSR_SPOF_MASK (0x40000U)
#define SNVS_LPSR_SPOF_SHIFT (18U)
/*! SPOF
* 0b0..Set Power Off was not detected.
* 0b1..Set Power Off was detected.
*/
#define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
/*! @} */
/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
/*! @{ */
#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
/*! @} */
/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
/*! @{ */
#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
/*! @} */
/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
/*! @{ */
#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
#define SNVS_LPPGDR_PGD_SHIFT (0U)
#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
/*! @} */
/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
/*! @{ */
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
/*! @} */
/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
/*! @{ */
#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR_ALIAS */
#define SNVS_LPGPR_ALIAS_COUNT (4U)
/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
/*! @{ */
#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_GPR_SHIFT (0U)
#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR */
#define SNVS_LPGPR_COUNT (4U)
/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
/*! @{ */
#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
/*! @} */
/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
/*! @{ */
#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SNVS_Register_Masks */
/* SNVS - Peripheral instance base addresses */
/** Peripheral SNVS base address */
#define SNVS_BASE (0x30370000u)
/** Peripheral SNVS base pointer */
#define SNVS ((SNVS_Type *)SNVS_BASE)
/** Array initializer of SNVS peripheral base addresses */
#define SNVS_BASE_ADDRS { SNVS_BASE }
/** Array initializer of SNVS peripheral base pointers */
#define SNVS_BASE_PTRS { SNVS }
/*!
* @}
*/ /* end of group SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPBA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
* @{
*/
/** SPBA - Register Layout Typedef */
typedef struct {
__IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
} SPBA_Type;
/* ----------------------------------------------------------------------------
-- SPBA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPBA_Register_Masks SPBA Register Masks
* @{
*/
/*! @name PRR - Peripheral Rights Register */
/*! @{ */
#define SPBA_PRR_RARA_MASK (0x1U)
#define SPBA_PRR_RARA_SHIFT (0U)
/*! RARA
* 0b0..Access to peripheral is not allowed.
* 0b1..Access to peripheral is granted.
*/
#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK)
#define SPBA_PRR_RARB_MASK (0x2U)
#define SPBA_PRR_RARB_SHIFT (1U)
/*! RARB
* 0b0..Access to peripheral is not allowed.
* 0b1..Access to peripheral is granted.
*/
#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK)
#define SPBA_PRR_RARC_MASK (0x4U)
#define SPBA_PRR_RARC_SHIFT (2U)
/*! RARC
* 0b0..Access to peripheral is not allowed.
* 0b1..Access to peripheral is granted.
*/
#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK)
#define SPBA_PRR_ROI_MASK (0x30000U)
#define SPBA_PRR_ROI_SHIFT (16U)
/*! ROI
* 0b00..Unowned resource.
* 0b01..The resource is owned by master A port.
* 0b10..The resource is owned by master B port.
* 0b11..The resource is owned by master C port.
*/
#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK)
#define SPBA_PRR_RMO_MASK (0xC0000000U)
#define SPBA_PRR_RMO_SHIFT (30U)
/*! RMO
* 0b00..The resource is unowned.
* 0b01..Reserved.
* 0b10..The resource is owned by another master.
* 0b11..The resource is owned by the requesting master.
*/
#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK)
/*! @} */
/* The count of SPBA_PRR */
#define SPBA_PRR_COUNT (32U)
/*!
* @}
*/ /* end of group SPBA_Register_Masks */
/* SPBA - Peripheral instance base addresses */
/** Peripheral SPBA1 base address */
#define SPBA1_BASE (0x308F0000u)
/** Peripheral SPBA1 base pointer */
#define SPBA1 ((SPBA_Type *)SPBA1_BASE)
/** Peripheral SPBA2 base address */
#define SPBA2_BASE (0x30CF0000u)
/** Peripheral SPBA2 base pointer */
#define SPBA2 ((SPBA_Type *)SPBA2_BASE)
/** Array initializer of SPBA peripheral base addresses */
#define SPBA_BASE_ADDRS { SPBA1_BASE, SPBA2_BASE }
/** Array initializer of SPBA peripheral base pointers */
#define SPBA_BASE_PTRS { SPBA1, SPBA2 }
/*!
* @}
*/ /* end of group SPBA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
* @{
*/
/** SRC - Register Layout Typedef */
typedef struct {
__IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */
__IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */
__IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */
__IO uint32_t M7RCR; /**< M7 Reset Control Register, offset: 0xC */
uint8_t RESERVED_0[8];
__IO uint32_t SUPERMIX_RCR; /**< SUPERMIX Reset Control Register, offset: 0x18 */
__IO uint32_t AUDIOMIX_RCR; /**< AUDIOMIX Reset Control Register, offset: 0x1C */
__IO uint32_t USBPHY1_RCR; /**< USB PHY1 Reset Control Register, offset: 0x20 */
__IO uint32_t USBPHY2_RCR; /**< USB PHY2 Reset Control Register, offset: 0x24 */
__IO uint32_t MLMIX_RCR; /**< MLMIX Reset Control Register, offset: 0x28 */
__IO uint32_t PCIEPHY_RCR; /**< PCIE PHY Reset Control Register, offset: 0x2C */
__IO uint32_t HDMI_RCR; /**< HDMI Reset Control Register, offset: 0x30 */
__IO uint32_t MEDIA_RCR; /**< MEDIAMIX Reset Control Register, offset: 0x34 */
__IO uint32_t GPU2D_RCR; /**< GPU2D Reset Control Register, offset: 0x38 */
__IO uint32_t GPU3D_RCR; /**< GPU3D Reset Control Register, offset: 0x3C */
__IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */
__IO uint32_t VPU_RCR; /**< VPU Reset Control Register, offset: 0x44 */
__IO uint32_t VPU_G1_RCR; /**< VPU G1 Reset Control Register, offset: 0x48 */
__IO uint32_t VPU_G2_RCR; /**< VPU G2 Reset Control Register, offset: 0x4C */
__IO uint32_t VPUVC8KE_RCR; /**< VPU VC8000E Reset Control Register, offset: 0x50 */
__IO uint32_t NOC_RCR; /**< NOC Wrapper Reset Control Register, offset: 0x54 */
__I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */
__IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */
uint8_t RESERVED_1[8];
__IO uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */
__IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */
__I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */
__IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x74 */
__IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x78 */
__IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x7C */
__IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x80 */
__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84 */
__IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x88 */
__IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x8C */
__IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x90 */
uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x94 */
uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x98 */
uint8_t RESERVED_2[3940];
__IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */
uint8_t RESERVED_3[4];
__IO uint32_t HDMIPHY_RCR; /**< HDMIPHY Reset Control Register, offset: 0x1008 */
__IO uint32_t MIPIPHY1_RCR; /**< MIPI PHY1 Reset Control Register, offset: 0x100C */
__IO uint32_t MIPIPHY2_RCR; /**< MIPI PHY2 Reset Control Register, offset: 0x1010 */
__IO uint32_t HSIO_RCR; /**< HSIO Reset Control Register, offset: 0x1014 */
__IO uint32_t MEDIAISPDWP_RCR; /**< MEDIAMIX ISP and Dewarp Reset Control Register, offset: 0x1018 */
} SRC_Type;
/* ----------------------------------------------------------------------------
-- SRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Register_Masks SRC Register Masks
* @{
*/
/*! @name SCR - SRC Reset Control Register */
/*! @{ */
#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U)
#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U)
/*! MASK_TEMPSENSE_RESET
* 0b0101..tempsense_reset is masked
* 0b1010..tempsense_reset is not masked
*/
#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK)
#define SRC_SCR_DOMAIN0_MASK (0x1000000U)
#define SRC_SCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK)
#define SRC_SCR_DOMAIN1_MASK (0x2000000U)
#define SRC_SCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK)
#define SRC_SCR_DOMAIN2_MASK (0x4000000U)
#define SRC_SCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK)
#define SRC_SCR_DOMAIN3_MASK (0x8000000U)
#define SRC_SCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK)
#define SRC_SCR_LOCK_MASK (0x40000000U)
#define SRC_SCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK)
#define SRC_SCR_DOM_EN_MASK (0x80000000U)
#define SRC_SCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK)
/*! @} */
/*! @name A53RCR0 - A53 Reset Control Register */
/*! @{ */
#define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U)
#define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U)
/*! A53_CORE_POR_RESET0
* 0b0..do not assert core0 reset
* 0b1..assert core0 reset
*/
#define SRC_A53RCR0_A53_CORE_POR_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK)
#define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U)
#define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U)
/*! A53_CORE_POR_RESET1
* 0b0..do not assert core1 reset
* 0b1..assert core1 reset
*/
#define SRC_A53RCR0_A53_CORE_POR_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK)
#define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U)
#define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U)
/*! A53_CORE_POR_RESET2
* 0b0..do not assert core2 reset
* 0b1..assert core2 reset
*/
#define SRC_A53RCR0_A53_CORE_POR_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK)
#define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U)
#define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U)
/*! A53_CORE_POR_RESET3
* 0b0..do not assert core3 reset
* 0b1..assert core3 reset
*/
#define SRC_A53RCR0_A53_CORE_POR_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK)
#define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U)
#define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U)
/*! A53_CORE_RESET0
* 0b0..do not assert core0 reset
* 0b1..assert core0 reset
*/
#define SRC_A53RCR0_A53_CORE_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK)
#define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U)
#define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U)
/*! A53_CORE_RESET1
* 0b0..do not assert core1 reset
* 0b1..assert core1 reset
*/
#define SRC_A53RCR0_A53_CORE_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK)
#define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U)
#define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U)
/*! A53_CORE_RESET2
* 0b0..do not assert core2 reset
* 0b1..assert core2 reset
*/
#define SRC_A53RCR0_A53_CORE_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK)
#define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U)
#define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U)
/*! A53_CORE_RESET3
* 0b0..do not assert core3 reset
* 0b1..assert core3 reset
*/
#define SRC_A53RCR0_A53_CORE_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK)
#define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U)
#define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U)
/*! A53_DBG_RESET0
* 0b0..do not assert core0 debug reset
* 0b1..assert core0 debug reset
*/
#define SRC_A53RCR0_A53_DBG_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK)
#define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U)
#define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U)
/*! A53_DBG_RESET1
* 0b0..do not assert core1 debug reset
* 0b1..assert core1 debug reset
*/
#define SRC_A53RCR0_A53_DBG_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK)
#define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U)
#define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U)
/*! A53_DBG_RESET2
* 0b0..do not assert core2 debug reset
* 0b1..assert core2 debug reset
*/
#define SRC_A53RCR0_A53_DBG_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK)
#define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U)
#define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U)
/*! A53_DBG_RESET3
* 0b0..do not assert core3 debug reset
* 0b1..assert core3 debug reset
*/
#define SRC_A53RCR0_A53_DBG_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK)
#define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U)
#define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U)
/*! A53_ETM_RESET0
* 0b0..do not assert core0 ETM reset
* 0b1..assert core0 ETM reset
*/
#define SRC_A53RCR0_A53_ETM_RESET0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK)
#define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U)
#define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U)
/*! A53_ETM_RESET1
* 0b0..do not assert core1 ETM reset
* 0b1..assert core1 ETM reset
*/
#define SRC_A53RCR0_A53_ETM_RESET1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK)
#define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U)
#define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U)
/*! A53_ETM_RESET2
* 0b0..do not assert core2 ETM reset
* 0b1..assert core2 ETM reset
*/
#define SRC_A53RCR0_A53_ETM_RESET2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK)
#define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U)
#define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U)
/*! A53_ETM_RESET3
* 0b0..do not assert core3 ETM reset
* 0b1..assert core3 ETM reset
*/
#define SRC_A53RCR0_A53_ETM_RESET3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK)
#define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U)
#define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U)
/*! MASK_WDOG1_RST
* 0b0101..wdog1_rst_b is masked
* 0b1010..wdog1_rst_b is not masked
*/
#define SRC_A53RCR0_MASK_WDOG1_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK)
#define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U)
#define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U)
/*! A53_SOC_DBG_RESET
* 0b0..do not assert system level debug reset
* 0b1..assert system level debug reset
*/
#define SRC_A53RCR0_A53_SOC_DBG_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK)
#define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U)
#define SRC_A53RCR0_A53_L2RESET_SHIFT (21U)
/*! A53_L2RESET
* 0b0..do not assert SCU reset
* 0b1..assert SCU reset
*/
#define SRC_A53RCR0_A53_L2RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK)
#define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U)
#define SRC_A53RCR0_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK)
#define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U)
#define SRC_A53RCR0_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK)
#define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U)
#define SRC_A53RCR0_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK)
#define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U)
#define SRC_A53RCR0_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK)
#define SRC_A53RCR0_LOCK_MASK (0x40000000U)
#define SRC_A53RCR0_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK)
#define SRC_A53RCR0_DOM_EN_MASK (0x80000000U)
#define SRC_A53RCR0_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK)
/*! @} */
/*! @name A53RCR1 - A53 Reset Control Register */
/*! @{ */
#define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U)
#define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U)
#define SRC_A53RCR1_A53_CORE0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK)
#define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U)
#define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U)
/*! A53_CORE1_ENABLE
* 0b0..core1 is disabled
* 0b1..core1 is enabled
*/
#define SRC_A53RCR1_A53_CORE1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK)
#define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U)
#define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U)
/*! A53_CORE2_ENABLE
* 0b0..core2 is disabled
* 0b1..core2 is enabled
*/
#define SRC_A53RCR1_A53_CORE2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK)
#define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U)
#define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U)
/*! A53_CORE3_ENABLE
* 0b0..core3 is disabled
* 0b1..core3 is enabled
*/
#define SRC_A53RCR1_A53_CORE3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK)
#define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U)
#define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U)
/*! A53_RST_SLOW - A53_RST_SLOW
*/
#define SRC_A53RCR1_A53_RST_SLOW(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK)
#define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U)
#define SRC_A53RCR1_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK)
#define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U)
#define SRC_A53RCR1_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK)
#define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U)
#define SRC_A53RCR1_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK)
#define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U)
#define SRC_A53RCR1_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK)
#define SRC_A53RCR1_LOCK_MASK (0x40000000U)
#define SRC_A53RCR1_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK)
#define SRC_A53RCR1_DOM_EN_MASK (0x80000000U)
#define SRC_A53RCR1_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK)
/*! @} */
/*! @name M7RCR - M7 Reset Control Register */
/*! @{ */
#define SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK (0x1U)
#define SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT (0U)
/*! SW_M7C_NON_SCLR_RST
* 0b0..do not assert M7 core reset
* 0b1..assert M7 core reset
*/
#define SRC_M7RCR_SW_M7C_NON_SCLR_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT)) & SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK)
#define SRC_M7RCR_SW_M7C_RST_MASK (0x2U)
#define SRC_M7RCR_SW_M7C_RST_SHIFT (1U)
/*! SW_M7C_RST
* 0b0..do not assert M7 core reset
* 0b1..assert M7 core reset
*/
#define SRC_M7RCR_SW_M7C_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_RST_SHIFT)) & SRC_M7RCR_SW_M7C_RST_MASK)
#define SRC_M7RCR_ENABLE_M7_MASK (0x8U)
#define SRC_M7RCR_ENABLE_M7_SHIFT (3U)
/*! ENABLE_M7
* 0b0..M7 is disabled
* 0b1..M7 is enabled
*/
#define SRC_M7RCR_ENABLE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_ENABLE_M7_SHIFT)) & SRC_M7RCR_ENABLE_M7_MASK)
#define SRC_M7RCR_MASK_WDOG3_RST_MASK (0xF0U)
#define SRC_M7RCR_MASK_WDOG3_RST_SHIFT (4U)
/*! MASK_WDOG3_RST
* 0b0101..wdog3_rst_b is masked
* 0b1010..wdog3_rst_b is not masked
*/
#define SRC_M7RCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M7RCR_MASK_WDOG3_RST_MASK)
#define SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK (0x100U)
#define SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT (8U)
/*! WDOG3_RST_OPTION_M7
* 0b0..wdgo3_rst_b Reset M7 core only
* 0b1..Reset both M7 core and platform
*/
#define SRC_M7RCR_WDOG3_RST_OPTION_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK)
#define SRC_M7RCR_WDOG3_RST_OPTION_MASK (0x200U)
#define SRC_M7RCR_WDOG3_RST_OPTION_SHIFT (9U)
/*! WDOG3_RST_OPTION
* 0b0..Wdog3_rst_b asserts M7 reset
* 0b1..Wdog3_rst_b asserts global reset
*/
#define SRC_M7RCR_WDOG3_RST_OPTION(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_MASK)
#define SRC_M7RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_M7RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_M7RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN0_SHIFT)) & SRC_M7RCR_DOMAIN0_MASK)
#define SRC_M7RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_M7RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_M7RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN1_SHIFT)) & SRC_M7RCR_DOMAIN1_MASK)
#define SRC_M7RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_M7RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_M7RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN2_SHIFT)) & SRC_M7RCR_DOMAIN2_MASK)
#define SRC_M7RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_M7RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_M7RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN3_SHIFT)) & SRC_M7RCR_DOMAIN3_MASK)
#define SRC_M7RCR_LOCK_MASK (0x40000000U)
#define SRC_M7RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_M7RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_LOCK_SHIFT)) & SRC_M7RCR_LOCK_MASK)
#define SRC_M7RCR_DOM_EN_MASK (0x80000000U)
#define SRC_M7RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_M7RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOM_EN_SHIFT)) & SRC_M7RCR_DOM_EN_MASK)
/*! @} */
/*! @name SUPERMIX_RCR - SUPERMIX Reset Control Register */
/*! @{ */
#define SRC_SUPERMIX_RCR_SUPERMIX_RESET_MASK (0x1U)
#define SRC_SUPERMIX_RCR_SUPERMIX_RESET_SHIFT (0U)
/*! SUPERMIX_RESET
* 0b0..Do not assert SUPERMIX reset
* 0b1..Assert SUPERMIX reset
*/
#define SRC_SUPERMIX_RCR_SUPERMIX_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_SUPERMIX_RESET_SHIFT)) & SRC_SUPERMIX_RCR_SUPERMIX_RESET_MASK)
#define SRC_SUPERMIX_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_SUPERMIX_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_SUPERMIX_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN0_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN0_MASK)
#define SRC_SUPERMIX_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_SUPERMIX_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_SUPERMIX_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN1_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN1_MASK)
#define SRC_SUPERMIX_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_SUPERMIX_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_SUPERMIX_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN2_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN2_MASK)
#define SRC_SUPERMIX_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_SUPERMIX_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_SUPERMIX_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOMAIN3_SHIFT)) & SRC_SUPERMIX_RCR_DOMAIN3_MASK)
#define SRC_SUPERMIX_RCR_LOCK_MASK (0x40000000U)
#define SRC_SUPERMIX_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_SUPERMIX_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_LOCK_SHIFT)) & SRC_SUPERMIX_RCR_LOCK_MASK)
#define SRC_SUPERMIX_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_SUPERMIX_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_SUPERMIX_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SUPERMIX_RCR_DOM_EN_SHIFT)) & SRC_SUPERMIX_RCR_DOM_EN_MASK)
/*! @} */
/*! @name AUDIOMIX_RCR - AUDIOMIX Reset Control Register */
/*! @{ */
#define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_MASK (0x1U)
#define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_SHIFT (0U)
/*! AUDIOMIX_RESET
* 0b0..Do not assert AUDIOMIX reset
* 0b1..Assert AUDIOMIX reset
*/
#define SRC_AUDIOMIX_RCR_AUDIOMIX_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_SHIFT)) & SRC_AUDIOMIX_RCR_AUDIOMIX_RESET_MASK)
#define SRC_AUDIOMIX_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_AUDIOMIX_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_AUDIOMIX_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN0_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN0_MASK)
#define SRC_AUDIOMIX_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_AUDIOMIX_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_AUDIOMIX_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN1_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN1_MASK)
#define SRC_AUDIOMIX_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_AUDIOMIX_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_AUDIOMIX_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN2_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN2_MASK)
#define SRC_AUDIOMIX_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_AUDIOMIX_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_AUDIOMIX_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOMAIN3_SHIFT)) & SRC_AUDIOMIX_RCR_DOMAIN3_MASK)
#define SRC_AUDIOMIX_RCR_LOCK_MASK (0x40000000U)
#define SRC_AUDIOMIX_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_AUDIOMIX_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_LOCK_SHIFT)) & SRC_AUDIOMIX_RCR_LOCK_MASK)
#define SRC_AUDIOMIX_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_AUDIOMIX_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_AUDIOMIX_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUDIOMIX_RCR_DOM_EN_SHIFT)) & SRC_AUDIOMIX_RCR_DOM_EN_MASK)
/*! @} */
/*! @name USBPHY1_RCR - USB PHY1 Reset Control Register */
/*! @{ */
#define SRC_USBPHY1_RCR_USB1_PHY_RESET_MASK (0x1U)
#define SRC_USBPHY1_RCR_USB1_PHY_RESET_SHIFT (0U)
/*! USB1_PHY_RESET
* 0b0..Don't reset USB 1 PHY
* 0b1..Reset USB 1 PHY
*/
#define SRC_USBPHY1_RCR_USB1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_USB1_PHY_RESET_SHIFT)) & SRC_USBPHY1_RCR_USB1_PHY_RESET_MASK)
#define SRC_USBPHY1_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_USBPHY1_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_USBPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN0_MASK)
#define SRC_USBPHY1_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_USBPHY1_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_USBPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN1_MASK)
#define SRC_USBPHY1_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_USBPHY1_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_USBPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN2_MASK)
#define SRC_USBPHY1_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_USBPHY1_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_USBPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBPHY1_RCR_DOMAIN3_MASK)
#define SRC_USBPHY1_RCR_LOCK_MASK (0x40000000U)
#define SRC_USBPHY1_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_USBPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_LOCK_SHIFT)) & SRC_USBPHY1_RCR_LOCK_MASK)
#define SRC_USBPHY1_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_USBPHY1_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_USBPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBPHY1_RCR_DOM_EN_MASK)
/*! @} */
/*! @name USBPHY2_RCR - USB PHY2 Reset Control Register */
/*! @{ */
#define SRC_USBPHY2_RCR_USB2_PHY_RESET_MASK (0x1U)
#define SRC_USBPHY2_RCR_USB2_PHY_RESET_SHIFT (0U)
/*! USB2_PHY_RESET
* 0b0..Don't reset USB 2 PHY
* 0b1..Reset USB 2 PHY
*/
#define SRC_USBPHY2_RCR_USB2_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_USB2_PHY_RESET_SHIFT)) & SRC_USBPHY2_RCR_USB2_PHY_RESET_MASK)
#define SRC_USBPHY2_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_USBPHY2_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_USBPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN0_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN0_MASK)
#define SRC_USBPHY2_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_USBPHY2_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_USBPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN1_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN1_MASK)
#define SRC_USBPHY2_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_USBPHY2_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_USBPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN2_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN2_MASK)
#define SRC_USBPHY2_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_USBPHY2_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_USBPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOMAIN3_SHIFT)) & SRC_USBPHY2_RCR_DOMAIN3_MASK)
#define SRC_USBPHY2_RCR_LOCK_MASK (0x40000000U)
#define SRC_USBPHY2_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_USBPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_LOCK_SHIFT)) & SRC_USBPHY2_RCR_LOCK_MASK)
#define SRC_USBPHY2_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_USBPHY2_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_USBPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_USBPHY2_RCR_DOM_EN_SHIFT)) & SRC_USBPHY2_RCR_DOM_EN_MASK)
/*! @} */
/*! @name MLMIX_RCR - MLMIX Reset Control Register */
/*! @{ */
#define SRC_MLMIX_RCR_MLMIX_RESET_MASK (0x1U)
#define SRC_MLMIX_RCR_MLMIX_RESET_SHIFT (0U)
/*! MLMIX_RESET
* 0b0..Do not assert MLMIX reset
* 0b1..Assert MLMIX reset
*/
#define SRC_MLMIX_RCR_MLMIX_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_MLMIX_RESET_SHIFT)) & SRC_MLMIX_RCR_MLMIX_RESET_MASK)
#define SRC_MLMIX_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_MLMIX_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_MLMIX_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN0_SHIFT)) & SRC_MLMIX_RCR_DOMAIN0_MASK)
#define SRC_MLMIX_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_MLMIX_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_MLMIX_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN1_SHIFT)) & SRC_MLMIX_RCR_DOMAIN1_MASK)
#define SRC_MLMIX_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_MLMIX_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_MLMIX_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN2_SHIFT)) & SRC_MLMIX_RCR_DOMAIN2_MASK)
#define SRC_MLMIX_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_MLMIX_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_MLMIX_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOMAIN3_SHIFT)) & SRC_MLMIX_RCR_DOMAIN3_MASK)
#define SRC_MLMIX_RCR_LOCK_MASK (0x40000000U)
#define SRC_MLMIX_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_MLMIX_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_LOCK_SHIFT)) & SRC_MLMIX_RCR_LOCK_MASK)
#define SRC_MLMIX_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_MLMIX_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_MLMIX_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MLMIX_RCR_DOM_EN_SHIFT)) & SRC_MLMIX_RCR_DOM_EN_MASK)
/*! @} */
/*! @name PCIEPHY_RCR - PCIE PHY Reset Control Register */
/*! @{ */
#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_MASK (0x1U)
#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_SHIFT (0U)
#define SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_PHY_POWER_ON_RESET_MASK)
#define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_MASK (0x4U)
#define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_SHIFT (2U)
#define SRC_PCIEPHY_RCR_PCIEPHY_BTNRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_BTNRST_MASK)
#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK (0x8U)
#define SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT (3U)
#define SRC_PCIEPHY_RCR_PCIEPHY_PERST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIEPHY_PERST_SHIFT)) & SRC_PCIEPHY_RCR_PCIEPHY_PERST_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK (0x10U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT (4U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_CLK_REQ_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK (0x20U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT (5U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_RST_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK (0x40U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT (6U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EN_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK (0x80U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT (7U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_READY_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK (0x100U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT (8U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_ENTER_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK (0x200U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT (9U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_EXIT_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK (0x400U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT (10U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_PME_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK (0x800U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT (11U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APPS_TURNOFF_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK (0x1000U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT (12U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_CFG_L1_AUX_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK (0x4000U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT (14U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_SYS_INT_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK (0x8000U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT (15U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_UNLOCK_MSG_MASK)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK (0x10000U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT (16U)
#define SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_SHIFT)) & SRC_PCIEPHY_RCR_PCIE_CTRL_APP_XFER_PENDING_MASK)
#define SRC_PCIEPHY_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_PCIEPHY_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_PCIEPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN0_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN0_MASK)
#define SRC_PCIEPHY_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_PCIEPHY_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_PCIEPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN1_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN1_MASK)
#define SRC_PCIEPHY_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_PCIEPHY_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_PCIEPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN2_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN2_MASK)
#define SRC_PCIEPHY_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_PCIEPHY_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_PCIEPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOMAIN3_SHIFT)) & SRC_PCIEPHY_RCR_DOMAIN3_MASK)
#define SRC_PCIEPHY_RCR_LOCK_MASK (0x40000000U)
#define SRC_PCIEPHY_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_PCIEPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_LOCK_SHIFT)) & SRC_PCIEPHY_RCR_LOCK_MASK)
#define SRC_PCIEPHY_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_PCIEPHY_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_PCIEPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_PCIEPHY_RCR_DOM_EN_SHIFT)) & SRC_PCIEPHY_RCR_DOM_EN_MASK)
/*! @} */
/*! @name HDMI_RCR - HDMI Reset Control Register */
/*! @{ */
#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK (0x1U)
#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT (0U)
#define SRC_HDMI_RCR_HDMI_PHY_APB_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_HDMI_PHY_APB_RESET_SHIFT)) & SRC_HDMI_RCR_HDMI_PHY_APB_RESET_MASK)
#define SRC_HDMI_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_HDMI_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_HDMI_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN0_SHIFT)) & SRC_HDMI_RCR_DOMAIN0_MASK)
#define SRC_HDMI_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_HDMI_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_HDMI_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN1_SHIFT)) & SRC_HDMI_RCR_DOMAIN1_MASK)
#define SRC_HDMI_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_HDMI_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_HDMI_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN2_SHIFT)) & SRC_HDMI_RCR_DOMAIN2_MASK)
#define SRC_HDMI_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_HDMI_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_HDMI_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOMAIN3_SHIFT)) & SRC_HDMI_RCR_DOMAIN3_MASK)
#define SRC_HDMI_RCR_LOCK_MASK (0x40000000U)
#define SRC_HDMI_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_HDMI_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_LOCK_SHIFT)) & SRC_HDMI_RCR_LOCK_MASK)
#define SRC_HDMI_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_HDMI_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_HDMI_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMI_RCR_DOM_EN_SHIFT)) & SRC_HDMI_RCR_DOM_EN_MASK)
/*! @} */
/*! @name MEDIA_RCR - MEDIAMIX Reset Control Register */
/*! @{ */
#define SRC_MEDIA_RCR_MEDIAMIX_RESET_MASK (0x1U)
#define SRC_MEDIA_RCR_MEDIAMIX_RESET_SHIFT (0U)
/*! MEDIAMIX_RESET
* 0b0..Don't reset MEDIAMIX
* 0b1..Reset MEDIAMIX
*/
#define SRC_MEDIA_RCR_MEDIAMIX_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_MEDIAMIX_RESET_SHIFT)) & SRC_MEDIA_RCR_MEDIAMIX_RESET_MASK)
#define SRC_MEDIA_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_MEDIA_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_MEDIA_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN0_SHIFT)) & SRC_MEDIA_RCR_DOMAIN0_MASK)
#define SRC_MEDIA_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_MEDIA_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_MEDIA_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN1_SHIFT)) & SRC_MEDIA_RCR_DOMAIN1_MASK)
#define SRC_MEDIA_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_MEDIA_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_MEDIA_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN2_SHIFT)) & SRC_MEDIA_RCR_DOMAIN2_MASK)
#define SRC_MEDIA_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_MEDIA_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_MEDIA_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOMAIN3_SHIFT)) & SRC_MEDIA_RCR_DOMAIN3_MASK)
#define SRC_MEDIA_RCR_LOCK_MASK (0x40000000U)
#define SRC_MEDIA_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_MEDIA_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_LOCK_SHIFT)) & SRC_MEDIA_RCR_LOCK_MASK)
#define SRC_MEDIA_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_MEDIA_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_MEDIA_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIA_RCR_DOM_EN_SHIFT)) & SRC_MEDIA_RCR_DOM_EN_MASK)
/*! @} */
/*! @name GPU2D_RCR - GPU2D Reset Control Register */
/*! @{ */
#define SRC_GPU2D_RCR_GPU2D_RESET_MASK (0x1U)
#define SRC_GPU2D_RCR_GPU2D_RESET_SHIFT (0U)
#define SRC_GPU2D_RCR_GPU2D_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_GPU2D_RESET_SHIFT)) & SRC_GPU2D_RCR_GPU2D_RESET_MASK)
#define SRC_GPU2D_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_GPU2D_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_GPU2D_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN0_SHIFT)) & SRC_GPU2D_RCR_DOMAIN0_MASK)
#define SRC_GPU2D_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_GPU2D_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_GPU2D_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN1_SHIFT)) & SRC_GPU2D_RCR_DOMAIN1_MASK)
#define SRC_GPU2D_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_GPU2D_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_GPU2D_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN2_SHIFT)) & SRC_GPU2D_RCR_DOMAIN2_MASK)
#define SRC_GPU2D_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_GPU2D_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_GPU2D_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOMAIN3_SHIFT)) & SRC_GPU2D_RCR_DOMAIN3_MASK)
#define SRC_GPU2D_RCR_LOCK_MASK (0x40000000U)
#define SRC_GPU2D_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_GPU2D_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_LOCK_SHIFT)) & SRC_GPU2D_RCR_LOCK_MASK)
#define SRC_GPU2D_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_GPU2D_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_GPU2D_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU2D_RCR_DOM_EN_SHIFT)) & SRC_GPU2D_RCR_DOM_EN_MASK)
/*! @} */
/*! @name GPU3D_RCR - GPU3D Reset Control Register */
/*! @{ */
#define SRC_GPU3D_RCR_GPU3D_RESET_MASK (0x1U)
#define SRC_GPU3D_RCR_GPU3D_RESET_SHIFT (0U)
#define SRC_GPU3D_RCR_GPU3D_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_GPU3D_RESET_SHIFT)) & SRC_GPU3D_RCR_GPU3D_RESET_MASK)
#define SRC_GPU3D_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_GPU3D_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_GPU3D_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN0_SHIFT)) & SRC_GPU3D_RCR_DOMAIN0_MASK)
#define SRC_GPU3D_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_GPU3D_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_GPU3D_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN1_SHIFT)) & SRC_GPU3D_RCR_DOMAIN1_MASK)
#define SRC_GPU3D_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_GPU3D_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_GPU3D_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN2_SHIFT)) & SRC_GPU3D_RCR_DOMAIN2_MASK)
#define SRC_GPU3D_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_GPU3D_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_GPU3D_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOMAIN3_SHIFT)) & SRC_GPU3D_RCR_DOMAIN3_MASK)
#define SRC_GPU3D_RCR_LOCK_MASK (0x40000000U)
#define SRC_GPU3D_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_GPU3D_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_LOCK_SHIFT)) & SRC_GPU3D_RCR_LOCK_MASK)
#define SRC_GPU3D_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_GPU3D_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_GPU3D_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU3D_RCR_DOM_EN_SHIFT)) & SRC_GPU3D_RCR_DOM_EN_MASK)
/*! @} */
/*! @name GPU_RCR - GPU Reset Control Register */
/*! @{ */
#define SRC_GPU_RCR_GPU_RESET_MASK (0x1U)
#define SRC_GPU_RCR_GPU_RESET_SHIFT (0U)
#define SRC_GPU_RCR_GPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK)
#define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_GPU_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK)
#define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_GPU_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK)
#define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_GPU_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK)
#define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_GPU_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK)
#define SRC_GPU_RCR_LOCK_MASK (0x40000000U)
#define SRC_GPU_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK)
#define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_GPU_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK)
/*! @} */
/*! @name VPU_RCR - VPU Reset Control Register */
/*! @{ */
#define SRC_VPU_RCR_VPU_RESET_MASK (0x1U)
#define SRC_VPU_RCR_VPU_RESET_SHIFT (0U)
#define SRC_VPU_RCR_VPU_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_VPU_RESET_SHIFT)) & SRC_VPU_RCR_VPU_RESET_MASK)
#define SRC_VPU_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_VPU_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_VPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN0_SHIFT)) & SRC_VPU_RCR_DOMAIN0_MASK)
#define SRC_VPU_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_VPU_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_VPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN1_SHIFT)) & SRC_VPU_RCR_DOMAIN1_MASK)
#define SRC_VPU_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_VPU_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_VPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN2_SHIFT)) & SRC_VPU_RCR_DOMAIN2_MASK)
#define SRC_VPU_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_VPU_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_VPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOMAIN3_SHIFT)) & SRC_VPU_RCR_DOMAIN3_MASK)
#define SRC_VPU_RCR_LOCK_MASK (0x40000000U)
#define SRC_VPU_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_VPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_LOCK_SHIFT)) & SRC_VPU_RCR_LOCK_MASK)
#define SRC_VPU_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_VPU_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_VPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_RCR_DOM_EN_SHIFT)) & SRC_VPU_RCR_DOM_EN_MASK)
/*! @} */
/*! @name VPU_G1_RCR - VPU G1 Reset Control Register */
/*! @{ */
#define SRC_VPU_G1_RCR_VPU_G1_RESET_MASK (0x1U)
#define SRC_VPU_G1_RCR_VPU_G1_RESET_SHIFT (0U)
#define SRC_VPU_G1_RCR_VPU_G1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_VPU_G1_RESET_SHIFT)) & SRC_VPU_G1_RCR_VPU_G1_RESET_MASK)
#define SRC_VPU_G1_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_VPU_G1_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_VPU_G1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN0_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN0_MASK)
#define SRC_VPU_G1_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_VPU_G1_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_VPU_G1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN1_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN1_MASK)
#define SRC_VPU_G1_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_VPU_G1_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_VPU_G1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN2_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN2_MASK)
#define SRC_VPU_G1_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_VPU_G1_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_VPU_G1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOMAIN3_SHIFT)) & SRC_VPU_G1_RCR_DOMAIN3_MASK)
#define SRC_VPU_G1_RCR_LOCK_MASK (0x40000000U)
#define SRC_VPU_G1_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_VPU_G1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_LOCK_SHIFT)) & SRC_VPU_G1_RCR_LOCK_MASK)
#define SRC_VPU_G1_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_VPU_G1_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_VPU_G1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G1_RCR_DOM_EN_SHIFT)) & SRC_VPU_G1_RCR_DOM_EN_MASK)
/*! @} */
/*! @name VPU_G2_RCR - VPU G2 Reset Control Register */
/*! @{ */
#define SRC_VPU_G2_RCR_VPU_G2_RESET_MASK (0x1U)
#define SRC_VPU_G2_RCR_VPU_G2_RESET_SHIFT (0U)
#define SRC_VPU_G2_RCR_VPU_G2_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_VPU_G2_RESET_SHIFT)) & SRC_VPU_G2_RCR_VPU_G2_RESET_MASK)
#define SRC_VPU_G2_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_VPU_G2_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_VPU_G2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN0_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN0_MASK)
#define SRC_VPU_G2_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_VPU_G2_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_VPU_G2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN1_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN1_MASK)
#define SRC_VPU_G2_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_VPU_G2_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_VPU_G2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN2_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN2_MASK)
#define SRC_VPU_G2_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_VPU_G2_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_VPU_G2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOMAIN3_SHIFT)) & SRC_VPU_G2_RCR_DOMAIN3_MASK)
#define SRC_VPU_G2_RCR_LOCK_MASK (0x40000000U)
#define SRC_VPU_G2_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_VPU_G2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_LOCK_SHIFT)) & SRC_VPU_G2_RCR_LOCK_MASK)
#define SRC_VPU_G2_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_VPU_G2_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_VPU_G2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPU_G2_RCR_DOM_EN_SHIFT)) & SRC_VPU_G2_RCR_DOM_EN_MASK)
/*! @} */
/*! @name VPUVC8KE_RCR - VPU VC8000E Reset Control Register */
/*! @{ */
#define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_MASK (0x1U)
#define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_SHIFT (0U)
#define SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_SHIFT)) & SRC_VPUVC8KE_RCR_VPU_VPUVC8KE_RESET_MASK)
#define SRC_VPUVC8KE_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_VPUVC8KE_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_VPUVC8KE_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN0_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN0_MASK)
#define SRC_VPUVC8KE_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_VPUVC8KE_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_VPUVC8KE_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN1_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN1_MASK)
#define SRC_VPUVC8KE_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_VPUVC8KE_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_VPUVC8KE_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN2_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN2_MASK)
#define SRC_VPUVC8KE_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_VPUVC8KE_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_VPUVC8KE_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOMAIN3_SHIFT)) & SRC_VPUVC8KE_RCR_DOMAIN3_MASK)
#define SRC_VPUVC8KE_RCR_LOCK_MASK (0x40000000U)
#define SRC_VPUVC8KE_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_VPUVC8KE_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_LOCK_SHIFT)) & SRC_VPUVC8KE_RCR_LOCK_MASK)
#define SRC_VPUVC8KE_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_VPUVC8KE_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_VPUVC8KE_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_VPUVC8KE_RCR_DOM_EN_SHIFT)) & SRC_VPUVC8KE_RCR_DOM_EN_MASK)
/*! @} */
/*! @name NOC_RCR - NOC Wrapper Reset Control Register */
/*! @{ */
#define SRC_NOC_RCR_NOC_RESET_MASK (0x1U)
#define SRC_NOC_RCR_NOC_RESET_SHIFT (0U)
#define SRC_NOC_RCR_NOC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_NOC_RESET_SHIFT)) & SRC_NOC_RCR_NOC_RESET_MASK)
#define SRC_NOC_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_NOC_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_NOC_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN0_SHIFT)) & SRC_NOC_RCR_DOMAIN0_MASK)
#define SRC_NOC_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_NOC_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_NOC_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN1_SHIFT)) & SRC_NOC_RCR_DOMAIN1_MASK)
#define SRC_NOC_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_NOC_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_NOC_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN2_SHIFT)) & SRC_NOC_RCR_DOMAIN2_MASK)
#define SRC_NOC_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_NOC_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_NOC_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOMAIN3_SHIFT)) & SRC_NOC_RCR_DOMAIN3_MASK)
#define SRC_NOC_RCR_LOCK_MASK (0x40000000U)
#define SRC_NOC_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_NOC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_LOCK_SHIFT)) & SRC_NOC_RCR_LOCK_MASK)
#define SRC_NOC_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_NOC_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_NOC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_NOC_RCR_DOM_EN_SHIFT)) & SRC_NOC_RCR_DOM_EN_MASK)
/*! @} */
/*! @name SBMR1 - SRC Boot Mode Register 1 */
/*! @{ */
#define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFU)
#define SRC_SBMR1_BOOT_CFG_SHIFT (0U)
#define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK)
/*! @} */
/*! @name SRSR - SRC Reset Status Register */
/*! @{ */
#define SRC_SRSR_ipp_reset_b_MASK (0x1U)
#define SRC_SRSR_ipp_reset_b_SHIFT (0U)
/*! ipp_reset_b
* 0b0..Reset is not a result of ipp_reset_b pin.
* 0b1..Reset is a result of ipp_reset_b pin.
*/
#define SRC_SRSR_ipp_reset_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_reset_b_SHIFT)) & SRC_SRSR_ipp_reset_b_MASK)
#define SRC_SRSR_csu_reset_b_MASK (0x4U)
#define SRC_SRSR_csu_reset_b_SHIFT (2U)
/*! csu_reset_b
* 0b0..Reset is not a result of the csu_reset_b event.
* 0b1..Reset is a result of the csu_reset_b event.
*/
#define SRC_SRSR_csu_reset_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_csu_reset_b_SHIFT)) & SRC_SRSR_csu_reset_b_MASK)
#define SRC_SRSR_ipp_user_reset_b_MASK (0x8U)
#define SRC_SRSR_ipp_user_reset_b_SHIFT (3U)
/*! ipp_user_reset_b
* 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
* 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
*/
#define SRC_SRSR_ipp_user_reset_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_user_reset_b_SHIFT)) & SRC_SRSR_ipp_user_reset_b_MASK)
#define SRC_SRSR_wdog1_rst_b_MASK (0x10U)
#define SRC_SRSR_wdog1_rst_b_SHIFT (4U)
/*! wdog1_rst_b
* 0b0..Reset is not a result of the watchdog1 time-out event.
* 0b1..Reset is a result of the watchdog1 time-out event.
*/
#define SRC_SRSR_wdog1_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog1_rst_b_SHIFT)) & SRC_SRSR_wdog1_rst_b_MASK)
#define SRC_SRSR_jtag_rst_b_MASK (0x20U)
#define SRC_SRSR_jtag_rst_b_SHIFT (5U)
/*! jtag_rst_b
* 0b0..Reset is not a result of HIGH-Z reset from JTAG.
* 0b1..Reset is a result of HIGH-Z reset from JTAG.
*/
#define SRC_SRSR_jtag_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_rst_b_SHIFT)) & SRC_SRSR_jtag_rst_b_MASK)
#define SRC_SRSR_jtag_sw_rst_MASK (0x40U)
#define SRC_SRSR_jtag_sw_rst_SHIFT (6U)
/*! jtag_sw_rst
* 0b0..Reset is not a result of software reset from JTAG.
* 0b1..Reset is a result of software reset from JTAG.
*/
#define SRC_SRSR_jtag_sw_rst(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_sw_rst_SHIFT)) & SRC_SRSR_jtag_sw_rst_MASK)
#define SRC_SRSR_wdog3_rst_b_MASK (0x80U)
#define SRC_SRSR_wdog3_rst_b_SHIFT (7U)
/*! wdog3_rst_b
* 0b0..Reset is not a result of the watchdog3 time-out event.
* 0b1..Reset is a result of the watchdog3 time-out event.
*/
#define SRC_SRSR_wdog3_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog3_rst_b_SHIFT)) & SRC_SRSR_wdog3_rst_b_MASK)
#define SRC_SRSR_wdog2_rst_b_MASK (0x100U)
#define SRC_SRSR_wdog2_rst_b_SHIFT (8U)
/*! wdog2_rst_b
* 0b0..Reset is not a result of the watchdog4 time-out event.
* 0b1..Reset is a result of the watchdog4 time-out event.
*/
#define SRC_SRSR_wdog2_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog2_rst_b_SHIFT)) & SRC_SRSR_wdog2_rst_b_MASK)
#define SRC_SRSR_tempsense_rst_b_MASK (0x200U)
#define SRC_SRSR_tempsense_rst_b_SHIFT (9U)
/*! tempsense_rst_b
* 0b0..Reset is not a result of software reset from Temperature Sensor.
* 0b1..Reset is a result of software reset from Temperature Sensor.
*/
#define SRC_SRSR_tempsense_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_tempsense_rst_b_SHIFT)) & SRC_SRSR_tempsense_rst_b_MASK)
/*! @} */
/*! @name SISR - SRC Interrupt Status Register */
/*! @{ */
#define SRC_SISR_USBPHY1_PASSED_RESET_MASK (0x4U)
#define SRC_SISR_USBPHY1_PASSED_RESET_SHIFT (2U)
/*! USBPHY1_PASSED_RESET
* 0b0..Interrupt generated not due to USB PHY1 passed reset
* 0b1..Interrupt generated due to USB PHY1 passed reset
*/
#define SRC_SISR_USBPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_USBPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_USBPHY1_PASSED_RESET_MASK)
#define SRC_SISR_USBPHY2_PASSED_RESET_MASK (0x8U)
#define SRC_SISR_USBPHY2_PASSED_RESET_SHIFT (3U)
/*! USBPHY2_PASSED_RESET
* 0b0..Interrupt generated not due to USB PHY2 passed reset
* 0b1..Interrupt generated due to USB PHY2 passed reset
*/
#define SRC_SISR_USBPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_USBPHY2_PASSED_RESET_SHIFT)) & SRC_SISR_USBPHY2_PASSED_RESET_MASK)
#define SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK (0x20U)
#define SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT (5U)
/*! PCIE1_PHY_PASSED_RESET
* 0b0..Interrupt generated not due to PCIE1 PHY passed reset
* 0b1..Interrupt generated due to PCIE1 PHY passed reset
*/
#define SRC_SISR_PCIE1_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_PCIE1_PHY_PASSED_RESET_SHIFT)) & SRC_SISR_PCIE1_PHY_PASSED_RESET_MASK)
#define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U)
#define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U)
/*! DISPLAY_PASSED_RESET
* 0b0..Interrupt generated not due to DISPLAY passed reset
* 0b1..Interrupt generated due to DISPLAY passed reset
*/
#define SRC_SISR_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK)
#define SRC_SISR_M7C_PASSED_RESET_MASK (0x100U)
#define SRC_SISR_M7C_PASSED_RESET_SHIFT (8U)
/*! M7C_PASSED_RESET
* 0b0..interrupt generated not due to m7core reset
* 0b1..interrupt generated due to m7core reset
*/
#define SRC_SISR_M7C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7C_PASSED_RESET_SHIFT)) & SRC_SISR_M7C_PASSED_RESET_MASK)
#define SRC_SISR_M7P_PASSED_RESET_MASK (0x200U)
#define SRC_SISR_M7P_PASSED_RESET_SHIFT (9U)
/*! M7P_PASSED_RESET
* 0b0..interrupt generated not due to m7 platform reset
* 0b1..interrupt generated due to m7 platform reset
*/
#define SRC_SISR_M7P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7P_PASSED_RESET_SHIFT)) & SRC_SISR_M7P_PASSED_RESET_MASK)
#define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U)
#define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U)
/*! GPU_PASSED_RESET
* 0b0..interrupt generated not due to GPU reset
* 0b1..interrupt generated due to GPU reset
*/
#define SRC_SISR_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK)
#define SRC_SISR_VPU_PASSED_RESET_MASK (0x800U)
#define SRC_SISR_VPU_PASSED_RESET_SHIFT (11U)
/*! VPU_PASSED_RESET
* 0b0..interrupt generated not due to VPU reset
* 0b1..interrupt generated due to VPU reset
*/
#define SRC_SISR_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_VPU_PASSED_RESET_SHIFT)) & SRC_SISR_VPU_PASSED_RESET_MASK)
/*! @} */
/*! @name SIMR - SRC Interrupt Mask Register */
/*! @{ */
#define SRC_SIMR_MASK_USBPHY1_PASSED_RESET_MASK (0x4U)
#define SRC_SIMR_MASK_USBPHY1_PASSED_RESET_SHIFT (2U)
/*! MASK_USBPHY1_PASSED_RESET
* 0b0..do not mask interrupt due to USB PHY1 passed reset - interrupt will be created
* 0b1..mask interrupt due to USB PHY1 passed reset
*/
#define SRC_SIMR_MASK_USBPHY1_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_USBPHY1_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_USBPHY1_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_USBPHY2_PASSED_RESET_MASK (0x8U)
#define SRC_SIMR_MASK_USBPHY2_PASSED_RESET_SHIFT (3U)
/*! MASK_USBPHY2_PASSED_RESET
* 0b0..do not mask interrupt due to USB PHY2 passed reset - interrupt will be created
* 0b1..mask interrupt due to USB PHY2 passed reset
*/
#define SRC_SIMR_MASK_USBPHY2_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_USBPHY2_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_USBPHY2_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_MASK (0x20U)
#define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_SHIFT (5U)
/*! MASK_PCIE_PHY_PASSED_RESET
* 0b0..do not mask interrupt due to PCIE PHY passed reset - interrupt will be created
* 0b1..mask interrupt due to PCIE PHY passed reset
*/
#define SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_PCIE_PHY_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U)
#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U)
/*! MASK_DISPLAY_PASSED_RESET
* 0b0..do not mask interrupt due to display passed reset - interrupt will be created
* 0b1..mask interrupt due to display passed reset
*/
#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_M7C_PASSED_RESET_MASK (0x100U)
#define SRC_SIMR_MASK_M7C_PASSED_RESET_SHIFT (8U)
/*! MASK_M7C_PASSED_RESET
* 0b0..do not mask interrupt due to m7 core passed reset - interrupt will be created
* 0b1..mask interrupt due to m7 core passed reset
*/
#define SRC_SIMR_MASK_M7C_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7C_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7C_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_M7P_PASSED_RESET_MASK (0x200U)
#define SRC_SIMR_MASK_M7P_PASSED_RESET_SHIFT (9U)
/*! MASK_M7P_PASSED_RESET
* 0b0..do not mask interrupt due to m7 platform passed reset - interrupt will be created
* 0b1..mask interrupt due to m7 platform passed reset
*/
#define SRC_SIMR_MASK_M7P_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7P_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7P_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U)
#define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U)
/*! MASK_GPU_PASSED_RESET
* 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created
* 0b1..mask interrupt due to GPU passed reset
*/
#define SRC_SIMR_MASK_GPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK)
#define SRC_SIMR_MASK_VPU_PASSED_RESET_MASK (0x800U)
#define SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT (11U)
/*! MASK_VPU_PASSED_RESET
* 0b0..do not mask interrupt due to VPU passed reset - interrupt will be created
* 0b1..mask interrupt due to VPU passed reset
*/
#define SRC_SIMR_MASK_VPU_PASSED_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_VPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_VPU_PASSED_RESET_MASK)
/*! @} */
/*! @name SBMR2 - SRC Boot Mode Register 2 */
/*! @{ */
#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
#define SRC_SBMR2_FORCE_COLD_BOOT_MASK (0xE0U)
#define SRC_SBMR2_FORCE_COLD_BOOT_SHIFT (5U)
#define SRC_SBMR2_FORCE_COLD_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FORCE_COLD_BOOT_MASK)
#define SRC_SBMR2_IPP_BOOT_MODE_MASK (0xF000000U)
#define SRC_SBMR2_IPP_BOOT_MODE_SHIFT (24U)
#define SRC_SBMR2_IPP_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_SBMR2_IPP_BOOT_MODE_MASK)
/*! @} */
/*! @name GPR1 - SRC General Purpose Register 1 */
/*! @{ */
#define SRC_GPR1_C0_START_ADDRH_MASK (0xFFFFU)
#define SRC_GPR1_C0_START_ADDRH_SHIFT (0U)
#define SRC_GPR1_C0_START_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR1_C0_START_ADDRH_SHIFT)) & SRC_GPR1_C0_START_ADDRH_MASK)
/*! @} */
/*! @name GPR2 - SRC General Purpose Register 2 */
/*! @{ */
#define SRC_GPR2_C0_START_ADDRL_MASK (0x3FFFFFU)
#define SRC_GPR2_C0_START_ADDRL_SHIFT (0U)
#define SRC_GPR2_C0_START_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR2_C0_START_ADDRL_SHIFT)) & SRC_GPR2_C0_START_ADDRL_MASK)
/*! @} */
/*! @name GPR3 - SRC General Purpose Register 3 */
/*! @{ */
#define SRC_GPR3_C1_START_ADDRH_MASK (0xFFFFU)
#define SRC_GPR3_C1_START_ADDRH_SHIFT (0U)
#define SRC_GPR3_C1_START_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR3_C1_START_ADDRH_SHIFT)) & SRC_GPR3_C1_START_ADDRH_MASK)
/*! @} */
/*! @name GPR4 - SRC General Purpose Register 4 */
/*! @{ */
#define SRC_GPR4_C1_START_ADDRL_MASK (0x3FFFFFU)
#define SRC_GPR4_C1_START_ADDRL_SHIFT (0U)
#define SRC_GPR4_C1_START_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR4_C1_START_ADDRL_SHIFT)) & SRC_GPR4_C1_START_ADDRL_MASK)
/*! @} */
/*! @name GPR5 - SRC General Purpose Register 5 */
/*! @{ */
#define SRC_GPR5_C2_START_ADDRH_MASK (0xFFFFU)
#define SRC_GPR5_C2_START_ADDRH_SHIFT (0U)
#define SRC_GPR5_C2_START_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR5_C2_START_ADDRH_SHIFT)) & SRC_GPR5_C2_START_ADDRH_MASK)
/*! @} */
/*! @name GPR6 - SRC General Purpose Register 6 */
/*! @{ */
#define SRC_GPR6_C2_START_ADDRL_MASK (0x3FFFFFU)
#define SRC_GPR6_C2_START_ADDRL_SHIFT (0U)
#define SRC_GPR6_C2_START_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR6_C2_START_ADDRL_SHIFT)) & SRC_GPR6_C2_START_ADDRL_MASK)
/*! @} */
/*! @name GPR7 - SRC General Purpose Register 7 */
/*! @{ */
#define SRC_GPR7_C3_START_ADDRH_MASK (0xFFFFU)
#define SRC_GPR7_C3_START_ADDRH_SHIFT (0U)
#define SRC_GPR7_C3_START_ADDRH(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR7_C3_START_ADDRH_SHIFT)) & SRC_GPR7_C3_START_ADDRH_MASK)
/*! @} */
/*! @name GPR8 - SRC General Purpose Register 8 */
/*! @{ */
#define SRC_GPR8_C3_START_ADDRL_MASK (0x3FFFFFU)
#define SRC_GPR8_C3_START_ADDRL_SHIFT (0U)
#define SRC_GPR8_C3_START_ADDRL(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR8_C3_START_ADDRL_SHIFT)) & SRC_GPR8_C3_START_ADDRL_MASK)
/*! @} */
/*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */
/*! @{ */
#define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U)
#define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U)
/*! DDRC1_PRST
* 0b0..De-assert DDR Controller preset and DDR PHY reset reset
* 0b1..Assert DDR Controller preset and DDR PHY reset
*/
#define SRC_DDRC_RCR_DDRC1_PRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK)
#define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U)
#define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U)
/*! DDRC1_CORE_RST
* 0b0..De-assert DDR controller aresetn and core_ddrc_rstn
* 0b1..Assert DDR Controller preset and DDR PHY reset
*/
#define SRC_DDRC_RCR_DDRC1_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK)
#define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U)
#define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U)
/*! DDRC1_PHY_RESET
* 0b0..De-assert DDR controller
* 0b1..Assert DDR Controller
*/
#define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK)
#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U)
#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U)
/*! DDRC1_PHY_PWROKIN
* 0b0..De-assert DDR controller
* 0b1..Assert DDR Controller
*/
#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK)
#define SRC_DDRC_RCR_DDRC1_SYS_RST_MASK (0x10U)
#define SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT (4U)
#define SRC_DDRC_RCR_DDRC1_SYS_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_SYS_RST_MASK)
#define SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK (0x20U)
#define SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT (5U)
#define SRC_DDRC_RCR_DDRC1_PHY_WRST(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK)
#define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain0 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain0 can write to this register
*/
#define SRC_DDRC_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK)
#define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_DDRC_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK)
#define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_DDRC_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK)
#define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_DDRC_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK)
#define SRC_DDRC_RCR_LOCK_MASK (0x40000000U)
#define SRC_DDRC_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK)
#define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_DDRC_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK)
/*! @} */
/*! @name HDMIPHY_RCR - HDMIPHY Reset Control Register */
/*! @{ */
#define SRC_HDMIPHY_RCR_HDMIPHY_RESET_MASK (0x1U)
#define SRC_HDMIPHY_RCR_HDMIPHY_RESET_SHIFT (0U)
/*! HDMIPHY_RESET
* 0b0..Do not assert HDMI PHY reset
* 0b1..Assert HDMI PHY reset
*/
#define SRC_HDMIPHY_RCR_HDMIPHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_HDMIPHY_RESET_SHIFT)) & SRC_HDMIPHY_RCR_HDMIPHY_RESET_MASK)
#define SRC_HDMIPHY_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_HDMIPHY_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_HDMIPHY_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN0_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN0_MASK)
#define SRC_HDMIPHY_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_HDMIPHY_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_HDMIPHY_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN1_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN1_MASK)
#define SRC_HDMIPHY_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_HDMIPHY_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_HDMIPHY_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN2_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN2_MASK)
#define SRC_HDMIPHY_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_HDMIPHY_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_HDMIPHY_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOMAIN3_SHIFT)) & SRC_HDMIPHY_RCR_DOMAIN3_MASK)
#define SRC_HDMIPHY_RCR_LOCK_MASK (0x40000000U)
#define SRC_HDMIPHY_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_HDMIPHY_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_LOCK_SHIFT)) & SRC_HDMIPHY_RCR_LOCK_MASK)
#define SRC_HDMIPHY_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_HDMIPHY_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_HDMIPHY_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HDMIPHY_RCR_DOM_EN_SHIFT)) & SRC_HDMIPHY_RCR_DOM_EN_MASK)
/*! @} */
/*! @name MIPIPHY1_RCR - MIPI PHY1 Reset Control Register */
/*! @{ */
#define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_MASK (0x1U)
#define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_SHIFT (0U)
/*! MIPIPHY1_RESET
* 0b0..Do not assert MIPI PHY1 reset
* 0b1..Assert MIPI PHY1 reset
*/
#define SRC_MIPIPHY1_RCR_MIPIPHY1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_SHIFT)) & SRC_MIPIPHY1_RCR_MIPIPHY1_RESET_MASK)
#define SRC_MIPIPHY1_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_MIPIPHY1_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN0_MASK)
#define SRC_MIPIPHY1_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_MIPIPHY1_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN1_MASK)
#define SRC_MIPIPHY1_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_MIPIPHY1_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN2_MASK)
#define SRC_MIPIPHY1_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_MIPIPHY1_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY1_RCR_DOMAIN3_MASK)
#define SRC_MIPIPHY1_RCR_LOCK_MASK (0x40000000U)
#define SRC_MIPIPHY1_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_MIPIPHY1_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_LOCK_SHIFT)) & SRC_MIPIPHY1_RCR_LOCK_MASK)
#define SRC_MIPIPHY1_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_MIPIPHY1_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_MIPIPHY1_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY1_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY1_RCR_DOM_EN_MASK)
/*! @} */
/*! @name MIPIPHY2_RCR - MIPI PHY2 Reset Control Register */
/*! @{ */
#define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_MASK (0x1U)
#define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_SHIFT (0U)
/*! MIPIPHY2_RESET
* 0b0..Do not assert MIPI PHY2 reset
* 0b1..Assert MIPI PHY2 reset
*/
#define SRC_MIPIPHY2_RCR_MIPIPHY2_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_SHIFT)) & SRC_MIPIPHY2_RCR_MIPIPHY2_RESET_MASK)
#define SRC_MIPIPHY2_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_MIPIPHY2_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN0_MASK)
#define SRC_MIPIPHY2_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_MIPIPHY2_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN1_MASK)
#define SRC_MIPIPHY2_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_MIPIPHY2_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN2_MASK)
#define SRC_MIPIPHY2_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_MIPIPHY2_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY2_RCR_DOMAIN3_MASK)
#define SRC_MIPIPHY2_RCR_LOCK_MASK (0x40000000U)
#define SRC_MIPIPHY2_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_MIPIPHY2_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_LOCK_SHIFT)) & SRC_MIPIPHY2_RCR_LOCK_MASK)
#define SRC_MIPIPHY2_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_MIPIPHY2_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_MIPIPHY2_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY2_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY2_RCR_DOM_EN_MASK)
/*! @} */
/*! @name HSIO_RCR - HSIO Reset Control Register */
/*! @{ */
#define SRC_HSIO_RCR_HSIO_RESET_MASK (0x1U)
#define SRC_HSIO_RCR_HSIO_RESET_SHIFT (0U)
/*! HSIO_RESET
* 0b0..Do not assert HSIOMIX reset
* 0b1..Assert HSIOMIX reset
*/
#define SRC_HSIO_RCR_HSIO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_HSIO_RESET_SHIFT)) & SRC_HSIO_RCR_HSIO_RESET_MASK)
#define SRC_HSIO_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_HSIO_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_HSIO_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN0_SHIFT)) & SRC_HSIO_RCR_DOMAIN0_MASK)
#define SRC_HSIO_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_HSIO_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_HSIO_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN1_SHIFT)) & SRC_HSIO_RCR_DOMAIN1_MASK)
#define SRC_HSIO_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_HSIO_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_HSIO_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN2_SHIFT)) & SRC_HSIO_RCR_DOMAIN2_MASK)
#define SRC_HSIO_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_HSIO_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_HSIO_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOMAIN3_SHIFT)) & SRC_HSIO_RCR_DOMAIN3_MASK)
#define SRC_HSIO_RCR_LOCK_MASK (0x40000000U)
#define SRC_HSIO_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_HSIO_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_LOCK_SHIFT)) & SRC_HSIO_RCR_LOCK_MASK)
#define SRC_HSIO_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_HSIO_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_HSIO_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_HSIO_RCR_DOM_EN_SHIFT)) & SRC_HSIO_RCR_DOM_EN_MASK)
/*! @} */
/*! @name MEDIAISPDWP_RCR - MEDIAMIX ISP and Dewarp Reset Control Register */
/*! @{ */
#define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_MASK (0x1U)
#define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_SHIFT (0U)
/*! MEDIAISPDWP_RESET
* 0b0..Do not assert MEDIAMIX ISP and Dewarp reset
* 0b1..Assert MEDIAMIX ISP and Dewarp reset
*/
#define SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_SHIFT)) & SRC_MEDIAISPDWP_RCR_MEDIAISPDWP_RESET_MASK)
#define SRC_MEDIAISPDWP_RCR_DOMAIN0_MASK (0x1000000U)
#define SRC_MEDIAISPDWP_RCR_DOMAIN0_SHIFT (24U)
/*! DOMAIN0
* 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain0. The master from domain3 can write to this register
*/
#define SRC_MEDIAISPDWP_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN0_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN0_MASK)
#define SRC_MEDIAISPDWP_RCR_DOMAIN1_MASK (0x2000000U)
#define SRC_MEDIAISPDWP_RCR_DOMAIN1_SHIFT (25U)
/*! DOMAIN1
* 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
* 0b1..This register is assigned to domain1. The master from domain1 can write to this register
*/
#define SRC_MEDIAISPDWP_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN1_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN1_MASK)
#define SRC_MEDIAISPDWP_RCR_DOMAIN2_MASK (0x4000000U)
#define SRC_MEDIAISPDWP_RCR_DOMAIN2_SHIFT (26U)
/*! DOMAIN2
* 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
* 0b1..This register is assigned to domain2. The master from domain2 can write to this register
*/
#define SRC_MEDIAISPDWP_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN2_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN2_MASK)
#define SRC_MEDIAISPDWP_RCR_DOMAIN3_MASK (0x8000000U)
#define SRC_MEDIAISPDWP_RCR_DOMAIN3_SHIFT (27U)
/*! DOMAIN3
* 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
* 0b1..This register is assigned to domain3. The master from domain3 can write to this register
*/
#define SRC_MEDIAISPDWP_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOMAIN3_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOMAIN3_MASK)
#define SRC_MEDIAISPDWP_RCR_LOCK_MASK (0x40000000U)
#define SRC_MEDIAISPDWP_RCR_LOCK_SHIFT (30U)
/*! LOCK
* 0b0..[31] and [27:24] bits can be modified
* 0b1..[31] and [27:24] bits cannot be modified
*/
#define SRC_MEDIAISPDWP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_LOCK_SHIFT)) & SRC_MEDIAISPDWP_RCR_LOCK_MASK)
#define SRC_MEDIAISPDWP_RCR_DOM_EN_MASK (0x80000000U)
#define SRC_MEDIAISPDWP_RCR_DOM_EN_SHIFT (31U)
/*! DOM_EN
* 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
* 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
* the masters from the domains specified in [27:24] area.
*/
#define SRC_MEDIAISPDWP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_MEDIAISPDWP_RCR_DOM_EN_SHIFT)) & SRC_MEDIAISPDWP_RCR_DOM_EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SRC_Register_Masks */
/* SRC - Peripheral instance base addresses */
/** Peripheral SRC base address */
#define SRC_BASE (0x30390000u)
/** Peripheral SRC base pointer */
#define SRC ((SRC_Type *)SRC_BASE)
/** Array initializer of SRC peripheral base addresses */
#define SRC_BASE_ADDRS { SRC_BASE }
/** Array initializer of SRC peripheral base pointers */
#define SRC_BASE_PTRS { SRC }
/*!
* @}
*/ /* end of group SRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SYS_CTR_COMPARE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_COMPARE_Peripheral_Access_Layer SYS_CTR_COMPARE Peripheral Access Layer
* @{
*/
/** SYS_CTR_COMPARE - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[32];
__I uint32_t CMPCVL0; /**< Compare Count Value Low Register, offset: 0x20 */
__I uint32_t CMPCVH0; /**< Compare Count Value High Register, offset: 0x24 */
uint8_t RESERVED_1[4];
__IO uint32_t CMPCR0; /**< Compare Control Register, offset: 0x2C */
uint8_t RESERVED_2[240];
__I uint32_t CMPCVL1; /**< Compare Count Value Low Register, offset: 0x120 */
__I uint32_t CMPCVH1; /**< Compare Count Value High Register, offset: 0x124 */
uint8_t RESERVED_3[4];
__IO uint32_t CMPCR; /**< Compare Control Register, offset: 0x12C */
uint8_t RESERVED_4[3744];
__I uint32_t CNTID0; /**< Counter ID Register, offset: 0xFD0 */
} SYS_CTR_COMPARE_Type;
/* ----------------------------------------------------------------------------
-- SYS_CTR_COMPARE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_COMPARE_Register_Masks SYS_CTR_COMPARE Register Masks
* @{
*/
/*! @name CMPCVL0 - Compare Count Value Low Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK (0xFFFFFFFFU)
#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT (0U)
#define SYS_CTR_COMPARE_CMPCVL0_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL0_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL0_CMPCV0_MASK)
/*! @} */
/*! @name CMPCVH0 - Compare Count Value High Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK (0x1FFFFFFU)
#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT (0U)
#define SYS_CTR_COMPARE_CMPCVH0_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH0_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH0_CMPCV1_MASK)
/*! @} */
/*! @name CMPCR0 - Compare Control Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCR0_EN_MASK (0x1U)
#define SYS_CTR_COMPARE_CMPCR0_EN_SHIFT (0U)
/*! EN
* 0b0..Compare disabled
* 0b1..Compare enabled
*/
#define SYS_CTR_COMPARE_CMPCR0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_EN_MASK)
#define SYS_CTR_COMPARE_CMPCR0_IMASK_MASK (0x2U)
#define SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT (1U)
/*! IMASK
* 0b0..Interrupt output signal is not masked.
* 0b1..Interrupt output signal is masked.
*/
#define SYS_CTR_COMPARE_CMPCR0_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_IMASK_MASK)
#define SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK (0x4U)
#define SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT (2U)
/*! ISTAT
* 0b0..Counter value is less than the compare value or compare is disabled.
* 0b1..Counter value is greater than or equal to the compare value and compare is enabled.
*/
#define SYS_CTR_COMPARE_CMPCR0_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR0_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR0_ISTAT_MASK)
/*! @} */
/*! @name CMPCVL1 - Compare Count Value Low Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK (0xFFFFFFFFU)
#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT (0U)
#define SYS_CTR_COMPARE_CMPCVL1_CMPCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVL1_CMPCV0_SHIFT)) & SYS_CTR_COMPARE_CMPCVL1_CMPCV0_MASK)
/*! @} */
/*! @name CMPCVH1 - Compare Count Value High Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK (0x1FFFFFFU)
#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT (0U)
#define SYS_CTR_COMPARE_CMPCVH1_CMPCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCVH1_CMPCV1_SHIFT)) & SYS_CTR_COMPARE_CMPCVH1_CMPCV1_MASK)
/*! @} */
/*! @name CMPCR - Compare Control Register */
/*! @{ */
#define SYS_CTR_COMPARE_CMPCR_EN_MASK (0x1U)
#define SYS_CTR_COMPARE_CMPCR_EN_SHIFT (0U)
/*! EN
* 0b0..Compare disabled
* 0b1..Compare enabled
*/
#define SYS_CTR_COMPARE_CMPCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_EN_SHIFT)) & SYS_CTR_COMPARE_CMPCR_EN_MASK)
#define SYS_CTR_COMPARE_CMPCR_IMASK_MASK (0x2U)
#define SYS_CTR_COMPARE_CMPCR_IMASK_SHIFT (1U)
/*! IMASK
* 0b0..Interrupt output signal is not masked.
* 0b1..Interrupt output signal is masked.
*/
#define SYS_CTR_COMPARE_CMPCR_IMASK(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_IMASK_SHIFT)) & SYS_CTR_COMPARE_CMPCR_IMASK_MASK)
#define SYS_CTR_COMPARE_CMPCR_ISTAT_MASK (0x4U)
#define SYS_CTR_COMPARE_CMPCR_ISTAT_SHIFT (2U)
/*! ISTAT
* 0b0..Counter value is less than the compare value or compare is disabled.
* 0b1..Counter value is greater than or equal to the compare value and compare is enabled.
*/
#define SYS_CTR_COMPARE_CMPCR_ISTAT(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CMPCR_ISTAT_SHIFT)) & SYS_CTR_COMPARE_CMPCR_ISTAT_MASK)
/*! @} */
/*! @name CNTID0 - Counter ID Register */
/*! @{ */
#define SYS_CTR_COMPARE_CNTID0_CNTID_MASK (0xFFFFFFFFU)
#define SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT (0U)
#define SYS_CTR_COMPARE_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_COMPARE_CNTID0_CNTID_SHIFT)) & SYS_CTR_COMPARE_CNTID0_CNTID_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SYS_CTR_COMPARE_Register_Masks */
/* SYS_CTR_COMPARE - Peripheral instance base addresses */
/** Peripheral SYS_CTR_COMPARE base address */
#define SYS_CTR_COMPARE_BASE (0x306B0000u)
/** Peripheral SYS_CTR_COMPARE base pointer */
#define SYS_CTR_COMPARE ((SYS_CTR_COMPARE_Type *)SYS_CTR_COMPARE_BASE)
/** Array initializer of SYS_CTR_COMPARE peripheral base addresses */
#define SYS_CTR_COMPARE_BASE_ADDRS { SYS_CTR_COMPARE_BASE }
/** Array initializer of SYS_CTR_COMPARE peripheral base pointers */
#define SYS_CTR_COMPARE_BASE_PTRS { SYS_CTR_COMPARE }
/*!
* @}
*/ /* end of group SYS_CTR_COMPARE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SYS_CTR_CONTROL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_CONTROL_Peripheral_Access_Layer SYS_CTR_CONTROL Peripheral Access Layer
* @{
*/
/** SYS_CTR_CONTROL - Register Layout Typedef */
typedef struct {
__IO uint32_t CNTCR; /**< Counter Control Register, offset: 0x0 */
__I uint32_t CNTSR; /**< Counter Status Register, offset: 0x4 */
__IO uint32_t CNTCV0; /**< Counter Count Value Low Register, offset: 0x8 */
__IO uint32_t CNTCV1; /**< Counter Count Value High Register, offset: 0xC */
uint8_t RESERVED_0[16];
__I uint32_t CNTFID0; /**< Frequency Modes Table 0 Register, offset: 0x20 */
__I uint32_t CNTFID1; /**< Frequency Modes Table 1 Register, offset: 0x24 */
__I uint32_t CNTFID2; /**< Frequency Modes Table 2 Register, offset: 0x28 */
uint8_t RESERVED_1[4004];
__I uint32_t CNTID0; /**< Counter ID Register, offset: 0xFD0 */
} SYS_CTR_CONTROL_Type;
/* ----------------------------------------------------------------------------
-- SYS_CTR_CONTROL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_CONTROL_Register_Masks SYS_CTR_CONTROL Register Masks
* @{
*/
/*! @name CNTCR - Counter Control Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTCR_EN_MASK (0x1U)
#define SYS_CTR_CONTROL_CNTCR_EN_SHIFT (0U)
/*! EN
* 0b0..Counter disabled
* 0b1..Counter enabled
*/
#define SYS_CTR_CONTROL_CNTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_EN_SHIFT)) & SYS_CTR_CONTROL_CNTCR_EN_MASK)
#define SYS_CTR_CONTROL_CNTCR_HDBG_MASK (0x2U)
#define SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT (1U)
/*! HDBG
* 0b0..The assertion of the debug input is ignored.
* 0b1..The assertion of the debug input causes the System Counter to halt.
*/
#define SYS_CTR_CONTROL_CNTCR_HDBG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_HDBG_SHIFT)) & SYS_CTR_CONTROL_CNTCR_HDBG_MASK)
#define SYS_CTR_CONTROL_CNTCR_FCR0_MASK (0x100U)
#define SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT (8U)
/*! FCR0
* 0b0..No change.
* 0b1..Select frequency modes table entry 0, the base frequency.
*/
#define SYS_CTR_CONTROL_CNTCR_FCR0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR0_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR0_MASK)
#define SYS_CTR_CONTROL_CNTCR_FCR1_MASK (0x200U)
#define SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT (9U)
/*! FCR1
* 0b0..No change.
* 0b1..Select frequency modes table entry 1, the base frequency.
*/
#define SYS_CTR_CONTROL_CNTCR_FCR1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCR_FCR1_SHIFT)) & SYS_CTR_CONTROL_CNTCR_FCR1_MASK)
/*! @} */
/*! @name CNTSR - Counter Status Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTSR_DBGH_MASK (0x1U)
#define SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT (0U)
/*! DBGH
* 0b0..Counter is not halted by debug.
* 0b1..Counter is halted by debug.
*/
#define SYS_CTR_CONTROL_CNTSR_DBGH(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_DBGH_SHIFT)) & SYS_CTR_CONTROL_CNTSR_DBGH_MASK)
#define SYS_CTR_CONTROL_CNTSR_FCA0_MASK (0x100U)
#define SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT (8U)
/*! FCA0
* 0b0..Base frequency is not selected.
* 0b1..Base frequency is selected.
*/
#define SYS_CTR_CONTROL_CNTSR_FCA0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA0_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA0_MASK)
#define SYS_CTR_CONTROL_CNTSR_FCA1_MASK (0x200U)
#define SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT (9U)
/*! FCA1
* 0b0..Base frequency is not selected.
* 0b1..Base frequency is selected.
*/
#define SYS_CTR_CONTROL_CNTSR_FCA1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTSR_FCA1_SHIFT)) & SYS_CTR_CONTROL_CNTSR_FCA1_MASK)
/*! @} */
/*! @name CNTCV0 - Counter Count Value Low Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU)
#define SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_CONTROL_CNTCV0_CNTCV0_MASK)
/*! @} */
/*! @name CNTCV1 - Counter Count Value High Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK (0x1FFFFFFU)
#define SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_CONTROL_CNTCV1_CNTCV1_MASK)
/*! @} */
/*! @name CNTFID0 - Frequency Modes Table 0 Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK (0xFFFFFFFFU)
#define SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTFID0_CNTFID0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID0_CNTFID0_SHIFT)) & SYS_CTR_CONTROL_CNTFID0_CNTFID0_MASK)
/*! @} */
/*! @name CNTFID1 - Frequency Modes Table 1 Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK (0xFFFFFFFFU)
#define SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTFID1_CNTFID1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID1_CNTFID1_SHIFT)) & SYS_CTR_CONTROL_CNTFID1_CNTFID1_MASK)
/*! @} */
/*! @name CNTFID2 - Frequency Modes Table 2 Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK (0xFFFFFFFFU)
#define SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTFID2_CNTFID2(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTFID2_CNTFID2_SHIFT)) & SYS_CTR_CONTROL_CNTFID2_CNTFID2_MASK)
/*! @} */
/*! @name CNTID0 - Counter ID Register */
/*! @{ */
#define SYS_CTR_CONTROL_CNTID0_CNTID_MASK (0xFFFFFFFFU)
#define SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT (0U)
#define SYS_CTR_CONTROL_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_CONTROL_CNTID0_CNTID_SHIFT)) & SYS_CTR_CONTROL_CNTID0_CNTID_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SYS_CTR_CONTROL_Register_Masks */
/* SYS_CTR_CONTROL - Peripheral instance base addresses */
/** Peripheral SYS_CTR_CONTROL base address */
#define SYS_CTR_CONTROL_BASE (0x306C0000u)
/** Peripheral SYS_CTR_CONTROL base pointer */
#define SYS_CTR_CONTROL ((SYS_CTR_CONTROL_Type *)SYS_CTR_CONTROL_BASE)
/** Array initializer of SYS_CTR_CONTROL peripheral base addresses */
#define SYS_CTR_CONTROL_BASE_ADDRS { SYS_CTR_CONTROL_BASE }
/** Array initializer of SYS_CTR_CONTROL peripheral base pointers */
#define SYS_CTR_CONTROL_BASE_PTRS { SYS_CTR_CONTROL }
/*!
* @}
*/ /* end of group SYS_CTR_CONTROL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SYS_CTR_READ Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_READ_Peripheral_Access_Layer SYS_CTR_READ Peripheral Access Layer
* @{
*/
/** SYS_CTR_READ - Register Layout Typedef */
typedef struct {
__I uint32_t CNTCV0; /**< Counter Count Value Low Register, offset: 0x0 */
__I uint32_t CNTCV1; /**< Counter Count Value High Register, offset: 0x4 */
uint8_t RESERVED_0[4040];
__I uint32_t CNTID0; /**< Counter ID Register, offset: 0xFD0 */
} SYS_CTR_READ_Type;
/* ----------------------------------------------------------------------------
-- SYS_CTR_READ Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SYS_CTR_READ_Register_Masks SYS_CTR_READ Register Masks
* @{
*/
/*! @name CNTCV0 - Counter Count Value Low Register */
/*! @{ */
#define SYS_CTR_READ_CNTCV0_CNTCV0_MASK (0xFFFFFFFFU)
#define SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT (0U)
#define SYS_CTR_READ_CNTCV0_CNTCV0(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV0_CNTCV0_SHIFT)) & SYS_CTR_READ_CNTCV0_CNTCV0_MASK)
/*! @} */
/*! @name CNTCV1 - Counter Count Value High Register */
/*! @{ */
#define SYS_CTR_READ_CNTCV1_CNTCV1_MASK (0x1FFFFFFU)
#define SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT (0U)
#define SYS_CTR_READ_CNTCV1_CNTCV1(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTCV1_CNTCV1_SHIFT)) & SYS_CTR_READ_CNTCV1_CNTCV1_MASK)
/*! @} */
/*! @name CNTID0 - Counter ID Register */
/*! @{ */
#define SYS_CTR_READ_CNTID0_CNTID_MASK (0xFFFFFFFFU)
#define SYS_CTR_READ_CNTID0_CNTID_SHIFT (0U)
#define SYS_CTR_READ_CNTID0_CNTID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTR_READ_CNTID0_CNTID_SHIFT)) & SYS_CTR_READ_CNTID0_CNTID_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SYS_CTR_READ_Register_Masks */
/* SYS_CTR_READ - Peripheral instance base addresses */
/** Peripheral SYS_CTR_READ base address */
#define SYS_CTR_READ_BASE (0x306A0000u)
/** Peripheral SYS_CTR_READ base pointer */
#define SYS_CTR_READ ((SYS_CTR_READ_Type *)SYS_CTR_READ_BASE)
/** Array initializer of SYS_CTR_READ peripheral base addresses */
#define SYS_CTR_READ_BASE_ADDRS { SYS_CTR_READ_BASE }
/** Array initializer of SYS_CTR_READ peripheral base pointers */
#define SYS_CTR_READ_BASE_PTRS { SYS_CTR_READ }
/*!
* @}
*/ /* end of group SYS_CTR_READ_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer
* @{
*/
/** TMU - Register Layout Typedef */
typedef struct {
__IO uint32_t TER; /**< TMU Enable register, offset: 0x0 */
__IO uint32_t TPS; /**< TMU Probe Select register, offset: 0x4 */
__IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */
__IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0xC */
__IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x10 */
__IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x14 */
__IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x18 */
__I uint32_t TSCR; /**< TMU Sensor Calibration register, offset: 0x1C */
__I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, offset: 0x20 */
__I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, offset: 0x24 */
} TMU_Type;
/* ----------------------------------------------------------------------------
-- TMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMU_Register_Masks TMU Register Masks
* @{
*/
/*! @name TER - TMU Enable register */
/*! @{ */
#define TMU_TER_ALPF_MASK (0x3U)
#define TMU_TER_ALPF_SHIFT (0U)
/*! ALPF
* 0b00..1.0
* 0b01..0.5
* 0b10..0.25
* 0b11..0.125
*/
#define TMU_TER_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_ALPF_SHIFT)) & TMU_TER_ALPF_MASK)
#define TMU_TER_ADC_PD_MASK (0x40000000U)
#define TMU_TER_ADC_PD_SHIFT (30U)
/*! ADC_PD
* 0b0..normal operating mode
* 0b1..power down mode
*/
#define TMU_TER_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_ADC_PD_SHIFT)) & TMU_TER_ADC_PD_MASK)
#define TMU_TER_EN_MASK (0x80000000U)
#define TMU_TER_EN_SHIFT (31U)
/*! EN
* 0b0..Disable
* 0b1..Enable
*/
#define TMU_TER_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_EN_SHIFT)) & TMU_TER_EN_MASK)
/*! @} */
/*! @name TPS - TMU Probe Select register */
/*! @{ */
#define TMU_TPS_PROBE_SEL_MASK (0xC0000000U)
#define TMU_TPS_PROBE_SEL_SHIFT (30U)
/*! PROBE_SEL
* 0b00..select the main probe only
* 0b01..select the remote probe(near A53) only
* 0b1x..select both 2 probes
*/
#define TMU_TPS_PROBE_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMU_TPS_PROBE_SEL_SHIFT)) & TMU_TPS_PROBE_SEL_MASK)
/*! @} */
/*! @name TIER - TMU Interrupt Enable register */
/*! @{ */
#define TMU_TIER_ATCTEIE0_MASK (0x2000000U)
#define TMU_TIER_ATCTEIE0_SHIFT (25U)
/*! ATCTEIE0
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
*/
#define TMU_TIER_ATCTEIE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE0_SHIFT)) & TMU_TIER_ATCTEIE0_MASK)
#define TMU_TIER_ATTEIE0_MASK (0x4000000U)
#define TMU_TIER_ATTEIE0_SHIFT (26U)
/*! ATTEIE0
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
*/
#define TMU_TIER_ATTEIE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE0_SHIFT)) & TMU_TIER_ATTEIE0_MASK)
#define TMU_TIER_ITTEIE0_MASK (0x8000000U)
#define TMU_TIER_ITTEIE0_SHIFT (27U)
/*! ITTEIE0
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
*/
#define TMU_TIER_ITTEIE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE0_SHIFT)) & TMU_TIER_ITTEIE0_MASK)
#define TMU_TIER_ATCTEIE1_MASK (0x20000000U)
#define TMU_TIER_ATCTEIE1_SHIFT (29U)
/*! ATCTEIE1
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
*/
#define TMU_TIER_ATCTEIE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE1_SHIFT)) & TMU_TIER_ATCTEIE1_MASK)
#define TMU_TIER_ATTEIE1_MASK (0x40000000U)
#define TMU_TIER_ATTEIE1_SHIFT (30U)
/*! ATTEIE1
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
*/
#define TMU_TIER_ATTEIE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE1_SHIFT)) & TMU_TIER_ATTEIE1_MASK)
#define TMU_TIER_ITTEIE1_MASK (0x80000000U)
#define TMU_TIER_ITTEIE1_SHIFT (31U)
/*! ITTEIE1
* 0b0..Disabled.
* 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
*/
#define TMU_TIER_ITTEIE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE1_SHIFT)) & TMU_TIER_ITTEIE1_MASK)
/*! @} */
/*! @name TIDR - TMU Interrupt Detect register */
/*! @{ */
#define TMU_TIDR_ATCTE0_MASK (0x2000000U)
#define TMU_TIDR_ATCTE0_SHIFT (25U)
/*! ATCTE0
* 0b0..No threshold exceeded.
* 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
*/
#define TMU_TIDR_ATCTE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE0_SHIFT)) & TMU_TIDR_ATCTE0_MASK)
#define TMU_TIDR_ATTE0_MASK (0x4000000U)
#define TMU_TIDR_ATTE0_SHIFT (26U)
/*! ATTE0
* 0b0..No threshold exceeded.
* 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded.
*/
#define TMU_TIDR_ATTE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE0_SHIFT)) & TMU_TIDR_ATTE0_MASK)
#define TMU_TIDR_ITTE0_MASK (0x8000000U)
#define TMU_TIDR_ITTE0_SHIFT (27U)
/*! ITTE0
* 0b0..No threshold exceeded.
* 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range
* measured temperature above 125 degree C.
*/
#define TMU_TIDR_ITTE0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE0_SHIFT)) & TMU_TIDR_ITTE0_MASK)
#define TMU_TIDR_ATCTE1_MASK (0x20000000U)
#define TMU_TIDR_ATCTE1_SHIFT (29U)
/*! ATCTE1
* 0b0..No threshold exceeded.
* 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
*/
#define TMU_TIDR_ATCTE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE1_SHIFT)) & TMU_TIDR_ATCTE1_MASK)
#define TMU_TIDR_ATTE1_MASK (0x40000000U)
#define TMU_TIDR_ATTE1_SHIFT (30U)
/*! ATTE1
* 0b0..No threshold exceeded.
* 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded.
*/
#define TMU_TIDR_ATTE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE1_SHIFT)) & TMU_TIDR_ATTE1_MASK)
#define TMU_TIDR_ITTE1_MASK (0x80000000U)
#define TMU_TIDR_ITTE1_SHIFT (31U)
/*! ITTE1
* 0b0..No threshold exceeded.
* 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range
* measured temperature above 125 degree C.
*/
#define TMU_TIDR_ITTE1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE1_SHIFT)) & TMU_TIDR_ITTE1_MASK)
/*! @} */
/*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */
/*! @{ */
#define TMU_TMHTITR_TEMP0_MASK (0xFFU)
#define TMU_TMHTITR_TEMP0_SHIFT (0U)
#define TMU_TMHTITR_TEMP0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP0_SHIFT)) & TMU_TMHTITR_TEMP0_MASK)
#define TMU_TMHTITR_TEMP1_MASK (0xFF0000U)
#define TMU_TMHTITR_TEMP1_SHIFT (16U)
#define TMU_TMHTITR_TEMP1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP1_SHIFT)) & TMU_TMHTITR_TEMP1_MASK)
#define TMU_TMHTITR_EN0_MASK (0x40000000U)
#define TMU_TMHTITR_EN0_SHIFT (30U)
/*! EN0
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTITR_EN0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN0_SHIFT)) & TMU_TMHTITR_EN0_MASK)
#define TMU_TMHTITR_EN1_MASK (0x80000000U)
#define TMU_TMHTITR_EN1_SHIFT (31U)
/*! EN1
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTITR_EN1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN1_SHIFT)) & TMU_TMHTITR_EN1_MASK)
/*! @} */
/*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */
/*! @{ */
#define TMU_TMHTATR_TEMP0_MASK (0xFFU)
#define TMU_TMHTATR_TEMP0_SHIFT (0U)
#define TMU_TMHTATR_TEMP0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP0_SHIFT)) & TMU_TMHTATR_TEMP0_MASK)
#define TMU_TMHTATR_TEMP1_MASK (0xFF0000U)
#define TMU_TMHTATR_TEMP1_SHIFT (16U)
#define TMU_TMHTATR_TEMP1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP1_SHIFT)) & TMU_TMHTATR_TEMP1_MASK)
#define TMU_TMHTATR_EN0_MASK (0x40000000U)
#define TMU_TMHTATR_EN0_SHIFT (30U)
/*! EN0
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTATR_EN0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN0_SHIFT)) & TMU_TMHTATR_EN0_MASK)
#define TMU_TMHTATR_EN1_MASK (0x80000000U)
#define TMU_TMHTATR_EN1_SHIFT (31U)
/*! EN1
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTATR_EN1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN1_SHIFT)) & TMU_TMHTATR_EN1_MASK)
/*! @} */
/*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */
/*! @{ */
#define TMU_TMHTACTR_TEMP0_MASK (0xFFU)
#define TMU_TMHTACTR_TEMP0_SHIFT (0U)
#define TMU_TMHTACTR_TEMP0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP0_SHIFT)) & TMU_TMHTACTR_TEMP0_MASK)
#define TMU_TMHTACTR_TEMP1_MASK (0xFF0000U)
#define TMU_TMHTACTR_TEMP1_SHIFT (16U)
#define TMU_TMHTACTR_TEMP1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP1_SHIFT)) & TMU_TMHTACTR_TEMP1_MASK)
#define TMU_TMHTACTR_EN0_MASK (0x40000000U)
#define TMU_TMHTACTR_EN0_SHIFT (30U)
/*! EN0
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTACTR_EN0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN0_SHIFT)) & TMU_TMHTACTR_EN0_MASK)
#define TMU_TMHTACTR_EN1_MASK (0x80000000U)
#define TMU_TMHTACTR_EN1_SHIFT (31U)
/*! EN1
* 0b0..Disabled.
* 0b1..Threshold enabled.
*/
#define TMU_TMHTACTR_EN1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN1_SHIFT)) & TMU_TMHTACTR_EN1_MASK)
/*! @} */
/*! @name TSCR - TMU Sensor Calibration register */
/*! @{ */
#define TMU_TSCR_SNSR0_MASK (0xFFFU)
#define TMU_TSCR_SNSR0_SHIFT (0U)
#define TMU_TSCR_SNSR0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SNSR0_SHIFT)) & TMU_TSCR_SNSR0_MASK)
#define TMU_TSCR_SNSR1_MASK (0xFFF0000U)
#define TMU_TSCR_SNSR1_SHIFT (16U)
#define TMU_TSCR_SNSR1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SNSR1_SHIFT)) & TMU_TSCR_SNSR1_MASK)
#define TMU_TSCR_V0_MASK (0x40000000U)
#define TMU_TSCR_V0_SHIFT (30U)
/*! V0
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [SNSR0] value after this bit is set.
*/
#define TMU_TSCR_V0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_V0_SHIFT)) & TMU_TSCR_V0_MASK)
#define TMU_TSCR_V1_MASK (0x80000000U)
#define TMU_TSCR_V1_SHIFT (31U)
/*! V1
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [SNSR1] value after this bit is set.
*/
#define TMU_TSCR_V1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_V1_SHIFT)) & TMU_TSCR_V1_MASK)
/*! @} */
/*! @name TRITSR - TMU Report Immediate Temperature Site register n */
/*! @{ */
#define TMU_TRITSR_TEMP0_MASK (0xFFU)
#define TMU_TRITSR_TEMP0_SHIFT (0U)
#define TMU_TRITSR_TEMP0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP0_SHIFT)) & TMU_TRITSR_TEMP0_MASK)
#define TMU_TRITSR_TEMP1_MASK (0xFF0000U)
#define TMU_TRITSR_TEMP1_SHIFT (16U)
#define TMU_TRITSR_TEMP1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP1_SHIFT)) & TMU_TRITSR_TEMP1_MASK)
#define TMU_TRITSR_V0_MASK (0x40000000U)
#define TMU_TRITSR_V0_SHIFT (30U)
/*! V0
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
*/
#define TMU_TRITSR_V0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V0_SHIFT)) & TMU_TRITSR_V0_MASK)
#define TMU_TRITSR_V1_MASK (0x80000000U)
#define TMU_TRITSR_V1_SHIFT (31U)
/*! V1
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
*/
#define TMU_TRITSR_V1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V1_SHIFT)) & TMU_TRITSR_V1_MASK)
/*! @} */
/*! @name TRATSR - TMU Report Average Temperature Site register n */
/*! @{ */
#define TMU_TRATSR_TEMP0_MASK (0xFFU)
#define TMU_TRATSR_TEMP0_SHIFT (0U)
#define TMU_TRATSR_TEMP0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP0_SHIFT)) & TMU_TRATSR_TEMP0_MASK)
#define TMU_TRATSR_TEMP1_MASK (0xFF0000U)
#define TMU_TRATSR_TEMP1_SHIFT (16U)
#define TMU_TRATSR_TEMP1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP1_SHIFT)) & TMU_TRATSR_TEMP1_MASK)
#define TMU_TRATSR_V0_MASK (0x40000000U)
#define TMU_TRATSR_V0_SHIFT (30U)
/*! V0
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
*/
#define TMU_TRATSR_V0(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V0_SHIFT)) & TMU_TRATSR_V0_MASK)
#define TMU_TRATSR_V1_MASK (0x80000000U)
#define TMU_TRATSR_V1_SHIFT (31U)
/*! V1
* 0b0..Not ready. First measurement still pending.
* 0b1..Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
*/
#define TMU_TRATSR_V1(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V1_SHIFT)) & TMU_TRATSR_V1_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TMU_Register_Masks */
/* TMU - Peripheral instance base addresses */
/** Peripheral TMU base address */
#define TMU_BASE (0x30260000u)
/** Peripheral TMU base pointer */
#define TMU ((TMU_Type *)TMU_BASE)
/** Array initializer of TMU peripheral base addresses */
#define TMU_BASE_ADDRS { TMU_BASE }
/** Array initializer of TMU peripheral base pointers */
#define TMU_BASE_PTRS { TMU }
/*!
* @}
*/ /* end of group TMU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- UART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
* @{
*/
/** UART - Register Layout Typedef */
typedef struct {
__I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */
uint8_t RESERVED_0[60];
__O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */
uint8_t RESERVED_1[60];
__IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */
__IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */
__IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */
__IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */
__IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */
__IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */
__IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */
__IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */
__IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */
__IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */
__IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */
__I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */
__IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */
__IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */
__IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */
} UART_Type;
/* ----------------------------------------------------------------------------
-- UART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup UART_Register_Masks UART Register Masks
* @{
*/
/*! @name URXD - UART Receiver Register */
/*! @{ */
#define UART_URXD_RX_DATA_MASK (0xFFU)
#define UART_URXD_RX_DATA_SHIFT (0U)
#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK)
#define UART_URXD_PRERR_MASK (0x400U)
#define UART_URXD_PRERR_SHIFT (10U)
/*! PRERR
* 0b0..= No parity error was detected for data in the RX_DATA field
* 0b1..= A parity error was detected for data in the RX_DATA field
*/
#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK)
#define UART_URXD_BRK_MASK (0x800U)
#define UART_URXD_BRK_SHIFT (11U)
/*! BRK
* 0b0..The current character is not a BREAK character
* 0b1..The current character is a BREAK character
*/
#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK)
#define UART_URXD_FRMERR_MASK (0x1000U)
#define UART_URXD_FRMERR_SHIFT (12U)
/*! FRMERR
* 0b0..The current character has no framing error
* 0b1..The current character has a framing error
*/
#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK)
#define UART_URXD_OVRRUN_MASK (0x2000U)
#define UART_URXD_OVRRUN_SHIFT (13U)
/*! OVRRUN
* 0b0..No RxFIFO overrun was detected
* 0b1..A RxFIFO overrun was detected
*/
#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK)
#define UART_URXD_ERR_MASK (0x4000U)
#define UART_URXD_ERR_SHIFT (14U)
/*! ERR
* 0b0..No error status was detected
* 0b1..An error status was detected
*/
#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK)
#define UART_URXD_CHARRDY_MASK (0x8000U)
#define UART_URXD_CHARRDY_SHIFT (15U)
/*! CHARRDY
* 0b0..Character in RX_DATA field and associated flags are invalid.
* 0b1..Character in RX_DATA field and associated flags valid and ready for reading.
*/
#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK)
/*! @} */
/*! @name UTXD - UART Transmitter Register */
/*! @{ */
#define UART_UTXD_TX_DATA_MASK (0xFFU)
#define UART_UTXD_TX_DATA_SHIFT (0U)
#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK)
/*! @} */
/*! @name UCR1 - UART Control Register 1 */
/*! @{ */
#define UART_UCR1_UARTEN_MASK (0x1U)
#define UART_UCR1_UARTEN_SHIFT (0U)
/*! UARTEN
* 0b0..Disable the UART
* 0b1..Enable the UART
*/
#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK)
#define UART_UCR1_DOZE_MASK (0x2U)
#define UART_UCR1_DOZE_SHIFT (1U)
/*! DOZE
* 0b0..The UART is enabled when in DOZE state
* 0b1..The UART is disabled when in DOZE state
*/
#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK)
#define UART_UCR1_ATDMAEN_MASK (0x4U)
#define UART_UCR1_ATDMAEN_SHIFT (2U)
/*! ATDMAEN
* 0b0..Disable AGTIM DMA request
* 0b1..Enable AGTIM DMA request
*/
#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK)
#define UART_UCR1_TXDMAEN_MASK (0x8U)
#define UART_UCR1_TXDMAEN_SHIFT (3U)
/*! TXDMAEN
* 0b0..Disable transmit DMA request
* 0b1..Enable transmit DMA request
*/
#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK)
#define UART_UCR1_SNDBRK_MASK (0x10U)
#define UART_UCR1_SNDBRK_SHIFT (4U)
/*! SNDBRK
* 0b0..Do not send a BREAK character
* 0b1..Send a BREAK character (continuous 0s)
*/
#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK)
#define UART_UCR1_RTSDEN_MASK (0x20U)
#define UART_UCR1_RTSDEN_SHIFT (5U)
/*! RTSDEN
* 0b0..Disable RTSD interrupt
* 0b1..Enable RTSD interrupt
*/
#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK)
#define UART_UCR1_TXMPTYEN_MASK (0x40U)
#define UART_UCR1_TXMPTYEN_SHIFT (6U)
/*! TXMPTYEN
* 0b0..Disable the transmitter FIFO empty interrupt
* 0b1..Enable the transmitter FIFO empty interrupt
*/
#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK)
#define UART_UCR1_IREN_MASK (0x80U)
#define UART_UCR1_IREN_SHIFT (7U)
/*! IREN
* 0b0..Disable the IR interface
* 0b1..Enable the IR interface
*/
#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK)
#define UART_UCR1_RXDMAEN_MASK (0x100U)
#define UART_UCR1_RXDMAEN_SHIFT (8U)
/*! RXDMAEN
* 0b0..Disable DMA request
* 0b1..Enable DMA request
*/
#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK)
#define UART_UCR1_RRDYEN_MASK (0x200U)
#define UART_UCR1_RRDYEN_SHIFT (9U)
/*! RRDYEN
* 0b0..Disables the RRDY interrupt
* 0b1..Enables the RRDY interrupt
*/
#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK)
#define UART_UCR1_ICD_MASK (0xC00U)
#define UART_UCR1_ICD_SHIFT (10U)
/*! ICD
* 0b00..Idle for more than 4 frames
* 0b01..Idle for more than 8 frames
* 0b10..Idle for more than 16 frames
* 0b11..Idle for more than 32 frames
*/
#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK)
#define UART_UCR1_IDEN_MASK (0x1000U)
#define UART_UCR1_IDEN_SHIFT (12U)
/*! IDEN
* 0b0..Disable the IDLE interrupt
* 0b1..Enable the IDLE interrupt
*/
#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK)
#define UART_UCR1_TRDYEN_MASK (0x2000U)
#define UART_UCR1_TRDYEN_SHIFT (13U)
/*! TRDYEN
* 0b0..Disable the transmitter ready interrupt
* 0b1..Enable the transmitter ready interrupt
*/
#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK)
#define UART_UCR1_ADBR_MASK (0x4000U)
#define UART_UCR1_ADBR_SHIFT (14U)
/*! ADBR
* 0b0..Disable automatic detection of baud rate
* 0b1..Enable automatic detection of baud rate
*/
#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK)
#define UART_UCR1_ADEN_MASK (0x8000U)
#define UART_UCR1_ADEN_SHIFT (15U)
/*! ADEN
* 0b0..Disable the automatic baud rate detection interrupt
* 0b1..Enable the automatic baud rate detection interrupt
*/
#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK)
/*! @} */
/*! @name UCR2 - UART Control Register 2 */
/*! @{ */
#define UART_UCR2_SRST_MASK (0x1U)
#define UART_UCR2_SRST_SHIFT (0U)
/*! SRST
* 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD and UTS[6-3].
* 0b1..No reset
*/
#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK)
#define UART_UCR2_RXEN_MASK (0x2U)
#define UART_UCR2_RXEN_SHIFT (1U)
/*! RXEN
* 0b0..Disable the receiver
* 0b1..Enable the receiver
*/
#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK)
#define UART_UCR2_TXEN_MASK (0x4U)
#define UART_UCR2_TXEN_SHIFT (2U)
/*! TXEN
* 0b0..Disable the transmitter
* 0b1..Enable the transmitter
*/
#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK)
#define UART_UCR2_ATEN_MASK (0x8U)
#define UART_UCR2_ATEN_SHIFT (3U)
/*! ATEN
* 0b0..AGTIM interrupt disabled
* 0b1..AGTIM interrupt enabled
*/
#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK)
#define UART_UCR2_RTSEN_MASK (0x10U)
#define UART_UCR2_RTSEN_SHIFT (4U)
/*! RTSEN
* 0b0..Disable request to send interrupt
* 0b1..Enable request to send interrupt
*/
#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK)
#define UART_UCR2_WS_MASK (0x20U)
#define UART_UCR2_WS_SHIFT (5U)
/*! WS
* 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits)
* 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits)
*/
#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK)
#define UART_UCR2_STPB_MASK (0x40U)
#define UART_UCR2_STPB_SHIFT (6U)
/*! STPB
* 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits.
* 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits.
*/
#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK)
#define UART_UCR2_PROE_MASK (0x80U)
#define UART_UCR2_PROE_SHIFT (7U)
/*! PROE
* 0b0..Even parity
* 0b1..Odd parity
*/
#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK)
#define UART_UCR2_PREN_MASK (0x100U)
#define UART_UCR2_PREN_SHIFT (8U)
/*! PREN
* 0b0..Disable parity generator and checker
* 0b1..Enable parity generator and checker
*/
#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK)
#define UART_UCR2_RTEC_MASK (0x600U)
#define UART_UCR2_RTEC_SHIFT (9U)
/*! RTEC
* 0b00..Trigger interrupt on a rising edge
* 0b01..Trigger interrupt on a falling edge
* 0b1x..Trigger interrupt on any edge
*/
#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK)
#define UART_UCR2_ESCEN_MASK (0x800U)
#define UART_UCR2_ESCEN_SHIFT (11U)
/*! ESCEN
* 0b0..Disable escape sequence detection
* 0b1..Enable escape sequence detection
*/
#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK)
#define UART_UCR2_CTS_MASK (0x1000U)
#define UART_UCR2_CTS_SHIFT (12U)
/*! CTS
* 0b0..The CTS_B pin is high (inactive)
* 0b1..The CTS_B pin is low (active)
*/
#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK)
#define UART_UCR2_CTSC_MASK (0x2000U)
#define UART_UCR2_CTSC_SHIFT (13U)
/*! CTSC
* 0b0..The CTS_B pin is controlled by the CTS bit
* 0b1..The CTS_B pin is controlled by the receiver
*/
#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK)
#define UART_UCR2_IRTS_MASK (0x4000U)
#define UART_UCR2_IRTS_SHIFT (14U)
/*! IRTS
* 0b0..Transmit only when the RTS pin is asserted
* 0b1..Ignore the RTS pin
*/
#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK)
#define UART_UCR2_ESCI_MASK (0x8000U)
#define UART_UCR2_ESCI_SHIFT (15U)
/*! ESCI
* 0b0..Disable the escape sequence interrupt
* 0b1..Enable the escape sequence interrupt
*/
#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK)
/*! @} */
/*! @name UCR3 - UART Control Register 3 */
/*! @{ */
#define UART_UCR3_ACIEN_MASK (0x1U)
#define UART_UCR3_ACIEN_SHIFT (0U)
/*! ACIEN
* 0b0..ACST interrupt disabled
* 0b1..ACST interrupt enabled
*/
#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK)
#define UART_UCR3_INVT_MASK (0x2U)
#define UART_UCR3_INVT_SHIFT (1U)
/*! INVT
* 0b0..TXD is not inverted
* 0b1..TXD is inverted
* 0b0..TXD Active low transmission
* 0b1..TXD Active high transmission
*/
#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK)
#define UART_UCR3_RXDMUXSEL_MASK (0x4U)
#define UART_UCR3_RXDMUXSEL_SHIFT (2U)
#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK)
#define UART_UCR3_DTRDEN_MASK (0x8U)
#define UART_UCR3_DTRDEN_SHIFT (3U)
#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK)
#define UART_UCR3_AWAKEN_MASK (0x10U)
#define UART_UCR3_AWAKEN_SHIFT (4U)
/*! AWAKEN
* 0b0..Disable the AWAKE interrupt
* 0b1..Enable the AWAKE interrupt
*/
#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK)
#define UART_UCR3_AIRINTEN_MASK (0x20U)
#define UART_UCR3_AIRINTEN_SHIFT (5U)
/*! AIRINTEN
* 0b0..Disable the AIRINT interrupt
* 0b1..Enable the AIRINT interrupt
*/
#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK)
#define UART_UCR3_RXDSEN_MASK (0x40U)
#define UART_UCR3_RXDSEN_SHIFT (6U)
/*! RXDSEN
* 0b0..Disable the RXDS interrupt
* 0b1..Enable the RXDS interrupt
*/
#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK)
#define UART_UCR3_ADNIMP_MASK (0x80U)
#define UART_UCR3_ADNIMP_SHIFT (7U)
/*! ADNIMP
* 0b0..Autobaud detection new features selected
* 0b1..Keep old autobaud detection mechanism
*/
#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK)
#define UART_UCR3_RI_MASK (0x100U)
#define UART_UCR3_RI_SHIFT (8U)
#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK)
#define UART_UCR3_DCD_MASK (0x200U)
#define UART_UCR3_DCD_SHIFT (9U)
#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK)
#define UART_UCR3_DSR_MASK (0x400U)
#define UART_UCR3_DSR_SHIFT (10U)
#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK)
#define UART_UCR3_FRAERREN_MASK (0x800U)
#define UART_UCR3_FRAERREN_SHIFT (11U)
/*! FRAERREN
* 0b0..Disable the frame error interrupt
* 0b1..Enable the frame error interrupt
*/
#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK)
#define UART_UCR3_PARERREN_MASK (0x1000U)
#define UART_UCR3_PARERREN_SHIFT (12U)
/*! PARERREN
* 0b0..Disable the parity error interrupt
* 0b1..Enable the parity error interrupt
*/
#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK)
#define UART_UCR3_DTREN_MASK (0x2000U)
#define UART_UCR3_DTREN_SHIFT (13U)
#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK)
#define UART_UCR3_DPEC_MASK (0xC000U)
#define UART_UCR3_DPEC_SHIFT (14U)
#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK)
/*! @} */
/*! @name UCR4 - UART Control Register 4 */
/*! @{ */
#define UART_UCR4_DREN_MASK (0x1U)
#define UART_UCR4_DREN_SHIFT (0U)
/*! DREN
* 0b0..Disable RDR interrupt
* 0b1..Enable RDR interrupt
*/
#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK)
#define UART_UCR4_OREN_MASK (0x2U)
#define UART_UCR4_OREN_SHIFT (1U)
/*! OREN
* 0b0..Disable ORE interrupt
* 0b1..Enable ORE interrupt
*/
#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK)
#define UART_UCR4_BKEN_MASK (0x4U)
#define UART_UCR4_BKEN_SHIFT (2U)
/*! BKEN
* 0b0..Disable the BRCD interrupt
* 0b1..Enable the BRCD interrupt
*/
#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK)
#define UART_UCR4_TCEN_MASK (0x8U)
#define UART_UCR4_TCEN_SHIFT (3U)
/*! TCEN
* 0b0..Disable TXDC interrupt
* 0b1..Enable TXDC interrupt
*/
#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK)
#define UART_UCR4_LPBYP_MASK (0x10U)
#define UART_UCR4_LPBYP_SHIFT (4U)
/*! LPBYP
* 0b0..Low power features enabled
* 0b1..Low power features disabled
*/
#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK)
#define UART_UCR4_IRSC_MASK (0x20U)
#define UART_UCR4_IRSC_SHIFT (5U)
/*! IRSC
* 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation
* 0b1..The vote logic uses the UART reference clock
*/
#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK)
#define UART_UCR4_IDDMAEN_MASK (0x40U)
#define UART_UCR4_IDDMAEN_SHIFT (6U)
/*! IDDMAEN
* 0b0..DMA IDLE interrupt disabled
* 0b1..DMA IDLE interrupt enabled
*/
#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK)
#define UART_UCR4_WKEN_MASK (0x80U)
#define UART_UCR4_WKEN_SHIFT (7U)
/*! WKEN
* 0b0..Disable the WAKE interrupt
* 0b1..Enable the WAKE interrupt
*/
#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK)
#define UART_UCR4_ENIRI_MASK (0x100U)
#define UART_UCR4_ENIRI_SHIFT (8U)
/*! ENIRI
* 0b0..Serial infrared Interrupt disabled
* 0b1..Serial infrared Interrupt enabled
*/
#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK)
#define UART_UCR4_INVR_MASK (0x200U)
#define UART_UCR4_INVR_SHIFT (9U)
/*! INVR
* 0b0..RXD input is not inverted
* 0b1..RXD input is inverted
* 0b0..RXD active low detection
* 0b1..RXD active high detection
*/
#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK)
#define UART_UCR4_CTSTL_MASK (0xFC00U)
#define UART_UCR4_CTSTL_SHIFT (10U)
/*! CTSTL
* 0b000000..0 characters received
* 0b000001..1 characters in the RxFIFO
* 0b100000..32 characters in the RxFIFO (maximum)
*/
#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK)
/*! @} */
/*! @name UFCR - UART FIFO Control Register */
/*! @{ */
#define UART_UFCR_RXTL_MASK (0x3FU)
#define UART_UFCR_RXTL_SHIFT (0U)
/*! RXTL
* 0b000000..0 characters received
* 0b000001..RxFIFO has 1 character
* 0b011111..RxFIFO has 31 characters
* 0b100000..RxFIFO has 32 characters (maximum)
*/
#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK)
#define UART_UFCR_DCEDTE_MASK (0x40U)
#define UART_UFCR_DCEDTE_SHIFT (6U)
/*! DCEDTE
* 0b0..DCE mode selected
* 0b1..DTE mode selected
*/
#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK)
#define UART_UFCR_RFDIV_MASK (0x380U)
#define UART_UFCR_RFDIV_SHIFT (7U)
/*! RFDIV
* 0b000..Divide input clock by 6
* 0b001..Divide input clock by 5
* 0b010..Divide input clock by 4
* 0b011..Divide input clock by 3
* 0b100..Divide input clock by 2
* 0b101..Divide input clock by 1
* 0b110..Divide input clock by 7
* 0b111..Reserved
*/
#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK)
#define UART_UFCR_TXTL_MASK (0xFC00U)
#define UART_UFCR_TXTL_SHIFT (10U)
/*! TXTL
* 0b000000..Reserved
* 0b000001..Reserved
* 0b000010..TxFIFO has 2 or fewer characters
* 0b011111..TxFIFO has 31 or fewer characters
* 0b100000..TxFIFO has 32 characters (maximum)
*/
#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK)
/*! @} */
/*! @name USR1 - UART Status Register 1 */
/*! @{ */
#define UART_USR1_SAD_MASK (0x8U)
#define UART_USR1_SAD_SHIFT (3U)
/*! SAD
* 0b0..No slave address detected
* 0b1..Slave address detected
*/
#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK)
#define UART_USR1_AWAKE_MASK (0x10U)
#define UART_USR1_AWAKE_SHIFT (4U)
/*! AWAKE
* 0b0..No falling edge was detected on the RXD Serial pin
* 0b1..A falling edge was detected on the RXD Serial pin
*/
#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK)
#define UART_USR1_AIRINT_MASK (0x20U)
#define UART_USR1_AIRINT_SHIFT (5U)
/*! AIRINT
* 0b0..No pulse was detected on the RXD IrDA pin
* 0b1..A pulse was detected on the RXD IrDA pin
*/
#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK)
#define UART_USR1_RXDS_MASK (0x40U)
#define UART_USR1_RXDS_SHIFT (6U)
/*! RXDS
* 0b0..Receive in progress
* 0b1..Receiver is IDLE
*/
#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK)
#define UART_USR1_DTRD_MASK (0x80U)
#define UART_USR1_DTRD_SHIFT (7U)
#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK)
#define UART_USR1_AGTIM_MASK (0x100U)
#define UART_USR1_AGTIM_SHIFT (8U)
/*! AGTIM
* 0b0..AGTIM is not active
* 0b1..AGTIM is active (write 1 to clear)
*/
#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK)
#define UART_USR1_RRDY_MASK (0x200U)
#define UART_USR1_RRDY_SHIFT (9U)
/*! RRDY
* 0b0..No character ready
* 0b1..Character(s) ready (interrupt posted)
*/
#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK)
#define UART_USR1_FRAMERR_MASK (0x400U)
#define UART_USR1_FRAMERR_SHIFT (10U)
/*! FRAMERR
* 0b0..No frame error detected
* 0b1..Frame error detected (write 1 to clear)
*/
#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK)
#define UART_USR1_ESCF_MASK (0x800U)
#define UART_USR1_ESCF_SHIFT (11U)
/*! ESCF
* 0b0..No escape sequence detected
* 0b1..Escape sequence detected (write 1 to clear).
*/
#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK)
#define UART_USR1_RTSD_MASK (0x1000U)
#define UART_USR1_RTSD_SHIFT (12U)
/*! RTSD
* 0b0..RTS_B pin did not change state since last cleared
* 0b1..RTS_B pin changed state (write 1 to clear)
*/
#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK)
#define UART_USR1_TRDY_MASK (0x2000U)
#define UART_USR1_TRDY_SHIFT (13U)
/*! TRDY
* 0b0..The transmitter does not require data
* 0b1..The transmitter requires data (interrupt posted)
*/
#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK)
#define UART_USR1_RTSS_MASK (0x4000U)
#define UART_USR1_RTSS_SHIFT (14U)
/*! RTSS
* 0b0..The RTS_B module input is high (inactive)
* 0b1..The RTS_B module input is low (active)
*/
#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK)
#define UART_USR1_PARITYERR_MASK (0x8000U)
#define UART_USR1_PARITYERR_SHIFT (15U)
/*! PARITYERR
* 0b0..No parity error detected
* 0b1..Parity error detected (write 1 to clear)
*/
#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK)
/*! @} */
/*! @name USR2 - UART Status Register 2 */
/*! @{ */
#define UART_USR2_RDR_MASK (0x1U)
#define UART_USR2_RDR_SHIFT (0U)
/*! RDR
* 0b0..No receive data ready
* 0b1..Receive data ready
*/
#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK)
#define UART_USR2_ORE_MASK (0x2U)
#define UART_USR2_ORE_SHIFT (1U)
/*! ORE
* 0b0..No overrun error
* 0b1..Overrun error (write 1 to clear)
*/
#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK)
#define UART_USR2_BRCD_MASK (0x4U)
#define UART_USR2_BRCD_SHIFT (2U)
/*! BRCD
* 0b0..No BREAK condition was detected
* 0b1..A BREAK condition was detected (write 1 to clear)
*/
#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK)
#define UART_USR2_TXDC_MASK (0x8U)
#define UART_USR2_TXDC_SHIFT (3U)
/*! TXDC
* 0b0..Transmit is incomplete
* 0b1..Transmit is complete
*/
#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK)
#define UART_USR2_RTSF_MASK (0x10U)
#define UART_USR2_RTSF_SHIFT (4U)
/*! RTSF
* 0b0..Programmed edge not detected on RTS_B
* 0b1..Programmed edge detected on RTS_B (write 1 to clear)
*/
#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK)
#define UART_USR2_DCDIN_MASK (0x20U)
#define UART_USR2_DCDIN_SHIFT (5U)
#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK)
#define UART_USR2_DCDDELT_MASK (0x40U)
#define UART_USR2_DCDDELT_SHIFT (6U)
#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK)
#define UART_USR2_WAKE_MASK (0x80U)
#define UART_USR2_WAKE_SHIFT (7U)
/*! WAKE
* 0b0..start bit not detected
* 0b1..start bit detected (write 1 to clear)
*/
#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK)
#define UART_USR2_IRINT_MASK (0x100U)
#define UART_USR2_IRINT_SHIFT (8U)
/*! IRINT
* 0b0..no edge detected
* 0b1..valid edge detected (write 1 to clear)
*/
#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK)
#define UART_USR2_RIIN_MASK (0x200U)
#define UART_USR2_RIIN_SHIFT (9U)
#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK)
#define UART_USR2_RIDELT_MASK (0x400U)
#define UART_USR2_RIDELT_SHIFT (10U)
#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK)
#define UART_USR2_ACST_MASK (0x800U)
#define UART_USR2_ACST_SHIFT (11U)
/*! ACST
* 0b0..Measurement of bit length not finished (in autobaud)
* 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear)
*/
#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK)
#define UART_USR2_IDLE_MASK (0x1000U)
#define UART_USR2_IDLE_SHIFT (12U)
/*! IDLE
* 0b0..No idle condition detected
* 0b1..Idle condition detected (write 1 to clear)
*/
#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK)
#define UART_USR2_DTRF_MASK (0x2000U)
#define UART_USR2_DTRF_SHIFT (13U)
#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK)
#define UART_USR2_TXFE_MASK (0x4000U)
#define UART_USR2_TXFE_SHIFT (14U)
/*! TXFE
* 0b0..The transmit buffer (TxFIFO) is not empty
* 0b1..The transmit buffer (TxFIFO) is empty
*/
#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK)
#define UART_USR2_ADET_MASK (0x8000U)
#define UART_USR2_ADET_SHIFT (15U)
/*! ADET
* 0b0..ASCII "A" or "a" was not received
* 0b1..ASCII "A" or "a" was received (write 1 to clear)
*/
#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK)
/*! @} */
/*! @name UESC - UART Escape Character Register */
/*! @{ */
#define UART_UESC_ESC_CHAR_MASK (0xFFU)
#define UART_UESC_ESC_CHAR_SHIFT (0U)
#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK)
/*! @} */
/*! @name UTIM - UART Escape Timer Register */
/*! @{ */
#define UART_UTIM_TIM_MASK (0xFFFU)
#define UART_UTIM_TIM_SHIFT (0U)
#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK)
/*! @} */
/*! @name UBIR - UART BRM Incremental Register */
/*! @{ */
#define UART_UBIR_INC_MASK (0xFFFFU)
#define UART_UBIR_INC_SHIFT (0U)
#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK)
/*! @} */
/*! @name UBMR - UART BRM Modulator Register */
/*! @{ */
#define UART_UBMR_MOD_MASK (0xFFFFU)
#define UART_UBMR_MOD_SHIFT (0U)
#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK)
/*! @} */
/*! @name UBRC - UART Baud Rate Count Register */
/*! @{ */
#define UART_UBRC_BCNT_MASK (0xFFFFU)
#define UART_UBRC_BCNT_SHIFT (0U)
#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK)
/*! @} */
/*! @name ONEMS - UART One Millisecond Register */
/*! @{ */
#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU)
#define UART_ONEMS_ONEMS_SHIFT (0U)
#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK)
/*! @} */
/*! @name UTS - UART Test Register */
/*! @{ */
#define UART_UTS_SOFTRST_MASK (0x1U)
#define UART_UTS_SOFTRST_SHIFT (0U)
/*! SOFTRST
* 0b0..Software reset inactive
* 0b1..Software reset active
*/
#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK)
#define UART_UTS_RXFULL_MASK (0x8U)
#define UART_UTS_RXFULL_SHIFT (3U)
/*! RXFULL
* 0b0..The RxFIFO is not full
* 0b1..The RxFIFO is full
*/
#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK)
#define UART_UTS_TXFULL_MASK (0x10U)
#define UART_UTS_TXFULL_SHIFT (4U)
/*! TXFULL
* 0b0..The TxFIFO is not full
* 0b1..The TxFIFO is full
*/
#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK)
#define UART_UTS_RXEMPTY_MASK (0x20U)
#define UART_UTS_RXEMPTY_SHIFT (5U)
/*! RXEMPTY
* 0b0..The RxFIFO is not empty
* 0b1..The RxFIFO is empty
*/
#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK)
#define UART_UTS_TXEMPTY_MASK (0x40U)
#define UART_UTS_TXEMPTY_SHIFT (6U)
/*! TXEMPTY
* 0b0..The TxFIFO is not empty
* 0b1..The TxFIFO is empty
*/
#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK)
#define UART_UTS_RXDBG_MASK (0x200U)
#define UART_UTS_RXDBG_SHIFT (9U)
/*! RXDBG
* 0b0..rx fifo read pointer does not increment
* 0b1..rx_fifo read pointer increments as normal
*/
#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK)
#define UART_UTS_LOOPIR_MASK (0x400U)
#define UART_UTS_LOOPIR_SHIFT (10U)
/*! LOOPIR
* 0b0..No IR loop
* 0b1..Connect IR transmitter to IR receiver
*/
#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK)
#define UART_UTS_DBGEN_MASK (0x800U)
#define UART_UTS_DBGEN_SHIFT (11U)
/*! DBGEN
* 0b0..UART will go into debug mode when debug_req is HIGH
* 0b1..UART will not go into debug mode even if debug_req is HIGH
*/
#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK)
#define UART_UTS_LOOP_MASK (0x1000U)
#define UART_UTS_LOOP_SHIFT (12U)
/*! LOOP
* 0b0..Normal receiver operation
* 0b1..Internally connect the transmitter output to the receiver input
*/
#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK)
#define UART_UTS_FRCPERR_MASK (0x2000U)
#define UART_UTS_FRCPERR_SHIFT (13U)
/*! FRCPERR
* 0b0..Generate normal parity
* 0b1..Generate inverted parity (error)
*/
#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK)
/*! @} */
/*! @name UMCR - UART RS-485 Mode Control Register */
/*! @{ */
#define UART_UMCR_MDEN_MASK (0x1U)
#define UART_UMCR_MDEN_SHIFT (0U)
/*! MDEN
* 0b0..Normal RS-232 or IrDA mode, see for detail.
* 0b1..Enable RS-485 mode, see for detail
*/
#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK)
#define UART_UMCR_SLAM_MASK (0x2U)
#define UART_UMCR_SLAM_SHIFT (1U)
/*! SLAM
* 0b0..Select Normal Address Detect mode
* 0b1..Select Automatic Address Detect mode
*/
#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK)
#define UART_UMCR_TXB8_MASK (0x4U)
#define UART_UMCR_TXB8_SHIFT (2U)
/*! TXB8
* 0b0..0 will be transmitted as the RS485 9th data bit
* 0b1..1 will be transmitted as the RS485 9th data bit
*/
#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK)
#define UART_UMCR_SADEN_MASK (0x8U)
#define UART_UMCR_SADEN_SHIFT (3U)
/*! SADEN
* 0b0..Disable RS-485 Slave Address Detected Interrupt
* 0b1..Enable RS-485 Slave Address Detected Interrupt
*/
#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK)
#define UART_UMCR_SLADDR_MASK (0xFF00U)
#define UART_UMCR_SLADDR_SHIFT (8U)
#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group UART_Register_Masks */
/* UART - Peripheral instance base addresses */
/** Peripheral UART1 base address */
#define UART1_BASE (0x30860000u)
/** Peripheral UART1 base pointer */
#define UART1 ((UART_Type *)UART1_BASE)
/** Peripheral UART2 base address */
#define UART2_BASE (0x30890000u)
/** Peripheral UART2 base pointer */
#define UART2 ((UART_Type *)UART2_BASE)
/** Peripheral UART3 base address */
#define UART3_BASE (0x30880000u)
/** Peripheral UART3 base pointer */
#define UART3 ((UART_Type *)UART3_BASE)
/** Peripheral UART4 base address */
#define UART4_BASE (0x30A60000u)
/** Peripheral UART4 base pointer */
#define UART4 ((UART_Type *)UART4_BASE)
/** Array initializer of UART peripheral base addresses */
#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
/** Array initializer of UART peripheral base pointers */
#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4 }
/** Interrupt vectors for the UART peripheral type */
#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn }
/*!
* @}
*/ /* end of group UART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint32_t CAPLENGTH; /**< Capability registers length and Host Controller Operational Registers, offset: 0x0 */
__I uint32_t HCSPARAMS1; /**< Structural Parameters 1 Register, offset: 0x4 */
__I uint32_t HCSPARAMS2; /**< Structural Parameters 2 Register, offset: 0x8 */
__I uint32_t HCSPARAMS3; /**< Structural Parameters 3 Register, offset: 0xC */
__I uint32_t HCCPARAMS1; /**< Capability Parameters 1 Register, offset: 0x10 */
__I uint32_t DBOFF; /**< Doorbell Offset Register, offset: 0x14 */
__I uint32_t RTSOFF; /**< Runtime Register Space Offset Register, offset: 0x18 */
__I uint32_t HCCPARAMS2; /**< Host Controller Capability Parameters 2, offset: 0x1C */
__IO uint32_t USBCMD; /**< USB Command Register, offset: 0x20 */
__IO uint32_t USBSTS; /**< USB Status Register, offset: 0x24 */
__I uint32_t PAGESIZE; /**< Page Size Register, offset: 0x28 */
uint8_t RESERVED_0[8];
__IO uint32_t DNCTRL; /**< Device Notification Register, offset: 0x34 */
__IO uint32_t CRCR_LO; /**< CRCR_LO, offset: 0x38 */
__IO uint32_t CRCR_HI; /**< , offset: 0x3C */
uint8_t RESERVED_1[16];
__IO uint32_t DCBAAP_LO; /**< DCBAAP_LO, offset: 0x50 */
__IO uint32_t DCBAAP_HI; /**< DCBAAP_HI, offset: 0x54 */
__IO uint32_t CONFIG; /**< Configuration Register, offset: 0x58 */
uint8_t RESERVED_2[964];
__IO uint32_t PORTSC_20; /**< Port Status and Control Register, offset: 0x420 */
__IO uint32_t PORTPMSC_20; /**< USB3 Port Power Management Status and Control Register, offset: 0x424 */
uint32_t PORTLI_20; /**< , offset: 0x428 */
__IO uint32_t PORTHLPMC_20; /**< , offset: 0x42C */
__IO uint32_t PORTSC_30; /**< , offset: 0x430 */
__IO uint32_t PORTPMSC_30; /**< USB3 Port Power Management Status and Control Register, offset: 0x434 */
__I uint32_t PORTLI_30; /**< Port Link Info Register, offset: 0x438 */
uint32_t PORTHLPMC_30; /**< USB2 Port Hardware LPM Control Register, offset: 0x43C */
__I uint32_t MFINDEX; /**< Microframe Index Register, offset: 0x440 */
uint8_t RESERVED_3[28];
__IO uint32_t IMAN; /**< Interrupter Management Register, offset: 0x460 */
__IO uint32_t IMOD; /**< Interrupter Moderation Register, offset: 0x464 */
__IO uint32_t ERSTSZ; /**< ERSTSZ, offset: 0x468 */
uint8_t RESERVED_4[4];
__IO uint32_t ERSTBA_LO; /**< ERSTBA_LO, offset: 0x470 */
__IO uint32_t ERSTBA_HI; /**< ERSTBA_HI, offset: 0x474 */
__IO uint32_t ERDP_LO; /**< ERDP_LO, offset: 0x478 */
__IO uint32_t ERDP_HI; /**< ERDP_HI, offset: 0x47C */
__IO uint32_t DB; /**< Doorbell Register, offset: 0x480 */
uint8_t RESERVED_5[1020];
__IO uint32_t USBLEGSUP; /**< USBLEGSUP, offset: 0x880 */
__IO uint32_t USBLEGCTLSTS; /**< USBLEGCTLSTS, offset: 0x884 */
uint8_t RESERVED_6[8];
__I uint32_t SUPTPRT2_DW0; /**< SUPTPRT2_DW0, offset: 0x890 */
__I uint32_t SUPTPRT2_DW1; /**< SUPTPRT2_DW1 Register, offset: 0x894 */
__I uint32_t SUPTPRT2_DW2; /**< xHCI Supported Protocol Capability_ Data Word 2, offset: 0x898 */
__I uint32_t SUPTPRT2_DW3; /**< SUPTPRT2_DW3 Register, offset: 0x89C */
__I uint32_t SUPTPRT3_DW0; /**< , offset: 0x8A0 */
__I uint32_t SUPTPRT3_DW1; /**< SUPTPRT3_DW1 Register, offset: 0x8A4 */
__I uint32_t SUPTPRT3_DW2; /**< SUPTPRT3_DW2, offset: 0x8A8 */
__I uint32_t SUPTPRT3_DW3; /**< SUPTPRT3_DW3, offset: 0x8AC */
uint8_t RESERVED_7[47184];
__IO uint32_t GSBUSCFG0; /**< Global SoC Bus Configuration Register 0, offset: 0xC100 */
__IO uint32_t GSBUSCFG1; /**< Global SoC Bus Configuration Register 1, offset: 0xC104 */
__IO uint32_t GTXTHRCFG; /**< Global Tx Threshold Control Register, offset: 0xC108 */
__IO uint32_t GRXTHRCFG; /**< Global Rx Threshold Control Register, offset: 0xC10C */
__IO uint32_t GCTL; /**< Global Core Control Register, offset: 0xC110 */
uint8_t RESERVED_8[4];
__IO uint32_t GSTS; /**< Global Status Register, offset: 0xC118 */
__IO uint32_t GUCTL1; /**< , offset: 0xC11C */
uint8_t RESERVED_9[8];
__IO uint32_t GUID; /**< Global User ID Register, offset: 0xC128 */
__IO uint32_t GUCTL; /**< Global User Control Register, offset: 0xC12C */
__I uint32_t GBUSERRADDRLO; /**< Gobal SoC Bus Error Address Register - Low, offset: 0xC130 */
__I uint32_t GBUSERRADDRHI; /**< Gobal SoC Bus Error Address Register - High, offset: 0xC134 */
__IO uint32_t GPRTBIMAPLO; /**< Global SS Port to Bus Instance Mapping Register - Low, offset: 0xC138 */
__IO uint32_t GPRTBIMAPHI; /**< Global SS Port to Bus Instance Mapping Register - High, offset: 0xC13C */
__I uint32_t GHWPARAMS0; /**< Global Hardware Parameters Register 0, offset: 0xC140 */
__I uint32_t GHWPARAMS1; /**< Global Hardware Parameters Register 1, offset: 0xC144 */
__I uint32_t GHWPARAMS2; /**< Global Hardware Parameters Register 2, offset: 0xC148 */
__I uint32_t GHWPARAMS3; /**< Global Hardware Parameters Register 3, offset: 0xC14C */
__I uint32_t GHWPARAMS4; /**< Global Hardware Parameters Register 4, offset: 0xC150 */
__I uint32_t GHWPARAMS5; /**< Global Hardware Parameters Register 5, offset: 0xC154 */
__I uint32_t GHWPARAMS6; /**< Global Hardware Parameters Register 6, offset: 0xC158 */
__I uint32_t GHWPARAMS7; /**< Global Hardware Parameters Register 7, offset: 0xC15C */
uint8_t RESERVED_10[32];
__IO uint32_t GPRTBIMAP_HSLO; /**< Global High-Speed Port to Bus Instance Mapping Register - Low, offset: 0xC180 */
__IO uint32_t GPRTBIMAP_HSHI; /**< Global High-Speed Port to Bus Instance Mapping Register - High, offset: 0xC184 */
__IO uint32_t GPRTBIMAP_FSLO; /**< Global Full-Speed Port to Bus Instance Mapping Register - Low, offset: 0xC188 */
__IO uint32_t GPRTBIMAP_FSHI; /**< Global Full-Speed Port to Bus Instance Mapping Register - High, offset: 0xC18C */
uint8_t RESERVED_11[12];
__IO uint32_t GUCTL2; /**< Global User Control Register 2, offset: 0xC19C */
uint8_t RESERVED_12[96];
__IO uint32_t GUSB2PHYCFG; /**< Global USB2 PHY Configuration Register, offset: 0xC200 */
uint8_t RESERVED_13[124];
__I uint32_t GUSB2PHYACC_ULPI; /**< Global USB 2.0 UTMI PHY vendor control register, offset: 0xC280 */
uint8_t RESERVED_14[60];
__IO uint32_t GUSB3PIPECTL; /**< Global USB 3.0 PIPE control register, offset: 0xC2C0 */
uint8_t RESERVED_15[60];
__IO uint32_t GTXFIFOSIZ[8]; /**< Global transmit FIFO size register, array offset: 0xC300, array step: 0x4 */
uint8_t RESERVED_16[96];
__IO uint32_t GRXFIFOSIZ[3]; /**< Global receive FIFO size register, array offset: 0xC380, array step: 0x4 */
uint8_t RESERVED_17[116];
__IO uint32_t GEVNTADRLO; /**< Global Event Buffer Address (Low) Register, offset: 0xC400 */
__IO uint32_t GEVNTADRHI; /**< Global Event Buffer Address (High) Register, offset: 0xC404 */
__IO uint32_t GEVNTSIZ; /**< Global event buffer size register, offset: 0xC408 */
__IO uint32_t GEVNTCOUNT; /**< Global event buffer count register, offset: 0xC40C */
uint8_t RESERVED_18[496];
__I uint32_t GHWPARAMS8; /**< Global Hardware Parameters Register 8, offset: 0xC600 */
uint8_t RESERVED_19[12];
__IO uint32_t GTXFIFOPRIDEV; /**< Global Device TX FIFO DMA Priority Register, offset: 0xC610 */
uint8_t RESERVED_20[4];
__IO uint32_t GTXFIFOPRIHST; /**< Global Host TX FIFO DMA Priority Register, offset: 0xC618 */
__IO uint32_t GRXFIFOPRIHST; /**< Global Host RX FIFO DMA Priority Register, offset: 0xC61C */
__IO uint32_t GFIFOPRIDBC; /**< Global Host Debug Capability DMA Priority Register, offset: 0xC620 */
__IO uint32_t GDMAHLRATIO; /**< , offset: 0xC624 */
uint8_t RESERVED_21[8];
__IO uint32_t GFLADJ; /**< Global Frame Length Adjustment Register, offset: 0xC630 */
uint8_t RESERVED_22[204];
__IO uint32_t DCFG; /**< Device Configuration Register, offset: 0xC700 */
__IO uint32_t DCTL; /**< Device control register, offset: 0xC704 */
__IO uint32_t DEVTEN; /**< Device Event Enable Register, offset: 0xC708 */
__IO uint32_t DSTS; /**< Device Status Register, offset: 0xC70C */
__IO uint32_t DGCMDPAR; /**< Device Generic Command Parameter Register, offset: 0xC710 */
__IO uint32_t DGCMD; /**< , offset: 0xC714 */
uint8_t RESERVED_23[8];
__IO uint32_t DALEPENA; /**< Device Active USB Endpoint Enable Register, offset: 0xC720 */
uint8_t RESERVED_24[220];
__IO uint32_t DEPCMDPAR2; /**< Device physical endpoint-n command parameter 2 register, offset: 0xC800 */
__IO uint32_t DEPCMDPAR1; /**< Device Physical Endpoint-n Command Parameter 1 Register, offset: 0xC804 */
__IO uint32_t DEPCMDPAR0; /**< Device Physical Endpoint-n Command Parameter 0 Register, offset: 0xC808 */
__IO uint32_t DEPCMD; /**< Device Physical Endpoint-n Command Register, offset: 0xC80C */
uint8_t RESERVED_25[496];
__IO uint32_t DEV_IMOD; /**< Device Interrupt Moderation Register, offset: 0xCA00 */
uint8_t RESERVED_26[556];
__IO uint32_t BCFG; /**< BCFG, offset: 0xCC30 */
uint8_t RESERVED_27[4];
__IO uint32_t BCEVT; /**< BCEVT, offset: 0xCC38 */
__IO uint32_t BCEVTEN; /**< BCEVTEN, offset: 0xCC3C */
} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/*! @name CAPLENGTH - Capability registers length and Host Controller Operational Registers */
/*! @{ */
#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
#define USB_CAPLENGTH_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
#define USB_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U)
#define USB_CAPLENGTH_HCIVERSION_SHIFT (16U)
#define USB_CAPLENGTH_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USB_CAPLENGTH_HCIVERSION_SHIFT)) & USB_CAPLENGTH_HCIVERSION_MASK)
/*! @} */
/*! @name HCSPARAMS1 - Structural Parameters 1 Register */
/*! @{ */
#define USB_HCSPARAMS1_MAXSLOTS_MASK (0xFFU)
#define USB_HCSPARAMS1_MAXSLOTS_SHIFT (0U)
#define USB_HCSPARAMS1_MAXSLOTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXSLOTS_SHIFT)) & USB_HCSPARAMS1_MAXSLOTS_MASK)
#define USB_HCSPARAMS1_MAXINTRS_MASK (0x7FF00U)
#define USB_HCSPARAMS1_MAXINTRS_SHIFT (8U)
#define USB_HCSPARAMS1_MAXINTRS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXINTRS_SHIFT)) & USB_HCSPARAMS1_MAXINTRS_MASK)
#define USB_HCSPARAMS1_MAXPORTS_MASK (0xFF000000U)
#define USB_HCSPARAMS1_MAXPORTS_SHIFT (24U)
#define USB_HCSPARAMS1_MAXPORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS1_MAXPORTS_SHIFT)) & USB_HCSPARAMS1_MAXPORTS_MASK)
/*! @} */
/*! @name HCSPARAMS2 - Structural Parameters 2 Register */
/*! @{ */
#define USB_HCSPARAMS2_IST_MASK (0xFU)
#define USB_HCSPARAMS2_IST_SHIFT (0U)
#define USB_HCSPARAMS2_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_IST_SHIFT)) & USB_HCSPARAMS2_IST_MASK)
#define USB_HCSPARAMS2_ERSTMAX_MASK (0xF0U)
#define USB_HCSPARAMS2_ERSTMAX_SHIFT (4U)
#define USB_HCSPARAMS2_ERSTMAX(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_ERSTMAX_SHIFT)) & USB_HCSPARAMS2_ERSTMAX_MASK)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK (0x3E00000U)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT (21U)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_SHIFT)) & USB_HCSPARAMS2_MAXSCRATCHPADBUFS_HI_MASK)
#define USB_HCSPARAMS2_SPR_MASK (0x4000000U)
#define USB_HCSPARAMS2_SPR_SHIFT (26U)
#define USB_HCSPARAMS2_SPR(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_SPR_SHIFT)) & USB_HCSPARAMS2_SPR_MASK)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK (0xF8000000U)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT (27U)
#define USB_HCSPARAMS2_MAXSCRATCHPADBUFS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS2_MAXSCRATCHPADBUFS_SHIFT)) & USB_HCSPARAMS2_MAXSCRATCHPADBUFS_MASK)
/*! @} */
/*! @name HCSPARAMS3 - Structural Parameters 3 Register */
/*! @{ */
#define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK (0xFFU)
#define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT (0U)
#define USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_SHIFT)) & USB_HCSPARAMS3_U1_DEVICE_EXIT_LAT_MASK)
#define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK (0xFFFF0000U)
#define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT (16U)
#define USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_SHIFT)) & USB_HCSPARAMS3_U2_DEVICE_EXIT_LAT_MASK)
/*! @} */
/*! @name HCCPARAMS1 - Capability Parameters 1 Register */
/*! @{ */
#define USB_HCCPARAMS1_AC64_MASK (0x1U)
#define USB_HCCPARAMS1_AC64_SHIFT (0U)
#define USB_HCCPARAMS1_AC64(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_AC64_SHIFT)) & USB_HCCPARAMS1_AC64_MASK)
#define USB_HCCPARAMS1_BNC_MASK (0x2U)
#define USB_HCCPARAMS1_BNC_SHIFT (1U)
#define USB_HCCPARAMS1_BNC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_BNC_SHIFT)) & USB_HCCPARAMS1_BNC_MASK)
#define USB_HCCPARAMS1_CSZ_MASK (0x4U)
#define USB_HCCPARAMS1_CSZ_SHIFT (2U)
#define USB_HCCPARAMS1_CSZ(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_CSZ_SHIFT)) & USB_HCCPARAMS1_CSZ_MASK)
#define USB_HCCPARAMS1_PPC_MASK (0x8U)
#define USB_HCCPARAMS1_PPC_SHIFT (3U)
#define USB_HCCPARAMS1_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PPC_SHIFT)) & USB_HCCPARAMS1_PPC_MASK)
#define USB_HCCPARAMS1_PIND_MASK (0x10U)
#define USB_HCCPARAMS1_PIND_SHIFT (4U)
#define USB_HCCPARAMS1_PIND(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PIND_SHIFT)) & USB_HCCPARAMS1_PIND_MASK)
#define USB_HCCPARAMS1_LHRC_MASK (0x20U)
#define USB_HCCPARAMS1_LHRC_SHIFT (5U)
#define USB_HCCPARAMS1_LHRC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_LHRC_SHIFT)) & USB_HCCPARAMS1_LHRC_MASK)
#define USB_HCCPARAMS1_LTC_MASK (0x40U)
#define USB_HCCPARAMS1_LTC_SHIFT (6U)
#define USB_HCCPARAMS1_LTC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_LTC_SHIFT)) & USB_HCCPARAMS1_LTC_MASK)
#define USB_HCCPARAMS1_NSS_MASK (0x80U)
#define USB_HCCPARAMS1_NSS_SHIFT (7U)
#define USB_HCCPARAMS1_NSS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_NSS_SHIFT)) & USB_HCCPARAMS1_NSS_MASK)
#define USB_HCCPARAMS1_PAE_MASK (0x100U)
#define USB_HCCPARAMS1_PAE_SHIFT (8U)
#define USB_HCCPARAMS1_PAE(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_PAE_SHIFT)) & USB_HCCPARAMS1_PAE_MASK)
#define USB_HCCPARAMS1_SPC_MASK (0x200U)
#define USB_HCCPARAMS1_SPC_SHIFT (9U)
#define USB_HCCPARAMS1_SPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_SPC_SHIFT)) & USB_HCCPARAMS1_SPC_MASK)
#define USB_HCCPARAMS1_SEC_MASK (0x400U)
#define USB_HCCPARAMS1_SEC_SHIFT (10U)
#define USB_HCCPARAMS1_SEC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_SEC_SHIFT)) & USB_HCCPARAMS1_SEC_MASK)
#define USB_HCCPARAMS1_CFC_MASK (0x800U)
#define USB_HCCPARAMS1_CFC_SHIFT (11U)
#define USB_HCCPARAMS1_CFC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_CFC_SHIFT)) & USB_HCCPARAMS1_CFC_MASK)
#define USB_HCCPARAMS1_MAXPSASIZE_MASK (0xF000U)
#define USB_HCCPARAMS1_MAXPSASIZE_SHIFT (12U)
#define USB_HCCPARAMS1_MAXPSASIZE(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_MAXPSASIZE_SHIFT)) & USB_HCCPARAMS1_MAXPSASIZE_MASK)
#define USB_HCCPARAMS1_XECP_MASK (0xFFFF0000U)
#define USB_HCCPARAMS1_XECP_SHIFT (16U)
#define USB_HCCPARAMS1_XECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS1_XECP_SHIFT)) & USB_HCCPARAMS1_XECP_MASK)
/*! @} */
/*! @name DBOFF - Doorbell Offset Register */
/*! @{ */
#define USB_DBOFF_DOORBELL_ARRAY_OFFSET_MASK (0xFFFFFFFCU)
#define USB_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT (2U)
#define USB_DBOFF_DOORBELL_ARRAY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_DBOFF_DOORBELL_ARRAY_OFFSET_SHIFT)) & USB_DBOFF_DOORBELL_ARRAY_OFFSET_MASK)
/*! @} */
/*! @name RTSOFF - Runtime Register Space Offset Register */
/*! @{ */
#define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK (0xFFFFFFE0U)
#define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT (5U)
#define USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_SHIFT)) & USB_RTSOFF_RUNTIME_REG_SPACE_OFFSET_MASK)
/*! @} */
/*! @name HCCPARAMS2 - Host Controller Capability Parameters 2 */
/*! @{ */
#define USB_HCCPARAMS2_U3C_MASK (0x1U)
#define USB_HCCPARAMS2_U3C_SHIFT (0U)
#define USB_HCCPARAMS2_U3C(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_U3C_SHIFT)) & USB_HCCPARAMS2_U3C_MASK)
#define USB_HCCPARAMS2_CMC_MASK (0x2U)
#define USB_HCCPARAMS2_CMC_SHIFT (1U)
#define USB_HCCPARAMS2_CMC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CMC_SHIFT)) & USB_HCCPARAMS2_CMC_MASK)
#define USB_HCCPARAMS2_FSC_MASK (0x4U)
#define USB_HCCPARAMS2_FSC_SHIFT (2U)
#define USB_HCCPARAMS2_FSC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_FSC_SHIFT)) & USB_HCCPARAMS2_FSC_MASK)
#define USB_HCCPARAMS2_CTC_MASK (0x8U)
#define USB_HCCPARAMS2_CTC_SHIFT (3U)
#define USB_HCCPARAMS2_CTC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CTC_SHIFT)) & USB_HCCPARAMS2_CTC_MASK)
#define USB_HCCPARAMS2_LEC_MASK (0x10U)
#define USB_HCCPARAMS2_LEC_SHIFT (4U)
#define USB_HCCPARAMS2_LEC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_LEC_SHIFT)) & USB_HCCPARAMS2_LEC_MASK)
#define USB_HCCPARAMS2_CIC_MASK (0x20U)
#define USB_HCCPARAMS2_CIC_SHIFT (5U)
#define USB_HCCPARAMS2_CIC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS2_CIC_SHIFT)) & USB_HCCPARAMS2_CIC_MASK)
/*! @} */
/*! @name USBCMD - USB Command Register */
/*! @{ */
#define USB_USBCMD_R_S_MASK (0x1U)
#define USB_USBCMD_R_S_SHIFT (0U)
#define USB_USBCMD_R_S(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_R_S_SHIFT)) & USB_USBCMD_R_S_MASK)
#define USB_USBCMD_HCRST_MASK (0x2U)
#define USB_USBCMD_HCRST_SHIFT (1U)
#define USB_USBCMD_HCRST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_HCRST_SHIFT)) & USB_USBCMD_HCRST_MASK)
#define USB_USBCMD_INTE_MASK (0x4U)
#define USB_USBCMD_INTE_SHIFT (2U)
#define USB_USBCMD_INTE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_INTE_SHIFT)) & USB_USBCMD_INTE_MASK)
#define USB_USBCMD_HSEE_MASK (0x8U)
#define USB_USBCMD_HSEE_SHIFT (3U)
#define USB_USBCMD_HSEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_HSEE_SHIFT)) & USB_USBCMD_HSEE_MASK)
#define USB_USBCMD_LHCRST_MASK (0x80U)
#define USB_USBCMD_LHCRST_SHIFT (7U)
#define USB_USBCMD_LHCRST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_LHCRST_SHIFT)) & USB_USBCMD_LHCRST_MASK)
#define USB_USBCMD_CSS_MASK (0x100U)
#define USB_USBCMD_CSS_SHIFT (8U)
#define USB_USBCMD_CSS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CSS_SHIFT)) & USB_USBCMD_CSS_MASK)
#define USB_USBCMD_CRS_MASK (0x200U)
#define USB_USBCMD_CRS_SHIFT (9U)
#define USB_USBCMD_CRS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CRS_SHIFT)) & USB_USBCMD_CRS_MASK)
#define USB_USBCMD_EWE_MASK (0x400U)
#define USB_USBCMD_EWE_SHIFT (10U)
#define USB_USBCMD_EWE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_EWE_SHIFT)) & USB_USBCMD_EWE_MASK)
#define USB_USBCMD_EU3S_MASK (0x800U)
#define USB_USBCMD_EU3S_SHIFT (11U)
#define USB_USBCMD_EU3S(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_EU3S_SHIFT)) & USB_USBCMD_EU3S_MASK)
#define USB_USBCMD_CME_MASK (0x2000U)
#define USB_USBCMD_CME_SHIFT (13U)
#define USB_USBCMD_CME(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_CME_SHIFT)) & USB_USBCMD_CME_MASK)
/*! @} */
/*! @name USBSTS - USB Status Register */
/*! @{ */
#define USB_USBSTS_HCH_MASK (0x1U)
#define USB_USBSTS_HCH_SHIFT (0U)
#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
#define USB_USBSTS_HSE_MASK (0x4U)
#define USB_USBSTS_HSE_SHIFT (2U)
#define USB_USBSTS_HSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HSE_SHIFT)) & USB_USBSTS_HSE_MASK)
#define USB_USBSTS_EINT_MASK (0x8U)
#define USB_USBSTS_EINT_SHIFT (3U)
#define USB_USBSTS_EINT(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_EINT_SHIFT)) & USB_USBSTS_EINT_MASK)
#define USB_USBSTS_PCD_MASK (0x10U)
#define USB_USBSTS_PCD_SHIFT (4U)
#define USB_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCD_SHIFT)) & USB_USBSTS_PCD_MASK)
#define USB_USBSTS_SSS_MASK (0x100U)
#define USB_USBSTS_SSS_SHIFT (8U)
#define USB_USBSTS_SSS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SSS_SHIFT)) & USB_USBSTS_SSS_MASK)
#define USB_USBSTS_RSS_MASK (0x200U)
#define USB_USBSTS_RSS_SHIFT (9U)
#define USB_USBSTS_RSS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RSS_SHIFT)) & USB_USBSTS_RSS_MASK)
#define USB_USBSTS_SRE_MASK (0x400U)
#define USB_USBSTS_SRE_SHIFT (10U)
#define USB_USBSTS_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRE_SHIFT)) & USB_USBSTS_SRE_MASK)
#define USB_USBSTS_CNR_MASK (0x800U)
#define USB_USBSTS_CNR_SHIFT (11U)
#define USB_USBSTS_CNR(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_CNR_SHIFT)) & USB_USBSTS_CNR_MASK)
#define USB_USBSTS_HCE_MASK (0x1000U)
#define USB_USBSTS_HCE_SHIFT (12U)
#define USB_USBSTS_HCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCE_SHIFT)) & USB_USBSTS_HCE_MASK)
/*! @} */
/*! @name PAGESIZE - Page Size Register */
/*! @{ */
#define USB_PAGESIZE_PAGE_SIZE_MASK (0xFFFFU)
#define USB_PAGESIZE_PAGE_SIZE_SHIFT (0U)
#define USB_PAGESIZE_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB_PAGESIZE_PAGE_SIZE_SHIFT)) & USB_PAGESIZE_PAGE_SIZE_MASK)
/*! @} */
/*! @name DNCTRL - Device Notification Register */
/*! @{ */
#define USB_DNCTRL_N0_N15_MASK (0xFFFFU)
#define USB_DNCTRL_N0_N15_SHIFT (0U)
#define USB_DNCTRL_N0_N15(x) (((uint32_t)(((uint32_t)(x)) << USB_DNCTRL_N0_N15_SHIFT)) & USB_DNCTRL_N0_N15_MASK)
/*! @} */
/*! @name CRCR_LO - CRCR_LO */
/*! @{ */
#define USB_CRCR_LO_RCS_MASK (0x1U)
#define USB_CRCR_LO_RCS_SHIFT (0U)
#define USB_CRCR_LO_RCS(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_RCS_SHIFT)) & USB_CRCR_LO_RCS_MASK)
#define USB_CRCR_LO_CS_MASK (0x2U)
#define USB_CRCR_LO_CS_SHIFT (1U)
#define USB_CRCR_LO_CS(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CS_SHIFT)) & USB_CRCR_LO_CS_MASK)
#define USB_CRCR_LO_CA_MASK (0x4U)
#define USB_CRCR_LO_CA_SHIFT (2U)
#define USB_CRCR_LO_CA(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CA_SHIFT)) & USB_CRCR_LO_CA_MASK)
#define USB_CRCR_LO_CRR_MASK (0x8U)
#define USB_CRCR_LO_CRR_SHIFT (3U)
#define USB_CRCR_LO_CRR(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CRR_SHIFT)) & USB_CRCR_LO_CRR_MASK)
#define USB_CRCR_LO_CMD_RING_PNTR_MASK (0xFFFFFFC0U)
#define USB_CRCR_LO_CMD_RING_PNTR_SHIFT (6U)
#define USB_CRCR_LO_CMD_RING_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_LO_CMD_RING_PNTR_SHIFT)) & USB_CRCR_LO_CMD_RING_PNTR_MASK)
/*! @} */
/*! @name CRCR_HI - */
/*! @{ */
#define USB_CRCR_HI_CMD_RING_PNTR_MASK (0xFFFFFFFFU)
#define USB_CRCR_HI_CMD_RING_PNTR_SHIFT (0U)
#define USB_CRCR_HI_CMD_RING_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB_CRCR_HI_CMD_RING_PNTR_SHIFT)) & USB_CRCR_HI_CMD_RING_PNTR_MASK)
/*! @} */
/*! @name DCBAAP_LO - DCBAAP_LO */
/*! @{ */
#define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK (0xFFFFFFC0U)
#define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT (6U)
#define USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_SHIFT)) & USB_DCBAAP_LO_DEVICE_CONTEXT_BAAP_MASK)
/*! @} */
/*! @name DCBAAP_HI - DCBAAP_HI */
/*! @{ */
#define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK (0xFFFFFFFFU)
#define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT (0U)
#define USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_SHIFT)) & USB_DCBAAP_HI_DEVICE_CONTEXT_BAAP_MASK)
/*! @} */
/*! @name CONFIG - Configuration Register */
/*! @{ */
#define USB_CONFIG_MAXSLOTSEN_MASK (0xFFU)
#define USB_CONFIG_MAXSLOTSEN_SHIFT (0U)
#define USB_CONFIG_MAXSLOTSEN(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_MAXSLOTSEN_SHIFT)) & USB_CONFIG_MAXSLOTSEN_MASK)
#define USB_CONFIG_U3E_MASK (0x100U)
#define USB_CONFIG_U3E_SHIFT (8U)
#define USB_CONFIG_U3E(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_U3E_SHIFT)) & USB_CONFIG_U3E_MASK)
#define USB_CONFIG_CIE_MASK (0x200U)
#define USB_CONFIG_CIE_SHIFT (9U)
#define USB_CONFIG_CIE(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIG_CIE_SHIFT)) & USB_CONFIG_CIE_MASK)
/*! @} */
/*! @name PORTSC_20 - Port Status and Control Register */
/*! @{ */
#define USB_PORTSC_20_CCS_MASK (0x1U)
#define USB_PORTSC_20_CCS_SHIFT (0U)
#define USB_PORTSC_20_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CCS_SHIFT)) & USB_PORTSC_20_CCS_MASK)
#define USB_PORTSC_20_PED_MASK (0x2U)
#define USB_PORTSC_20_PED_SHIFT (1U)
/*! PED - PED
*/
#define USB_PORTSC_20_PED(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PED_SHIFT)) & USB_PORTSC_20_PED_MASK)
#define USB_PORTSC_20_OCA_MASK (0x8U)
#define USB_PORTSC_20_OCA_SHIFT (3U)
/*! OCA - OCA
*/
#define USB_PORTSC_20_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_OCA_SHIFT)) & USB_PORTSC_20_OCA_MASK)
#define USB_PORTSC_20_PR_MASK (0x10U)
#define USB_PORTSC_20_PR_SHIFT (4U)
/*! PR - PR
*/
#define USB_PORTSC_20_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PR_SHIFT)) & USB_PORTSC_20_PR_MASK)
#define USB_PORTSC_20_PLS_MASK (0x1E0U)
#define USB_PORTSC_20_PLS_SHIFT (5U)
/*! PLS - PLS
*/
#define USB_PORTSC_20_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PLS_SHIFT)) & USB_PORTSC_20_PLS_MASK)
#define USB_PORTSC_20_PP_MASK (0x200U)
#define USB_PORTSC_20_PP_SHIFT (9U)
/*! PP - PP
*/
#define USB_PORTSC_20_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PP_SHIFT)) & USB_PORTSC_20_PP_MASK)
#define USB_PORTSC_20_PORTSPEED_MASK (0x3C00U)
#define USB_PORTSC_20_PORTSPEED_SHIFT (10U)
/*! PORTSPEED - PORTSPEED
*/
#define USB_PORTSC_20_PORTSPEED(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PORTSPEED_SHIFT)) & USB_PORTSC_20_PORTSPEED_MASK)
#define USB_PORTSC_20_PIC_MASK (0xC000U)
#define USB_PORTSC_20_PIC_SHIFT (14U)
/*! PIC - PIC
*/
#define USB_PORTSC_20_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PIC_SHIFT)) & USB_PORTSC_20_PIC_MASK)
#define USB_PORTSC_20_LWS_MASK (0x10000U)
#define USB_PORTSC_20_LWS_SHIFT (16U)
/*! LWS - LWS
*/
#define USB_PORTSC_20_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_LWS_SHIFT)) & USB_PORTSC_20_LWS_MASK)
#define USB_PORTSC_20_CSC_MASK (0x20000U)
#define USB_PORTSC_20_CSC_SHIFT (17U)
/*! CSC - CSC
*/
#define USB_PORTSC_20_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CSC_SHIFT)) & USB_PORTSC_20_CSC_MASK)
#define USB_PORTSC_20_PEC_MASK (0x40000U)
#define USB_PORTSC_20_PEC_SHIFT (18U)
#define USB_PORTSC_20_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PEC_SHIFT)) & USB_PORTSC_20_PEC_MASK)
#define USB_PORTSC_20_OCC_MASK (0x100000U)
#define USB_PORTSC_20_OCC_SHIFT (20U)
/*! OCC - OCC
*/
#define USB_PORTSC_20_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_OCC_SHIFT)) & USB_PORTSC_20_OCC_MASK)
#define USB_PORTSC_20_PRC_MASK (0x200000U)
#define USB_PORTSC_20_PRC_SHIFT (21U)
/*! PRC - PRC
*/
#define USB_PORTSC_20_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PRC_SHIFT)) & USB_PORTSC_20_PRC_MASK)
#define USB_PORTSC_20_PLC_MASK (0x400000U)
#define USB_PORTSC_20_PLC_SHIFT (22U)
/*! PLC - PLC
*/
#define USB_PORTSC_20_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_PLC_SHIFT)) & USB_PORTSC_20_PLC_MASK)
#define USB_PORTSC_20_CAS_MASK (0x1000000U)
#define USB_PORTSC_20_CAS_SHIFT (24U)
/*! CAS - CAS
*/
#define USB_PORTSC_20_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_CAS_SHIFT)) & USB_PORTSC_20_CAS_MASK)
#define USB_PORTSC_20_WCE_MASK (0x2000000U)
#define USB_PORTSC_20_WCE_SHIFT (25U)
/*! WCE - WCE
*/
#define USB_PORTSC_20_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WCE_SHIFT)) & USB_PORTSC_20_WCE_MASK)
#define USB_PORTSC_20_WDE_MASK (0x4000000U)
#define USB_PORTSC_20_WDE_SHIFT (26U)
/*! WDE - WDE
*/
#define USB_PORTSC_20_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WDE_SHIFT)) & USB_PORTSC_20_WDE_MASK)
#define USB_PORTSC_20_WOE_MASK (0x8000000U)
#define USB_PORTSC_20_WOE_SHIFT (27U)
/*! WOE - WOE
*/
#define USB_PORTSC_20_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_WOE_SHIFT)) & USB_PORTSC_20_WOE_MASK)
#define USB_PORTSC_20_DR_MASK (0x40000000U)
#define USB_PORTSC_20_DR_SHIFT (30U)
/*! DR - Reset value
*/
#define USB_PORTSC_20_DR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_20_DR_SHIFT)) & USB_PORTSC_20_DR_MASK)
/*! @} */
/*! @name PORTPMSC_20 - USB3 Port Power Management Status and Control Register */
/*! @{ */
#define USB_PORTPMSC_20_L1S_MASK (0x7U)
#define USB_PORTPMSC_20_L1S_SHIFT (0U)
/*! L1S - L1 Status (L1S)
*/
#define USB_PORTPMSC_20_L1S(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_L1S_SHIFT)) & USB_PORTPMSC_20_L1S_MASK)
#define USB_PORTPMSC_20_RWE_MASK (0x8U)
#define USB_PORTPMSC_20_RWE_SHIFT (3U)
/*! RWE - RWE Port Test Control
*/
#define USB_PORTPMSC_20_RWE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_RWE_SHIFT)) & USB_PORTPMSC_20_RWE_MASK)
#define USB_PORTPMSC_20_HIRD_MASK (0xF0U)
#define USB_PORTPMSC_20_HIRD_SHIFT (4U)
#define USB_PORTPMSC_20_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_HIRD_SHIFT)) & USB_PORTPMSC_20_HIRD_MASK)
#define USB_PORTPMSC_20_L1DSLOT_MASK (0xFF00U)
#define USB_PORTPMSC_20_L1DSLOT_SHIFT (8U)
#define USB_PORTPMSC_20_L1DSLOT(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_L1DSLOT_SHIFT)) & USB_PORTPMSC_20_L1DSLOT_MASK)
#define USB_PORTPMSC_20_HLE_MASK (0x10000U)
#define USB_PORTPMSC_20_HLE_SHIFT (16U)
#define USB_PORTPMSC_20_HLE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_HLE_SHIFT)) & USB_PORTPMSC_20_HLE_MASK)
#define USB_PORTPMSC_20_PRTTSTCTRL_MASK (0xF0000000U)
#define USB_PORTPMSC_20_PRTTSTCTRL_SHIFT (28U)
#define USB_PORTPMSC_20_PRTTSTCTRL(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_20_PRTTSTCTRL_SHIFT)) & USB_PORTPMSC_20_PRTTSTCTRL_MASK)
/*! @} */
/*! @name PORTHLPMC_20 - */
/*! @{ */
#define USB_PORTHLPMC_20_HIRDM_MASK (0x3U)
#define USB_PORTHLPMC_20_HIRDM_SHIFT (0U)
#define USB_PORTHLPMC_20_HIRDM(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_HIRDM_SHIFT)) & USB_PORTHLPMC_20_HIRDM_MASK)
#define USB_PORTHLPMC_20_L1_TIMEOUT_MASK (0x3FCU)
#define USB_PORTHLPMC_20_L1_TIMEOUT_SHIFT (2U)
#define USB_PORTHLPMC_20_L1_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_L1_TIMEOUT_SHIFT)) & USB_PORTHLPMC_20_L1_TIMEOUT_MASK)
#define USB_PORTHLPMC_20_HIRDD_MASK (0x3C00U)
#define USB_PORTHLPMC_20_HIRDD_SHIFT (10U)
#define USB_PORTHLPMC_20_HIRDD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTHLPMC_20_HIRDD_SHIFT)) & USB_PORTHLPMC_20_HIRDD_MASK)
/*! @} */
/*! @name PORTSC_30 - */
/*! @{ */
#define USB_PORTSC_30_CCS_MASK (0x1U)
#define USB_PORTSC_30_CCS_SHIFT (0U)
#define USB_PORTSC_30_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CCS_SHIFT)) & USB_PORTSC_30_CCS_MASK)
#define USB_PORTSC_30_PED_MASK (0x2U)
#define USB_PORTSC_30_PED_SHIFT (1U)
#define USB_PORTSC_30_PED(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PED_SHIFT)) & USB_PORTSC_30_PED_MASK)
#define USB_PORTSC_30_OCA_MASK (0x8U)
#define USB_PORTSC_30_OCA_SHIFT (3U)
#define USB_PORTSC_30_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_OCA_SHIFT)) & USB_PORTSC_30_OCA_MASK)
#define USB_PORTSC_30_PR_MASK (0x10U)
#define USB_PORTSC_30_PR_SHIFT (4U)
#define USB_PORTSC_30_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PR_SHIFT)) & USB_PORTSC_30_PR_MASK)
#define USB_PORTSC_30_PLS_MASK (0x1E0U)
#define USB_PORTSC_30_PLS_SHIFT (5U)
#define USB_PORTSC_30_PLS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PLS_SHIFT)) & USB_PORTSC_30_PLS_MASK)
#define USB_PORTSC_30_PP_MASK (0x200U)
#define USB_PORTSC_30_PP_SHIFT (9U)
#define USB_PORTSC_30_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PP_SHIFT)) & USB_PORTSC_30_PP_MASK)
#define USB_PORTSC_30_PORTSPEED_MASK (0x3C00U)
#define USB_PORTSC_30_PORTSPEED_SHIFT (10U)
#define USB_PORTSC_30_PORTSPEED(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PORTSPEED_SHIFT)) & USB_PORTSC_30_PORTSPEED_MASK)
#define USB_PORTSC_30_PIC_MASK (0xC000U)
#define USB_PORTSC_30_PIC_SHIFT (14U)
#define USB_PORTSC_30_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PIC_SHIFT)) & USB_PORTSC_30_PIC_MASK)
#define USB_PORTSC_30_LWS_MASK (0x10000U)
#define USB_PORTSC_30_LWS_SHIFT (16U)
#define USB_PORTSC_30_LWS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_LWS_SHIFT)) & USB_PORTSC_30_LWS_MASK)
#define USB_PORTSC_30_CSC_MASK (0x20000U)
#define USB_PORTSC_30_CSC_SHIFT (17U)
#define USB_PORTSC_30_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CSC_SHIFT)) & USB_PORTSC_30_CSC_MASK)
#define USB_PORTSC_30_PEC_MASK (0x40000U)
#define USB_PORTSC_30_PEC_SHIFT (18U)
#define USB_PORTSC_30_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PEC_SHIFT)) & USB_PORTSC_30_PEC_MASK)
#define USB_PORTSC_30_WRC_MASK (0x80000U)
#define USB_PORTSC_30_WRC_SHIFT (19U)
#define USB_PORTSC_30_WRC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WRC_SHIFT)) & USB_PORTSC_30_WRC_MASK)
#define USB_PORTSC_30_OCC_MASK (0x100000U)
#define USB_PORTSC_30_OCC_SHIFT (20U)
#define USB_PORTSC_30_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_OCC_SHIFT)) & USB_PORTSC_30_OCC_MASK)
#define USB_PORTSC_30_PRC_MASK (0x200000U)
#define USB_PORTSC_30_PRC_SHIFT (21U)
/*! PRC - PRC
*/
#define USB_PORTSC_30_PRC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PRC_SHIFT)) & USB_PORTSC_30_PRC_MASK)
#define USB_PORTSC_30_PLC_MASK (0x400000U)
#define USB_PORTSC_30_PLC_SHIFT (22U)
/*! PLC - PLC
*/
#define USB_PORTSC_30_PLC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_PLC_SHIFT)) & USB_PORTSC_30_PLC_MASK)
#define USB_PORTSC_30_CEC_MASK (0x800000U)
#define USB_PORTSC_30_CEC_SHIFT (23U)
/*! CEC - CEC
*/
#define USB_PORTSC_30_CEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CEC_SHIFT)) & USB_PORTSC_30_CEC_MASK)
#define USB_PORTSC_30_CAS_MASK (0x1000000U)
#define USB_PORTSC_30_CAS_SHIFT (24U)
/*! CAS - Cold Attach Status
*/
#define USB_PORTSC_30_CAS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_CAS_SHIFT)) & USB_PORTSC_30_CAS_MASK)
#define USB_PORTSC_30_WCE_MASK (0x2000000U)
#define USB_PORTSC_30_WCE_SHIFT (25U)
/*! WCE - WCE
*/
#define USB_PORTSC_30_WCE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WCE_SHIFT)) & USB_PORTSC_30_WCE_MASK)
#define USB_PORTSC_30_WDE_MASK (0x4000000U)
#define USB_PORTSC_30_WDE_SHIFT (26U)
/*! WDE - WDE
*/
#define USB_PORTSC_30_WDE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WDE_SHIFT)) & USB_PORTSC_30_WDE_MASK)
#define USB_PORTSC_30_WOE_MASK (0x8000000U)
#define USB_PORTSC_30_WOE_SHIFT (27U)
/*! WOE - WOE
*/
#define USB_PORTSC_30_WOE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WOE_SHIFT)) & USB_PORTSC_30_WOE_MASK)
#define USB_PORTSC_30_DR_MASK (0x40000000U)
#define USB_PORTSC_30_DR_SHIFT (30U)
#define USB_PORTSC_30_DR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_DR_SHIFT)) & USB_PORTSC_30_DR_MASK)
#define USB_PORTSC_30_WPR_MASK (0x80000000U)
#define USB_PORTSC_30_WPR_SHIFT (31U)
#define USB_PORTSC_30_WPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC_30_WPR_SHIFT)) & USB_PORTSC_30_WPR_MASK)
/*! @} */
/*! @name PORTPMSC_30 - USB3 Port Power Management Status and Control Register */
/*! @{ */
#define USB_PORTPMSC_30_U1_TIMEOUT_MASK (0xFFU)
#define USB_PORTPMSC_30_U1_TIMEOUT_SHIFT (0U)
/*! U1_TIMEOUT - U1_TIMEOUT
*/
#define USB_PORTPMSC_30_U1_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_U1_TIMEOUT_SHIFT)) & USB_PORTPMSC_30_U1_TIMEOUT_MASK)
#define USB_PORTPMSC_30_U2_TIMEOUT_MASK (0xFF00U)
#define USB_PORTPMSC_30_U2_TIMEOUT_SHIFT (8U)
/*! U2_TIMEOUT - U2_TIMEOUT
*/
#define USB_PORTPMSC_30_U2_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_U2_TIMEOUT_SHIFT)) & USB_PORTPMSC_30_U2_TIMEOUT_MASK)
#define USB_PORTPMSC_30_FLA_MASK (0x10000U)
#define USB_PORTPMSC_30_FLA_SHIFT (16U)
#define USB_PORTPMSC_30_FLA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTPMSC_30_FLA_SHIFT)) & USB_PORTPMSC_30_FLA_MASK)
/*! @} */
/*! @name PORTLI_30 - Port Link Info Register */
/*! @{ */
#define USB_PORTLI_30_LINK_ERROR_COUNT_MASK (0xFFFFU)
#define USB_PORTLI_30_LINK_ERROR_COUNT_SHIFT (0U)
/*! LINK_ERROR_COUNT - LINK_ERROR_COUNT
*/
#define USB_PORTLI_30_LINK_ERROR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTLI_30_LINK_ERROR_COUNT_SHIFT)) & USB_PORTLI_30_LINK_ERROR_COUNT_MASK)
/*! @} */
/*! @name MFINDEX - Microframe Index Register */
/*! @{ */
#define USB_MFINDEX_MICROFRAME_INDEX_MASK (0x3FFFU)
#define USB_MFINDEX_MICROFRAME_INDEX_SHIFT (0U)
#define USB_MFINDEX_MICROFRAME_INDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_MFINDEX_MICROFRAME_INDEX_SHIFT)) & USB_MFINDEX_MICROFRAME_INDEX_MASK)
/*! @} */
/*! @name IMAN - Interrupter Management Register */
/*! @{ */
#define USB_IMAN_IP_MASK (0x1U)
#define USB_IMAN_IP_SHIFT (0U)
/*! IP - IP Interrupt Pending
*/
#define USB_IMAN_IP(x) (((uint32_t)(((uint32_t)(x)) << USB_IMAN_IP_SHIFT)) & USB_IMAN_IP_MASK)
#define USB_IMAN_IE_MASK (0x2U)
#define USB_IMAN_IE_SHIFT (1U)
#define USB_IMAN_IE(x) (((uint32_t)(((uint32_t)(x)) << USB_IMAN_IE_SHIFT)) & USB_IMAN_IE_MASK)
/*! @} */
/*! @name IMOD - Interrupter Moderation Register */
/*! @{ */
#define USB_IMOD_IMODI_MASK (0xFFFFU)
#define USB_IMOD_IMODI_SHIFT (0U)
#define USB_IMOD_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB_IMOD_IMODI_SHIFT)) & USB_IMOD_IMODI_MASK)
#define USB_IMOD_IMODC_MASK (0xFFFF0000U)
#define USB_IMOD_IMODC_SHIFT (16U)
#define USB_IMOD_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB_IMOD_IMODC_SHIFT)) & USB_IMOD_IMODC_MASK)
/*! @} */
/*! @name ERSTSZ - ERSTSZ */
/*! @{ */
#define USB_ERSTSZ_ERS_TABLE_SIZE_MASK (0xFFFFU)
#define USB_ERSTSZ_ERS_TABLE_SIZE_SHIFT (0U)
#define USB_ERSTSZ_ERS_TABLE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USB_ERSTSZ_ERS_TABLE_SIZE_SHIFT)) & USB_ERSTSZ_ERS_TABLE_SIZE_MASK)
/*! @} */
/*! @name ERSTBA_LO - ERSTBA_LO */
/*! @{ */
#define USB_ERSTBA_LO_ERS_TABLE_BAR_MASK (0xFFFFFFC0U)
#define USB_ERSTBA_LO_ERS_TABLE_BAR_SHIFT (6U)
#define USB_ERSTBA_LO_ERS_TABLE_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB_ERSTBA_LO_ERS_TABLE_BAR_SHIFT)) & USB_ERSTBA_LO_ERS_TABLE_BAR_MASK)
/*! @} */
/*! @name ERSTBA_HI - ERSTBA_HI */
/*! @{ */
#define USB_ERSTBA_HI_ERS_TABLE_BAR_MASK (0xFFFFFFFFU)
#define USB_ERSTBA_HI_ERS_TABLE_BAR_SHIFT (0U)
#define USB_ERSTBA_HI_ERS_TABLE_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB_ERSTBA_HI_ERS_TABLE_BAR_SHIFT)) & USB_ERSTBA_HI_ERS_TABLE_BAR_MASK)
/*! @} */
/*! @name ERDP_LO - ERDP_LO */
/*! @{ */
#define USB_ERDP_LO_DESI_MASK (0x7U)
#define USB_ERDP_LO_DESI_SHIFT (0U)
#define USB_ERDP_LO_DESI(x) (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_DESI_SHIFT)) & USB_ERDP_LO_DESI_MASK)
#define USB_ERDP_LO_EHB_MASK (0x8U)
#define USB_ERDP_LO_EHB_SHIFT (3U)
/*! EHB - EHB
*/
#define USB_ERDP_LO_EHB(x) (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_EHB_SHIFT)) & USB_ERDP_LO_EHB_MASK)
#define USB_ERDP_LO_ERD_PNTR_MASK (0xFFFFFFF0U)
#define USB_ERDP_LO_ERD_PNTR_SHIFT (4U)
/*! ERD_PNTR - ERD_PNTR
*/
#define USB_ERDP_LO_ERD_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB_ERDP_LO_ERD_PNTR_SHIFT)) & USB_ERDP_LO_ERD_PNTR_MASK)
/*! @} */
/*! @name ERDP_HI - ERDP_HI */
/*! @{ */
#define USB_ERDP_HI_ERD_PNTR_MASK (0xFFFFFFFFU)
#define USB_ERDP_HI_ERD_PNTR_SHIFT (0U)
#define USB_ERDP_HI_ERD_PNTR(x) (((uint32_t)(((uint32_t)(x)) << USB_ERDP_HI_ERD_PNTR_SHIFT)) & USB_ERDP_HI_ERD_PNTR_MASK)
/*! @} */
/*! @name DB - Doorbell Register */
/*! @{ */
#define USB_DB_DB_TARGET_MASK (0xFFU)
#define USB_DB_DB_TARGET_SHIFT (0U)
#define USB_DB_DB_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USB_DB_DB_TARGET_SHIFT)) & USB_DB_DB_TARGET_MASK)
#define USB_DB_DB_STREAM_ID_MASK (0xFFFF0000U)
#define USB_DB_DB_STREAM_ID_SHIFT (16U)
#define USB_DB_DB_STREAM_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_DB_DB_STREAM_ID_SHIFT)) & USB_DB_DB_STREAM_ID_MASK)
/*! @} */
/*! @name USBLEGSUP - USBLEGSUP */
/*! @{ */
#define USB_USBLEGSUP_CAPABILITY_ID_MASK (0xFFU)
#define USB_USBLEGSUP_CAPABILITY_ID_SHIFT (0U)
#define USB_USBLEGSUP_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_CAPABILITY_ID_SHIFT)) & USB_USBLEGSUP_CAPABILITY_ID_MASK)
#define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
#define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT (8U)
#define USB_USBLEGSUP_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_USBLEGSUP_NEXT_CAPABILITY_POINTER_MASK)
#define USB_USBLEGSUP_HC_BIOS_OWNED_MASK (0x10000U)
#define USB_USBLEGSUP_HC_BIOS_OWNED_SHIFT (16U)
#define USB_USBLEGSUP_HC_BIOS_OWNED(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_HC_BIOS_OWNED_SHIFT)) & USB_USBLEGSUP_HC_BIOS_OWNED_MASK)
#define USB_USBLEGSUP_HC_OS_OWNED_MASK (0x1000000U)
#define USB_USBLEGSUP_HC_OS_OWNED_SHIFT (24U)
#define USB_USBLEGSUP_HC_OS_OWNED(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGSUP_HC_OS_OWNED_SHIFT)) & USB_USBLEGSUP_HC_OS_OWNED_MASK)
/*! @} */
/*! @name USBLEGCTLSTS - USBLEGCTLSTS */
/*! @{ */
#define USB_USBLEGCTLSTS_USB_SMI_ENABLE_MASK (0x1U)
#define USB_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT (0U)
#define USB_USBLEGCTLSTS_USB_SMI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_USB_SMI_ENABLE_SHIFT)) & USB_USBLEGCTLSTS_USB_SMI_ENABLE_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_HOST_E_MASK (0x10U)
#define USB_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT (4U)
#define USB_USBLEGCTLSTS_SMI_ON_HOST_E(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_HOST_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_HOST_E_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_OS_E_MASK (0x2000U)
#define USB_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT (13U)
#define USB_USBLEGCTLSTS_SMI_ON_OS_E(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_OS_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_OS_E_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_PCI_E_MASK (0x4000U)
#define USB_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT (14U)
#define USB_USBLEGCTLSTS_SMI_ON_PCI_E(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_PCI_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_PCI_E_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_BAR_E_MASK (0x8000U)
#define USB_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT (15U)
#define USB_USBLEGCTLSTS_SMI_ON_BAR_E(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_BAR_E_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_BAR_E_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_EVENT_MASK (0x10000U)
#define USB_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT (16U)
#define USB_USBLEGCTLSTS_SMI_ON_EVENT(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_EVENT_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_EVENT_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_HOST_MASK (0x100000U)
#define USB_USBLEGCTLSTS_SMI_ON_HOST_SHIFT (20U)
#define USB_USBLEGCTLSTS_SMI_ON_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_HOST_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_HOST_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_OS_MASK (0x20000000U)
#define USB_USBLEGCTLSTS_SMI_ON_OS_SHIFT (29U)
#define USB_USBLEGCTLSTS_SMI_ON_OS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_OS_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_OS_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_PCI_MASK (0x40000000U)
#define USB_USBLEGCTLSTS_SMI_ON_PCI_SHIFT (30U)
#define USB_USBLEGCTLSTS_SMI_ON_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_PCI_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_PCI_MASK)
#define USB_USBLEGCTLSTS_SMI_ON_BAR_MASK (0x80000000U)
#define USB_USBLEGCTLSTS_SMI_ON_BAR_SHIFT (31U)
#define USB_USBLEGCTLSTS_SMI_ON_BAR(x) (((uint32_t)(((uint32_t)(x)) << USB_USBLEGCTLSTS_SMI_ON_BAR_SHIFT)) & USB_USBLEGCTLSTS_SMI_ON_BAR_MASK)
/*! @} */
/*! @name SUPTPRT2_DW0 - SUPTPRT2_DW0 */
/*! @{ */
#define USB_SUPTPRT2_DW0_CAPABILITY_ID_MASK (0xFFU)
#define USB_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT (0U)
#define USB_SUPTPRT2_DW0_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_CAPABILITY_ID_SHIFT)) & USB_SUPTPRT2_DW0_CAPABILITY_ID_MASK)
#define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
#define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U)
#define USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_SUPTPRT2_DW0_NEXT_CAPABILITY_POINTER_MASK)
#define USB_SUPTPRT2_DW0_MINOR_REVISION_MASK (0xFF0000U)
#define USB_SUPTPRT2_DW0_MINOR_REVISION_SHIFT (16U)
#define USB_SUPTPRT2_DW0_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_MINOR_REVISION_SHIFT)) & USB_SUPTPRT2_DW0_MINOR_REVISION_MASK)
#define USB_SUPTPRT2_DW0_MAJOR_REVISION_MASK (0xFF000000U)
#define USB_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT (24U)
#define USB_SUPTPRT2_DW0_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW0_MAJOR_REVISION_SHIFT)) & USB_SUPTPRT2_DW0_MAJOR_REVISION_MASK)
/*! @} */
/*! @name SUPTPRT2_DW1 - SUPTPRT2_DW1 Register */
/*! @{ */
#define USB_SUPTPRT2_DW1_NAME_STRING_MASK (0xFFFFFFFFU)
#define USB_SUPTPRT2_DW1_NAME_STRING_SHIFT (0U)
#define USB_SUPTPRT2_DW1_NAME_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW1_NAME_STRING_SHIFT)) & USB_SUPTPRT2_DW1_NAME_STRING_MASK)
/*! @} */
/*! @name SUPTPRT2_DW2 - xHCI Supported Protocol Capability_ Data Word 2 */
/*! @{ */
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU)
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U)
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB_SUPTPRT2_DW2_COMPATIBLE_PORT_OFFSET_MASK)
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U)
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U)
#define USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB_SUPTPRT2_DW2_COMPATIBLE_PORT_COUNT_MASK)
#define USB_SUPTPRT2_DW2_HSO_MASK (0x20000U)
#define USB_SUPTPRT2_DW2_HSO_SHIFT (17U)
#define USB_SUPTPRT2_DW2_HSO(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_HSO_SHIFT)) & USB_SUPTPRT2_DW2_HSO_MASK)
#define USB_SUPTPRT2_DW2_IHI_MASK (0x40000U)
#define USB_SUPTPRT2_DW2_IHI_SHIFT (18U)
#define USB_SUPTPRT2_DW2_IHI(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_IHI_SHIFT)) & USB_SUPTPRT2_DW2_IHI_MASK)
#define USB_SUPTPRT2_DW2_HLC_MASK (0x80000U)
#define USB_SUPTPRT2_DW2_HLC_SHIFT (19U)
#define USB_SUPTPRT2_DW2_HLC(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_HLC_SHIFT)) & USB_SUPTPRT2_DW2_HLC_MASK)
#define USB_SUPTPRT2_DW2_BLC_MASK (0x100000U)
#define USB_SUPTPRT2_DW2_BLC_SHIFT (20U)
/*! BLC - BESL LPM Capability
*/
#define USB_SUPTPRT2_DW2_BLC(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_BLC_SHIFT)) & USB_SUPTPRT2_DW2_BLC_MASK)
#define USB_SUPTPRT2_DW2_MHD_MASK (0xE000000U)
#define USB_SUPTPRT2_DW2_MHD_SHIFT (25U)
/*! MHD - Hub Depth
*/
#define USB_SUPTPRT2_DW2_MHD(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_MHD_SHIFT)) & USB_SUPTPRT2_DW2_MHD_MASK)
#define USB_SUPTPRT2_DW2_PSIC_MASK (0xF0000000U)
#define USB_SUPTPRT2_DW2_PSIC_SHIFT (28U)
#define USB_SUPTPRT2_DW2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW2_PSIC_SHIFT)) & USB_SUPTPRT2_DW2_PSIC_MASK)
/*! @} */
/*! @name SUPTPRT2_DW3 - SUPTPRT2_DW3 Register */
/*! @{ */
#define USB_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK (0x1FU)
#define USB_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT (0U)
#define USB_SUPTPRT2_DW3_PROTCL_SLT_TY(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT2_DW3_PROTCL_SLT_TY_SHIFT)) & USB_SUPTPRT2_DW3_PROTCL_SLT_TY_MASK)
/*! @} */
/*! @name SUPTPRT3_DW0 - */
/*! @{ */
#define USB_SUPTPRT3_DW0_CAPABILITY_ID_MASK (0xFFU)
#define USB_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT (0U)
#define USB_SUPTPRT3_DW0_CAPABILITY_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_CAPABILITY_ID_SHIFT)) & USB_SUPTPRT3_DW0_CAPABILITY_ID_MASK)
#define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK (0xFF00U)
#define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT (8U)
#define USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_SHIFT)) & USB_SUPTPRT3_DW0_NEXT_CAPABILITY_POINTER_MASK)
#define USB_SUPTPRT3_DW0_MINOR_REVISION_MASK (0xFF0000U)
#define USB_SUPTPRT3_DW0_MINOR_REVISION_SHIFT (16U)
#define USB_SUPTPRT3_DW0_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_MINOR_REVISION_SHIFT)) & USB_SUPTPRT3_DW0_MINOR_REVISION_MASK)
#define USB_SUPTPRT3_DW0_MAJOR_REVISION_MASK (0xFF000000U)
#define USB_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT (24U)
#define USB_SUPTPRT3_DW0_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW0_MAJOR_REVISION_SHIFT)) & USB_SUPTPRT3_DW0_MAJOR_REVISION_MASK)
/*! @} */
/*! @name SUPTPRT3_DW1 - SUPTPRT3_DW1 Register */
/*! @{ */
#define USB_SUPTPRT3_DW1_NAME_STRING_MASK (0xFFFFFFFFU)
#define USB_SUPTPRT3_DW1_NAME_STRING_SHIFT (0U)
/*! NAME_STRING - NAME_STRING
*/
#define USB_SUPTPRT3_DW1_NAME_STRING(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW1_NAME_STRING_SHIFT)) & USB_SUPTPRT3_DW1_NAME_STRING_MASK)
/*! @} */
/*! @name SUPTPRT3_DW2 - SUPTPRT3_DW2 */
/*! @{ */
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK (0xFFU)
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT (0U)
/*! COMPATIBLE_PORT_OFFSET - COMPATIBLE_PORT_OFFSET
*/
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_SHIFT)) & USB_SUPTPRT3_DW2_COMPATIBLE_PORT_OFFSET_MASK)
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK (0xFF00U)
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT (8U)
/*! COMPATIBLE_PORT_COUNT - COMPATIBLE_PORT_COUNT
*/
#define USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_SHIFT)) & USB_SUPTPRT3_DW2_COMPATIBLE_PORT_COUNT_MASK)
#define USB_SUPTPRT3_DW2_MHD_MASK (0xE000000U)
#define USB_SUPTPRT3_DW2_MHD_SHIFT (25U)
/*! MHD - Hub Depth
*/
#define USB_SUPTPRT3_DW2_MHD(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_MHD_SHIFT)) & USB_SUPTPRT3_DW2_MHD_MASK)
#define USB_SUPTPRT3_DW2_PSIC_MASK (0xF0000000U)
#define USB_SUPTPRT3_DW2_PSIC_SHIFT (28U)
#define USB_SUPTPRT3_DW2_PSIC(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW2_PSIC_SHIFT)) & USB_SUPTPRT3_DW2_PSIC_MASK)
/*! @} */
/*! @name SUPTPRT3_DW3 - SUPTPRT3_DW3 */
/*! @{ */
#define USB_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK (0x1FU)
#define USB_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT (0U)
/*! PROTCL_SLT_TY - Protocol Slot Type
*/
#define USB_SUPTPRT3_DW3_PROTCL_SLT_TY(x) (((uint32_t)(((uint32_t)(x)) << USB_SUPTPRT3_DW3_PROTCL_SLT_TY_SHIFT)) & USB_SUPTPRT3_DW3_PROTCL_SLT_TY_MASK)
/*! @} */
/*! @name GSBUSCFG0 - Global SoC Bus Configuration Register 0 */
/*! @{ */
#define USB_GSBUSCFG0_INCRBRSTENA_MASK (0x1U)
#define USB_GSBUSCFG0_INCRBRSTENA_SHIFT (0U)
/*! INCRBRSTENA - INCRBRSTENA
*/
#define USB_GSBUSCFG0_INCRBRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCRBRSTENA_SHIFT)) & USB_GSBUSCFG0_INCRBRSTENA_MASK)
#define USB_GSBUSCFG0_INCR4BRSTENA_MASK (0x2U)
#define USB_GSBUSCFG0_INCR4BRSTENA_SHIFT (1U)
/*! INCR4BRSTENA - INCR4BRSTENA
*/
#define USB_GSBUSCFG0_INCR4BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR4BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR4BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR8BRSTENA_MASK (0x4U)
#define USB_GSBUSCFG0_INCR8BRSTENA_SHIFT (2U)
/*! INCR8BRSTENA - INCR8BRSTENA
*/
#define USB_GSBUSCFG0_INCR8BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR8BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR8BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR16BRSTENA_MASK (0x8U)
#define USB_GSBUSCFG0_INCR16BRSTENA_SHIFT (3U)
/*! INCR16BRSTENA - INCR16BRSTENA
*/
#define USB_GSBUSCFG0_INCR16BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR16BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR16BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR32BRSTENA_MASK (0x10U)
#define USB_GSBUSCFG0_INCR32BRSTENA_SHIFT (4U)
/*! INCR32BRSTENA - INCR32BRSTENA
*/
#define USB_GSBUSCFG0_INCR32BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR32BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR32BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR64BRSTENA_MASK (0x20U)
#define USB_GSBUSCFG0_INCR64BRSTENA_SHIFT (5U)
#define USB_GSBUSCFG0_INCR64BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR64BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR64BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR128BRSTENA_MASK (0x40U)
#define USB_GSBUSCFG0_INCR128BRSTENA_SHIFT (6U)
#define USB_GSBUSCFG0_INCR128BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR128BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR128BRSTENA_MASK)
#define USB_GSBUSCFG0_INCR256BRSTENA_MASK (0x80U)
#define USB_GSBUSCFG0_INCR256BRSTENA_SHIFT (7U)
#define USB_GSBUSCFG0_INCR256BRSTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_INCR256BRSTENA_SHIFT)) & USB_GSBUSCFG0_INCR256BRSTENA_MASK)
#define USB_GSBUSCFG0_DESBIGEND_MASK (0x400U)
#define USB_GSBUSCFG0_DESBIGEND_SHIFT (10U)
#define USB_GSBUSCFG0_DESBIGEND(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESBIGEND_SHIFT)) & USB_GSBUSCFG0_DESBIGEND_MASK)
#define USB_GSBUSCFG0_DATBIGEND_MASK (0x800U)
#define USB_GSBUSCFG0_DATBIGEND_SHIFT (11U)
#define USB_GSBUSCFG0_DATBIGEND(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATBIGEND_SHIFT)) & USB_GSBUSCFG0_DATBIGEND_MASK)
#define USB_GSBUSCFG0_DESWRREQINFO_MASK (0xF0000U)
#define USB_GSBUSCFG0_DESWRREQINFO_SHIFT (16U)
#define USB_GSBUSCFG0_DESWRREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESWRREQINFO_SHIFT)) & USB_GSBUSCFG0_DESWRREQINFO_MASK)
#define USB_GSBUSCFG0_DATWRREQINFO_MASK (0xF00000U)
#define USB_GSBUSCFG0_DATWRREQINFO_SHIFT (20U)
#define USB_GSBUSCFG0_DATWRREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATWRREQINFO_SHIFT)) & USB_GSBUSCFG0_DATWRREQINFO_MASK)
#define USB_GSBUSCFG0_DESRDREQINFO_MASK (0xF000000U)
#define USB_GSBUSCFG0_DESRDREQINFO_SHIFT (24U)
#define USB_GSBUSCFG0_DESRDREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DESRDREQINFO_SHIFT)) & USB_GSBUSCFG0_DESRDREQINFO_MASK)
#define USB_GSBUSCFG0_DATRDREQINFO_MASK (0xF0000000U)
#define USB_GSBUSCFG0_DATRDREQINFO_SHIFT (28U)
#define USB_GSBUSCFG0_DATRDREQINFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG0_DATRDREQINFO_SHIFT)) & USB_GSBUSCFG0_DATRDREQINFO_MASK)
/*! @} */
/*! @name GSBUSCFG1 - Global SoC Bus Configuration Register 1 */
/*! @{ */
#define USB_GSBUSCFG1_PIPETRANSLIMIT_MASK (0xF00U)
#define USB_GSBUSCFG1_PIPETRANSLIMIT_SHIFT (8U)
#define USB_GSBUSCFG1_PIPETRANSLIMIT(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG1_PIPETRANSLIMIT_SHIFT)) & USB_GSBUSCFG1_PIPETRANSLIMIT_MASK)
#define USB_GSBUSCFG1_EN1KPAGE_MASK (0x1000U)
#define USB_GSBUSCFG1_EN1KPAGE_SHIFT (12U)
#define USB_GSBUSCFG1_EN1KPAGE(x) (((uint32_t)(((uint32_t)(x)) << USB_GSBUSCFG1_EN1KPAGE_SHIFT)) & USB_GSBUSCFG1_EN1KPAGE_MASK)
/*! @} */
/*! @name GTXTHRCFG - Global Tx Threshold Control Register */
/*! @{ */
#define USB_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK (0xFF0000U)
#define USB_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT (16U)
#define USB_GTXTHRCFG_USBMAXTXBURSTSIZE(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBMAXTXBURSTSIZE_SHIFT)) & USB_GTXTHRCFG_USBMAXTXBURSTSIZE_MASK)
#define USB_GTXTHRCFG_USBTXPKTCNT_MASK (0xF000000U)
#define USB_GTXTHRCFG_USBTXPKTCNT_SHIFT (24U)
#define USB_GTXTHRCFG_USBTXPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBTXPKTCNT_SHIFT)) & USB_GTXTHRCFG_USBTXPKTCNT_MASK)
#define USB_GTXTHRCFG_USBTXPKTCNTSEL_MASK (0x20000000U)
#define USB_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT (29U)
#define USB_GTXTHRCFG_USBTXPKTCNTSEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXTHRCFG_USBTXPKTCNTSEL_SHIFT)) & USB_GTXTHRCFG_USBTXPKTCNTSEL_MASK)
/*! @} */
/*! @name GRXTHRCFG - Global Rx Threshold Control Register */
/*! @{ */
#define USB_GRXTHRCFG_RESVISOCOUTSPC_MASK (0x1FFFU)
#define USB_GRXTHRCFG_RESVISOCOUTSPC_SHIFT (0U)
#define USB_GRXTHRCFG_RESVISOCOUTSPC(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_RESVISOCOUTSPC_SHIFT)) & USB_GRXTHRCFG_RESVISOCOUTSPC_MASK)
#define USB_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK (0xF80000U)
#define USB_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT (19U)
#define USB_GRXTHRCFG_USBMAXRXBURSTSIZE(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT)) & USB_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK)
#define USB_GRXTHRCFG_USBRXPKTCNT_MASK (0xF000000U)
#define USB_GRXTHRCFG_USBRXPKTCNT_SHIFT (24U)
#define USB_GRXTHRCFG_USBRXPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBRXPKTCNT_SHIFT)) & USB_GRXTHRCFG_USBRXPKTCNT_MASK)
#define USB_GRXTHRCFG_USBRXPKTCNTSEL_MASK (0x20000000U)
#define USB_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT (29U)
#define USB_GRXTHRCFG_USBRXPKTCNTSEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXTHRCFG_USBRXPKTCNTSEL_SHIFT)) & USB_GRXTHRCFG_USBRXPKTCNTSEL_MASK)
/*! @} */
/*! @name GCTL - Global Core Control Register */
/*! @{ */
#define USB_GCTL_DSBLCLKGTNG_MASK (0x1U)
#define USB_GCTL_DSBLCLKGTNG_SHIFT (0U)
#define USB_GCTL_DSBLCLKGTNG(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DSBLCLKGTNG_SHIFT)) & USB_GCTL_DSBLCLKGTNG_MASK)
#define USB_GCTL_GBLHIBERNATIONEN_MASK (0x2U)
#define USB_GCTL_GBLHIBERNATIONEN_SHIFT (1U)
#define USB_GCTL_GBLHIBERNATIONEN(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_GBLHIBERNATIONEN_SHIFT)) & USB_GCTL_GBLHIBERNATIONEN_MASK)
#define USB_GCTL_U2EXIT_LFPS_MASK (0x4U)
#define USB_GCTL_U2EXIT_LFPS_SHIFT (2U)
#define USB_GCTL_U2EXIT_LFPS(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U2EXIT_LFPS_SHIFT)) & USB_GCTL_U2EXIT_LFPS_MASK)
#define USB_GCTL_DISSCRAMBLE_MASK (0x8U)
#define USB_GCTL_DISSCRAMBLE_SHIFT (3U)
#define USB_GCTL_DISSCRAMBLE(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DISSCRAMBLE_SHIFT)) & USB_GCTL_DISSCRAMBLE_MASK)
#define USB_GCTL_SCALEDOWN_MASK (0x30U)
#define USB_GCTL_SCALEDOWN_SHIFT (4U)
#define USB_GCTL_SCALEDOWN(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_SCALEDOWN_SHIFT)) & USB_GCTL_SCALEDOWN_MASK)
#define USB_GCTL_RAMCLKSEL_MASK (0xC0U)
#define USB_GCTL_RAMCLKSEL_SHIFT (6U)
#define USB_GCTL_RAMCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_RAMCLKSEL_SHIFT)) & USB_GCTL_RAMCLKSEL_MASK)
#define USB_GCTL_DEBUGATTACH_MASK (0x100U)
#define USB_GCTL_DEBUGATTACH_SHIFT (8U)
#define USB_GCTL_DEBUGATTACH(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_DEBUGATTACH_SHIFT)) & USB_GCTL_DEBUGATTACH_MASK)
#define USB_GCTL_U1U2TIMERSCALE_MASK (0x200U)
#define USB_GCTL_U1U2TIMERSCALE_SHIFT (9U)
#define USB_GCTL_U1U2TIMERSCALE(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U1U2TIMERSCALE_SHIFT)) & USB_GCTL_U1U2TIMERSCALE_MASK)
#define USB_GCTL_SOFITPSYNC_MASK (0x400U)
#define USB_GCTL_SOFITPSYNC_SHIFT (10U)
#define USB_GCTL_SOFITPSYNC(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_SOFITPSYNC_SHIFT)) & USB_GCTL_SOFITPSYNC_MASK)
#define USB_GCTL_CORESOFTRESET_MASK (0x800U)
#define USB_GCTL_CORESOFTRESET_SHIFT (11U)
#define USB_GCTL_CORESOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_CORESOFTRESET_SHIFT)) & USB_GCTL_CORESOFTRESET_MASK)
#define USB_GCTL_PRTCAPDIR_MASK (0x3000U)
#define USB_GCTL_PRTCAPDIR_SHIFT (12U)
#define USB_GCTL_PRTCAPDIR(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_PRTCAPDIR_SHIFT)) & USB_GCTL_PRTCAPDIR_MASK)
#define USB_GCTL_FRMSCLDWN_MASK (0xC000U)
#define USB_GCTL_FRMSCLDWN_SHIFT (14U)
#define USB_GCTL_FRMSCLDWN(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_FRMSCLDWN_SHIFT)) & USB_GCTL_FRMSCLDWN_MASK)
#define USB_GCTL_U2RSTECN_MASK (0x10000U)
#define USB_GCTL_U2RSTECN_SHIFT (16U)
#define USB_GCTL_U2RSTECN(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_U2RSTECN_SHIFT)) & USB_GCTL_U2RSTECN_MASK)
#define USB_GCTL_BYPSSETADDR_MASK (0x20000U)
#define USB_GCTL_BYPSSETADDR_SHIFT (17U)
#define USB_GCTL_BYPSSETADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_BYPSSETADDR_SHIFT)) & USB_GCTL_BYPSSETADDR_MASK)
#define USB_GCTL_MASTERFILTBYPASS_MASK (0x40000U)
#define USB_GCTL_MASTERFILTBYPASS_SHIFT (18U)
#define USB_GCTL_MASTERFILTBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_MASTERFILTBYPASS_SHIFT)) & USB_GCTL_MASTERFILTBYPASS_MASK)
#define USB_GCTL_PWRDNSCALE_MASK (0xFFF80000U)
#define USB_GCTL_PWRDNSCALE_SHIFT (19U)
#define USB_GCTL_PWRDNSCALE(x) (((uint32_t)(((uint32_t)(x)) << USB_GCTL_PWRDNSCALE_SHIFT)) & USB_GCTL_PWRDNSCALE_MASK)
/*! @} */
/*! @name GSTS - Global Status Register */
/*! @{ */
#define USB_GSTS_CURMOD_MASK (0x3U)
#define USB_GSTS_CURMOD_SHIFT (0U)
#define USB_GSTS_CURMOD(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CURMOD_SHIFT)) & USB_GSTS_CURMOD_MASK)
#define USB_GSTS_BUSERRADDRVLD_MASK (0x10U)
#define USB_GSTS_BUSERRADDRVLD_SHIFT (4U)
#define USB_GSTS_BUSERRADDRVLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_BUSERRADDRVLD_SHIFT)) & USB_GSTS_BUSERRADDRVLD_MASK)
#define USB_GSTS_CSRTIMEOUT_MASK (0x20U)
#define USB_GSTS_CSRTIMEOUT_SHIFT (5U)
#define USB_GSTS_CSRTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CSRTIMEOUT_SHIFT)) & USB_GSTS_CSRTIMEOUT_MASK)
#define USB_GSTS_DEVICE_IP_MASK (0x40U)
#define USB_GSTS_DEVICE_IP_SHIFT (6U)
#define USB_GSTS_DEVICE_IP(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_DEVICE_IP_SHIFT)) & USB_GSTS_DEVICE_IP_MASK)
#define USB_GSTS_HOST_IP_MASK (0x80U)
#define USB_GSTS_HOST_IP_SHIFT (7U)
#define USB_GSTS_HOST_IP(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_HOST_IP_SHIFT)) & USB_GSTS_HOST_IP_MASK)
#define USB_GSTS_BC_IP_MASK (0x200U)
#define USB_GSTS_BC_IP_SHIFT (9U)
#define USB_GSTS_BC_IP(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_BC_IP_SHIFT)) & USB_GSTS_BC_IP_MASK)
#define USB_GSTS_SSIC_IP_MASK (0x800U)
#define USB_GSTS_SSIC_IP_SHIFT (11U)
#define USB_GSTS_SSIC_IP(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_SSIC_IP_SHIFT)) & USB_GSTS_SSIC_IP_MASK)
#define USB_GSTS_CBELT_MASK (0xFFF00000U)
#define USB_GSTS_CBELT_SHIFT (20U)
#define USB_GSTS_CBELT(x) (((uint32_t)(((uint32_t)(x)) << USB_GSTS_CBELT_SHIFT)) & USB_GSTS_CBELT_MASK)
/*! @} */
/*! @name GUCTL1 - */
/*! @{ */
#define USB_GUCTL1_LOA_FILTER_EN_MASK (0x1U)
#define USB_GUCTL1_LOA_FILTER_EN_SHIFT (0U)
#define USB_GUCTL1_LOA_FILTER_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_LOA_FILTER_EN_SHIFT)) & USB_GUCTL1_LOA_FILTER_EN_MASK)
#define USB_GUCTL1_OVRLD_L1_SUSP_COM_MASK (0x2U)
#define USB_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT (1U)
#define USB_GUCTL1_OVRLD_L1_SUSP_COM(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_OVRLD_L1_SUSP_COM_SHIFT)) & USB_GUCTL1_OVRLD_L1_SUSP_COM_MASK)
#define USB_GUCTL1_HC_PARCHK_DISABLE_MASK (0x4U)
#define USB_GUCTL1_HC_PARCHK_DISABLE_SHIFT (2U)
#define USB_GUCTL1_HC_PARCHK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_HC_PARCHK_DISABLE_SHIFT)) & USB_GUCTL1_HC_PARCHK_DISABLE_MASK)
#define USB_GUCTL1_HC_ERRATA_ENABLE_MASK (0x8U)
#define USB_GUCTL1_HC_ERRATA_ENABLE_SHIFT (3U)
#define USB_GUCTL1_HC_ERRATA_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_HC_ERRATA_ENABLE_SHIFT)) & USB_GUCTL1_HC_ERRATA_ENABLE_MASK)
#define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK (0xF0U)
#define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT (4U)
#define USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_SHIFT)) & USB_GUCTL1_L1_SUSP_THRLD_FOR_HOST_MASK)
#define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK (0x100U)
#define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT (8U)
#define USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_SHIFT)) & USB_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST_MASK)
#define USB_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK (0x200U)
#define USB_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT (9U)
#define USB_GUCTL1_DEV_HS_NYET_BULK_SPR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_HS_NYET_BULK_SPR_SHIFT)) & USB_GUCTL1_DEV_HS_NYET_BULK_SPR_MASK)
#define USB_GUCTL1_RESUME_OPMODE_HS_HOST_MASK (0x400U)
#define USB_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT (10U)
#define USB_GUCTL1_RESUME_OPMODE_HS_HOST(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_RESUME_OPMODE_HS_HOST_SHIFT)) & USB_GUCTL1_RESUME_OPMODE_HS_HOST_MASK)
#define USB_GUCTL1_PARKMODE_DISABLE_FSLS_MASK (0x8000U)
#define USB_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT (15U)
#define USB_GUCTL1_PARKMODE_DISABLE_FSLS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_FSLS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_FSLS_MASK)
#define USB_GUCTL1_PARKMODE_DISABLE_HS_MASK (0x10000U)
#define USB_GUCTL1_PARKMODE_DISABLE_HS_SHIFT (16U)
#define USB_GUCTL1_PARKMODE_DISABLE_HS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_HS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_HS_MASK)
#define USB_GUCTL1_PARKMODE_DISABLE_SS_MASK (0x20000U)
#define USB_GUCTL1_PARKMODE_DISABLE_SS_SHIFT (17U)
#define USB_GUCTL1_PARKMODE_DISABLE_SS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_PARKMODE_DISABLE_SS_SHIFT)) & USB_GUCTL1_PARKMODE_DISABLE_SS_MASK)
#define USB_GUCTL1_NAK_PER_ENH_HS_MASK (0x40000U)
#define USB_GUCTL1_NAK_PER_ENH_HS_SHIFT (18U)
#define USB_GUCTL1_NAK_PER_ENH_HS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_NAK_PER_ENH_HS_SHIFT)) & USB_GUCTL1_NAK_PER_ENH_HS_MASK)
#define USB_GUCTL1_NAK_PER_ENH_FS_MASK (0x80000U)
#define USB_GUCTL1_NAK_PER_ENH_FS_SHIFT (19U)
#define USB_GUCTL1_NAK_PER_ENH_FS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_NAK_PER_ENH_FS_SHIFT)) & USB_GUCTL1_NAK_PER_ENH_FS_MASK)
#define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK (0x100000U)
#define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT (20U)
#define USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_SHIFT)) & USB_GUCTL1_DEV_LSP_TAIL_LOCK_DIS_MASK)
#define USB_GUCTL1_IP_GAP_ADD_ON_MASK (0xE00000U)
#define USB_GUCTL1_IP_GAP_ADD_ON_SHIFT (21U)
#define USB_GUCTL1_IP_GAP_ADD_ON(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_IP_GAP_ADD_ON_SHIFT)) & USB_GUCTL1_IP_GAP_ADD_ON_MASK)
#define USB_GUCTL1_DEV_L1_EXIT_BY_HW_MASK (0x1000000U)
#define USB_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT (24U)
#define USB_GUCTL1_DEV_L1_EXIT_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_L1_EXIT_BY_HW_SHIFT)) & USB_GUCTL1_DEV_L1_EXIT_BY_HW_MASK)
#define USB_GUCTL1_P3_IN_U2_MASK (0x2000000U)
#define USB_GUCTL1_P3_IN_U2_SHIFT (25U)
#define USB_GUCTL1_P3_IN_U2(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_P3_IN_U2_SHIFT)) & USB_GUCTL1_P3_IN_U2_MASK)
#define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK (0x4000000U)
#define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT (26U)
#define USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_SHIFT)) & USB_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK_MASK)
#define USB_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK (0x8000000U)
#define USB_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT (27U)
#define USB_GUCTL1_DEV_TRB_OUT_SPR_IND(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_TRB_OUT_SPR_IND_SHIFT)) & USB_GUCTL1_DEV_TRB_OUT_SPR_IND_MASK)
#define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK (0x10000000U)
#define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT (28U)
#define USB_GUCTL1_TX_IPGAP_LINECHECK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_SHIFT)) & USB_GUCTL1_TX_IPGAP_LINECHECK_DIS_MASK)
#define USB_GUCTL1_FILTER_SE0_FSLS_EOP_MASK (0x20000000U)
#define USB_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT (29U)
#define USB_GUCTL1_FILTER_SE0_FSLS_EOP(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_FILTER_SE0_FSLS_EOP_SHIFT)) & USB_GUCTL1_FILTER_SE0_FSLS_EOP_MASK)
#define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK (0x40000000U)
#define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT (30U)
#define USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_SHIFT)) & USB_GUCTL1_DS_RXDET_MAX_TOUT_CTRL_MASK)
#define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK (0x80000000U)
#define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT (31U)
#define USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_SHIFT)) & USB_GUCTL1_DEV_DECOUPLE_L1L2_EVT_MASK)
/*! @} */
/*! @name GUID - Global User ID Register */
/*! @{ */
#define USB_GUID_USERID_MASK (0xFFFFFFFFU)
#define USB_GUID_USERID_SHIFT (0U)
#define USB_GUID_USERID(x) (((uint32_t)(((uint32_t)(x)) << USB_GUID_USERID_SHIFT)) & USB_GUID_USERID_MASK)
/*! @} */
/*! @name GUCTL - Global User Control Register */
/*! @{ */
#define USB_GUCTL_DTFT_MASK (0x1FFU)
#define USB_GUCTL_DTFT_SHIFT (0U)
#define USB_GUCTL_DTFT(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_DTFT_SHIFT)) & USB_GUCTL_DTFT_MASK)
#define USB_GUCTL_DTCT_MASK (0x600U)
#define USB_GUCTL_DTCT_SHIFT (9U)
#define USB_GUCTL_DTCT(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_DTCT_SHIFT)) & USB_GUCTL_DTCT_MASK)
#define USB_GUCTL_INSRTEXTRFSBODI_MASK (0x800U)
#define USB_GUCTL_INSRTEXTRFSBODI_SHIFT (11U)
#define USB_GUCTL_INSRTEXTRFSBODI(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_INSRTEXTRFSBODI_SHIFT)) & USB_GUCTL_INSRTEXTRFSBODI_MASK)
#define USB_GUCTL_EXTCAPSUPPTEN_MASK (0x1000U)
#define USB_GUCTL_EXTCAPSUPPTEN_SHIFT (12U)
#define USB_GUCTL_EXTCAPSUPPTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_EXTCAPSUPPTEN_SHIFT)) & USB_GUCTL_EXTCAPSUPPTEN_MASK)
#define USB_GUCTL_ENOVERLAPCHK_MASK (0x2000U)
#define USB_GUCTL_ENOVERLAPCHK_SHIFT (13U)
#define USB_GUCTL_ENOVERLAPCHK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_ENOVERLAPCHK_SHIFT)) & USB_GUCTL_ENOVERLAPCHK_MASK)
#define USB_GUCTL_USBHSTINAUTORETRYEN_MASK (0x4000U)
#define USB_GUCTL_USBHSTINAUTORETRYEN_SHIFT (14U)
#define USB_GUCTL_USBHSTINAUTORETRYEN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_USBHSTINAUTORETRYEN_SHIFT)) & USB_GUCTL_USBHSTINAUTORETRYEN_MASK)
#define USB_GUCTL_RESBWHSEPS_MASK (0x10000U)
#define USB_GUCTL_RESBWHSEPS_SHIFT (16U)
#define USB_GUCTL_RESBWHSEPS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_RESBWHSEPS_SHIFT)) & USB_GUCTL_RESBWHSEPS_MASK)
#define USB_GUCTL_SPRSCTRLTRANSEN_MASK (0x20000U)
#define USB_GUCTL_SPRSCTRLTRANSEN_SHIFT (17U)
#define USB_GUCTL_SPRSCTRLTRANSEN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_SPRSCTRLTRANSEN_SHIFT)) & USB_GUCTL_SPRSCTRLTRANSEN_MASK)
#define USB_GUCTL_NOEXTRDL_MASK (0x200000U)
#define USB_GUCTL_NOEXTRDL_SHIFT (21U)
#define USB_GUCTL_NOEXTRDL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_NOEXTRDL_SHIFT)) & USB_GUCTL_NOEXTRDL_MASK)
#define USB_GUCTL_REFCLKPER_MASK (0xFFC00000U)
#define USB_GUCTL_REFCLKPER_SHIFT (22U)
#define USB_GUCTL_REFCLKPER(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL_REFCLKPER_SHIFT)) & USB_GUCTL_REFCLKPER_MASK)
/*! @} */
/*! @name GBUSERRADDRLO - Gobal SoC Bus Error Address Register - Low */
/*! @{ */
#define USB_GBUSERRADDRLO_BUSERRADDR_MASK (0xFFFFFFFFU)
#define USB_GBUSERRADDRLO_BUSERRADDR_SHIFT (0U)
#define USB_GBUSERRADDRLO_BUSERRADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_GBUSERRADDRLO_BUSERRADDR_SHIFT)) & USB_GBUSERRADDRLO_BUSERRADDR_MASK)
/*! @} */
/*! @name GBUSERRADDRHI - Gobal SoC Bus Error Address Register - High */
/*! @{ */
#define USB_GBUSERRADDRHI_BUSERRADDR_MASK (0xFFFFFFFFU)
#define USB_GBUSERRADDRHI_BUSERRADDR_SHIFT (0U)
#define USB_GBUSERRADDRHI_BUSERRADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_GBUSERRADDRHI_BUSERRADDR_SHIFT)) & USB_GBUSERRADDRHI_BUSERRADDR_MASK)
/*! @} */
/*! @name GPRTBIMAPLO - Global SS Port to Bus Instance Mapping Register - Low */
/*! @{ */
#define USB_GPRTBIMAPLO_BINUM1_MASK (0xFU)
#define USB_GPRTBIMAPLO_BINUM1_SHIFT (0U)
#define USB_GPRTBIMAPLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM1_SHIFT)) & USB_GPRTBIMAPLO_BINUM1_MASK)
#define USB_GPRTBIMAPLO_BINUM2_MASK (0xF0U)
#define USB_GPRTBIMAPLO_BINUM2_SHIFT (4U)
#define USB_GPRTBIMAPLO_BINUM2(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM2_SHIFT)) & USB_GPRTBIMAPLO_BINUM2_MASK)
#define USB_GPRTBIMAPLO_BINUM3_MASK (0xF00U)
#define USB_GPRTBIMAPLO_BINUM3_SHIFT (8U)
#define USB_GPRTBIMAPLO_BINUM3(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM3_SHIFT)) & USB_GPRTBIMAPLO_BINUM3_MASK)
#define USB_GPRTBIMAPLO_BINUM4_MASK (0xF000U)
#define USB_GPRTBIMAPLO_BINUM4_SHIFT (12U)
#define USB_GPRTBIMAPLO_BINUM4(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM4_SHIFT)) & USB_GPRTBIMAPLO_BINUM4_MASK)
#define USB_GPRTBIMAPLO_BINUM5_MASK (0xF0000U)
#define USB_GPRTBIMAPLO_BINUM5_SHIFT (16U)
#define USB_GPRTBIMAPLO_BINUM5(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM5_SHIFT)) & USB_GPRTBIMAPLO_BINUM5_MASK)
#define USB_GPRTBIMAPLO_BINUM6_MASK (0xF00000U)
#define USB_GPRTBIMAPLO_BINUM6_SHIFT (20U)
#define USB_GPRTBIMAPLO_BINUM6(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM6_SHIFT)) & USB_GPRTBIMAPLO_BINUM6_MASK)
#define USB_GPRTBIMAPLO_BINUM7_MASK (0xF000000U)
#define USB_GPRTBIMAPLO_BINUM7_SHIFT (24U)
#define USB_GPRTBIMAPLO_BINUM7(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM7_SHIFT)) & USB_GPRTBIMAPLO_BINUM7_MASK)
#define USB_GPRTBIMAPLO_BINUM8_MASK (0xF0000000U)
#define USB_GPRTBIMAPLO_BINUM8_SHIFT (28U)
#define USB_GPRTBIMAPLO_BINUM8(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPLO_BINUM8_SHIFT)) & USB_GPRTBIMAPLO_BINUM8_MASK)
/*! @} */
/*! @name GPRTBIMAPHI - Global SS Port to Bus Instance Mapping Register - High */
/*! @{ */
#define USB_GPRTBIMAPHI_BINUM9_MASK (0xFU)
#define USB_GPRTBIMAPHI_BINUM9_SHIFT (0U)
#define USB_GPRTBIMAPHI_BINUM9(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM9_SHIFT)) & USB_GPRTBIMAPHI_BINUM9_MASK)
#define USB_GPRTBIMAPHI_BINUM10_MASK (0xF0U)
#define USB_GPRTBIMAPHI_BINUM10_SHIFT (4U)
#define USB_GPRTBIMAPHI_BINUM10(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM10_SHIFT)) & USB_GPRTBIMAPHI_BINUM10_MASK)
#define USB_GPRTBIMAPHI_BINUM11_MASK (0xF00U)
#define USB_GPRTBIMAPHI_BINUM11_SHIFT (8U)
#define USB_GPRTBIMAPHI_BINUM11(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM11_SHIFT)) & USB_GPRTBIMAPHI_BINUM11_MASK)
#define USB_GPRTBIMAPHI_BINUM12_MASK (0xF000U)
#define USB_GPRTBIMAPHI_BINUM12_SHIFT (12U)
#define USB_GPRTBIMAPHI_BINUM12(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM12_SHIFT)) & USB_GPRTBIMAPHI_BINUM12_MASK)
#define USB_GPRTBIMAPHI_BINUM13_MASK (0xF0000U)
#define USB_GPRTBIMAPHI_BINUM13_SHIFT (16U)
#define USB_GPRTBIMAPHI_BINUM13(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM13_SHIFT)) & USB_GPRTBIMAPHI_BINUM13_MASK)
#define USB_GPRTBIMAPHI_BINUM14_MASK (0xF00000U)
#define USB_GPRTBIMAPHI_BINUM14_SHIFT (20U)
#define USB_GPRTBIMAPHI_BINUM14(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM14_SHIFT)) & USB_GPRTBIMAPHI_BINUM14_MASK)
#define USB_GPRTBIMAPHI_BINUM15_MASK (0xF000000U)
#define USB_GPRTBIMAPHI_BINUM15_SHIFT (24U)
#define USB_GPRTBIMAPHI_BINUM15(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAPHI_BINUM15_SHIFT)) & USB_GPRTBIMAPHI_BINUM15_MASK)
/*! @} */
/*! @name GHWPARAMS0 - Global Hardware Parameters Register 0 */
/*! @{ */
#define USB_GHWPARAMS0_GHWPARAMS0_2_0_MASK (0x7U)
#define USB_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT (0U)
#define USB_GHWPARAMS0_GHWPARAMS0_2_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_2_0_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_2_0_MASK)
#define USB_GHWPARAMS0_GHWPARAMS0_5_3_MASK (0x38U)
#define USB_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT (3U)
#define USB_GHWPARAMS0_GHWPARAMS0_5_3(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_5_3_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_5_3_MASK)
#define USB_GHWPARAMS0_GHWPARAMS0_7_6_MASK (0xC0U)
#define USB_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT (6U)
#define USB_GHWPARAMS0_GHWPARAMS0_7_6(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_7_6_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_7_6_MASK)
#define USB_GHWPARAMS0_GHWPARAMS0_15_8_MASK (0xFF00U)
#define USB_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT (8U)
#define USB_GHWPARAMS0_GHWPARAMS0_15_8(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_15_8_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_15_8_MASK)
#define USB_GHWPARAMS0_GHWPARAMS0_23_16_MASK (0xFF0000U)
#define USB_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT (16U)
#define USB_GHWPARAMS0_GHWPARAMS0_23_16(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_23_16_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_23_16_MASK)
#define USB_GHWPARAMS0_GHWPARAMS0_31_24_MASK (0xFF000000U)
#define USB_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT (24U)
#define USB_GHWPARAMS0_GHWPARAMS0_31_24(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS0_GHWPARAMS0_31_24_SHIFT)) & USB_GHWPARAMS0_GHWPARAMS0_31_24_MASK)
/*! @} */
/*! @name GHWPARAMS1 - Global Hardware Parameters Register 1 */
/*! @{ */
#define USB_GHWPARAMS1_GHWPARAMS1_2_0_MASK (0x7U)
#define USB_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT (0U)
#define USB_GHWPARAMS1_GHWPARAMS1_2_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_2_0_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_2_0_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_5_3_MASK (0x38U)
#define USB_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT (3U)
#define USB_GHWPARAMS1_GHWPARAMS1_5_3(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_5_3_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_5_3_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_8_6_MASK (0x1C0U)
#define USB_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT (6U)
#define USB_GHWPARAMS1_GHWPARAMS1_8_6(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_8_6_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_8_6_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_11_9_MASK (0xE00U)
#define USB_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT (9U)
#define USB_GHWPARAMS1_GHWPARAMS1_11_9(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_11_9_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_11_9_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_14_12_MASK (0x7000U)
#define USB_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT (12U)
#define USB_GHWPARAMS1_GHWPARAMS1_14_12(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_14_12_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_14_12_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_20_15_MASK (0x1F8000U)
#define USB_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT (15U)
#define USB_GHWPARAMS1_GHWPARAMS1_20_15(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_20_15_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_20_15_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_22_21_MASK (0x600000U)
#define USB_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT (21U)
#define USB_GHWPARAMS1_GHWPARAMS1_22_21(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_22_21_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_22_21_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_23_MASK (0x800000U)
#define USB_GHWPARAMS1_GHWPARAMS1_23_SHIFT (23U)
#define USB_GHWPARAMS1_GHWPARAMS1_23(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_23_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_23_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_25_24_MASK (0x3000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT (24U)
#define USB_GHWPARAMS1_GHWPARAMS1_25_24(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_25_24_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_25_24_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_26_MASK (0x4000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_26_SHIFT (26U)
#define USB_GHWPARAMS1_GHWPARAMS1_26(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_26_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_26_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_27_MASK (0x8000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_27_SHIFT (27U)
#define USB_GHWPARAMS1_GHWPARAMS1_27(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_27_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_27_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_28_MASK (0x10000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_28_SHIFT (28U)
#define USB_GHWPARAMS1_GHWPARAMS1_28(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_28_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_28_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_30_MASK (0x40000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_30_SHIFT (30U)
#define USB_GHWPARAMS1_GHWPARAMS1_30(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_30_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_30_MASK)
#define USB_GHWPARAMS1_GHWPARAMS1_31_MASK (0x80000000U)
#define USB_GHWPARAMS1_GHWPARAMS1_31_SHIFT (31U)
#define USB_GHWPARAMS1_GHWPARAMS1_31(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS1_GHWPARAMS1_31_SHIFT)) & USB_GHWPARAMS1_GHWPARAMS1_31_MASK)
/*! @} */
/*! @name GHWPARAMS2 - Global Hardware Parameters Register 2 */
/*! @{ */
#define USB_GHWPARAMS2_GHWPARAMS2_31_0_MASK (0xFFFFFFFFU)
#define USB_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT (0U)
#define USB_GHWPARAMS2_GHWPARAMS2_31_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS2_GHWPARAMS2_31_0_SHIFT)) & USB_GHWPARAMS2_GHWPARAMS2_31_0_MASK)
/*! @} */
/*! @name GHWPARAMS3 - Global Hardware Parameters Register 3 */
/*! @{ */
#define USB_GHWPARAMS3_GHWPARAMS3_1_0_MASK (0x3U)
#define USB_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT (0U)
#define USB_GHWPARAMS3_GHWPARAMS3_1_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_1_0_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_1_0_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_3_2_MASK (0xCU)
#define USB_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT (2U)
#define USB_GHWPARAMS3_GHWPARAMS3_3_2(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_3_2_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_3_2_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_5_4_MASK (0x30U)
#define USB_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT (4U)
#define USB_GHWPARAMS3_GHWPARAMS3_5_4(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_5_4_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_5_4_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_7_6_MASK (0xC0U)
#define USB_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT (6U)
#define USB_GHWPARAMS3_GHWPARAMS3_7_6(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_7_6_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_7_6_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_10_MASK (0x400U)
#define USB_GHWPARAMS3_GHWPARAMS3_10_SHIFT (10U)
#define USB_GHWPARAMS3_GHWPARAMS3_10(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_10_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_10_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_11_MASK (0x800U)
#define USB_GHWPARAMS3_GHWPARAMS3_11_SHIFT (11U)
#define USB_GHWPARAMS3_GHWPARAMS3_11(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_11_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_11_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_17_12_MASK (0x3F000U)
#define USB_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT (12U)
#define USB_GHWPARAMS3_GHWPARAMS3_17_12(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_17_12_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_17_12_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_22_18_MASK (0x7C0000U)
#define USB_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT (18U)
#define USB_GHWPARAMS3_GHWPARAMS3_22_18(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_22_18_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_22_18_MASK)
#define USB_GHWPARAMS3_GHWPARAMS3_30_23_MASK (0x7F800000U)
#define USB_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT (23U)
#define USB_GHWPARAMS3_GHWPARAMS3_30_23(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS3_GHWPARAMS3_30_23_SHIFT)) & USB_GHWPARAMS3_GHWPARAMS3_30_23_MASK)
/*! @} */
/*! @name GHWPARAMS4 - Global Hardware Parameters Register 4 */
/*! @{ */
#define USB_GHWPARAMS4_GHWPARAMS4_5_0_MASK (0x3FU)
#define USB_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT (0U)
#define USB_GHWPARAMS4_GHWPARAMS4_5_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_5_0_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_5_0_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_8_7_MASK (0x180U)
#define USB_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT (7U)
#define USB_GHWPARAMS4_GHWPARAMS4_8_7(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_8_7_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_8_7_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_10_9_MASK (0x600U)
#define USB_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT (9U)
#define USB_GHWPARAMS4_GHWPARAMS4_10_9(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_10_9_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_10_9_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_11_MASK (0x800U)
#define USB_GHWPARAMS4_GHWPARAMS4_11_SHIFT (11U)
#define USB_GHWPARAMS4_GHWPARAMS4_11(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_11_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_11_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_12_MASK (0x1000U)
#define USB_GHWPARAMS4_GHWPARAMS4_12_SHIFT (12U)
#define USB_GHWPARAMS4_GHWPARAMS4_12(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_12_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_12_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_16_13_MASK (0x1E000U)
#define USB_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT (13U)
#define USB_GHWPARAMS4_GHWPARAMS4_16_13(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_16_13_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_16_13_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_20_17_MASK (0x1E0000U)
#define USB_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT (17U)
#define USB_GHWPARAMS4_GHWPARAMS4_20_17(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_20_17_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_20_17_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_21_MASK (0x200000U)
#define USB_GHWPARAMS4_GHWPARAMS4_21_SHIFT (21U)
#define USB_GHWPARAMS4_GHWPARAMS4_21(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_21_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_21_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_23_MASK (0x800000U)
#define USB_GHWPARAMS4_GHWPARAMS4_23_SHIFT (23U)
#define USB_GHWPARAMS4_GHWPARAMS4_23(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_23_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_23_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_27_24_MASK (0xF000000U)
#define USB_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT (24U)
#define USB_GHWPARAMS4_GHWPARAMS4_27_24(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_27_24_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_27_24_MASK)
#define USB_GHWPARAMS4_GHWPARAMS4_31_28_MASK (0xF0000000U)
#define USB_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT (28U)
#define USB_GHWPARAMS4_GHWPARAMS4_31_28(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS4_GHWPARAMS4_31_28_SHIFT)) & USB_GHWPARAMS4_GHWPARAMS4_31_28_MASK)
/*! @} */
/*! @name GHWPARAMS5 - Global Hardware Parameters Register 5 */
/*! @{ */
#define USB_GHWPARAMS5_GHWPARAMS5_3_0_MASK (0xFU)
#define USB_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT (0U)
#define USB_GHWPARAMS5_GHWPARAMS5_3_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_3_0_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_3_0_MASK)
#define USB_GHWPARAMS5_GHWPARAMS5_9_4_MASK (0x3F0U)
#define USB_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT (4U)
#define USB_GHWPARAMS5_GHWPARAMS5_9_4(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_9_4_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_9_4_MASK)
#define USB_GHWPARAMS5_GHWPARAMS5_15_10_MASK (0xFC00U)
#define USB_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT (10U)
#define USB_GHWPARAMS5_GHWPARAMS5_15_10(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_15_10_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_15_10_MASK)
#define USB_GHWPARAMS5_GHWPARAMS5_21_16_MASK (0x3F0000U)
#define USB_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT (16U)
#define USB_GHWPARAMS5_GHWPARAMS5_21_16(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_21_16_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_21_16_MASK)
#define USB_GHWPARAMS5_GHWPARAMS5_27_22_MASK (0xFC00000U)
#define USB_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT (22U)
#define USB_GHWPARAMS5_GHWPARAMS5_27_22(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS5_GHWPARAMS5_27_22_SHIFT)) & USB_GHWPARAMS5_GHWPARAMS5_27_22_MASK)
/*! @} */
/*! @name GHWPARAMS6 - Global Hardware Parameters Register 6 */
/*! @{ */
#define USB_GHWPARAMS6_GHWPARAMS6_5_0_MASK (0x3FU)
#define USB_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT (0U)
#define USB_GHWPARAMS6_GHWPARAMS6_5_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_5_0_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_5_0_MASK)
#define USB_GHWPARAMS6_GHWPARAMS6_6_MASK (0x40U)
#define USB_GHWPARAMS6_GHWPARAMS6_6_SHIFT (6U)
#define USB_GHWPARAMS6_GHWPARAMS6_6(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_6_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_6_MASK)
#define USB_GHWPARAMS6_GHWPARAMS6_7_MASK (0x80U)
#define USB_GHWPARAMS6_GHWPARAMS6_7_SHIFT (7U)
#define USB_GHWPARAMS6_GHWPARAMS6_7(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_7_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_7_MASK)
#define USB_GHWPARAMS6_GHWPARAMS6_9_8_MASK (0x300U)
#define USB_GHWPARAMS6_GHWPARAMS6_9_8_SHIFT (8U)
#define USB_GHWPARAMS6_GHWPARAMS6_9_8(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_9_8_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_9_8_MASK)
#define USB_GHWPARAMS6_BCSUPPORT_MASK (0x4000U)
#define USB_GHWPARAMS6_BCSUPPORT_SHIFT (14U)
#define USB_GHWPARAMS6_BCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_BCSUPPORT_SHIFT)) & USB_GHWPARAMS6_BCSUPPORT_MASK)
#define USB_GHWPARAMS6_BUSFLTRSSUPPORT_MASK (0x8000U)
#define USB_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT (15U)
#define USB_GHWPARAMS6_BUSFLTRSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_BUSFLTRSSUPPORT_SHIFT)) & USB_GHWPARAMS6_BUSFLTRSSUPPORT_MASK)
#define USB_GHWPARAMS6_GHWPARAMS6_31_16_MASK (0xFFFF0000U)
#define USB_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT (16U)
#define USB_GHWPARAMS6_GHWPARAMS6_31_16(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS6_GHWPARAMS6_31_16_SHIFT)) & USB_GHWPARAMS6_GHWPARAMS6_31_16_MASK)
/*! @} */
/*! @name GHWPARAMS7 - Global Hardware Parameters Register 7 */
/*! @{ */
#define USB_GHWPARAMS7_GHWPARAMS7_15_0_MASK (0xFFFFU)
#define USB_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT (0U)
#define USB_GHWPARAMS7_GHWPARAMS7_15_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS7_GHWPARAMS7_15_0_SHIFT)) & USB_GHWPARAMS7_GHWPARAMS7_15_0_MASK)
#define USB_GHWPARAMS7_GHWPARAMS7_31_16_MASK (0xFFFF0000U)
#define USB_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT (16U)
#define USB_GHWPARAMS7_GHWPARAMS7_31_16(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS7_GHWPARAMS7_31_16_SHIFT)) & USB_GHWPARAMS7_GHWPARAMS7_31_16_MASK)
/*! @} */
/*! @name GPRTBIMAP_HSLO - Global High-Speed Port to Bus Instance Mapping Register - Low */
/*! @{ */
#define USB_GPRTBIMAP_HSLO_BINUM1_MASK (0xFU)
#define USB_GPRTBIMAP_HSLO_BINUM1_SHIFT (0U)
#define USB_GPRTBIMAP_HSLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM1_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM1_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM2_MASK (0xF0U)
#define USB_GPRTBIMAP_HSLO_BINUM2_SHIFT (4U)
#define USB_GPRTBIMAP_HSLO_BINUM2(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM2_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM2_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM3_MASK (0xF00U)
#define USB_GPRTBIMAP_HSLO_BINUM3_SHIFT (8U)
#define USB_GPRTBIMAP_HSLO_BINUM3(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM3_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM3_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM4_MASK (0xF000U)
#define USB_GPRTBIMAP_HSLO_BINUM4_SHIFT (12U)
#define USB_GPRTBIMAP_HSLO_BINUM4(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM4_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM4_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM5_MASK (0xF0000U)
#define USB_GPRTBIMAP_HSLO_BINUM5_SHIFT (16U)
#define USB_GPRTBIMAP_HSLO_BINUM5(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM5_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM5_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM6_MASK (0xF00000U)
#define USB_GPRTBIMAP_HSLO_BINUM6_SHIFT (20U)
#define USB_GPRTBIMAP_HSLO_BINUM6(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM6_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM6_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM7_MASK (0xF000000U)
#define USB_GPRTBIMAP_HSLO_BINUM7_SHIFT (24U)
#define USB_GPRTBIMAP_HSLO_BINUM7(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM7_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM7_MASK)
#define USB_GPRTBIMAP_HSLO_BINUM8_MASK (0xF0000000U)
#define USB_GPRTBIMAP_HSLO_BINUM8_SHIFT (28U)
#define USB_GPRTBIMAP_HSLO_BINUM8(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSLO_BINUM8_SHIFT)) & USB_GPRTBIMAP_HSLO_BINUM8_MASK)
/*! @} */
/*! @name GPRTBIMAP_HSHI - Global High-Speed Port to Bus Instance Mapping Register - High */
/*! @{ */
#define USB_GPRTBIMAP_HSHI_BINUM9_MASK (0xFU)
#define USB_GPRTBIMAP_HSHI_BINUM9_SHIFT (0U)
#define USB_GPRTBIMAP_HSHI_BINUM9(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM9_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM9_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM10_MASK (0xF0U)
#define USB_GPRTBIMAP_HSHI_BINUM10_SHIFT (4U)
#define USB_GPRTBIMAP_HSHI_BINUM10(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM10_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM10_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM11_MASK (0xF00U)
#define USB_GPRTBIMAP_HSHI_BINUM11_SHIFT (8U)
#define USB_GPRTBIMAP_HSHI_BINUM11(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM11_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM11_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM12_MASK (0xF000U)
#define USB_GPRTBIMAP_HSHI_BINUM12_SHIFT (12U)
#define USB_GPRTBIMAP_HSHI_BINUM12(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM12_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM12_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM13_MASK (0xF0000U)
#define USB_GPRTBIMAP_HSHI_BINUM13_SHIFT (16U)
#define USB_GPRTBIMAP_HSHI_BINUM13(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM13_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM13_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM14_MASK (0xF00000U)
#define USB_GPRTBIMAP_HSHI_BINUM14_SHIFT (20U)
#define USB_GPRTBIMAP_HSHI_BINUM14(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM14_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM14_MASK)
#define USB_GPRTBIMAP_HSHI_BINUM15_MASK (0xF000000U)
#define USB_GPRTBIMAP_HSHI_BINUM15_SHIFT (24U)
#define USB_GPRTBIMAP_HSHI_BINUM15(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_HSHI_BINUM15_SHIFT)) & USB_GPRTBIMAP_HSHI_BINUM15_MASK)
/*! @} */
/*! @name GPRTBIMAP_FSLO - Global Full-Speed Port to Bus Instance Mapping Register - Low */
/*! @{ */
#define USB_GPRTBIMAP_FSLO_BINUM1_MASK (0xFU)
#define USB_GPRTBIMAP_FSLO_BINUM1_SHIFT (0U)
#define USB_GPRTBIMAP_FSLO_BINUM1(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM1_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM1_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM2_MASK (0xF0U)
#define USB_GPRTBIMAP_FSLO_BINUM2_SHIFT (4U)
#define USB_GPRTBIMAP_FSLO_BINUM2(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM2_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM2_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM3_MASK (0xF00U)
#define USB_GPRTBIMAP_FSLO_BINUM3_SHIFT (8U)
#define USB_GPRTBIMAP_FSLO_BINUM3(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM3_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM3_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM4_MASK (0xF000U)
#define USB_GPRTBIMAP_FSLO_BINUM4_SHIFT (12U)
#define USB_GPRTBIMAP_FSLO_BINUM4(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM4_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM4_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM5_MASK (0xF0000U)
#define USB_GPRTBIMAP_FSLO_BINUM5_SHIFT (16U)
#define USB_GPRTBIMAP_FSLO_BINUM5(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM5_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM5_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM6_MASK (0xF00000U)
#define USB_GPRTBIMAP_FSLO_BINUM6_SHIFT (20U)
#define USB_GPRTBIMAP_FSLO_BINUM6(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM6_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM6_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM7_MASK (0xF000000U)
#define USB_GPRTBIMAP_FSLO_BINUM7_SHIFT (24U)
#define USB_GPRTBIMAP_FSLO_BINUM7(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM7_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM7_MASK)
#define USB_GPRTBIMAP_FSLO_BINUM8_MASK (0xF0000000U)
#define USB_GPRTBIMAP_FSLO_BINUM8_SHIFT (28U)
#define USB_GPRTBIMAP_FSLO_BINUM8(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSLO_BINUM8_SHIFT)) & USB_GPRTBIMAP_FSLO_BINUM8_MASK)
/*! @} */
/*! @name GPRTBIMAP_FSHI - Global Full-Speed Port to Bus Instance Mapping Register - High */
/*! @{ */
#define USB_GPRTBIMAP_FSHI_BINUM9_MASK (0xFU)
#define USB_GPRTBIMAP_FSHI_BINUM9_SHIFT (0U)
#define USB_GPRTBIMAP_FSHI_BINUM9(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM9_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM9_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM10_MASK (0xF0U)
#define USB_GPRTBIMAP_FSHI_BINUM10_SHIFT (4U)
#define USB_GPRTBIMAP_FSHI_BINUM10(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM10_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM10_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM11_MASK (0xF00U)
#define USB_GPRTBIMAP_FSHI_BINUM11_SHIFT (8U)
#define USB_GPRTBIMAP_FSHI_BINUM11(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM11_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM11_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM12_MASK (0xF000U)
#define USB_GPRTBIMAP_FSHI_BINUM12_SHIFT (12U)
#define USB_GPRTBIMAP_FSHI_BINUM12(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM12_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM12_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM13_MASK (0xF0000U)
#define USB_GPRTBIMAP_FSHI_BINUM13_SHIFT (16U)
#define USB_GPRTBIMAP_FSHI_BINUM13(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM13_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM13_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM14_MASK (0xF00000U)
#define USB_GPRTBIMAP_FSHI_BINUM14_SHIFT (20U)
#define USB_GPRTBIMAP_FSHI_BINUM14(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM14_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM14_MASK)
#define USB_GPRTBIMAP_FSHI_BINUM15_MASK (0xF000000U)
#define USB_GPRTBIMAP_FSHI_BINUM15_SHIFT (24U)
#define USB_GPRTBIMAP_FSHI_BINUM15(x) (((uint32_t)(((uint32_t)(x)) << USB_GPRTBIMAP_FSHI_BINUM15_SHIFT)) & USB_GPRTBIMAP_FSHI_BINUM15_MASK)
/*! @} */
/*! @name GUCTL2 - Global User Control Register 2 */
/*! @{ */
#define USB_GUCTL2_TXPINGDURATION_MASK (0x1FU)
#define USB_GUCTL2_TXPINGDURATION_SHIFT (0U)
#define USB_GUCTL2_TXPINGDURATION(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_TXPINGDURATION_SHIFT)) & USB_GUCTL2_TXPINGDURATION_MASK)
#define USB_GUCTL2_RXPINGDURATION_MASK (0x7E0U)
#define USB_GUCTL2_RXPINGDURATION_SHIFT (5U)
#define USB_GUCTL2_RXPINGDURATION(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_RXPINGDURATION_SHIFT)) & USB_GUCTL2_RXPINGDURATION_MASK)
#define USB_GUCTL2_DISABLECFC_MASK (0x800U)
#define USB_GUCTL2_DISABLECFC_SHIFT (11U)
#define USB_GUCTL2_DISABLECFC(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_DISABLECFC_SHIFT)) & USB_GUCTL2_DISABLECFC_MASK)
#define USB_GUCTL2_ENABLEEPCACHEEVICT_MASK (0x1000U)
#define USB_GUCTL2_ENABLEEPCACHEEVICT_SHIFT (12U)
#define USB_GUCTL2_ENABLEEPCACHEEVICT(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_ENABLEEPCACHEEVICT_SHIFT)) & USB_GUCTL2_ENABLEEPCACHEEVICT_MASK)
#define USB_GUCTL2_RST_ACTBITLATER_MASK (0x4000U)
#define USB_GUCTL2_RST_ACTBITLATER_SHIFT (14U)
#define USB_GUCTL2_RST_ACTBITLATER(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_RST_ACTBITLATER_SHIFT)) & USB_GUCTL2_RST_ACTBITLATER_MASK)
#define USB_GUCTL2_NOLOWPWRDUR_MASK (0x78000U)
#define USB_GUCTL2_NOLOWPWRDUR_SHIFT (15U)
#define USB_GUCTL2_NOLOWPWRDUR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_NOLOWPWRDUR_SHIFT)) & USB_GUCTL2_NOLOWPWRDUR_MASK)
#define USB_GUCTL2_EN_HP_PM_TIMER_MASK (0x3F80000U)
#define USB_GUCTL2_EN_HP_PM_TIMER_SHIFT (19U)
#define USB_GUCTL2_EN_HP_PM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << USB_GUCTL2_EN_HP_PM_TIMER_SHIFT)) & USB_GUCTL2_EN_HP_PM_TIMER_MASK)
/*! @} */
/*! @name GUSB2PHYCFG - Global USB2 PHY Configuration Register */
/*! @{ */
#define USB_GUSB2PHYCFG_TOUTCAL_MASK (0x7U)
#define USB_GUSB2PHYCFG_TOUTCAL_SHIFT (0U)
#define USB_GUSB2PHYCFG_TOUTCAL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_TOUTCAL_SHIFT)) & USB_GUSB2PHYCFG_TOUTCAL_MASK)
#define USB_GUSB2PHYCFG_PHYIF_MASK (0x8U)
#define USB_GUSB2PHYCFG_PHYIF_SHIFT (3U)
#define USB_GUSB2PHYCFG_PHYIF(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYIF_SHIFT)) & USB_GUSB2PHYCFG_PHYIF_MASK)
#define USB_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK (0x10U)
#define USB_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT (4U)
#define USB_GUSB2PHYCFG_ULPI_UTMI_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT)) & USB_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK)
#define USB_GUSB2PHYCFG_FSINTF_MASK (0x20U)
#define USB_GUSB2PHYCFG_FSINTF_SHIFT (5U)
#define USB_GUSB2PHYCFG_FSINTF(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_FSINTF_SHIFT)) & USB_GUSB2PHYCFG_FSINTF_MASK)
#define USB_GUSB2PHYCFG_SUSPENDUSB20_MASK (0x40U)
#define USB_GUSB2PHYCFG_SUSPENDUSB20_SHIFT (6U)
#define USB_GUSB2PHYCFG_SUSPENDUSB20(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_SUSPENDUSB20_SHIFT)) & USB_GUSB2PHYCFG_SUSPENDUSB20_MASK)
#define USB_GUSB2PHYCFG_PHYSEL_MASK (0x80U)
#define USB_GUSB2PHYCFG_PHYSEL_SHIFT (7U)
#define USB_GUSB2PHYCFG_PHYSEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYSEL_SHIFT)) & USB_GUSB2PHYCFG_PHYSEL_MASK)
#define USB_GUSB2PHYCFG_ENBLSLPM_MASK (0x100U)
#define USB_GUSB2PHYCFG_ENBLSLPM_SHIFT (8U)
#define USB_GUSB2PHYCFG_ENBLSLPM(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ENBLSLPM_SHIFT)) & USB_GUSB2PHYCFG_ENBLSLPM_MASK)
#define USB_GUSB2PHYCFG_XCVRDLY_MASK (0x200U)
#define USB_GUSB2PHYCFG_XCVRDLY_SHIFT (9U)
#define USB_GUSB2PHYCFG_XCVRDLY(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_XCVRDLY_SHIFT)) & USB_GUSB2PHYCFG_XCVRDLY_MASK)
#define USB_GUSB2PHYCFG_USBTRDTIM_MASK (0x3C00U)
#define USB_GUSB2PHYCFG_USBTRDTIM_SHIFT (10U)
#define USB_GUSB2PHYCFG_USBTRDTIM(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_USBTRDTIM_SHIFT)) & USB_GUSB2PHYCFG_USBTRDTIM_MASK)
#define USB_GUSB2PHYCFG_ULPIAUTORES_MASK (0x8000U)
#define USB_GUSB2PHYCFG_ULPIAUTORES_SHIFT (15U)
#define USB_GUSB2PHYCFG_ULPIAUTORES(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIAUTORES_SHIFT)) & USB_GUSB2PHYCFG_ULPIAUTORES_MASK)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK (0x20000U)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT (17U)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSDRV(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT)) & USB_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK (0x40000U)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT (18U)
#define USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_SHIFT)) & USB_GUSB2PHYCFG_ULPIEXTVBUSINDIACTOR_MASK)
#define USB_GUSB2PHYCFG_LSIPD_MASK (0x380000U)
#define USB_GUSB2PHYCFG_LSIPD_SHIFT (19U)
#define USB_GUSB2PHYCFG_LSIPD(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_LSIPD_SHIFT)) & USB_GUSB2PHYCFG_LSIPD_MASK)
#define USB_GUSB2PHYCFG_LSTRD_MASK (0x1C00000U)
#define USB_GUSB2PHYCFG_LSTRD_SHIFT (22U)
#define USB_GUSB2PHYCFG_LSTRD(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_LSTRD_SHIFT)) & USB_GUSB2PHYCFG_LSTRD_MASK)
#define USB_GUSB2PHYCFG_INV_SEL_HSIC_MASK (0x4000000U)
#define USB_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT (26U)
#define USB_GUSB2PHYCFG_INV_SEL_HSIC(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_INV_SEL_HSIC_SHIFT)) & USB_GUSB2PHYCFG_INV_SEL_HSIC_MASK)
#define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK (0x18000000U)
#define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT (27U)
#define USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_SHIFT)) & USB_GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ_MASK)
#define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK (0x20000000U)
#define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT (29U)
#define USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_SHIFT)) & USB_GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK_MASK)
#define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK (0x40000000U)
#define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT (30U)
#define USB_GUSB2PHYCFG_U2_FREECLK_EXISTS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_SHIFT)) & USB_GUSB2PHYCFG_U2_FREECLK_EXISTS_MASK)
#define USB_GUSB2PHYCFG_PHYSOFTRST_MASK (0x80000000U)
#define USB_GUSB2PHYCFG_PHYSOFTRST_SHIFT (31U)
#define USB_GUSB2PHYCFG_PHYSOFTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYCFG_PHYSOFTRST_SHIFT)) & USB_GUSB2PHYCFG_PHYSOFTRST_MASK)
/*! @} */
/*! @name GUSB2PHYACC_ULPI - Global USB 2.0 UTMI PHY vendor control register */
/*! @{ */
#define USB_GUSB2PHYACC_ULPI_REGDATA_MASK (0xFFU)
#define USB_GUSB2PHYACC_ULPI_REGDATA_SHIFT (0U)
#define USB_GUSB2PHYACC_ULPI_REGDATA(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGDATA_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGDATA_MASK)
#define USB_GUSB2PHYACC_ULPI_EXTREGADDR_MASK (0xFF00U)
#define USB_GUSB2PHYACC_ULPI_EXTREGADDR_SHIFT (8U)
#define USB_GUSB2PHYACC_ULPI_EXTREGADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_EXTREGADDR_SHIFT)) & USB_GUSB2PHYACC_ULPI_EXTREGADDR_MASK)
#define USB_GUSB2PHYACC_ULPI_REGADDR_MASK (0x3F0000U)
#define USB_GUSB2PHYACC_ULPI_REGADDR_SHIFT (16U)
#define USB_GUSB2PHYACC_ULPI_REGADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGADDR_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGADDR_MASK)
#define USB_GUSB2PHYACC_ULPI_REGWR_MASK (0x400000U)
#define USB_GUSB2PHYACC_ULPI_REGWR_SHIFT (22U)
#define USB_GUSB2PHYACC_ULPI_REGWR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_REGWR_SHIFT)) & USB_GUSB2PHYACC_ULPI_REGWR_MASK)
#define USB_GUSB2PHYACC_ULPI_VSTSBSY_MASK (0x800000U)
#define USB_GUSB2PHYACC_ULPI_VSTSBSY_SHIFT (23U)
#define USB_GUSB2PHYACC_ULPI_VSTSBSY(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_VSTSBSY_SHIFT)) & USB_GUSB2PHYACC_ULPI_VSTSBSY_MASK)
#define USB_GUSB2PHYACC_ULPI_VSTSDONE_MASK (0x1000000U)
#define USB_GUSB2PHYACC_ULPI_VSTSDONE_SHIFT (24U)
#define USB_GUSB2PHYACC_ULPI_VSTSDONE(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_VSTSDONE_SHIFT)) & USB_GUSB2PHYACC_ULPI_VSTSDONE_MASK)
#define USB_GUSB2PHYACC_ULPI_NEWREGREQ_MASK (0x2000000U)
#define USB_GUSB2PHYACC_ULPI_NEWREGREQ_SHIFT (25U)
#define USB_GUSB2PHYACC_ULPI_NEWREGREQ(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_NEWREGREQ_SHIFT)) & USB_GUSB2PHYACC_ULPI_NEWREGREQ_MASK)
#define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_MASK (0x4000000U)
#define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHIFT (26U)
#define USB_GUSB2PHYACC_ULPI_DISUIPIDRVR(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_SHIFT)) & USB_GUSB2PHYACC_ULPI_DISUIPIDRVR_MASK)
/*! @} */
/*! @name GUSB3PIPECTL - Global USB 3.0 PIPE control register */
/*! @{ */
#define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK (0x1U)
#define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT (0U)
#define USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_SHIFT)) & USB_GUSB3PIPECTL_ELASTIC_BUFFER_MODE_MASK)
#define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK (0x6U)
#define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT (1U)
#define USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_SHIFT)) & USB_GUSB3PIPECTL_SS_TX_DE_EMPHASIS_MASK)
#define USB_GUSB3PIPECTL_TX_MARGIN_MASK (0x38U)
#define USB_GUSB3PIPECTL_TX_MARGIN_SHIFT (3U)
#define USB_GUSB3PIPECTL_TX_MARGIN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_TX_MARGIN_SHIFT)) & USB_GUSB3PIPECTL_TX_MARGIN_MASK)
#define USB_GUSB3PIPECTL_TX_SWING_MASK (0x40U)
#define USB_GUSB3PIPECTL_TX_SWING_SHIFT (6U)
#define USB_GUSB3PIPECTL_TX_SWING(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_TX_SWING_SHIFT)) & USB_GUSB3PIPECTL_TX_SWING_MASK)
#define USB_GUSB3PIPECTL_SSICEN_MASK (0x80U)
#define USB_GUSB3PIPECTL_SSICEN_SHIFT (7U)
#define USB_GUSB3PIPECTL_SSICEN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SSICEN_SHIFT)) & USB_GUSB3PIPECTL_SSICEN_MASK)
#define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_MASK (0x100U)
#define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_SHIFT (8U)
#define USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_SHIFT)) & USB_GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL_MASK)
#define USB_GUSB3PIPECTL_LFPSFILTER_MASK (0x200U)
#define USB_GUSB3PIPECTL_LFPSFILTER_SHIFT (9U)
#define USB_GUSB3PIPECTL_LFPSFILTER(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_LFPSFILTER_SHIFT)) & USB_GUSB3PIPECTL_LFPSFILTER_MASK)
#define USB_GUSB3PIPECTL_P3EXSIGP2_MASK (0x400U)
#define USB_GUSB3PIPECTL_P3EXSIGP2_SHIFT (10U)
#define USB_GUSB3PIPECTL_P3EXSIGP2(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_P3EXSIGP2_SHIFT)) & USB_GUSB3PIPECTL_P3EXSIGP2_MASK)
#define USB_GUSB3PIPECTL_P3P2TRANOK_MASK (0x800U)
#define USB_GUSB3PIPECTL_P3P2TRANOK_SHIFT (11U)
#define USB_GUSB3PIPECTL_P3P2TRANOK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_P3P2TRANOK_SHIFT)) & USB_GUSB3PIPECTL_P3P2TRANOK_MASK)
#define USB_GUSB3PIPECTL_LFPSP0ALGN_MASK (0x1000U)
#define USB_GUSB3PIPECTL_LFPSP0ALGN_SHIFT (12U)
#define USB_GUSB3PIPECTL_LFPSP0ALGN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_LFPSP0ALGN_SHIFT)) & USB_GUSB3PIPECTL_LFPSP0ALGN_MASK)
#define USB_GUSB3PIPECTL_SKIPRXDET_MASK (0x2000U)
#define USB_GUSB3PIPECTL_SKIPRXDET_SHIFT (13U)
#define USB_GUSB3PIPECTL_SKIPRXDET(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SKIPRXDET_SHIFT)) & USB_GUSB3PIPECTL_SKIPRXDET_MASK)
#define USB_GUSB3PIPECTL_ABORTRXDETINU2_MASK (0x4000U)
#define USB_GUSB3PIPECTL_ABORTRXDETINU2_SHIFT (14U)
#define USB_GUSB3PIPECTL_ABORTRXDETINU2(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_ABORTRXDETINU2_SHIFT)) & USB_GUSB3PIPECTL_ABORTRXDETINU2_MASK)
#define USB_GUSB3PIPECTL_DATWIDTH_MASK (0x18000U)
#define USB_GUSB3PIPECTL_DATWIDTH_SHIFT (15U)
#define USB_GUSB3PIPECTL_DATWIDTH(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DATWIDTH_SHIFT)) & USB_GUSB3PIPECTL_DATWIDTH_MASK)
#define USB_GUSB3PIPECTL_SUSPENDENABLE_MASK (0x20000U)
#define USB_GUSB3PIPECTL_SUSPENDENABLE_SHIFT (17U)
#define USB_GUSB3PIPECTL_SUSPENDENABLE(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_SUSPENDENABLE_SHIFT)) & USB_GUSB3PIPECTL_SUSPENDENABLE_MASK)
#define USB_GUSB3PIPECTL_DELAYP1TRANS_MASK (0x40000U)
#define USB_GUSB3PIPECTL_DELAYP1TRANS_SHIFT (18U)
#define USB_GUSB3PIPECTL_DELAYP1TRANS(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DELAYP1TRANS_SHIFT)) & USB_GUSB3PIPECTL_DELAYP1TRANS_MASK)
#define USB_GUSB3PIPECTL_DELAYP1P2P3_MASK (0x380000U)
#define USB_GUSB3PIPECTL_DELAYP1P2P3_SHIFT (19U)
#define USB_GUSB3PIPECTL_DELAYP1P2P3(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DELAYP1P2P3_SHIFT)) & USB_GUSB3PIPECTL_DELAYP1P2P3_MASK)
#define USB_GUSB3PIPECTL_DISRXDETU3RXDET_MASK (0x400000U)
#define USB_GUSB3PIPECTL_DISRXDETU3RXDET_SHIFT (22U)
#define USB_GUSB3PIPECTL_DISRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DISRXDETU3RXDET_SHIFT)) & USB_GUSB3PIPECTL_DISRXDETU3RXDET_MASK)
#define USB_GUSB3PIPECTL_STARTRXDETU3RXDET_MASK (0x800000U)
#define USB_GUSB3PIPECTL_STARTRXDETU3RXDET_SHIFT (23U)
#define USB_GUSB3PIPECTL_STARTRXDETU3RXDET(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_STARTRXDETU3RXDET_SHIFT)) & USB_GUSB3PIPECTL_STARTRXDETU3RXDET_MASK)
#define USB_GUSB3PIPECTL_REQUEST_P1P2P3_MASK (0x1000000U)
#define USB_GUSB3PIPECTL_REQUEST_P1P2P3_SHIFT (24U)
#define USB_GUSB3PIPECTL_REQUEST_P1P2P3(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_REQUEST_P1P2P3_SHIFT)) & USB_GUSB3PIPECTL_REQUEST_P1P2P3_MASK)
#define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_MASK (0x2000000U)
#define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHIFT (25U)
#define USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_SHIFT)) & USB_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV_MASK)
#define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_MASK (0x4000000U)
#define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHIFT (26U)
#define USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_SHIFT)) & USB_GUSB3PIPECTL_PING_ENHANCEMENT_EN_MASK)
#define USB_GUSB3PIPECTL_UX_EXIT_IN_PX_MASK (0x8000000U)
#define USB_GUSB3PIPECTL_UX_EXIT_IN_PX_SHIFT (27U)
#define USB_GUSB3PIPECTL_UX_EXIT_IN_PX(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_UX_EXIT_IN_PX_SHIFT)) & USB_GUSB3PIPECTL_UX_EXIT_IN_PX_MASK)
#define USB_GUSB3PIPECTL_DISRXDETP3_MASK (0x10000000U)
#define USB_GUSB3PIPECTL_DISRXDETP3_SHIFT (28U)
#define USB_GUSB3PIPECTL_DISRXDETP3(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_DISRXDETP3_SHIFT)) & USB_GUSB3PIPECTL_DISRXDETP3_MASK)
#define USB_GUSB3PIPECTL_U2P3OK_MASK (0x20000000U)
#define USB_GUSB3PIPECTL_U2P3OK_SHIFT (29U)
#define USB_GUSB3PIPECTL_U2P3OK(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_U2P3OK_SHIFT)) & USB_GUSB3PIPECTL_U2P3OK_MASK)
#define USB_GUSB3PIPECTL_HSTPRTCMPL_MASK (0x40000000U)
#define USB_GUSB3PIPECTL_HSTPRTCMPL_SHIFT (30U)
#define USB_GUSB3PIPECTL_HSTPRTCMPL(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_HSTPRTCMPL_SHIFT)) & USB_GUSB3PIPECTL_HSTPRTCMPL_MASK)
#define USB_GUSB3PIPECTL_PHYSOFTRST_MASK (0x80000000U)
#define USB_GUSB3PIPECTL_PHYSOFTRST_SHIFT (31U)
#define USB_GUSB3PIPECTL_PHYSOFTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GUSB3PIPECTL_PHYSOFTRST_SHIFT)) & USB_GUSB3PIPECTL_PHYSOFTRST_MASK)
/*! @} */
/*! @name GTXFIFOSIZ - Global transmit FIFO size register */
/*! @{ */
#define USB_GTXFIFOSIZ_TXFDEP_N_MASK (0xFFFFU)
#define USB_GTXFIFOSIZ_TXFDEP_N_SHIFT (0U)
/*! TXFDEP_N - TXFIFO depth
*/
#define USB_GTXFIFOSIZ_TXFDEP_N(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOSIZ_TXFDEP_N_SHIFT)) & USB_GTXFIFOSIZ_TXFDEP_N_MASK)
#define USB_GTXFIFOSIZ_TXFSTADDR_N_MASK (0xFFFF0000U)
#define USB_GTXFIFOSIZ_TXFSTADDR_N_SHIFT (16U)
#define USB_GTXFIFOSIZ_TXFSTADDR_N(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOSIZ_TXFSTADDR_N_SHIFT)) & USB_GTXFIFOSIZ_TXFSTADDR_N_MASK)
/*! @} */
/* The count of USB_GTXFIFOSIZ */
#define USB_GTXFIFOSIZ_COUNT (8U)
/*! @name GRXFIFOSIZ - Global receive FIFO size register */
/*! @{ */
#define USB_GRXFIFOSIZ_RXFDEP_N_MASK (0xFFFFU)
#define USB_GRXFIFOSIZ_RXFDEP_N_SHIFT (0U)
#define USB_GRXFIFOSIZ_RXFDEP_N(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOSIZ_RXFDEP_N_SHIFT)) & USB_GRXFIFOSIZ_RXFDEP_N_MASK)
#define USB_GRXFIFOSIZ_RXFSTADDR_N_MASK (0xFFFF0000U)
#define USB_GRXFIFOSIZ_RXFSTADDR_N_SHIFT (16U)
#define USB_GRXFIFOSIZ_RXFSTADDR_N(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOSIZ_RXFSTADDR_N_SHIFT)) & USB_GRXFIFOSIZ_RXFSTADDR_N_MASK)
/*! @} */
/* The count of USB_GRXFIFOSIZ */
#define USB_GRXFIFOSIZ_COUNT (3U)
/*! @name GEVNTADRLO - Global Event Buffer Address (Low) Register */
/*! @{ */
#define USB_GEVNTADRLO_EVNTADRLO_MASK (0xFFFFFFFFU)
#define USB_GEVNTADRLO_EVNTADRLO_SHIFT (0U)
#define USB_GEVNTADRLO_EVNTADRLO(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTADRLO_EVNTADRLO_SHIFT)) & USB_GEVNTADRLO_EVNTADRLO_MASK)
/*! @} */
/*! @name GEVNTADRHI - Global Event Buffer Address (High) Register */
/*! @{ */
#define USB_GEVNTADRHI_EVNTADRHI_MASK (0xFFFFFFFFU)
#define USB_GEVNTADRHI_EVNTADRHI_SHIFT (0U)
#define USB_GEVNTADRHI_EVNTADRHI(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTADRHI_EVNTADRHI_SHIFT)) & USB_GEVNTADRHI_EVNTADRHI_MASK)
/*! @} */
/*! @name GEVNTSIZ - Global event buffer size register */
/*! @{ */
#define USB_GEVNTSIZ_EVENTSIZ_MASK (0xFFFFU)
#define USB_GEVNTSIZ_EVENTSIZ_SHIFT (0U)
#define USB_GEVNTSIZ_EVENTSIZ(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTSIZ_EVENTSIZ_SHIFT)) & USB_GEVNTSIZ_EVENTSIZ_MASK)
#define USB_GEVNTSIZ_EVNTINTRPTMASK_MASK (0x80000000U)
#define USB_GEVNTSIZ_EVNTINTRPTMASK_SHIFT (31U)
#define USB_GEVNTSIZ_EVNTINTRPTMASK(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTSIZ_EVNTINTRPTMASK_SHIFT)) & USB_GEVNTSIZ_EVNTINTRPTMASK_MASK)
/*! @} */
/*! @name GEVNTCOUNT - Global event buffer count register */
/*! @{ */
#define USB_GEVNTCOUNT_EVNTCOUNT_MASK (0xFFFFU)
#define USB_GEVNTCOUNT_EVNTCOUNT_SHIFT (0U)
#define USB_GEVNTCOUNT_EVNTCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTCOUNT_EVNTCOUNT_SHIFT)) & USB_GEVNTCOUNT_EVNTCOUNT_MASK)
#define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK (0x80000000U)
#define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT (31U)
#define USB_GEVNTCOUNT_EVNT_HANDLER_BUSY(x) (((uint32_t)(((uint32_t)(x)) << USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_SHIFT)) & USB_GEVNTCOUNT_EVNT_HANDLER_BUSY_MASK)
/*! @} */
/*! @name GHWPARAMS8 - Global Hardware Parameters Register 8 */
/*! @{ */
#define USB_GHWPARAMS8_GHWPARAMS8_32_0_MASK (0xFFFFFFFFU)
#define USB_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT (0U)
#define USB_GHWPARAMS8_GHWPARAMS8_32_0(x) (((uint32_t)(((uint32_t)(x)) << USB_GHWPARAMS8_GHWPARAMS8_32_0_SHIFT)) & USB_GHWPARAMS8_GHWPARAMS8_32_0_MASK)
/*! @} */
/*! @name GTXFIFOPRIDEV - Global Device TX FIFO DMA Priority Register */
/*! @{ */
#define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_MASK (0xFFU)
#define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_SHIFT (0U)
#define USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_SHIFT)) & USB_GTXFIFOPRIDEV_GTXFIFOPRIDEV_MASK)
/*! @} */
/*! @name GTXFIFOPRIHST - Global Host TX FIFO DMA Priority Register */
/*! @{ */
#define USB_GTXFIFOPRIHST_GTXFIFOPRIHST_MASK (0xFU)
#define USB_GTXFIFOPRIHST_GTXFIFOPRIHST_SHIFT (0U)
#define USB_GTXFIFOPRIHST_GTXFIFOPRIHST(x) (((uint32_t)(((uint32_t)(x)) << USB_GTXFIFOPRIHST_GTXFIFOPRIHST_SHIFT)) & USB_GTXFIFOPRIHST_GTXFIFOPRIHST_MASK)
/*! @} */
/*! @name GRXFIFOPRIHST - Global Host RX FIFO DMA Priority Register */
/*! @{ */
#define USB_GRXFIFOPRIHST_GRXFIFOPRIHST_MASK (0x7U)
#define USB_GRXFIFOPRIHST_GRXFIFOPRIHST_SHIFT (0U)
#define USB_GRXFIFOPRIHST_GRXFIFOPRIHST(x) (((uint32_t)(((uint32_t)(x)) << USB_GRXFIFOPRIHST_GRXFIFOPRIHST_SHIFT)) & USB_GRXFIFOPRIHST_GRXFIFOPRIHST_MASK)
/*! @} */
/*! @name GFIFOPRIDBC - Global Host Debug Capability DMA Priority Register */
/*! @{ */
#define USB_GFIFOPRIDBC_GFIFOPRIDBC_MASK (0x3U)
#define USB_GFIFOPRIDBC_GFIFOPRIDBC_SHIFT (0U)
#define USB_GFIFOPRIDBC_GFIFOPRIDBC(x) (((uint32_t)(((uint32_t)(x)) << USB_GFIFOPRIDBC_GFIFOPRIDBC_SHIFT)) & USB_GFIFOPRIDBC_GFIFOPRIDBC_MASK)
/*! @} */
/*! @name GDMAHLRATIO - */
/*! @{ */
#define USB_GDMAHLRATIO_HSTTXFIFO_MASK (0x1FU)
#define USB_GDMAHLRATIO_HSTTXFIFO_SHIFT (0U)
#define USB_GDMAHLRATIO_HSTTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GDMAHLRATIO_HSTTXFIFO_SHIFT)) & USB_GDMAHLRATIO_HSTTXFIFO_MASK)
#define USB_GDMAHLRATIO_HSTRXFIFO_MASK (0x1F00U)
#define USB_GDMAHLRATIO_HSTRXFIFO_SHIFT (8U)
#define USB_GDMAHLRATIO_HSTRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << USB_GDMAHLRATIO_HSTRXFIFO_SHIFT)) & USB_GDMAHLRATIO_HSTRXFIFO_MASK)
/*! @} */
/*! @name GFLADJ - Global Frame Length Adjustment Register */
/*! @{ */
#define USB_GFLADJ_GFLADJ_30MHZ_MASK (0x3FU)
#define USB_GFLADJ_GFLADJ_30MHZ_SHIFT (0U)
#define USB_GFLADJ_GFLADJ_30MHZ(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_30MHZ_SHIFT)) & USB_GFLADJ_GFLADJ_30MHZ_MASK)
#define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK (0x80U)
#define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT (7U)
#define USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_SHIFT)) & USB_GFLADJ_GFLADJ_30MHZ_SDBND_SEL_MASK)
#define USB_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK (0x3FFF00U)
#define USB_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT (8U)
#define USB_GFLADJ_GFLADJ_REFCLK_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK)
#define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK (0x800000U)
#define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT (23U)
#define USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_LPM_SEL_MASK)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK (0x7F000000U)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT (24U)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_240MHZ_DECR_MASK)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK (0x80000000U)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT (31U)
#define USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1(x) (((uint32_t)(((uint32_t)(x)) << USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_SHIFT)) & USB_GFLADJ_GFLADJ_REFCLK_240MHZDECR_PLS1_MASK)
/*! @} */
/*! @name DCFG - Device Configuration Register */
/*! @{ */
#define USB_DCFG_DEVSPD_MASK (0x7U)
#define USB_DCFG_DEVSPD_SHIFT (0U)
/*! DEVSPD
* 0b001..
* 0b000..
* 0b100..
*/
#define USB_DCFG_DEVSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_DEVSPD_SHIFT)) & USB_DCFG_DEVSPD_MASK)
#define USB_DCFG_DEVADDR_MASK (0x3F8U)
#define USB_DCFG_DEVADDR_SHIFT (3U)
#define USB_DCFG_DEVADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_DEVADDR_SHIFT)) & USB_DCFG_DEVADDR_MASK)
#define USB_DCFG_INTRNUM_MASK (0x1F000U)
#define USB_DCFG_INTRNUM_SHIFT (12U)
#define USB_DCFG_INTRNUM(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_INTRNUM_SHIFT)) & USB_DCFG_INTRNUM_MASK)
#define USB_DCFG_NUMP_MASK (0x3E0000U)
#define USB_DCFG_NUMP_SHIFT (17U)
#define USB_DCFG_NUMP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_NUMP_SHIFT)) & USB_DCFG_NUMP_MASK)
#define USB_DCFG_LPMCAP_MASK (0x400000U)
#define USB_DCFG_LPMCAP_SHIFT (22U)
#define USB_DCFG_LPMCAP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_LPMCAP_SHIFT)) & USB_DCFG_LPMCAP_MASK)
#define USB_DCFG_IGNSTRMPP_MASK (0x800000U)
#define USB_DCFG_IGNSTRMPP_SHIFT (23U)
#define USB_DCFG_IGNSTRMPP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCFG_IGNSTRMPP_SHIFT)) & USB_DCFG_IGNSTRMPP_MASK)
/*! @} */
/*! @name DCTL - Device control register */
/*! @{ */
#define USB_DCTL_TSTCTL_MASK (0x1EU)
#define USB_DCTL_TSTCTL_SHIFT (1U)
#define USB_DCTL_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_TSTCTL_SHIFT)) & USB_DCTL_TSTCTL_MASK)
#define USB_DCTL_ULSTCHNGREQ_MASK (0x1E0U)
#define USB_DCTL_ULSTCHNGREQ_SHIFT (5U)
#define USB_DCTL_ULSTCHNGREQ(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ULSTCHNGREQ_SHIFT)) & USB_DCTL_ULSTCHNGREQ_MASK)
#define USB_DCTL_ACCEPTU1ENA_MASK (0x200U)
#define USB_DCTL_ACCEPTU1ENA_SHIFT (9U)
#define USB_DCTL_ACCEPTU1ENA(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ACCEPTU1ENA_SHIFT)) & USB_DCTL_ACCEPTU1ENA_MASK)
#define USB_DCTL_INITU1ENA_MASK (0x400U)
#define USB_DCTL_INITU1ENA_SHIFT (10U)
#define USB_DCTL_INITU1ENA(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_INITU1ENA_SHIFT)) & USB_DCTL_INITU1ENA_MASK)
#define USB_DCTL_ACCEPTU2ENA_MASK (0x800U)
#define USB_DCTL_ACCEPTU2ENA_SHIFT (11U)
#define USB_DCTL_ACCEPTU2ENA(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_ACCEPTU2ENA_SHIFT)) & USB_DCTL_ACCEPTU2ENA_MASK)
#define USB_DCTL_INITU2ENA_MASK (0x1000U)
#define USB_DCTL_INITU2ENA_SHIFT (12U)
#define USB_DCTL_INITU2ENA(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_INITU2ENA_SHIFT)) & USB_DCTL_INITU2ENA_MASK)
#define USB_DCTL_CSS_MASK (0x10000U)
#define USB_DCTL_CSS_SHIFT (16U)
#define USB_DCTL_CSS(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CSS_SHIFT)) & USB_DCTL_CSS_MASK)
#define USB_DCTL_CRS_MASK (0x20000U)
#define USB_DCTL_CRS_SHIFT (17U)
#define USB_DCTL_CRS(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CRS_SHIFT)) & USB_DCTL_CRS_MASK)
#define USB_DCTL_L1HIBERNATIONEN_MASK (0x40000U)
#define USB_DCTL_L1HIBERNATIONEN_SHIFT (18U)
#define USB_DCTL_L1HIBERNATIONEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_L1HIBERNATIONEN_SHIFT)) & USB_DCTL_L1HIBERNATIONEN_MASK)
#define USB_DCTL_KEEPCONNECT_MASK (0x80000U)
#define USB_DCTL_KEEPCONNECT_SHIFT (19U)
#define USB_DCTL_KEEPCONNECT(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_KEEPCONNECT_SHIFT)) & USB_DCTL_KEEPCONNECT_MASK)
#define USB_DCTL_LPM_NYET_THRES_MASK (0xF00000U)
#define USB_DCTL_LPM_NYET_THRES_SHIFT (20U)
#define USB_DCTL_LPM_NYET_THRES(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_LPM_NYET_THRES_SHIFT)) & USB_DCTL_LPM_NYET_THRES_MASK)
#define USB_DCTL_HIRDTHRES_MASK (0x1F000000U)
#define USB_DCTL_HIRDTHRES_SHIFT (24U)
#define USB_DCTL_HIRDTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_HIRDTHRES_SHIFT)) & USB_DCTL_HIRDTHRES_MASK)
#define USB_DCTL_CSFTRST_MASK (0x40000000U)
#define USB_DCTL_CSFTRST_SHIFT (30U)
#define USB_DCTL_CSFTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_CSFTRST_SHIFT)) & USB_DCTL_CSFTRST_MASK)
#define USB_DCTL_RUN_STOP_MASK (0x80000000U)
#define USB_DCTL_RUN_STOP_SHIFT (31U)
#define USB_DCTL_RUN_STOP(x) (((uint32_t)(((uint32_t)(x)) << USB_DCTL_RUN_STOP_SHIFT)) & USB_DCTL_RUN_STOP_MASK)
/*! @} */
/*! @name DEVTEN - Device Event Enable Register */
/*! @{ */
#define USB_DEVTEN_DISSCONNEVTEN_MASK (0x1U)
#define USB_DEVTEN_DISSCONNEVTEN_SHIFT (0U)
#define USB_DEVTEN_DISSCONNEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_DISSCONNEVTEN_SHIFT)) & USB_DEVTEN_DISSCONNEVTEN_MASK)
#define USB_DEVTEN_USBRSTEVTEN_MASK (0x2U)
#define USB_DEVTEN_USBRSTEVTEN_SHIFT (1U)
#define USB_DEVTEN_USBRSTEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_USBRSTEVTEN_SHIFT)) & USB_DEVTEN_USBRSTEVTEN_MASK)
#define USB_DEVTEN_CONNECTDONEEVTEN_MASK (0x4U)
#define USB_DEVTEN_CONNECTDONEEVTEN_SHIFT (2U)
#define USB_DEVTEN_CONNECTDONEEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_CONNECTDONEEVTEN_SHIFT)) & USB_DEVTEN_CONNECTDONEEVTEN_MASK)
#define USB_DEVTEN_ULSTCNGEN_MASK (0x8U)
#define USB_DEVTEN_ULSTCNGEN_SHIFT (3U)
#define USB_DEVTEN_ULSTCNGEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ULSTCNGEN_SHIFT)) & USB_DEVTEN_ULSTCNGEN_MASK)
#define USB_DEVTEN_WKUPEVTEN_MASK (0x10U)
#define USB_DEVTEN_WKUPEVTEN_SHIFT (4U)
#define USB_DEVTEN_WKUPEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_WKUPEVTEN_SHIFT)) & USB_DEVTEN_WKUPEVTEN_MASK)
#define USB_DEVTEN_HIBERNATIONREQEVTEN_MASK (0x20U)
#define USB_DEVTEN_HIBERNATIONREQEVTEN_SHIFT (5U)
#define USB_DEVTEN_HIBERNATIONREQEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_HIBERNATIONREQEVTEN_SHIFT)) & USB_DEVTEN_HIBERNATIONREQEVTEN_MASK)
#define USB_DEVTEN_U3L2L1SUSPEN_MASK (0x40U)
#define USB_DEVTEN_U3L2L1SUSPEN_SHIFT (6U)
#define USB_DEVTEN_U3L2L1SUSPEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_U3L2L1SUSPEN_SHIFT)) & USB_DEVTEN_U3L2L1SUSPEN_MASK)
#define USB_DEVTEN_SOFTEVTEN_MASK (0x80U)
#define USB_DEVTEN_SOFTEVTEN_SHIFT (7U)
#define USB_DEVTEN_SOFTEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_SOFTEVTEN_SHIFT)) & USB_DEVTEN_SOFTEVTEN_MASK)
#define USB_DEVTEN_L1SUSPEN_MASK (0x100U)
#define USB_DEVTEN_L1SUSPEN_SHIFT (8U)
#define USB_DEVTEN_L1SUSPEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_L1SUSPEN_SHIFT)) & USB_DEVTEN_L1SUSPEN_MASK)
#define USB_DEVTEN_ERRTICERREVTEN_MASK (0x200U)
#define USB_DEVTEN_ERRTICERREVTEN_SHIFT (9U)
#define USB_DEVTEN_ERRTICERREVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ERRTICERREVTEN_SHIFT)) & USB_DEVTEN_ERRTICERREVTEN_MASK)
#define USB_DEVTEN_VENDEVTSTRCVDEN_MASK (0x1000U)
#define USB_DEVTEN_VENDEVTSTRCVDEN_SHIFT (12U)
#define USB_DEVTEN_VENDEVTSTRCVDEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_VENDEVTSTRCVDEN_SHIFT)) & USB_DEVTEN_VENDEVTSTRCVDEN_MASK)
#define USB_DEVTEN_L1WKUPEVTEN_MASK (0x4000U)
#define USB_DEVTEN_L1WKUPEVTEN_SHIFT (14U)
#define USB_DEVTEN_L1WKUPEVTEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_L1WKUPEVTEN_SHIFT)) & USB_DEVTEN_L1WKUPEVTEN_MASK)
#define USB_DEVTEN_ECCERREN_MASK (0x10000U)
#define USB_DEVTEN_ECCERREN_SHIFT (16U)
#define USB_DEVTEN_ECCERREN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVTEN_ECCERREN_SHIFT)) & USB_DEVTEN_ECCERREN_MASK)
/*! @} */
/*! @name DSTS - Device Status Register */
/*! @{ */
#define USB_DSTS_CONNECTSPD_MASK (0x7U)
#define USB_DSTS_CONNECTSPD_SHIFT (0U)
/*! CONNECTSPD
* 0b001..
* 0b000..
* 0b100..
*/
#define USB_DSTS_CONNECTSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_CONNECTSPD_SHIFT)) & USB_DSTS_CONNECTSPD_MASK)
#define USB_DSTS_SOFFN_MASK (0x1FFF8U)
#define USB_DSTS_SOFFN_SHIFT (3U)
#define USB_DSTS_SOFFN(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SOFFN_SHIFT)) & USB_DSTS_SOFFN_MASK)
#define USB_DSTS_RXFIFOEMPTY_MASK (0x20000U)
#define USB_DSTS_RXFIFOEMPTY_SHIFT (17U)
#define USB_DSTS_RXFIFOEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_RXFIFOEMPTY_SHIFT)) & USB_DSTS_RXFIFOEMPTY_MASK)
#define USB_DSTS_USBLNKST_MASK (0x3C0000U)
#define USB_DSTS_USBLNKST_SHIFT (18U)
#define USB_DSTS_USBLNKST(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_USBLNKST_SHIFT)) & USB_DSTS_USBLNKST_MASK)
#define USB_DSTS_DEVCTRLHLT_MASK (0x400000U)
#define USB_DSTS_DEVCTRLHLT_SHIFT (22U)
#define USB_DSTS_DEVCTRLHLT(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_DEVCTRLHLT_SHIFT)) & USB_DSTS_DEVCTRLHLT_MASK)
#define USB_DSTS_COREIDLE_MASK (0x800000U)
#define USB_DSTS_COREIDLE_SHIFT (23U)
#define USB_DSTS_COREIDLE(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_COREIDLE_SHIFT)) & USB_DSTS_COREIDLE_MASK)
#define USB_DSTS_SSS_MASK (0x1000000U)
#define USB_DSTS_SSS_SHIFT (24U)
#define USB_DSTS_SSS(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SSS_SHIFT)) & USB_DSTS_SSS_MASK)
#define USB_DSTS_RSS_MASK (0x2000000U)
#define USB_DSTS_RSS_SHIFT (25U)
#define USB_DSTS_RSS(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_RSS_SHIFT)) & USB_DSTS_RSS_MASK)
#define USB_DSTS_SRE_MASK (0x10000000U)
#define USB_DSTS_SRE_SHIFT (28U)
#define USB_DSTS_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_SRE_SHIFT)) & USB_DSTS_SRE_MASK)
#define USB_DSTS_DCNRD_MASK (0x20000000U)
#define USB_DSTS_DCNRD_SHIFT (29U)
#define USB_DSTS_DCNRD(x) (((uint32_t)(((uint32_t)(x)) << USB_DSTS_DCNRD_SHIFT)) & USB_DSTS_DCNRD_MASK)
/*! @} */
/*! @name DGCMDPAR - Device Generic Command Parameter Register */
/*! @{ */
#define USB_DGCMDPAR_PARAMETER_MASK (0xFFFFFFFFU)
#define USB_DGCMDPAR_PARAMETER_SHIFT (0U)
#define USB_DGCMDPAR_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB_DGCMDPAR_PARAMETER_SHIFT)) & USB_DGCMDPAR_PARAMETER_MASK)
/*! @} */
/*! @name DGCMD - */
/*! @{ */
#define USB_DGCMD_CMDTYP_MASK (0xFFU)
#define USB_DGCMD_CMDTYP_SHIFT (0U)
#define USB_DGCMD_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDTYP_SHIFT)) & USB_DGCMD_CMDTYP_MASK)
#define USB_DGCMD_CMDIOC_MASK (0x100U)
#define USB_DGCMD_CMDIOC_SHIFT (8U)
#define USB_DGCMD_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDIOC_SHIFT)) & USB_DGCMD_CMDIOC_MASK)
#define USB_DGCMD_CMDACT_MASK (0x400U)
#define USB_DGCMD_CMDACT_SHIFT (10U)
#define USB_DGCMD_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDACT_SHIFT)) & USB_DGCMD_CMDACT_MASK)
#define USB_DGCMD_CMDSTATUS_MASK (0xF000U)
#define USB_DGCMD_CMDSTATUS_SHIFT (12U)
#define USB_DGCMD_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DGCMD_CMDSTATUS_SHIFT)) & USB_DGCMD_CMDSTATUS_MASK)
/*! @} */
/*! @name DALEPENA - Device Active USB Endpoint Enable Register */
/*! @{ */
#define USB_DALEPENA_USBACTEP_MASK (0xFFFFFFFFU)
#define USB_DALEPENA_USBACTEP_SHIFT (0U)
#define USB_DALEPENA_USBACTEP(x) (((uint32_t)(((uint32_t)(x)) << USB_DALEPENA_USBACTEP_SHIFT)) & USB_DALEPENA_USBACTEP_MASK)
/*! @} */
/*! @name DEPCMDPAR2 - Device physical endpoint-n command parameter 2 register */
/*! @{ */
#define USB_DEPCMDPAR2_PARAMETER_MASK (0xFFFFFFFFU)
#define USB_DEPCMDPAR2_PARAMETER_SHIFT (0U)
#define USB_DEPCMDPAR2_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR2_PARAMETER_SHIFT)) & USB_DEPCMDPAR2_PARAMETER_MASK)
/*! @} */
/*! @name DEPCMDPAR1 - Device Physical Endpoint-n Command Parameter 1 Register */
/*! @{ */
#define USB_DEPCMDPAR1_PARAMETER_MASK (0xFFFFFFFFU)
#define USB_DEPCMDPAR1_PARAMETER_SHIFT (0U)
#define USB_DEPCMDPAR1_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR1_PARAMETER_SHIFT)) & USB_DEPCMDPAR1_PARAMETER_MASK)
/*! @} */
/*! @name DEPCMDPAR0 - Device Physical Endpoint-n Command Parameter 0 Register */
/*! @{ */
#define USB_DEPCMDPAR0_PARAMETER_MASK (0xFFFFFFFFU)
#define USB_DEPCMDPAR0_PARAMETER_SHIFT (0U)
#define USB_DEPCMDPAR0_PARAMETER(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMDPAR0_PARAMETER_SHIFT)) & USB_DEPCMDPAR0_PARAMETER_MASK)
/*! @} */
/*! @name DEPCMD - Device Physical Endpoint-n Command Register */
/*! @{ */
#define USB_DEPCMD_CMDTYP_MASK (0xFU)
#define USB_DEPCMD_CMDTYP_SHIFT (0U)
#define USB_DEPCMD_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDTYP_SHIFT)) & USB_DEPCMD_CMDTYP_MASK)
#define USB_DEPCMD_CMDIOC_MASK (0x100U)
#define USB_DEPCMD_CMDIOC_SHIFT (8U)
#define USB_DEPCMD_CMDIOC(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDIOC_SHIFT)) & USB_DEPCMD_CMDIOC_MASK)
#define USB_DEPCMD_CMDACT_MASK (0x400U)
#define USB_DEPCMD_CMDACT_SHIFT (10U)
#define USB_DEPCMD_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDACT_SHIFT)) & USB_DEPCMD_CMDACT_MASK)
#define USB_DEPCMD_HIPRI_FORCERM_MASK (0x800U)
#define USB_DEPCMD_HIPRI_FORCERM_SHIFT (11U)
#define USB_DEPCMD_HIPRI_FORCERM(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_HIPRI_FORCERM_SHIFT)) & USB_DEPCMD_HIPRI_FORCERM_MASK)
#define USB_DEPCMD_CMDSTATUS_MASK (0xF000U)
#define USB_DEPCMD_CMDSTATUS_SHIFT (12U)
#define USB_DEPCMD_CMDSTATUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_CMDSTATUS_SHIFT)) & USB_DEPCMD_CMDSTATUS_MASK)
#define USB_DEPCMD_COMMANDPARAM_MASK (0xFFFF0000U)
#define USB_DEPCMD_COMMANDPARAM_SHIFT (16U)
#define USB_DEPCMD_COMMANDPARAM(x) (((uint32_t)(((uint32_t)(x)) << USB_DEPCMD_COMMANDPARAM_SHIFT)) & USB_DEPCMD_COMMANDPARAM_MASK)
/*! @} */
/*! @name DEV_IMOD - Device Interrupt Moderation Register */
/*! @{ */
#define USB_DEV_IMOD_DEVICE_IMODI_MASK (0xFFFFU)
#define USB_DEV_IMOD_DEVICE_IMODI_SHIFT (0U)
#define USB_DEV_IMOD_DEVICE_IMODI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEV_IMOD_DEVICE_IMODI_SHIFT)) & USB_DEV_IMOD_DEVICE_IMODI_MASK)
#define USB_DEV_IMOD_DEVICE_IMODC_MASK (0xFFFF0000U)
#define USB_DEV_IMOD_DEVICE_IMODC_SHIFT (16U)
#define USB_DEV_IMOD_DEVICE_IMODC(x) (((uint32_t)(((uint32_t)(x)) << USB_DEV_IMOD_DEVICE_IMODC_SHIFT)) & USB_DEV_IMOD_DEVICE_IMODC_MASK)
/*! @} */
/*! @name BCFG - BCFG */
/*! @{ */
#define USB_BCFG_CHIRP_EN_MASK (0x1U)
#define USB_BCFG_CHIRP_EN_SHIFT (0U)
#define USB_BCFG_CHIRP_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_BCFG_CHIRP_EN_SHIFT)) & USB_BCFG_CHIRP_EN_MASK)
#define USB_BCFG_IDDIG_SEL_MASK (0x2U)
#define USB_BCFG_IDDIG_SEL_SHIFT (1U)
#define USB_BCFG_IDDIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << USB_BCFG_IDDIG_SEL_SHIFT)) & USB_BCFG_IDDIG_SEL_MASK)
/*! @} */
/*! @name BCEVT - BCEVT */
/*! @{ */
#define USB_BCEVT_MULTVALIDBC_MASK (0x1FU)
#define USB_BCEVT_MULTVALIDBC_SHIFT (0U)
#define USB_BCEVT_MULTVALIDBC(x) (((uint32_t)(((uint32_t)(x)) << USB_BCEVT_MULTVALIDBC_SHIFT)) & USB_BCEVT_MULTVALIDBC_MASK)
#define USB_BCEVT_MV_CHNGEVNT_MASK (0x1000000U)
#define USB_BCEVT_MV_CHNGEVNT_SHIFT (24U)
#define USB_BCEVT_MV_CHNGEVNT(x) (((uint32_t)(((uint32_t)(x)) << USB_BCEVT_MV_CHNGEVNT_SHIFT)) & USB_BCEVT_MV_CHNGEVNT_MASK)
/*! @} */
/*! @name BCEVTEN - BCEVTEN */
/*! @{ */
#define USB_BCEVTEN_MV_CHNGEVNTENA_MASK (0x1000000U)
#define USB_BCEVTEN_MV_CHNGEVNTENA_SHIFT (24U)
#define USB_BCEVTEN_MV_CHNGEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << USB_BCEVTEN_MV_CHNGEVNTENA_SHIFT)) & USB_BCEVTEN_MV_CHNGEVNTENA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB1 base address */
#define USB1_BASE (0x38100000u)
/** Peripheral USB1 base pointer */
#define USB1 ((USB_Type *)USB1_BASE)
/** Peripheral USB2 base address */
#define USB2_BASE (0x38200000u)
/** Peripheral USB2 base pointer */
#define USB2 ((USB_Type *)USB2_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { USB1_BASE, USB2_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { USB1, USB2 }
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USDHC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
* @{
*/
/** USDHC - Register Layout Typedef */
typedef struct {
__IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
__IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
__IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
__IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
__I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
__I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
__I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
__I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
__IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
__I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
__IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
__IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
__IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
__IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
__IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
__IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
__IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
__IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
uint8_t RESERVED_0[4];
__O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
__I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */
__IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
uint8_t RESERVED_1[4];
__IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
__I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
__IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
uint8_t RESERVED_2[4];
__IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */
__I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */
uint8_t RESERVED_3[72];
__IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
__IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */
__IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
__IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */
uint8_t RESERVED_4[48];
__I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */
__I uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */
__IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */
__IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */
__IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */
__IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */
__IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */
__IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */
__IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */
__IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */
__IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */
__IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */
__I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */
__I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */
__IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */
uint8_t RESERVED_5[4];
__IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */
__IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */
__I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */
uint8_t RESERVED_6[4];
__IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */
__I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */
__I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */
__I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */
} USDHC_Type;
/* ----------------------------------------------------------------------------
-- USDHC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Register_Masks USDHC Register Masks
* @{
*/
/*! @name DS_ADDR - DMA System Address */
/*! @{ */
#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
/*! DS_ADDR - System address
*/
#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */
/*! @name BLK_ATT - Block Attributes */
/*! @{ */
#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
/*! BLKSIZE - Transfer block size
* 0b1000000000000..4096 bytes
* 0b0100000000000..2048 bytes
* 0b0001000000000..512 bytes
* 0b0000111111111..511 bytes
* 0b0000000000100..4 bytes
* 0b0000000000011..3 bytes
* 0b0000000000010..2 bytes
* 0b0000000000001..1 byte
* 0b0000000000000..No data transfer
*/
#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
/*! BLKCNT - Blocks count for current transfer
* 0b1111111111111111..65535 blocks
* 0b0000000000000010..2 blocks
* 0b0000000000000001..1 block
* 0b0000000000000000..Stop count
*/
#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */
/*! @name CMD_ARG - Command Argument */
/*! @{ */
#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
/*! CMDARG - Command argument
*/
#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */
/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
/*! RSPTYP - Response type select
* 0b00..No response
* 0b01..Response length 136
* 0b10..Response length 48
* 0b11..Response length 48, check busy after response
*/
#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
/*! CCCEN - Command CRC check enable
* 0b1..Enables command CRC check
* 0b0..Disables command CRC check
*/
#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
/*! CICEN - Command index check enable
* 0b1..Enables command index check
* 0b0..Disable command index check
*/
#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
/*! DPSEL - Data present select
* 0b1..Data present
* 0b0..No data present
*/
#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
/*! CMDTYP - Command type
* 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
* 0b10..Resume CMD52 for writing function select in CCCR
* 0b01..Suspend CMD52 for writing bus suspend in CCCR
* 0b00..Normal other commands
*/
#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
/*! CMDINX - Command index
*/
#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */
/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */
#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
/*! CMDRSP0 - Command response 0
*/
#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */
/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */
#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
/*! CMDRSP1 - Command response 1
*/
#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */
/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */
#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
/*! CMDRSP2 - Command response 2
*/
#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */
/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */
#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
/*! CMDRSP3 - Command response 3
*/
#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */
/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
/*! DATCONT - Data content
*/
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */
/*! @name PRES_STATE - Present State */
/*! @{ */
#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
/*! CIHB - Command inhibit (CMD)
* 0b1..Cannot issue command
* 0b0..Can issue command using only CMD line
*/
#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
/*! CDIHB - Command Inhibit Data (DATA)
* 0b1..Cannot issue command that uses the DATA line
* 0b0..Can issue command that uses the DATA line
*/
#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define USDHC_PRES_STATE_DLA_MASK (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT (2U)
/*! DLA - Data line active
* 0b1..DATA line active
* 0b0..DATA line inactive
*/
#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
/*! SDSTB - SD clock stable
* 0b1..Clock is stable.
* 0b0..Clock is changing frequency and not stable.
*/
#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
/*! IPGOFF - Peripheral clock gated off internally
* 0b1..Peripheral clock is gated off.
* 0b0..Peripheral clock is active.
*/
#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
/*! HCKOFF - HCLK gated off internally
* 0b1..HCLK is gated off.
* 0b0..HCLK is active.
*/
#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
/*! PEROFF - IPG_PERCLK gated off internally
* 0b1..IPG_PERCLK is gated off.
* 0b0..IPG_PERCLK is active.
*/
#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
/*! SDOFF - SD clock gated off internally
* 0b1..SD clock is gated off.
* 0b0..SD clock is active.
*/
#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define USDHC_PRES_STATE_WTA_MASK (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT (8U)
/*! WTA - Write transfer active
* 0b1..Transferring data
* 0b0..No valid data
*/
#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define USDHC_PRES_STATE_RTA_MASK (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT (9U)
/*! RTA - Read transfer active
* 0b1..Transferring data
* 0b0..No valid data
*/
#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
/*! BWEN - Buffer write enable
* 0b1..Write enable
* 0b0..Write disable
*/
#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define USDHC_PRES_STATE_BREN_MASK (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT (11U)
/*! BREN - Buffer read enable
* 0b1..Read enable
* 0b0..Read disable
*/
#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT (12U)
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
* 0b1..Sampling clock needs re-tuning
* 0b0..Fixed or well tuned sampling clock
*/
#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
/*! TSCD - Tap select change done
* 0b1..Delay cell select change is finished.
* 0b0..Delay cell select change is not finished.
*/
#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT (16U)
/*! CINST - Card inserted
* 0b1..Card inserted
* 0b0..Power on reset or no card
*/
#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
/*! CDPL - Card detect pin level
* 0b1..Card present (CD_B = 0)
* 0b0..No card present (CD_B = 1)
*/
#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
/*! WPSPL - Write protect switch pin level
* 0b1..Write enabled (WP = 0)
* 0b0..Write protected (WP = 1)
*/
#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
/*! CLSL - CMD line signal level
*/
#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
/*! DLSL - DATA[7:0] line signal level
* 0b00000111..Data 7 line signal level
* 0b00000110..Data 6 line signal level
* 0b00000101..Data 5 line signal level
* 0b00000100..Data 4 line signal level
* 0b00000011..Data 3 line signal level
* 0b00000010..Data 2 line signal level
* 0b00000001..Data 1 line signal level
* 0b00000000..Data 0 line signal level
*/
#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */
/*! @name PROT_CTRL - Protocol Control */
/*! @{ */
#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
/*! DTW - Data transfer width
* 0b10..8-bit mode
* 0b01..4-bit mode
* 0b00..1-bit mode
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
/*! D3CD - DATA3 as card detection pin
* 0b1..DATA3 as card detection pin
* 0b0..DATA3 does not monitor card insertion
*/
#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
/*! EMODE - Endian mode
* 0b00..Big endian mode
* 0b01..Half word big endian mode
* 0b10..Little endian mode
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
/*! CDTL - Card detect test level
* 0b1..Card detect test level is 1, card inserted
* 0b0..Card detect test level is 0, no card inserted
*/
#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
/*! CDSS - Card detect signal selection
* 0b1..Card detection test level is selected (for test purpose).
* 0b0..Card detection level is selected (for normal purpose).
*/
#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
/*! DMASEL - DMA select
* 0b00..No DMA or simple DMA is selected.
* 0b01..ADMA1 is selected.
* 0b10..ADMA2 is selected.
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
/*! SABGREQ - Stop at block gap request
* 0b1..Stop
* 0b0..Transfer
*/
#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
/*! CREQ - Continue request
* 0b1..Restart
* 0b0..No effect
*/
#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
/*! RWCTL - Read wait control
* 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
* 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
*/
#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
/*! IABG - Interrupt at block gap
* 0b1..Enables interrupt at block gap
* 0b0..Disables interrupt at block gap
*/
#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
/*! RD_DONE_NO_8CLK - Read performed number 8 clock
*/
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
/*! WECINT - Wakeup event enable on card interrupt
* 0b1..Enables wakeup event enable on card interrupt
* 0b0..Disables wakeup event enable on card interrupt
*/
#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
/*! WECINS - Wakeup event enable on SD card insertion
* 0b1..Enable wakeup event enable on SD card insertion
* 0b0..Disable wakeup event enable on SD card insertion
*/
#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
/*! WECRM - Wakeup event enable on SD card removal
* 0b1..Enables wakeup event enable on SD card removal
* 0b0..Disables wakeup event enable on SD card removal
*/
#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
/*! NON_EXACT_BLK_RD - Non-exact block read
* 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
* 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
*/
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
/*! @} */
/*! @name SYS_CTRL - System Control */
/*! @{ */
#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
/*! DVS - Divisor
* 0b0000..Divide-by-1
* 0b0001..Divide-by-2
* 0b1110..Divide-by-15
* 0b1111..Divide-by-16
*/
#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
/*! SDCLKFS - SDCLK frequency select
*/
#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
/*! DTOCV - Data timeout counter value
* 0b1111..SDCLK x 2 31 recommend to use for HS400 mode
* 0b1110..SDCLK x 2 30 recommend to use for HS200/SDR104 mode
* 0b1101..SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode
* 0b0011..SDCLK x 2 19
* 0b0010..SDCLK x 2 18
* 0b0001..SDCLK x 2 33
* 0b0000..SDCLK x 2 32
*/
#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
/*! IPP_RST_N - Hardware reset
*/
#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
/*! RSTA - Software reset for all
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
/*! RSTC - Software reset for CMD line
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
/*! RSTD - Software reset for data line
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
/*! INITA - Initialization active
*/
#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
/*! RSTT - Reset tuning
*/
#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status */
/*! @{ */
#define USDHC_INT_STATUS_CC_MASK (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT (0U)
/*! CC - Command complete
* 0b1..Command complete
* 0b0..Command not complete
*/
#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define USDHC_INT_STATUS_TC_MASK (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT (1U)
/*! TC - Transfer complete
* 0b1..Transfer complete
* 0b0..Transfer does not complete
*/
#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define USDHC_INT_STATUS_BGE_MASK (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT (2U)
/*! BGE - Block gap event
* 0b1..Transaction stopped at block gap
* 0b0..No block gap event
*/
#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define USDHC_INT_STATUS_DINT_MASK (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT (3U)
/*! DINT - DMA interrupt
* 0b1..DMA interrupt is generated.
* 0b0..No DMA interrupt
*/
#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define USDHC_INT_STATUS_BWR_MASK (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT (4U)
/*! BWR - Buffer write ready
* 0b1..Ready to write buffer
* 0b0..Not ready to write buffer
*/
#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define USDHC_INT_STATUS_BRR_MASK (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT (5U)
/*! BRR - Buffer read ready
* 0b1..Ready to read buffer
* 0b0..Not ready to read buffer
*/
#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define USDHC_INT_STATUS_CINS_MASK (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT (6U)
/*! CINS - Card insertion
* 0b1..Card inserted
* 0b0..Card state unstable or removed
*/
#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define USDHC_INT_STATUS_CRM_MASK (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT (7U)
/*! CRM - Card removal
* 0b1..Card removed
* 0b0..Card state unstable or inserted
*/
#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define USDHC_INT_STATUS_CINT_MASK (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT (8U)
/*! CINT - Card interrupt
* 0b1..Generate card interrupt
* 0b0..No card interrupt
*/
#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT (12U)
/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
* 0b1..Re-tuning should be performed.
* 0b0..Re-tuning is not required.
*/
#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define USDHC_INT_STATUS_TP_MASK (0x2000U)
#define USDHC_INT_STATUS_TP_SHIFT (13U)
/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
*/
#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define USDHC_INT_STATUS_CQI_MASK (0x4000U)
#define USDHC_INT_STATUS_CQI_SHIFT (14U)
/*! CQI - Command queuing interrupt
*/
#define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK)
#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
/*! CTOE - Command timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT (17U)
/*! CCE - Command CRC error
* 0b1..CRC error generated
* 0b0..No error
*/
#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
/*! CEBE - Command end bit error
* 0b1..End bit error generated
* 0b0..No error
*/
#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT (19U)
/*! CIE - Command index error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
/*! DTOE - Data timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT (21U)
/*! DCE - Data CRC error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
/*! DEBE - Data end bit error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
/*! AC12E - Auto CMD12 error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT (26U)
/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
*/
#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
/*! DMAE - DMA error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */
/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */
#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
/*! CCSEN - Command complete status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
/*! TCSEN - Transfer complete status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
/*! BGESEN - Block gap event status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
/*! DINTSEN - DMA interrupt status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
/*! BWRSEN - Buffer write ready status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
/*! BRRSEN - Buffer read ready status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
/*! CINSSEN - Card insertion status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
/*! CRMSEN - Card removal status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
/*! CINTSEN - Card interrupt status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
/*! RTESEN - Re-tuning event status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U)
/*! TPSEN - Tuning pass status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U)
#define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U)
/*! CQISEN - Command queuing status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK)
#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
/*! CTOESEN - Command timeout error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
/*! CCESEN - Command CRC error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
/*! CEBESEN - Command end bit error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
/*! CIESEN - Command index error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
/*! DTOESEN - Data timeout error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
/*! DCESEN - Data CRC error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
/*! DEBESEN - Data end bit error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
/*! AC12ESEN - Auto CMD12 error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
/*! TNESEN - Tuning error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
/*! DMAESEN - DMA error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */
/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
/*! CCIEN - Command complete interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
/*! TCIEN - Transfer complete interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
/*! BGEIEN - Block gap event interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
/*! DINTIEN - DMA interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
/*! BWRIEN - Buffer write ready interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
/*! BRRIEN - Buffer read ready interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
/*! CINSIEN - Card insertion interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
/*! CRMIEN - Card removal interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
/*! CINTIEN - Card interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
/*! RTEIEN - Re-tuning event interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U)
/*! TPIEN - Tuning pass interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U)
#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U)
/*! CQIIEN - Command queuing signal enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
/*! CTOEIEN - Command timeout error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
/*! CCEIEN - Command CRC error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
/*! CEBEIEN - Command end bit error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
/*! CIEIEN - Command index error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
/*! DTOEIEN - Data timeout error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
/*! DCEIEN - Data CRC error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
/*! DEBEIEN - Data end bit error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
/*! AC12EIEN - Auto CMD12 error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
/*! TNEIEN - Tuning error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
/*! DMAEIEN - DMA error interrupt enable
* 0b1..Enable
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */
/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
/*! AC12NE - Auto CMD12 not executed
* 0b1..Not executed
* 0b0..Executed
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
/*! AC12EBE - Auto CMD12 / 23 end bit error
* 0b1..End bit error generated
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
/*! AC12CE - Auto CMD12 / 23 CRC error
* 0b1..CRC error met in Auto CMD12/23 response
* 0b0..No CRC error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
/*! AC12IE - Auto CMD12 / 23 index error
* 0b1..Error, the CMD index in response is not CMD12/23
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command not issued by Auto CMD12 error
* 0b1..Not issued
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
/*! EXECUTE_TUNING - Execute tuning
* 0b1..Start tuning procedure
* 0b0..Tuning procedure is aborted
*/
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Sample clock select
* 0b1..Tuned clock is used to sample data
* 0b0..Fixed clock is used to sample data
*/
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */
/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
/*! SDR50_SUPPORT - SDR50 support
*/
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
/*! SDR104_SUPPORT - SDR104 support
*/
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
/*! DDR50_SUPPORT - DDR50 support
*/
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
/*! USE_TUNING_SDR50 - Use Tuning for SDR50
* 0b1..SDR50 supports tuning
* 0b0..SDR50 does not support tuning
*/
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
/*! MBL - Max block length
* 0b000..512 bytes
* 0b001..1024 bytes
* 0b010..2048 bytes
* 0b011..4096 bytes
*/
#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
/*! ADMAS - ADMA support
* 0b1..Advanced DMA supported
* 0b0..Advanced DMA not supported
*/
#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
/*! HSS - High speed support
* 0b1..High speed supported
* 0b0..High speed not supported
*/
#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
/*! DMAS - DMA support
* 0b1..DMA supported
* 0b0..DMA not supported
*/
#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
/*! SRS - Suspend / resume support
* 0b1..Supported
* 0b0..Not supported
*/
#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
/*! VS33 - Voltage support 3.3 V
* 0b1..3.3 V supported
* 0b0..3.3 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
/*! VS30 - Voltage support 3.0 V
* 0b1..3.0 V supported
* 0b0..3.0 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
/*! VS18 - Voltage support 1.8 V
* 0b1..1.8 V supported
* 0b0..1.8 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */
/*! @name WTMK_LVL - Watermark Level */
/*! @{ */
#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
/*! RD_WML - Read watermark level
*/
#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
/*! WR_WML - Write watermark level
*/
#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
/*! @} */
/*! @name MIX_CTRL - Mixer Control */
/*! @{ */
#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
/*! DMAEN - DMA enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
/*! BCEN - Block count enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
/*! AC12EN - Auto CMD12 enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
/*! DDR_EN - Dual data rate mode selection
*/
#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
/*! DTDSEL - Data transfer direction select
* 0b1..Read (Card to host)
* 0b0..Write (Host to card)
*/
#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
/*! MSBSEL - Multi / Single block select
* 0b1..Multiple blocks
* 0b0..Single block
*/
#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
/*! NIBBLE_POS - Nibble position indication
*/
#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
/*! AC23EN - Auto CMD23 enable
*/
#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
* 0b1..Execute tuning
* 0b0..Not tuned or tuning completed
*/
#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Clock selection
* 0b1..Tuned clock is used to sample data / cmd
* 0b0..Fixed clock is used to sample data / cmd
*/
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
* 0b1..Enable auto tuning
* 0b0..Disable auto tuning
*/
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
* 0b1..Feedback clock comes from the ipp_card_clk_out
* 0b0..Feedback clock comes from the loopback CLK
*/
#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
/*! HS400_MODE - Enable HS400 mode
*/
#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U)
#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U)
/*! EN_HS400_MODE - Enable enhance HS400 mode
*/
#define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK)
/*! @} */
/*! @name FORCE_EVENT - Force Event */
/*! @{ */
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
/*! FEVTAC12NE - Force event auto command 12 not executed
*/
#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
/*! FEVTAC12TOE - Force event auto command 12 time out error
*/
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
/*! FEVTAC12CE - Force event auto command 12 CRC error
*/
#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
/*! FEVTAC12EBE - Force event Auto Command 12 end bit error
*/
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
/*! FEVTAC12IE - Force event Auto Command 12 index error
*/
#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
*/
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
/*! FEVTCTOE - Force event command time out error
*/
#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
/*! FEVTCCE - Force event command CRC error
*/
#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
/*! FEVTCEBE - Force event command end bit error
*/
#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
/*! FEVTCIE - Force event command index error
*/
#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
/*! FEVTDTOE - Force event data time out error
*/
#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
/*! FEVTDCE - Force event data CRC error
*/
#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
/*! FEVTDEBE - Force event data end bit error
*/
#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
/*! FEVTAC12E - Force event Auto Command 12 error
*/
#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
/*! FEVTTNE - Force tuning error
*/
#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
/*! FEVTDMAE - Force event DMA error
*/
#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
/*! FEVTCINT - Force event card interrupt
*/
#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */
/*! @name ADMA_ERR_STATUS - ADMA Error Status */
/*! @{ */
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
/*! ADMAES - ADMA error state (when ADMA error is occurred)
*/
#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
/*! ADMALME - ADMA length mismatch error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
/*! ADMADCE - ADMA descriptor error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */
/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
/*! ADS_ADDR - ADMA system address
*/
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */
/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
/*! DLL_CTRL_ENABLE - DLL and delay chain
*/
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
/*! DLL_CTRL_RESET - DLL reset
*/
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! DLL_CTRL_GATE_UPDATE - DLL gate update
*/
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
*/
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name DLL_STATUS - DLL Status */
/*! @{ */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! DLL_STS_SLV_LOCK - Slave delay-line lock status
*/
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
/*! DLL_STS_REF_LOCK - Reference DLL lock status
*/
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
/*! DLL_STS_SLV_SEL - Slave delay line select status
*/
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
/*! DLL_STS_REF_SEL - Reference delay line select taps
*/
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */
/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
/*! NXT_ERR - NXT error
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
/*! TAP_SEL_PRE - TAP_SEL_PRE
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
/*! PRE_ERR - PRE error
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */
/*! @name STROBE_DLL_CTRL - Strobe DLL control */
/*! @{ */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name STROBE_DLL_STATUS - Strobe DLL status */
/*! @{ */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */
/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */
#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U)
#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U)
/*! EXT_DMA_EN - External DMA request enable
* 0b0..In any scenario, uSDHC does not send out external DMA request.
* 0b1..When internal DMA is not active, the external DMA request is sent out.
*/
#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK)
#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
/*! VSELECT - Voltage selection
* 0b1..Change the voltage to low voltage range, around 1.8 V
* 0b0..Change the voltage to high voltage range, around 3.0 V
*/
#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
/*! CONFLICT_CHK_EN - Conflict check enable
* 0b0..Conflict check disable
* 0b1..Conflict check enable
*/
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - Check busy enable
* 0b0..Do not check busy after auto CMD12 for write data packet
* 0b1..Check busy after auto CMD12 for write data packet
*/
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
/*! FRC_SDCLK_ON - Force CLK
* 0b0..CLK active or inactive is fully controlled by the hardware.
* 0b1..Force CLK active
*/
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
/*! CRC_CHK_DIS - CRC Check Disable
* 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
* 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
*/
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
/*! CMD_BYTE_EN - Byte access
* 0b0..Disable
* 0b1..Enable
*/
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */
/*! @name MMC_BOOT - MMC Boot */
/*! @{ */
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
/*! DTOCV_ACK - DTOCV_ACK
* 0b0000..SDCLK x 2^32
* 0b0001..SDCLK x 2^33
* 0b0010..SDCLK x 2^18
* 0b0011..SDCLK x 2^19
* 0b0100..SDCLK x 2^20
* 0b0101..SDCLK x 2^21
* 0b0110..SDCLK x 2^22
* 0b0111..SDCLK x 2^23
* 0b1110..SDCLK x 2^30
* 0b1111..SDCLK x 2^31
*/
#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
/*! BOOT_ACK - BOOT ACK
* 0b0..No ack
* 0b1..Ack
*/
#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
/*! BOOT_MODE - Boot mode
* 0b0..Normal boot
* 0b1..Alternative boot
*/
#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
/*! BOOT_EN - Boot enable
* 0b0..Fast boot disable
* 0b1..Fast boot enable
*/
#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
/*! AUTO_SABG_EN - Auto stop at block gap
*/
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
/*! DISABLE_TIME_OUT - Time out
* 0b0..Enable time out
* 0b1..Disable time out
*/
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
*/
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */
/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
/*! CARD_INT_D3_TEST - Card interrupt detection test
* 0b0..Check the card interrupt only when DATA3 is high.
* 0b1..Check the card interrupt by ignoring the status of DATA3.
*/
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
/*! TUNING_8bit_EN - Tuning 8bit enable
*/
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
/*! TUNING_1bit_EN - Tuning 1bit enable
*/
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
/*! TUNING_CMD_EN - Tuning command enable
* 0b0..Auto tuning circuit does not check the CMD line.
* 0b1..Auto tuning circuit checks the CMD line.
*/
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
*/
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
*/
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
* 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
* 0b0..Disable
*/
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U)
#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U)
/*! EN_32K_CLK - Enable 32khz clock for card detection
*/
#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U)
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U)
/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock
*/
#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK)
/*! @} */
/*! @name TUNING_CTRL - Tuning Control */
/*! @{ */
#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
/*! TUNING_START_TAP - Tuning start
*/
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning
*/
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
/*! TUNING_COUNTER - Tuning counter
*/
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
/*! TUNING_STEP - TUNING_STEP
*/
#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
/*! TUNING_WINDOW - Data window
*/
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
/*! STD_TUNING_EN - Standard tuning circuit and procedure enable
*/
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */
/*! @name CQVER - Command Queuing Version */
/*! @{ */
#define USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU)
#define USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U)
/*! VERSION_SUFFIX - e •MMC version suffix
*/
#define USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK)
#define USDHC_CQVER_MINOR_VN_MASK (0xF0U)
#define USDHC_CQVER_MINOR_VN_SHIFT (4U)
/*! MINOR_VN - e •MMC minor version number
*/
#define USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK)
#define USDHC_CQVER_MAJOR_VN_MASK (0xF00U)
#define USDHC_CQVER_MAJOR_VN_SHIFT (8U)
/*! MAJOR_VN - e •MMC major version number
*/
#define USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK)
/*! @} */
/*! @name CQCAP - Command Queuing Capabilities */
/*! @{ */
#define USDHC_CQCAP_ITCFVAL_MASK (0x3FFU)
#define USDHC_CQCAP_ITCFVAL_SHIFT (0U)
/*! ITCFVAL - Internal timer clock frequency value
*/
#define USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK)
#define USDHC_CQCAP_ITCFMUL_MASK (0xF000U)
#define USDHC_CQCAP_ITCFMUL_SHIFT (12U)
/*! ITCFMUL - Internal timer clock frequency multiplier
* 0b0001..0.001 MHz
* 0b0010..0.01 MHz
* 0b0011..0.1 MHz
* 0b0100..1 MHz
* 0b0101..10 MHz
* 0b0110-0b1001..Reserved
*/
#define USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK)
/*! @} */
/*! @name CQCFG - Command Queuing Configuration */
/*! @{ */
#define USDHC_CQCFG_CQUE_MASK (0x1U)
#define USDHC_CQCFG_CQUE_SHIFT (0U)
/*! CQUE - Command queuing enable
*/
#define USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK)
#define USDHC_CQCFG_TDS_MASK (0x100U)
#define USDHC_CQCFG_TDS_SHIFT (8U)
/*! TDS - Task descriptor size
* 0b0..Task descriptor size is 64 bits
* 0b1..Task descriptor size is 128 bits
*/
#define USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK)
#define USDHC_CQCFG_DCMDE_MASK (0x1000U)
#define USDHC_CQCFG_DCMDE_SHIFT (12U)
/*! DCMDE - Direct command (DCMD) enable
* 0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor
* 0b1..Task descriptor in slot #31 is a DCMD Task Descriptor
*/
#define USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK)
/*! @} */
/*! @name CQCTL - Command Queuing Control */
/*! @{ */
#define USDHC_CQCTL_HALT_MASK (0x1U)
#define USDHC_CQCTL_HALT_SHIFT (0U)
/*! HALT - Halt
*/
#define USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK)
#define USDHC_CQCTL_CLEAR_MASK (0x100U)
#define USDHC_CQCTL_CLEAR_SHIFT (8U)
/*! CLEAR - Clear all tasks
*/
#define USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK)
/*! @} */
/*! @name CQIS - Command Queuing Interrupt Status */
/*! @{ */
#define USDHC_CQIS_HAC_MASK (0x1U)
#define USDHC_CQIS_HAC_SHIFT (0U)
/*! HAC - Halt complete interrupt
*/
#define USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK)
#define USDHC_CQIS_TCC_MASK (0x2U)
#define USDHC_CQIS_TCC_SHIFT (1U)
/*! TCC - Task complete interrupt
*/
#define USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK)
#define USDHC_CQIS_RED_MASK (0x4U)
#define USDHC_CQIS_RED_SHIFT (2U)
/*! RED - Response error detected interrupt
*/
#define USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK)
#define USDHC_CQIS_TCL_MASK (0x8U)
#define USDHC_CQIS_TCL_SHIFT (3U)
/*! TCL - Task cleared
*/
#define USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK)
/*! @} */
/*! @name CQISTE - Command Queuing Interrupt Status Enable */
/*! @{ */
#define USDHC_CQISTE_HAC_STE_MASK (0x1U)
#define USDHC_CQISTE_HAC_STE_SHIFT (0U)
/*! HAC_STE - Halt complete status enable
* 0b0..CQIS[HAC] is disabled
* 0b1..CQIS[HAC] is set when its interrupt condition is active
*/
#define USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK)
#define USDHC_CQISTE_TCC_STE_MASK (0x2U)
#define USDHC_CQISTE_TCC_STE_SHIFT (1U)
/*! TCC_STE - Task complete status enable
* 0b0..CQIS[TCC] is disabled
* 0b1..CQIS[TCC] is set when its interrupt condition is active
*/
#define USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK)
#define USDHC_CQISTE_RED_STE_MASK (0x4U)
#define USDHC_CQISTE_RED_STE_SHIFT (2U)
/*! RED_STE - Response error detected status enable
* 0b0..CQIS[RED] is disabled
* 0b1..CQIS[RED] is set when its interrupt condition is active
*/
#define USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK)
#define USDHC_CQISTE_TCL_STE_MASK (0x8U)
#define USDHC_CQISTE_TCL_STE_SHIFT (3U)
/*! TCL_STE - Task cleared status enable
* 0b0..CQIS[TCL] is disabled
* 0b1..CQIS[TCL] is set when its interrupt condition is active
*/
#define USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK)
/*! @} */
/*! @name CQISGE - Command Queuing Interrupt Signal Enable */
/*! @{ */
#define USDHC_CQISGE_HAC_SGE_MASK (0x1U)
#define USDHC_CQISGE_HAC_SGE_SHIFT (0U)
/*! HAC_SGE - Halt complete signal enable
*/
#define USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK)
#define USDHC_CQISGE_TCC_SGE_MASK (0x2U)
#define USDHC_CQISGE_TCC_SGE_SHIFT (1U)
/*! TCC_SGE - Task complete signal enable
*/
#define USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK)
#define USDHC_CQISGE_RED_SGE_MASK (0x4U)
#define USDHC_CQISGE_RED_SGE_SHIFT (2U)
/*! RED_SGE - Response error detected signal enable
*/
#define USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK)
#define USDHC_CQISGE_TCL_SGE_MASK (0x8U)
#define USDHC_CQISGE_TCL_SGE_SHIFT (3U)
/*! TCL_SGE - Task cleared signal enable
*/
#define USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK)
/*! @} */
/*! @name CQIC - Command Queuing Interrupt Coalescing */
/*! @{ */
#define USDHC_CQIC_ICTOVAL_MASK (0x7FU)
#define USDHC_CQIC_ICTOVAL_SHIFT (0U)
/*! ICTOVAL - Interrupt coalescing timeout value
*/
#define USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK)
#define USDHC_CQIC_ICTOVALWEN_MASK (0x80U)
#define USDHC_CQIC_ICTOVALWEN_SHIFT (7U)
/*! ICTOVALWEN - Interrupt coalescing timeout value write enable
*/
#define USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK)
#define USDHC_CQIC_ICCTH_MASK (0x1F00U)
#define USDHC_CQIC_ICCTH_SHIFT (8U)
/*! ICCTH - Interrupt coalescing counter threshold
*/
#define USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK)
#define USDHC_CQIC_ICCTHWEN_MASK (0x8000U)
#define USDHC_CQIC_ICCTHWEN_SHIFT (15U)
/*! ICCTHWEN - Interrupt coalescing counter threshold write enable
*/
#define USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK)
#define USDHC_CQIC_ICCTR_MASK (0x10000U)
#define USDHC_CQIC_ICCTR_SHIFT (16U)
/*! ICCTR - Counter and timer reset
*/
#define USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK)
#define USDHC_CQIC_ICSB_MASK (0x100000U)
#define USDHC_CQIC_ICSB_SHIFT (20U)
/*! ICSB - Interrupt coalescing status
* 0b0..No task completions have occurred since last counter reset (IC counter =0)
* 0b1..At least one task completion has been counted (IC counter >0)
*/
#define USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK)
#define USDHC_CQIC_ICENDIS_MASK (0x80000000U)
#define USDHC_CQIC_ICENDIS_SHIFT (31U)
/*! ICENDIS - Interrupt coalescing enable/disable
*/
#define USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK)
/*! @} */
/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */
/*! @{ */
#define USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU)
#define USDHC_CQTDLBA_TDLBA_SHIFT (0U)
/*! TDLBA - Task descriptor list base address
*/
#define USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK)
/*! @} */
/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */
/*! @{ */
#define USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU)
#define USDHC_CQTDLBAU_TDLBAU_SHIFT (0U)
/*! TDLBAU - Task descriptor list base address
*/
#define USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK)
/*! @} */
/*! @name CQTDBR - Command Queuing Task Doorbell */
/*! @{ */
#define USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU)
#define USDHC_CQTDBR_TDBR_SHIFT (0U)
/*! TDBR - Task doorbell
*/
#define USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK)
/*! @} */
/*! @name CQTCN - Command Queuing Task Completion Notification */
/*! @{ */
#define USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU)
#define USDHC_CQTCN_TCN_SHIFT (0U)
/*! TCN - Task complete notification
*/
#define USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK)
/*! @} */
/*! @name CQDQS - Command Queuing Device Queue Status */
/*! @{ */
#define USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU)
#define USDHC_CQDQS_DQS_SHIFT (0U)
/*! DQS - Device queue status
*/
#define USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK)
/*! @} */
/*! @name CQDPT - Command Queuing Device Pending Tasks */
/*! @{ */
#define USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU)
#define USDHC_CQDPT_DPT_SHIFT (0U)
/*! DPT - Device pending tasks
*/
#define USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK)
/*! @} */
/*! @name CQTCLR - Command Queuing Task Clear */
/*! @{ */
#define USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU)
#define USDHC_CQTCLR_TCLR_SHIFT (0U)
/*! TCLR - Task clear
*/
#define USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK)
/*! @} */
/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */
/*! @{ */
#define USDHC_CQSSC1_CIT_MASK (0xFFFFU)
#define USDHC_CQSSC1_CIT_SHIFT (0U)
/*! CIT - Send status command idle timer
*/
#define USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK)
#define USDHC_CQSSC1_CBC_MASK (0xF0000U)
#define USDHC_CQSSC1_CBC_SHIFT (16U)
/*! CBC - Send status command block counter
*/
#define USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK)
/*! @} */
/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */
/*! @{ */
#define USDHC_CQSSC2_SSC2_MASK (0xFFFFU)
#define USDHC_CQSSC2_SSC2_SHIFT (0U)
/*! SSC2 - Send queue status RCA
*/
#define USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK)
/*! @} */
/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */
/*! @{ */
#define USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU)
#define USDHC_CQCRDCT_CRDCT_SHIFT (0U)
/*! CRDCT - Direct command last response
*/
#define USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK)
/*! @} */
/*! @name CQRMEM - Command Queuing Response Mode Error Mask */
/*! @{ */
#define USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU)
#define USDHC_CQRMEM_RMEM_SHIFT (0U)
/*! RMEM - Response mode error mask
* 0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored
* 0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated
*/
#define USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK)
/*! @} */
/*! @name CQTERRI - Command Queuing Task Error Information */
/*! @{ */
#define USDHC_CQTERRI_RMECI_MASK (0x3FU)
#define USDHC_CQTERRI_RMECI_SHIFT (0U)
/*! RMECI - Response mode error command index
*/
#define USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK)
#define USDHC_CQTERRI_RMETID_MASK (0x1F00U)
#define USDHC_CQTERRI_RMETID_SHIFT (8U)
/*! RMETID - Response mode error task ID
*/
#define USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK)
#define USDHC_CQTERRI_RMEFV_MASK (0x8000U)
#define USDHC_CQTERRI_RMEFV_SHIFT (15U)
/*! RMEFV - Response mode error fields valid
*/
#define USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK)
#define USDHC_CQTERRI_DTECI_MASK (0x3F0000U)
#define USDHC_CQTERRI_DTECI_SHIFT (16U)
/*! DTECI - Data transfer error command index
*/
#define USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK)
#define USDHC_CQTERRI_DTETID_MASK (0x1F000000U)
#define USDHC_CQTERRI_DTETID_SHIFT (24U)
/*! DTETID - Data transfer error task ID
*/
#define USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK)
#define USDHC_CQTERRI_DTEFV_MASK (0x80000000U)
#define USDHC_CQTERRI_DTEFV_SHIFT (31U)
/*! DTEFV - Data transfer error fields valid
*/
#define USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK)
/*! @} */
/*! @name CQCRI - Command Queuing Command Response Index */
/*! @{ */
#define USDHC_CQCRI_LCMDRI_MASK (0x3FU)
#define USDHC_CQCRI_LCMDRI_SHIFT (0U)
/*! LCMDRI - Last command response index
*/
#define USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK)
/*! @} */
/*! @name CQCRA - Command Queuing Command Response Argument */
/*! @{ */
#define USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU)
#define USDHC_CQCRA_LCMDRA_SHIFT (0U)
/*! LCMDRA - Last command response argument
*/
#define USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USDHC_Register_Masks */
/* USDHC - Peripheral instance base addresses */
/** Peripheral USDHC1 base address */
#define USDHC1_BASE (0x30B40000u)
/** Peripheral USDHC1 base pointer */
#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
/** Peripheral USDHC2 base address */
#define USDHC2_BASE (0x30B50000u)
/** Peripheral USDHC2 base pointer */
#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
/** Peripheral USDHC3 base address */
#define USDHC3_BASE (0x30B60000u)
/** Peripheral USDHC3 base pointer */
#define USDHC3 ((USDHC_Type *)USDHC3_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE, USDHC3_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2, USDHC3 }
/** Interrupt vectors for the USDHC peripheral type */
#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn }
/*!
* @}
*/ /* end of group USDHC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VIDEOPACKETIZER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEOPACKETIZER_Peripheral_Access_Layer VIDEOPACKETIZER Peripheral Access Layer
* @{
*/
/** VIDEOPACKETIZER - Register Layout Typedef */
typedef struct {
__I uint8_t VP_STATUS; /**< Video Packetizer Packing Phase Status Register, offset: 0x0 */
__IO uint8_t VP_PR_CD; /**< Video Packetizer Pixel Repetition and Color Depth Register, offset: 0x1 */
__IO uint8_t VP_STUFF; /**< Video Packetizer Stuffing and Default Packing Phase Register, offset: 0x2 */
__IO uint8_t VP_REMAP; /**< Video Packetizer YCbCr 422 Remapping Register, offset: 0x3 */
__IO uint8_t VP_CONF; /**< Video Packetizer Output and Enable Configuration Register, offset: 0x4 */
uint8_t RESERVED_0[2];
__IO uint8_t VP_MASK; /**< Video Packetizer Interrupt Mask Register, offset: 0x7 */
} VIDEOPACKETIZER_Type;
/* ----------------------------------------------------------------------------
-- VIDEOPACKETIZER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEOPACKETIZER_Register_Masks VIDEOPACKETIZER Register Masks
* @{
*/
/*! @name VP_STATUS - Video Packetizer Packing Phase Status Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_STATUS_packing_phase_MASK (0xFU)
#define VIDEOPACKETIZER_VP_STATUS_packing_phase_SHIFT (0U)
/*! packing_phase - Read only register that holds the "packing phase" output of the Video Packetizer block.
*/
#define VIDEOPACKETIZER_VP_STATUS_packing_phase(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STATUS_packing_phase_SHIFT)) & VIDEOPACKETIZER_VP_STATUS_packing_phase_MASK)
/*! @} */
/*! @name VP_PR_CD - Video Packetizer Pixel Repetition and Color Depth Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_MASK (0xFU)
#define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_SHIFT (0U)
/*! desired_pr_factor - Desired pixel repetition factor configuration.
*/
#define VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_SHIFT)) & VIDEOPACKETIZER_VP_PR_CD_desired_pr_factor_MASK)
#define VIDEOPACKETIZER_VP_PR_CD_color_depth_MASK (0xF0U)
#define VIDEOPACKETIZER_VP_PR_CD_color_depth_SHIFT (4U)
/*! color_depth - The Color depth configuration is described as the following, with the action
* stated corresponding to color_depth[3:0]: - 0000b: 24 bits per pixel video (8 bits per component).
*/
#define VIDEOPACKETIZER_VP_PR_CD_color_depth(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_PR_CD_color_depth_SHIFT)) & VIDEOPACKETIZER_VP_PR_CD_color_depth_MASK)
/*! @} */
/*! @name VP_STUFF - Video Packetizer Stuffing and Default Packing Phase Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_STUFF_pr_stuffing_MASK (0x1U)
#define VIDEOPACKETIZER_VP_STUFF_pr_stuffing_SHIFT (0U)
/*! pr_stuffing - Pixel repeater stuffing control.
*/
#define VIDEOPACKETIZER_VP_STUFF_pr_stuffing(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_pr_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_pr_stuffing_MASK)
#define VIDEOPACKETIZER_VP_STUFF_pp_stuffing_MASK (0x2U)
#define VIDEOPACKETIZER_VP_STUFF_pp_stuffing_SHIFT (1U)
/*! pp_stuffing - Pixel packing stuffing control.
*/
#define VIDEOPACKETIZER_VP_STUFF_pp_stuffing(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_pp_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_pp_stuffing_MASK)
#define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_MASK (0x4U)
#define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_SHIFT (2U)
/*! ycc422_stuffing - YCbCr 422 remap stuffing control.
*/
#define VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_ycc422_stuffing_MASK)
#define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_MASK (0x8U)
#define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_SHIFT (3U)
/*! icx_goto_p0_st - Reserved.
*/
#define VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_icx_goto_p0_st_MASK)
#define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_MASK (0x10U)
#define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_SHIFT (4U)
/*! ifix_pp_to_last - Reserved.
*/
#define VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_ifix_pp_to_last_MASK)
#define VIDEOPACKETIZER_VP_STUFF_idefault_phase_MASK (0x20U)
#define VIDEOPACKETIZER_VP_STUFF_idefault_phase_SHIFT (5U)
/*! idefault_phase - Controls the default phase packing machine used according to HDMI 1.
*/
#define VIDEOPACKETIZER_VP_STUFF_idefault_phase(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_STUFF_idefault_phase_SHIFT)) & VIDEOPACKETIZER_VP_STUFF_idefault_phase_MASK)
/*! @} */
/*! @name VP_REMAP - Video Packetizer YCbCr 422 Remapping Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_REMAP_ycc422_size_MASK (0x3U)
#define VIDEOPACKETIZER_VP_REMAP_ycc422_size_SHIFT (0U)
/*! ycc422_size - YCbCr 422 remap input video size ycc422_size[1:0] 00b: YCbCr 422 16-bit input
* video (8 bits per component) 01b: YCbCr 422 20-bit input video (10 bits per component) 10b: YCbCr
* 422 24-bit input video (12 bits per component) 11b: Reserved.
*/
#define VIDEOPACKETIZER_VP_REMAP_ycc422_size(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_REMAP_ycc422_size_SHIFT)) & VIDEOPACKETIZER_VP_REMAP_ycc422_size_MASK)
/*! @} */
/*! @name VP_CONF - Video Packetizer Output and Enable Configuration Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_CONF_output_selector_0_MASK (0x1U)
#define VIDEOPACKETIZER_VP_CONF_output_selector_0_SHIFT (0U)
/*! output_selector_0 - Video Packetizer output selection 0b: Data from pixel packing block 1b: Data from YCbCr 422 remap block
*/
#define VIDEOPACKETIZER_VP_CONF_output_selector_0(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_output_selector_0_SHIFT)) & VIDEOPACKETIZER_VP_CONF_output_selector_0_MASK)
#define VIDEOPACKETIZER_VP_CONF_output_selector_1_MASK (0x2U)
#define VIDEOPACKETIZER_VP_CONF_output_selector_1_SHIFT (1U)
/*! output_selector_1 - When set to 1'b1, Data from pixel packing block Note: the use of this field is deprecated
*/
#define VIDEOPACKETIZER_VP_CONF_output_selector_1(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_output_selector_1_SHIFT)) & VIDEOPACKETIZER_VP_CONF_output_selector_1_MASK)
#define VIDEOPACKETIZER_VP_CONF_bypass_select_MASK (0x4U)
#define VIDEOPACKETIZER_VP_CONF_bypass_select_SHIFT (2U)
/*! bypass_select - bypass_select 0b: Data from pixel repeater block 1b: Data from input of Video Packetizer block
*/
#define VIDEOPACKETIZER_VP_CONF_bypass_select(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_bypass_select_SHIFT)) & VIDEOPACKETIZER_VP_CONF_bypass_select_MASK)
#define VIDEOPACKETIZER_VP_CONF_ycc422_en_MASK (0x8U)
#define VIDEOPACKETIZER_VP_CONF_ycc422_en_SHIFT (3U)
/*! ycc422_en - YCbCr 422 select enable.
*/
#define VIDEOPACKETIZER_VP_CONF_ycc422_en(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_ycc422_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_ycc422_en_MASK)
#define VIDEOPACKETIZER_VP_CONF_pr_en_MASK (0x10U)
#define VIDEOPACKETIZER_VP_CONF_pr_en_SHIFT (4U)
/*! pr_en - Pixel repeater enable.
*/
#define VIDEOPACKETIZER_VP_CONF_pr_en(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_pr_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_pr_en_MASK)
#define VIDEOPACKETIZER_VP_CONF_pp_en_MASK (0x20U)
#define VIDEOPACKETIZER_VP_CONF_pp_en_SHIFT (5U)
/*! pp_en - Pixel packing enable.
*/
#define VIDEOPACKETIZER_VP_CONF_pp_en(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_pp_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_pp_en_MASK)
#define VIDEOPACKETIZER_VP_CONF_bypass_en_MASK (0x40U)
#define VIDEOPACKETIZER_VP_CONF_bypass_en_SHIFT (6U)
/*! bypass_en - When set to 1'b1, Pixel packing enable.
*/
#define VIDEOPACKETIZER_VP_CONF_bypass_en(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_CONF_bypass_en_SHIFT)) & VIDEOPACKETIZER_VP_CONF_bypass_en_MASK)
/*! @} */
/*! @name VP_MASK - Video Packetizer Interrupt Mask Register */
/*! @{ */
#define VIDEOPACKETIZER_VP_MASK_spare_1_MASK (0x1U)
#define VIDEOPACKETIZER_VP_MASK_spare_1_SHIFT (0U)
/*! spare_1 - Reserved as "spare" bit with no associated functionality.
*/
#define VIDEOPACKETIZER_VP_MASK_spare_1(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_spare_1_SHIFT)) & VIDEOPACKETIZER_VP_MASK_spare_1_MASK)
#define VIDEOPACKETIZER_VP_MASK_spare_2_MASK (0x2U)
#define VIDEOPACKETIZER_VP_MASK_spare_2_SHIFT (1U)
/*! spare_2 - Reserved as "spare" bit with no associated functionality.
*/
#define VIDEOPACKETIZER_VP_MASK_spare_2(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_spare_2_SHIFT)) & VIDEOPACKETIZER_VP_MASK_spare_2_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointemptyremap_MASK (0x4U)
#define VIDEOPACKETIZER_VP_MASK_ointemptyremap_SHIFT (2U)
/*! ointemptyremap - Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO empty
*/
#define VIDEOPACKETIZER_VP_MASK_ointemptyremap(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptyremap_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptyremap_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointfullremap_MASK (0x8U)
#define VIDEOPACKETIZER_VP_MASK_ointfullremap_SHIFT (3U)
/*! ointfullremap - Mask bit for Video Packetizer pixel YCbCr 422 re-mapper FIFO full
*/
#define VIDEOPACKETIZER_VP_MASK_ointfullremap(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullremap_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullremap_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointemptypp_MASK (0x10U)
#define VIDEOPACKETIZER_VP_MASK_ointemptypp_SHIFT (4U)
/*! ointemptypp - Mask bit for Video Packetizer pixel packing FIFO empty
*/
#define VIDEOPACKETIZER_VP_MASK_ointemptypp(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptypp_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptypp_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointfullpp_MASK (0x20U)
#define VIDEOPACKETIZER_VP_MASK_ointfullpp_SHIFT (5U)
/*! ointfullpp - Mask bit for Video Packetizer pixel packing FIFO full
*/
#define VIDEOPACKETIZER_VP_MASK_ointfullpp(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullpp_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullpp_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointemptyrepet_MASK (0x40U)
#define VIDEOPACKETIZER_VP_MASK_ointemptyrepet_SHIFT (6U)
/*! ointemptyrepet - Mask bit for Video Packetizer pixel repeater FIFO empty
*/
#define VIDEOPACKETIZER_VP_MASK_ointemptyrepet(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointemptyrepet_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointemptyrepet_MASK)
#define VIDEOPACKETIZER_VP_MASK_ointfullrepet_MASK (0x80U)
#define VIDEOPACKETIZER_VP_MASK_ointfullrepet_SHIFT (7U)
/*! ointfullrepet - Mask bit for Video Packetizer pixel repeater FIFO full
*/
#define VIDEOPACKETIZER_VP_MASK_ointfullrepet(x) (((uint8_t)(((uint8_t)(x)) << VIDEOPACKETIZER_VP_MASK_ointfullrepet_SHIFT)) & VIDEOPACKETIZER_VP_MASK_ointfullrepet_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VIDEOPACKETIZER_Register_Masks */
/* VIDEOPACKETIZER - Peripheral instance base addresses */
/** Peripheral VIDEOPACKETIZER base address */
#define VIDEOPACKETIZER_BASE (0x32FD8800u)
/** Peripheral VIDEOPACKETIZER base pointer */
#define VIDEOPACKETIZER ((VIDEOPACKETIZER_Type *)VIDEOPACKETIZER_BASE)
/** Array initializer of VIDEOPACKETIZER peripheral base addresses */
#define VIDEOPACKETIZER_BASE_ADDRS { VIDEOPACKETIZER_BASE }
/** Array initializer of VIDEOPACKETIZER peripheral base pointers */
#define VIDEOPACKETIZER_BASE_PTRS { VIDEOPACKETIZER }
/*!
* @}
*/ /* end of group VIDEOPACKETIZER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VIDEOSAMPLER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEOSAMPLER_Peripheral_Access_Layer VIDEOSAMPLER Peripheral Access Layer
* @{
*/
/** VIDEOSAMPLER - Register Layout Typedef */
typedef struct {
__IO uint8_t TX_INVID0; /**< Video Input Mapping and Internal Data Enable Configuration Register, offset: 0x0 */
__IO uint8_t TX_INSTUFFING; /**< Video Input Stuffing Enable Register, offset: 0x1 */
__IO uint8_t TX_GYDATA0; /**< Video Input gy Data Channel Stuffing Register 0, offset: 0x2 */
__IO uint8_t TX_GYDATA1; /**< Video Input gy Data Channel Stuffing Register 1, offset: 0x3 */
__IO uint8_t TX_RCRDATA0; /**< Video Input rcr Data Channel Stuffing Register 0, offset: 0x4 */
__IO uint8_t TX_RCRDATA1; /**< Video Input rcr Data Channel Stuffing Register 1, offset: 0x5 */
__IO uint8_t TX_BCBDATA0; /**< Video Input bcb Data Channel Stuffing Register 0, offset: 0x6 */
__IO uint8_t TX_BCBDATA1; /**< Video Input bcb Data Channel Stuffing Register 1, offset: 0x7 */
} VIDEOSAMPLER_Type;
/* ----------------------------------------------------------------------------
-- VIDEOSAMPLER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEOSAMPLER_Register_Masks VIDEOSAMPLER Register Masks
* @{
*/
/*! @name TX_INVID0 - Video Input Mapping and Internal Data Enable Configuration Register */
/*! @{ */
#define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_MASK (0x1FU)
#define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_SHIFT (0U)
/*! video_mapping - Video Input mapping (color space/color depth): 0x01: RGB 4:4:4/8 bits 0x03: RGB
* 4:4:4/10 bits 0x05: RGB 4:4:4/12 bits 0x07: RGB 4:4:4/16 bits 0x09: YCbCr 4:4:4 or 4:2:0/8
* bits 0x0B: YCbCr 4:4:4 or 4:2:0/10 bits 0x0D: YCbCr 4:4:4 or 4:2:0/12 bits 0x0F: YCbCr 4:4:4 or
* 4:2:0/16 bits 0x16: YCbCr 4:2:2/8 bits 0x14: YCbCr 4:2:2/10 bits 0x12: YCbCr 4:2:2/12 bits
* 0x17: YCbCr 4:4:4 (IPI)/8 bits 0x18: YCbCr 4:4:4 (IPI)/10 bits 0x19: YCbCr 4:4:4 (IPI)/12 bits
* 0x1A: YCbCr 4:4:4 (IPI)/16 bits 0x1B: YCbCr 4:2:2 (IPI)/12 bits 0x1C: YCbCr 4:2:0 (IPI)/8 bits
* 0x1D: YCbCr 4:2:0 (IPI)/10 bits 0x1E: YCbCr 4:2:0 (IPI)/12 bits 0x1F: YCbCr 4:2:0 (IPI)/16 bits
* Note: IPI means Image Pixel Interface and it is a proprietary interface used on SNPS MIPI
* Controllers.
*/
#define VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_SHIFT)) & VIDEOSAMPLER_TX_INVID0_VIDEO_MAPPING_MASK)
#define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_MASK (0x80U)
#define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_SHIFT (7U)
/*! internal_de_generator - Internal data enable (DE) generator enable.
*/
#define VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_SHIFT)) & VIDEOSAMPLER_TX_INVID0_INTERNAL_DE_GENERATOR_MASK)
/*! @} */
/*! @name TX_INSTUFFING - Video Input Stuffing Enable Register */
/*! @{ */
#define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_MASK (0x1U)
#define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_SHIFT (0U)
/*! gydata_stuffing - - 0b: When the dataen signal is low, the value in the gydata[15:0] output is
* the one sampled from the corresponding input data.
*/
#define VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_GYDATA_STUFFING_MASK)
#define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_MASK (0x2U)
#define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_SHIFT (1U)
/*! rcrdata_stuffing - - 0b: When the dataen signal is low, the value in the rcrdata[15:0] output is
* the one sampled from the corresponding input data.
*/
#define VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_RCRDATA_STUFFING_MASK)
#define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_MASK (0x4U)
#define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_SHIFT (2U)
/*! bcbdata_stuffing - - 0b: When the dataen signal is low, the value in the bcbdata[15:0] output is
* the one sampled from the corresponding input data.
*/
#define VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_SHIFT)) & VIDEOSAMPLER_TX_INSTUFFING_BCBDATA_STUFFING_MASK)
/*! @} */
/*! @name TX_GYDATA0 - Video Input gy Data Channel Stuffing Register 0 */
/*! @{ */
#define VIDEOSAMPLER_TX_GYDATA0_GYDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_GYDATA0_GYDATA_SHIFT (0U)
/*! gydata - This register defines the value of gydata[7:0] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_GYDATA0_GYDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_GYDATA0_GYDATA_SHIFT)) & VIDEOSAMPLER_TX_GYDATA0_GYDATA_MASK)
/*! @} */
/*! @name TX_GYDATA1 - Video Input gy Data Channel Stuffing Register 1 */
/*! @{ */
#define VIDEOSAMPLER_TX_GYDATA1_GYDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_GYDATA1_GYDATA_SHIFT (0U)
/*! gydata - This register defines the value of gydata[15:8] when TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_GYDATA1_GYDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_GYDATA1_GYDATA_SHIFT)) & VIDEOSAMPLER_TX_GYDATA1_GYDATA_MASK)
/*! @} */
/*! @name TX_RCRDATA0 - Video Input rcr Data Channel Stuffing Register 0 */
/*! @{ */
#define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_SHIFT (0U)
/*! rcrdata - This register defines the value of rcrydata[7:0] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_RCRDATA0_RCRDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_SHIFT)) & VIDEOSAMPLER_TX_RCRDATA0_RCRDATA_MASK)
/*! @} */
/*! @name TX_RCRDATA1 - Video Input rcr Data Channel Stuffing Register 1 */
/*! @{ */
#define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_SHIFT (0U)
/*! rcrdata - This register defines the value of rcrydata[15:8] when TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_RCRDATA1_RCRDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_SHIFT)) & VIDEOSAMPLER_TX_RCRDATA1_RCRDATA_MASK)
/*! @} */
/*! @name TX_BCBDATA0 - Video Input bcb Data Channel Stuffing Register 0 */
/*! @{ */
#define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_SHIFT (0U)
/*! bcbdata - This register defines the value of bcbdata[7:0] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_BCBDATA0_BCBDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_SHIFT)) & VIDEOSAMPLER_TX_BCBDATA0_BCBDATA_MASK)
/*! @} */
/*! @name TX_BCBDATA1 - Video Input bcb Data Channel Stuffing Register 1 */
/*! @{ */
#define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_MASK (0xFFU)
#define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_SHIFT (0U)
/*! bcbdata - This register defines the value of bcbdata[15:8] when TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.
*/
#define VIDEOSAMPLER_TX_BCBDATA1_BCBDATA(x) (((uint8_t)(((uint8_t)(x)) << VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_SHIFT)) & VIDEOSAMPLER_TX_BCBDATA1_BCBDATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VIDEOSAMPLER_Register_Masks */
/* VIDEOSAMPLER - Peripheral instance base addresses */
/** Peripheral VIDEOSAMPLER base address */
#define VIDEOSAMPLER_BASE (0x32FD8200u)
/** Peripheral VIDEOSAMPLER base pointer */
#define VIDEOSAMPLER ((VIDEOSAMPLER_Type *)VIDEOSAMPLER_BASE)
/** Array initializer of VIDEOSAMPLER peripheral base addresses */
#define VIDEOSAMPLER_BASE_ADDRS { VIDEOSAMPLER_BASE }
/** Array initializer of VIDEOSAMPLER peripheral base pointers */
#define VIDEOSAMPLER_BASE_PTRS { VIDEOSAMPLER }
/*!
* @}
*/ /* end of group VIDEOSAMPLER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_BLK_CTL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_BLK_CTL_Peripheral_Access_Layer VPU_BLK_CTL Peripheral Access Layer
* @{
*/
/** VPU_BLK_CTL - Register Layout Typedef */
typedef struct {
__IO uint32_t BLK_SFT_RSTN_CSR; /**< VPUMIX block soft reset control, offset: 0x0 */
__IO uint32_t BLK_CLK_EN_CSR; /**< VPUMIX block clock enable control, offset: 0x4 */
__IO uint32_t G1_FUSE_DEC_CSR; /**< VPUMIX G1 fuse_dec control, offset: 0x8 */
__IO uint32_t G1_FUSE_PP_CSR; /**< VPUMIX G1 fuse_pp control, offset: 0xC */
__IO uint32_t G2_FUSE_DEC_CSR; /**< VPUMIX G2 fuse_dec control, offset: 0x10 */
__IO uint32_t VC8000E_FUSE_ENC_CSR; /**< VPUMIX VC8000E fuse_enc control, offset: 0x14 */
__IO uint32_t VPU_CACHE_EN_CSR; /**< VPUMIX block cache enable control, offset: 0x18 */
__I uint32_t VPU_NO_PENDING_CSR; /**< VPUMIX block pending transaction status, offset: 0x1C */
__IO uint32_t G1_OTR_BEAT_LIMIT_CSR; /**< VPUMIX G1 outstanding read beat limit control, offset: 0x20 */
__IO uint32_t G2_OTR_BEAT_LIMIT_CSR; /**< VPUMIX G2 outstanding read beat limit control, offset: 0x24 */
__IO uint32_t VC8000E_OTR_BEAT_LIMIT_CSR; /**< VPUMIX VC8000E outstanding read beat limit control, offset: 0x28 */
} VPU_BLK_CTL_Type;
/* ----------------------------------------------------------------------------
-- VPU_BLK_CTL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_BLK_CTL_Register_Masks VPU_BLK_CTL Register Masks
* @{
*/
/*! @name BLK_SFT_RSTN_CSR - VPUMIX block soft reset control */
/*! @{ */
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_MASK (0x1U)
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_SHIFT (0U)
/*! G2_SFT_RSTN
* 0b1..Normal
* 0b0..Reset
*/
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G2_SFT_RSTN_MASK)
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_MASK (0x2U)
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_SHIFT (1U)
/*! G1_SFT_RSTN
* 0b1..Normal
* 0b0..Reset
*/
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_G1_SFT_RSTN_MASK)
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_MASK (0x4U)
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_SHIFT (2U)
/*! VC8000E_SFT_RSTN
* 0b1..Normal
* 0b0..Reset
*/
#define VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_SHIFT)) & VPU_BLK_CTL_BLK_SFT_RSTN_CSR_VC8000E_SFT_RSTN_MASK)
/*! @} */
/*! @name BLK_CLK_EN_CSR - VPUMIX block clock enable control */
/*! @{ */
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_MASK (0x1U)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_SHIFT (0U)
/*! G2_CLK_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_G2_CLK_EN_MASK)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_MASK (0x2U)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_SHIFT (1U)
/*! G1_CLK_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_G1_CLK_EN_MASK)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_MASK (0x4U)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_SHIFT (2U)
/*! VC8000E_CLK_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_VC8000E_CLK_EN_MASK)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_MASK (0x8U)
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_SHIFT (3U)
/*! MAIN_CLK_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_SHIFT)) & VPU_BLK_CTL_BLK_CLK_EN_CSR_MAIN_CLK_EN_MASK)
/*! @} */
/*! @name G1_FUSE_DEC_CSR - VPUMIX G1 fuse_dec control */
/*! @{ */
#define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_MASK (0xFFFFFFFFU)
#define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_SHIFT (0U)
/*! G1_FUSE_DEC
* 0b00000000000000000000000000000001..Enable
* 0b00000000000000000000000000000000..Disable
*/
#define VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_SHIFT)) & VPU_BLK_CTL_G1_FUSE_DEC_CSR_G1_FUSE_DEC_MASK)
/*! @} */
/*! @name G1_FUSE_PP_CSR - VPUMIX G1 fuse_pp control */
/*! @{ */
#define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_MASK (0xFFFFFFFFU)
#define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_SHIFT (0U)
/*! G1_FUSE_PP
* 0b00000000000000000000000000000001..Enable
* 0b00000000000000000000000000000000..Disable
*/
#define VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_SHIFT)) & VPU_BLK_CTL_G1_FUSE_PP_CSR_G1_FUSE_PP_MASK)
/*! @} */
/*! @name G2_FUSE_DEC_CSR - VPUMIX G2 fuse_dec control */
/*! @{ */
#define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_MASK (0xFFFFFFFFU)
#define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_SHIFT (0U)
/*! G2_FUSE_DEC
* 0b00000000000000000000000000000001..Enable
* 0b00000000000000000000000000000000..Disable
*/
#define VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_SHIFT)) & VPU_BLK_CTL_G2_FUSE_DEC_CSR_G2_FUSE_DEC_MASK)
/*! @} */
/*! @name VC8000E_FUSE_ENC_CSR - VPUMIX VC8000E fuse_enc control */
/*! @{ */
#define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_MASK (0xFFFFFFFFU)
#define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_SHIFT (0U)
/*! VC8000E_FUSE_ENC
* 0b00000000000000000000000000000001..Enable
* 0b00000000000000000000000000000000..Disable
*/
#define VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_SHIFT)) & VPU_BLK_CTL_VC8000E_FUSE_ENC_CSR_VC8000E_FUSE_ENC_MASK)
/*! @} */
/*! @name VPU_CACHE_EN_CSR - VPUMIX block cache enable control */
/*! @{ */
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_MASK (0x1U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_SHIFT (0U)
/*! G1_ARCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_ARCACHE_EN_MASK)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_MASK (0x2U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_SHIFT (1U)
/*! G1_AWCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G1_AWCACHE_EN_MASK)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_MASK (0x4U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_SHIFT (2U)
/*! G2_ARCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_ARCACHE_EN_MASK)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_MASK (0x8U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_SHIFT (3U)
/*! G2_AWCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_G2_AWCACHE_EN_MASK)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_MASK (0x10U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_SHIFT (4U)
/*! VC8000E_ARCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_ARCACHE_EN_MASK)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_MASK (0x20U)
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_SHIFT (5U)
/*! VC8000E_AWCACHE_EN
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_SHIFT)) & VPU_BLK_CTL_VPU_CACHE_EN_CSR_VC8000E_AWCACHE_EN_MASK)
/*! @} */
/*! @name VPU_NO_PENDING_CSR - VPUMIX block pending transaction status */
/*! @{ */
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_MASK (0x1U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_SHIFT (0U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_G1_NO_PENDING_MASK)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_MASK (0x2U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_SHIFT (1U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_G2_NO_PENDING_MASK)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_MASK (0x4U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_SHIFT (2U)
#define VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_SHIFT)) & VPU_BLK_CTL_VPU_NO_PENDING_CSR_VC8000E_NO_PENDING_MASK)
/*! @} */
/*! @name G1_OTR_BEAT_LIMIT_CSR - VPUMIX G1 outstanding read beat limit control */
/*! @{ */
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_MASK (0xFFFFU)
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_SHIFT (0U)
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_NUM_MASK)
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_MASK (0x10000U)
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_SHIFT (16U)
#define VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_G1_OTR_BEAT_LIMIT_CSR_G1_BEAT_LIMIT_ENABLE_MASK)
/*! @} */
/*! @name G2_OTR_BEAT_LIMIT_CSR - VPUMIX G2 outstanding read beat limit control */
/*! @{ */
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_MASK (0xFFFFU)
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_SHIFT (0U)
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_NUM_MASK)
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_MASK (0x10000U)
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_SHIFT (16U)
#define VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_G2_OTR_BEAT_LIMIT_CSR_G2_BEAT_LIMIT_ENABLE_MASK)
/*! @} */
/*! @name VC8000E_OTR_BEAT_LIMIT_CSR - VPUMIX VC8000E outstanding read beat limit control */
/*! @{ */
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_MASK (0xFFFFU)
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_SHIFT (0U)
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_SHIFT)) & VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_NUM_MASK)
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_MASK (0x10000U)
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_SHIFT (16U)
#define VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_SHIFT)) & VPU_BLK_CTL_VC8000E_OTR_BEAT_LIMIT_CSR_VC8000E_BEAT_LIMIT_ENABLE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_BLK_CTL_Register_Masks */
/* VPU_BLK_CTL - Peripheral instance base addresses */
/** Peripheral VPU_BLK_CTRL base address */
#define VPU_BLK_CTRL_BASE (0x38330000u)
/** Peripheral VPU_BLK_CTRL base pointer */
#define VPU_BLK_CTRL ((VPU_BLK_CTL_Type *)VPU_BLK_CTRL_BASE)
/** Array initializer of VPU_BLK_CTL peripheral base addresses */
#define VPU_BLK_CTL_BASE_ADDRS { VPU_BLK_CTRL_BASE }
/** Array initializer of VPU_BLK_CTL peripheral base pointers */
#define VPU_BLK_CTL_BASE_PTRS { VPU_BLK_CTRL }
/*!
* @}
*/ /* end of group VPU_BLK_CTL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_G1 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_Peripheral_Access_Layer VPU_G1 Peripheral Access Layer
* @{
*/
/** VPU_G1 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t SWREG1; /**< Interrupt register decoder, offset: 0x4 */
__IO uint32_t SWREG2; /**< Device configuration register decoder, offset: 0x8 */
__IO uint32_t SWREG3; /**< Decoder control register 0 (decmode,picture type etc), offset: 0xC */
uint8_t RESERVED_1[32];
__IO uint32_t SWREG12; /**< Base address for RLC data (RLC) / stream start address/decoded end addr register (VLC), offset: 0x30 */
__IO uint32_t SWREG13; /**< Base address for decoded picture, offset: 0x34 */
uint8_t RESERVED_2[104];
__IO uint32_t SWREG40; /**< Base address for standard dependent tables, offset: 0xA0 */
__IO uint32_t SWREG41; /**< Base address for direct mode motion vectors, offset: 0xA4 */
uint8_t RESERVED_3[24];
__IO uint32_t SWREG48; /**< Error concealment register, offset: 0xC0 */
__IO uint32_t SWREG49; /**< Prediction filter tap register for H264, offset: 0xC4 */
__I uint32_t SWREG50; /**< Synthesis configuration register decoder 0, offset: 0xC8 */
__IO uint32_t SWREG51; /**< Reference picture buffer control register, offset: 0xCC */
__I uint32_t SWREG52; /**< Reference picture buffer information register 1, offset: 0xD0 */
__I uint32_t SWREG53; /**< Reference picture buffer information register 2, offset: 0xD4 */
__I uint32_t SWREG54; /**< Synthesis configuration register decoder 1, offset: 0xD8 */
__IO uint32_t SWREG55; /**< Reference picture buffer 2 / Advanced prefetch control register, offset: 0xDC */
__I uint32_t SWREG56; /**< Reference buffer information register 3, offset: 0xE0 */
__I uint32_t SWREG57; /**< Decoder fuse register, offset: 0xE4 */
__IO uint32_t SWREG58; /**< Device configuration register decoder 2 + Multi core control register, offset: 0xE8 */
__IO uint32_t SWREG59; /**< H264 Chrominance 8 pixel interleaved data base, offset: 0xEC */
__IO uint32_t SWREG60; /**< Interrupt register post-processor, offset: 0xF0 */
__IO uint32_t SWREG61; /**< Device configuration register post-processor, offset: 0xF4 */
__IO uint32_t SWREG62; /**< Deinterlace control register, offset: 0xF8 */
__IO uint32_t SWREG63; /**< Base address for reading post-processing input picture luminance (top field/frame), offset: 0xFC */
__IO uint32_t SWREG64; /**< Base address for reading post-processing input picture Cb/Ch (top field/frame), offset: 0x100 */
__IO uint32_t SWREG65; /**< Base address for reading post-processing input picture Cr, offset: 0x104 */
__IO uint32_t SWREG66; /**< Base address for writing post-processed picture luminance/RGB, offset: 0x108 */
__IO uint32_t SWREG67; /**< Base address for writing post-processed picture Ch, offset: 0x10C */
__IO uint32_t SWREG68; /**< Register for contrast adjusting, offset: 0x110 */
__IO uint32_t SWREG69; /**< Register for colour conversion and contrast adjusting/YUYV 422 channel orders, offset: 0x114 */
__IO uint32_t SWREG70; /**< Register for colour conversion 0, offset: 0x118 */
__IO uint32_t SWREG71; /**< Register for colour conversion 1 + rotation mode, offset: 0x11C */
__IO uint32_t SWREG72; /**< PP input size and -cropping register, offset: 0x120 */
__IO uint32_t SWREG73; /**< PP input picture base address for Y bottom field, offset: 0x124 */
__IO uint32_t SWREG74; /**< PP input picture base for Ch bottom field, offset: 0x128 */
uint8_t RESERVED_4[16];
__IO uint32_t SWREG79; /**< Scaling register 0 ratio and padding for R and G, offset: 0x13C */
__IO uint32_t SWREG80; /**< Scaling ratio register 1 and padding for B, offset: 0x140 */
__IO uint32_t SWREG81; /**< Scaling ratio register 2, offset: 0x144 */
__IO uint32_t SWREG82; /**< Rmask register, offset: 0x148 */
__IO uint32_t SWREG83; /**< Gmask register, offset: 0x14C */
__IO uint32_t SWREG84; /**< Bmask register, offset: 0x150 */
__IO uint32_t SWREG85; /**< Post-processor control register, offset: 0x154 */
__IO uint32_t SWREG86; /**< Mask 1 start coordinate register, offset: 0x158 */
__IO uint32_t SWREG87; /**< Mask 2 start coordinate register + Mask extensions, offset: 0x15C */
__IO uint32_t SWREG88; /**< Mask 1 size and PP original width register, offset: 0x160 */
__IO uint32_t SWREG89; /**< Mask 2 size register + mask extensions, offset: 0x164 */
__IO uint32_t SWREG90; /**< PiP register 0, offset: 0x168 */
__IO uint32_t SWREG91; /**< PiP register 1 and dithering control, offset: 0x16C */
__IO uint32_t SWREG92; /**< Display width and PP input size extension register, offset: 0x170 */
__IO uint32_t SWREG93; /**< Base address for alpha blend 1 gui component, offset: 0x174 */
__IO uint32_t SWREG94; /**< Base address for alpha blend 2 gui component, offset: 0x178 */
__IO uint32_t SWREG95; /**< Alpha blend input cropping register (scanline for cropping), offset: 0x17C */
uint8_t RESERVED_5[12];
__I uint32_t SWREG99; /**< PP fuse register, offset: 0x18C */
__I uint32_t SWREG100; /**< Synthesis configuration register post-processor, offset: 0x190 */
uint8_t RESERVED_6[4];
__IO uint32_t SWREG102; /**< Base address for H264 decoded chroma picture, offset: 0x198 */
__IO uint32_t SWREG103; /**< Base address for reference chroma picture index 0, offset: 0x19C */
__IO uint32_t SWREG104; /**< Base address for reference chroma picture index 1, offset: 0x1A0 */
__IO uint32_t SWREG105; /**< Base address for reference chroma picture index 2, offset: 0x1A4 */
__IO uint32_t SWREG106; /**< Base address for reference chroma picture index 3, offset: 0x1A8 */
__IO uint32_t SWREG107; /**< Base address for reference chroma picture index 4, offset: 0x1AC */
__IO uint32_t SWREG108; /**< Base address for reference chroma picture index 5, offset: 0x1B0 */
__IO uint32_t SWREG109; /**< Base address for reference chroma picture index 6, offset: 0x1B4 */
__IO uint32_t SWREG110; /**< Base address for reference chroma picture index 7, offset: 0x1B8 */
__IO uint32_t SWREG111; /**< Base address for reference chroma picture index 8, offset: 0x1BC */
__IO uint32_t SWREG112; /**< Base address for reference chroma picture index 9, offset: 0x1C0 */
__IO uint32_t SWREG113; /**< Base address for reference chroma picture index 10, offset: 0x1C4 */
__IO uint32_t SWREG114; /**< Base address for reference chroma picture index 11, offset: 0x1C8 */
__IO uint32_t SWREG115; /**< Base address for reference chroma picture index 12, offset: 0x1CC */
__IO uint32_t SWREG116; /**< Base address for reference chroma picture index 13, offset: 0x1D0 */
__IO uint32_t SWREG117; /**< Base address for reference chroma picture index 14, offset: 0x1D4 */
__IO uint32_t SWREG118; /**< Base address for reference chroma picture index 15, offset: 0x1D8 */
} VPU_G1_Type;
/* ----------------------------------------------------------------------------
-- VPU_G1 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_Register_Masks VPU_G1 Register Masks
* @{
*/
/*! @name SWREG1 - Interrupt register decoder */
/*! @{ */
#define VPU_G1_SWREG1_SW_DEC_E_MASK (0x1U)
#define VPU_G1_SWREG1_SW_DEC_E_SHIFT (0U)
/*! SW_DEC_E - Decoder enable. Setting this bit high will start the decoding operation. HW will
* reset this when picture is processed or ASO or stream error is detected or bus error or timeout
* interrupt is given.
*/
#define VPU_G1_SWREG1_SW_DEC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_E_SHIFT)) & VPU_G1_SWREG1_SW_DEC_E_MASK)
#define VPU_G1_SWREG1_SW_DEC_IRQ_DIS_MASK (0x10U)
#define VPU_G1_SWREG1_SW_DEC_IRQ_DIS_SHIFT (4U)
/*! SW_DEC_IRQ_DIS - Decoder IRQ disable. When high, there are no interrupts concerning decoder from
* HW. Polling must be used to see the interrupt statuses.
*/
#define VPU_G1_SWREG1_SW_DEC_IRQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_IRQ_DIS_SHIFT)) & VPU_G1_SWREG1_SW_DEC_IRQ_DIS_MASK)
#define VPU_G1_SWREG1_SW_DEC_ABORT_E_MASK (0x20U)
#define VPU_G1_SWREG1_SW_DEC_ABORT_E_SHIFT (5U)
/*! SW_DEC_ABORT_E - Abort decoding enable. Setting this bit high will cause HW to abort decoding
* and safely to reset itself down. After abort is complete the corresponding interrupt status is
* set and this bit is set low as well as the decoder enable.
*/
#define VPU_G1_SWREG1_SW_DEC_ABORT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ABORT_E_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ABORT_E_MASK)
#define VPU_G1_SWREG1_SW_DEC_IRQ_MASK (0x100U)
#define VPU_G1_SWREG1_SW_DEC_IRQ_SHIFT (8U)
/*! SW_DEC_IRQ - Decoder IRQ. When high, decoder requests an interrupt. SW will reset this after interrupt is handled.
*/
#define VPU_G1_SWREG1_SW_DEC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_IRQ_SHIFT)) & VPU_G1_SWREG1_SW_DEC_IRQ_MASK)
#define VPU_G1_SWREG1_SW_DEC_RDY_INT_MASK (0x1000U)
#define VPU_G1_SWREG1_SW_DEC_RDY_INT_SHIFT (12U)
/*! SW_DEC_RDY_INT - Interrupt status bit decoder. When this bit is high decoder has decoded a picture. HW will self reset.
*/
#define VPU_G1_SWREG1_SW_DEC_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_RDY_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_RDY_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_BUS_INT_MASK (0x2000U)
#define VPU_G1_SWREG1_SW_DEC_BUS_INT_SHIFT (13U)
/*! SW_DEC_BUS_INT - Interrupt status bit bus. Error response from bus.
*/
#define VPU_G1_SWREG1_SW_DEC_BUS_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_BUS_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_BUS_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_BUFFER_INT_MASK (0x4000U)
#define VPU_G1_SWREG1_SW_DEC_BUFFER_INT_SHIFT (14U)
/*! SW_DEC_BUFFER_INT - Interrupt status bit input buffer empty. When high, input stream buffer is
* empty but picture is not ready. HW will not self reset.
*/
#define VPU_G1_SWREG1_SW_DEC_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_BUFFER_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_BUFFER_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_ASO_INT_MASK (0x8000U)
#define VPU_G1_SWREG1_SW_DEC_ASO_INT_SHIFT (15U)
/*! SW_DEC_ASO_INT - H264: Interrupt status bit ASO (Arbitrary Slice Ordering) detected. When high,
* ASO detected in input data stream decoding. HW will self reset. VP8: Error detected in
* Residual data. HW returns MB number in error concealment register for MB it detected it
*/
#define VPU_G1_SWREG1_SW_DEC_ASO_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ASO_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ASO_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_ERROR_INT_MASK (0x10000U)
#define VPU_G1_SWREG1_SW_DEC_ERROR_INT_SHIFT (16U)
/*! SW_DEC_ERROR_INT - Interrupt status bit input stream error. When high, an error is found in input data stream decoding. HW will self reset.
*/
#define VPU_G1_SWREG1_SW_DEC_ERROR_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_ERROR_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_ERROR_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_SLICE_INT_MASK (0x20000U)
#define VPU_G1_SWREG1_SW_DEC_SLICE_INT_SHIFT (17U)
/*! SW_DEC_SLICE_INT - Interrupt status bit dec_slice_decoded. When high SW must set new base
* addresses for sw_dec_out_base and sw_jpg_ch_out_base before resetting this status bit. Used for VP8
* web-p modes
*/
#define VPU_G1_SWREG1_SW_DEC_SLICE_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_SLICE_INT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_SLICE_INT_MASK)
#define VPU_G1_SWREG1_SW_DEC_TIMEOUT_MASK (0x40000U)
#define VPU_G1_SWREG1_SW_DEC_TIMEOUT_SHIFT (18U)
/*! SW_DEC_TIMEOUT - Interrupt status bit decoder timeout. When high the decoder has been idling for
* too long. HW will self reset. Possible only if timeout interrupt is enabled
*/
#define VPU_G1_SWREG1_SW_DEC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_TIMEOUT_SHIFT)) & VPU_G1_SWREG1_SW_DEC_TIMEOUT_MASK)
#define VPU_G1_SWREG1_SW_DEC_PIC_INF_MASK (0x1000000U)
#define VPU_G1_SWREG1_SW_DEC_PIC_INF_SHIFT (24U)
/*! SW_DEC_PIC_INF - B slice detected. This signal is driven high during picture ready interrupt if
* B-type slice is found. This bit does not launch interrupt but is used to inform SW about h264
* tools.
*/
#define VPU_G1_SWREG1_SW_DEC_PIC_INF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG1_SW_DEC_PIC_INF_SHIFT)) & VPU_G1_SWREG1_SW_DEC_PIC_INF_MASK)
/*! @} */
/*! @name SWREG2 - Device configuration register decoder */
/*! @{ */
#define VPU_G1_SWREG2_SW_DEC_MAX_BURST_MASK (0x1FU)
#define VPU_G1_SWREG2_SW_DEC_MAX_BURST_SHIFT (0U)
/*! SW_DEC_MAX_BURST - Maximum burst length for decoder bus transactions.
*/
#define VPU_G1_SWREG2_SW_DEC_MAX_BURST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_MAX_BURST_SHIFT)) & VPU_G1_SWREG2_SW_DEC_MAX_BURST_MASK)
#define VPU_G1_SWREG2_SW_DEC_SCMD_DIS_MASK (0x20U)
#define VPU_G1_SWREG2_SW_DEC_SCMD_DIS_SHIFT (5U)
/*! SW_DEC_SCMD_DIS - 9170 decoder and later->: AXI Single Command Multiple Data disable. 9170 axi
* wrapper supports this mode by default (where only the first addresses of the burst are given
* from address generator). This bit is used to disable the feature (possible SW workaround if
* something is not working correctly)
*/
#define VPU_G1_SWREG2_SW_DEC_SCMD_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_SCMD_DIS_SHIFT)) & VPU_G1_SWREG2_SW_DEC_SCMD_DIS_MASK)
#define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_MASK (0x40U)
#define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_SHIFT (6U)
/*! SW_DEC_ADV_PRE_DIS - Advanced PREFETCH mode disable (advanced reference picture reading mode for video)
*/
#define VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_SHIFT)) & VPU_G1_SWREG2_SW_DEC_ADV_PRE_DIS_MASK)
#define VPU_G1_SWREG2_SW_TILED_MODE_LSB_MASK (0x80U)
#define VPU_G1_SWREG2_SW_TILED_MODE_LSB_SHIFT (7U)
/*! SW_TILED_MODE_LSB - Tiled mode lsb. Concatenated to Tiled mode msb which form 2 bit tiled mode. Defined in tiled_mode_msb
*/
#define VPU_G1_SWREG2_SW_TILED_MODE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_TILED_MODE_LSB_SHIFT)) & VPU_G1_SWREG2_SW_TILED_MODE_LSB_MASK)
#define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_MASK (0x100U)
#define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_SHIFT (8U)
/*! SW_DEC_OUT_ENDIAN - Decoder output endian mode:
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_SHIFT)) & VPU_G1_SWREG2_SW_DEC_OUT_ENDIAN_MASK)
#define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_MASK (0x200U)
#define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_SHIFT (9U)
/*! SW_DEC_IN_ENDIAN - Decoder input endian mode for other than stream data:
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG2_SW_DEC_IN_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_SHIFT)) & VPU_G1_SWREG2_SW_DEC_IN_ENDIAN_MASK)
#define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_MASK (0x400U)
#define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_SHIFT (10U)
/*! SW_DEC_CLK_GATE_E - Decoder dynamic clock gating enable:
* 0b0..Clock is running for all structures
* 0b1..Clock is gated for decoder structures that are not used. Note: Clock gating value can be changed only when decoder is disabled.
*/
#define VPU_G1_SWREG2_SW_DEC_CLK_GATE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_CLK_GATE_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_LATENCY_MASK (0x1F800U)
#define VPU_G1_SWREG2_SW_DEC_LATENCY_SHIFT (11U)
/*! SW_DEC_LATENCY - Decoder master interface additional latency.
*/
#define VPU_G1_SWREG2_SW_DEC_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_LATENCY_SHIFT)) & VPU_G1_SWREG2_SW_DEC_LATENCY_MASK)
#define VPU_G1_SWREG2_SW_TILED_MODE_MSB_MASK (0x20000U)
#define VPU_G1_SWREG2_SW_TILED_MODE_MSB_SHIFT (17U)
/*! SW_TILED_MODE_MSB - Tiled mode msb. Concatenated to Tiled mode lsb which form 2 bit tiled mode.
* 0b0..Tiled mode not enabled
* 0b1..Tiled mode enabled for 8x4 tile size
*/
#define VPU_G1_SWREG2_SW_TILED_MODE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_TILED_MODE_MSB_SHIFT)) & VPU_G1_SWREG2_SW_TILED_MODE_MSB_MASK)
#define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_MASK (0x40000U)
#define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_SHIFT (18U)
/*! SW_DEC_DATA_DISC_E - Data discard enable. Precise burst lengths are used with reading services.
* Extra data is discarded internally. Note. If AHB maxburst 17 is used data discard cannot be
* enabled (causes conflict)
*/
#define VPU_G1_SWREG2_SW_DEC_DATA_DISC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_DATA_DISC_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_MASK (0x80000U)
#define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_SHIFT (19U)
/*! SW_DEC_OUTSWAP32_E - Decoder output 32bit data swap (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
*/
#define VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_OUTSWAP32_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_INSWAP32_E_MASK (0x100000U)
#define VPU_G1_SWREG2_SW_DEC_INSWAP32_E_SHIFT (20U)
/*! SW_DEC_INSWAP32_E - Decoder input 32bit data swap for other than stream data (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
*/
#define VPU_G1_SWREG2_SW_DEC_INSWAP32_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_INSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_INSWAP32_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_MASK (0x200000U)
#define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_SHIFT (21U)
/*! SW_DEC_STRENDIAN_E - Decoder input endian mode for stream data:
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG2_SW_DEC_STRENDIAN_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_STRENDIAN_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_MASK (0x400000U)
#define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_SHIFT (22U)
/*! SW_DEC_STRSWAP32_E - Decoder input 32bit data swap for stream data (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
*/
#define VPU_G1_SWREG2_SW_DEC_STRSWAP32_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_STRSWAP32_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_MASK (0x800000U)
#define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_SHIFT (23U)
/*! SW_DEC_TIMEOUT_E - Timeout interrupt enable. If enabled HW may return timeout interrupt in case HW gets stuck while decoding picture.
*/
#define VPU_G1_SWREG2_SW_DEC_TIMEOUT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_SHIFT)) & VPU_G1_SWREG2_SW_DEC_TIMEOUT_E_MASK)
#define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_MASK (0xFF000000U)
#define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_SHIFT (24U)
/*! SW_DEC_AXI_RD_ID - Read ID used for decoder reading services in AXI bus (if connected to AXI).
*/
#define VPU_G1_SWREG2_SW_DEC_AXI_RD_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_SHIFT)) & VPU_G1_SWREG2_SW_DEC_AXI_RD_ID_MASK)
/*! @} */
/*! @name SWREG3 - Decoder control register 0 (decmode,picture type etc) */
/*! @{ */
#define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_MASK (0xFFU)
#define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_SHIFT (0U)
/*! SW_DEC_AXI_WR_ID - Write ID used for decoder writing services in AXI bus (if connected to AXI)
*/
#define VPU_G1_SWREG3_SW_DEC_AXI_WR_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_SHIFT)) & VPU_G1_SWREG3_SW_DEC_AXI_WR_ID_MASK)
#define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_MASK (0x100U)
#define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_SHIFT (8U)
/*! SW_DEC_AHB_HLOCK_E - AHB master HLOCK enable. When high the service is locked to decoder as long
* as it needs the bus (whenever decoder requests the bus it will be granted)
*/
#define VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_SHIFT)) & VPU_G1_SWREG3_SW_DEC_AHB_HLOCK_E_MASK)
#define VPU_G1_SWREG3_SW_PICORD_COUNT_E_MASK (0x200U)
#define VPU_G1_SWREG3_SW_PICORD_COUNT_E_SHIFT (9U)
/*! SW_PICORD_COUNT_E - h264_high config: Picture order count table read enable. If enabled HW will
* read picture order counts from memory in the beginning of picture
*/
#define VPU_G1_SWREG3_SW_PICORD_COUNT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PICORD_COUNT_E_SHIFT)) & VPU_G1_SWREG3_SW_PICORD_COUNT_E_MASK)
#define VPU_G1_SWREG3_SW_SEQ_MBAFF_E_MASK (0x400U)
#define VPU_G1_SWREG3_SW_SEQ_MBAFF_E_SHIFT (10U)
/*! SW_SEQ_MBAFF_E - Sequence includes MBAFF coded pictures
*/
#define VPU_G1_SWREG3_SW_SEQ_MBAFF_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_SEQ_MBAFF_E_SHIFT)) & VPU_G1_SWREG3_SW_SEQ_MBAFF_E_MASK)
#define VPU_G1_SWREG3_SW_REFTOPFIRST_E_MASK (0x800U)
#define VPU_G1_SWREG3_SW_REFTOPFIRST_E_SHIFT (11U)
/*! SW_REFTOPFIRST_E - Indicates which FWD reference field has been decoded first.
* 0b0..FWD reference bottom field
* 0b1..FWD reference top field
*/
#define VPU_G1_SWREG3_SW_REFTOPFIRST_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_REFTOPFIRST_E_SHIFT)) & VPU_G1_SWREG3_SW_REFTOPFIRST_E_MASK)
#define VPU_G1_SWREG3_SW_WRITE_MVS_E_MASK (0x1000U)
#define VPU_G1_SWREG3_SW_WRITE_MVS_E_SHIFT (12U)
/*! SW_WRITE_MVS_E - Direct mode motion vector write enable for current picture / VPX motion vector
* write enable for error concealment purposes:
* 0b0..Writing disabled for current picture
* 0b1..The direct mode motion vectors are written to external memory. H264 direct mode motion vectors are
* written to DPB aside with the corresponding reference picture. Other decoding mode dir mode mvs are written to
* external memory starting from sw_dir_mv_base.
*/
#define VPU_G1_SWREG3_SW_WRITE_MVS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_WRITE_MVS_E_SHIFT)) & VPU_G1_SWREG3_SW_WRITE_MVS_E_MASK)
#define VPU_G1_SWREG3_SW_WEBP_E_MASK (0x2000U)
#define VPU_G1_SWREG3_SW_WEBP_E_SHIFT (13U)
#define VPU_G1_SWREG3_SW_WEBP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_WEBP_E_SHIFT)) & VPU_G1_SWREG3_SW_WEBP_E_MASK)
#define VPU_G1_SWREG3_SW_FILTERING_DIS_MASK (0x4000U)
#define VPU_G1_SWREG3_SW_FILTERING_DIS_SHIFT (14U)
/*! SW_FILTERING_DIS - De-block filtering disable:
* 0b1..filtering is disabled for current picture
* 0b0..filtering is enabled for current picture
*/
#define VPU_G1_SWREG3_SW_FILTERING_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_FILTERING_DIS_SHIFT)) & VPU_G1_SWREG3_SW_FILTERING_DIS_MASK)
#define VPU_G1_SWREG3_SW_DEC_OUT_DIS_MASK (0x8000U)
#define VPU_G1_SWREG3_SW_DEC_OUT_DIS_SHIFT (15U)
/*! SW_DEC_OUT_DIS - Disable decoder output picture writing:
* 0b0..Decoder output picture is written to external memory
* 0b1..Decoder output picture is not written to external memory
*/
#define VPU_G1_SWREG3_SW_DEC_OUT_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_OUT_DIS_SHIFT)) & VPU_G1_SWREG3_SW_DEC_OUT_DIS_MASK)
#define VPU_G1_SWREG3_SW_REF_TOPFIELD_E_MASK (0x10000U)
#define VPU_G1_SWREG3_SW_REF_TOPFIELD_E_SHIFT (16U)
/*! SW_REF_TOPFIELD_E - Indicates which field should be used as reference if sw_ref_frames = '0':
* 0b0..bottom field
* 0b1..top field
*/
#define VPU_G1_SWREG3_SW_REF_TOPFIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_REF_TOPFIELD_E_SHIFT)) & VPU_G1_SWREG3_SW_REF_TOPFIELD_E_MASK)
#define VPU_G1_SWREG3_SW_FWD_INTERLACE_E_MASK (0x40000U)
#define VPU_G1_SWREG3_SW_FWD_INTERLACE_E_SHIFT (18U)
/*! SW_FWD_INTERLACE_E - Coding mode of forward reference picture
* 0b0..progressive
* 0b1..interlaced
*/
#define VPU_G1_SWREG3_SW_FWD_INTERLACE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_FWD_INTERLACE_E_SHIFT)) & VPU_G1_SWREG3_SW_FWD_INTERLACE_E_MASK)
#define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_MASK (0x80000U)
#define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_SHIFT (19U)
/*! SW_PIC_TOPFIELD_E - If field structure is enabled, this bit informs which one of the fields is being decoded:
* 0b0..bottom field
* 0b1..top field
*/
#define VPU_G1_SWREG3_SW_PIC_TOPFIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_TOPFIELD_E_MASK)
#define VPU_G1_SWREG3_SW_PIC_INTER_E_MASK (0x100000U)
#define VPU_G1_SWREG3_SW_PIC_INTER_E_SHIFT (20U)
/*! SW_PIC_INTER_E - Picture type. Please also see SW_PIC_B_E.
* 0b1..Inter type (P)
* 0b0..Intra type (I)
*/
#define VPU_G1_SWREG3_SW_PIC_INTER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_INTER_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_INTER_E_MASK)
#define VPU_G1_SWREG3_SW_PIC_B_E_MASK (0x200000U)
#define VPU_G1_SWREG3_SW_PIC_B_E_SHIFT (21U)
/*! SW_PIC_B_E - B picture enable for current picture:
* 0b0..picture type is I or P depending on sw_pic_inter_e
* 0b1..picture type is B depending on sw_pic_inter_e (not valid for H264 since it is slice based information)
*/
#define VPU_G1_SWREG3_SW_PIC_B_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_B_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_B_E_MASK)
#define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_MASK (0x400000U)
#define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_SHIFT (22U)
/*! SW_PIC_FIELDMODE_E - Structure of the current picture (residual structure)
* 0b0..Frame structure. For H264, this means MBAFF structured picture for interlaced sequence
* 0b1..Field structure
*/
#define VPU_G1_SWREG3_SW_PIC_FIELDMODE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_FIELDMODE_E_MASK)
#define VPU_G1_SWREG3_SW_PIC_INTERLACE_E_MASK (0x800000U)
#define VPU_G1_SWREG3_SW_PIC_INTERLACE_E_SHIFT (23U)
/*! SW_PIC_INTERLACE_E - Coding mode of the current picture:
* 0b0..progressive
* 0b1..interlaced
*/
#define VPU_G1_SWREG3_SW_PIC_INTERLACE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_PIC_INTERLACE_E_SHIFT)) & VPU_G1_SWREG3_SW_PIC_INTERLACE_E_MASK)
#define VPU_G1_SWREG3_SW_SKIP_MODE_MASK (0x4000000U)
#define VPU_G1_SWREG3_SW_SKIP_MODE_SHIFT (26U)
#define VPU_G1_SWREG3_SW_SKIP_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_SKIP_MODE_SHIFT)) & VPU_G1_SWREG3_SW_SKIP_MODE_MASK)
#define VPU_G1_SWREG3_SW_RLC_MODE_E_MASK (0x8000000U)
#define VPU_G1_SWREG3_SW_RLC_MODE_E_SHIFT (27U)
/*! SW_RLC_MODE_E - RLC mode enable:
* 0b1..HW decodes video from RLC input data + side information (Differential MV's, separate DC coeffs, Intra 4x4
* modes, MB control). Valid only for H.264 Baseline.
* 0b0..HW decodes video from bit stream (VLC mode) + side information
*/
#define VPU_G1_SWREG3_SW_RLC_MODE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_RLC_MODE_E_SHIFT)) & VPU_G1_SWREG3_SW_RLC_MODE_E_MASK)
#define VPU_G1_SWREG3_SW_DEC_MODE_MASK (0xF0000000U)
#define VPU_G1_SWREG3_SW_DEC_MODE_SHIFT (28U)
/*! SW_DEC_MODE - Decoding mode:
* 0b0000..H.264
* 0b0001..Reserved
* 0b0010..Reserved
* 0b0011..Reserved
* 0b0100..Reserved
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
* 0b1000..Reserved
* 0b1001..Reserved
* 0b1010..VP8
* 0b1011..Reserved
* 0b1100..Reserved
* 0b1101..Reserved
* 0b1110..Reserved
* 0b1111..Reserved
*/
#define VPU_G1_SWREG3_SW_DEC_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG3_SW_DEC_MODE_SHIFT)) & VPU_G1_SWREG3_SW_DEC_MODE_MASK)
/*! @} */
/*! @name SWREG12 - Base address for RLC data (RLC) / stream start address/decoded end addr register (VLC) */
/*! @{ */
#define VPU_G1_SWREG12_SW_RLC_VLC_BASE_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG12_SW_RLC_VLC_BASE_SHIFT (0U)
#define VPU_G1_SWREG12_SW_RLC_VLC_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG12_SW_RLC_VLC_BASE_SHIFT)) & VPU_G1_SWREG12_SW_RLC_VLC_BASE_MASK)
/*! @} */
/*! @name SWREG13 - Base address for decoded picture */
/*! @{ */
#define VPU_G1_SWREG13_SW_DPB_ILACE_MODE_MASK (0x2U)
#define VPU_G1_SWREG13_SW_DPB_ILACE_MODE_SHIFT (1U)
/*! SW_DPB_ILACE_MODE - DPB ilaced mode: '0' : DPB consist of ilaced/progressive frames '1' : DPB
* consist of progressive frames / separate fields. This mode requires config support from HW
*/
#define VPU_G1_SWREG13_SW_DPB_ILACE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG13_SW_DPB_ILACE_MODE_SHIFT)) & VPU_G1_SWREG13_SW_DPB_ILACE_MODE_MASK)
#define VPU_G1_SWREG13_SW_DEC_OUT_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG13_SW_DEC_OUT_BASE_SHIFT (2U)
/*! SW_DEC_OUT_BASE - Video: Base address for decoder output picture. Points directly to start of decoder output picture or field.
*/
#define VPU_G1_SWREG13_SW_DEC_OUT_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG13_SW_DEC_OUT_BASE_SHIFT)) & VPU_G1_SWREG13_SW_DEC_OUT_BASE_MASK)
/*! @} */
/*! @name SWREG40 - Base address for standard dependent tables */
/*! @{ */
#define VPU_G1_SWREG40_SW_QTABLE_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG40_SW_QTABLE_BASE_SHIFT (2U)
/*! SW_QTABLE_BASE - Base address for standard dependent tables:
*/
#define VPU_G1_SWREG40_SW_QTABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG40_SW_QTABLE_BASE_SHIFT)) & VPU_G1_SWREG40_SW_QTABLE_BASE_MASK)
/*! @} */
/*! @name SWREG41 - Base address for direct mode motion vectors */
/*! @{ */
#define VPU_G1_SWREG41_SW_DIR_MV_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG41_SW_DIR_MV_BASE_SHIFT (2U)
/*! SW_DIR_MV_BASE - Direct mode motion vector write/read base address. For H264 this is used only
* for direct mode motion vector write base. VP8: Motion vectors are written for error concealment
* purposes if sw_write_mvs is high. In error concealment mode motion vectors are read from this
* base address
*/
#define VPU_G1_SWREG41_SW_DIR_MV_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG41_SW_DIR_MV_BASE_SHIFT)) & VPU_G1_SWREG41_SW_DIR_MV_BASE_MASK)
/*! @} */
/*! @name SWREG48 - Error concealment register */
/*! @{ */
#define VPU_G1_SWREG48_SW_ERROR_CONC_MODE_MASK (0x3000U)
#define VPU_G1_SWREG48_SW_ERROR_CONC_MODE_SHIFT (12U)
/*! SW_ERROR_CONC_MODE - Error concealment mode:
* 0b00..disabled (normal decoding mode)
* 0b01..enabled for direct mode MV usage starting from MB defined by sw_startmb_x, sw_startmb_y
*/
#define VPU_G1_SWREG48_SW_ERROR_CONC_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_ERROR_CONC_MODE_SHIFT)) & VPU_G1_SWREG48_SW_ERROR_CONC_MODE_MASK)
#define VPU_G1_SWREG48_SW_STARTMB_Y_MASK (0x7FC000U)
#define VPU_G1_SWREG48_SW_STARTMB_Y_SHIFT (14U)
/*! SW_STARTMB_Y - Start MB from SW for Y dimension. Used in error concealment case as HW return
* value if HW founds an error or in HW init mb for error concealment if SW enables error concealment
*/
#define VPU_G1_SWREG48_SW_STARTMB_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_STARTMB_Y_SHIFT)) & VPU_G1_SWREG48_SW_STARTMB_Y_MASK)
#define VPU_G1_SWREG48_SW_STARTMB_X_MASK (0xFF800000U)
#define VPU_G1_SWREG48_SW_STARTMB_X_SHIFT (23U)
/*! SW_STARTMB_X - Start MB from SW for X dimension. Used in error concealment case as HW return
* value if HW founds an error or in HW init mb for error concealment if SW enables error concealment
*/
#define VPU_G1_SWREG48_SW_STARTMB_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG48_SW_STARTMB_X_SHIFT)) & VPU_G1_SWREG48_SW_STARTMB_X_MASK)
/*! @} */
/*! @name SWREG49 - Prediction filter tap register for H264 */
/*! @{ */
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_MASK (0xFFCU)
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_SHIFT (2U)
/*! SW_PRED_BC_TAP_0_2 - Prediction filter set 0, tap 2
*/
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_2_MASK)
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_MASK (0x3FF000U)
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_SHIFT (12U)
/*! SW_PRED_BC_TAP_0_1 - Prediction filter set 0, tap 1
*/
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_1_MASK)
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_MASK (0xFFC00000U)
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_SHIFT (22U)
/*! SW_PRED_BC_TAP_0_0 - Prediction filter set 0, tap 0
*/
#define VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_SHIFT)) & VPU_G1_SWREG49_SW_PRED_BC_TAP_0_0_MASK)
/*! @} */
/*! @name SWREG50 - Synthesis configuration register decoder 0 */
/*! @{ */
#define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_MASK (0x7FFU)
#define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT (0U)
/*! SW_DEC_MAX_OWIDTH - Max configured decoder video resolution that can be decoded. Informed as width of the picture in pixels.
*/
#define VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT)) & VPU_G1_SWREG50_SW_DEC_MAX_OWIDTH_MASK)
#define VPU_G1_SWREG50_SW_DEC_SOREN_PROF_MASK (0x800U)
#define VPU_G1_SWREG50_SW_DEC_SOREN_PROF_SHIFT (11U)
/*! SW_DEC_SOREN_PROF - Decoding format support, Sorenson
* 0b0..not supported
* 0b1..supported
*/
#define VPU_G1_SWREG50_SW_DEC_SOREN_PROF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_SOREN_PROF_SHIFT)) & VPU_G1_SWREG50_SW_DEC_SOREN_PROF_MASK)
#define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_MASK (0x3000U)
#define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_SHIFT (12U)
/*! SW_DEC_BUS_WIDTH
* 0b00..error
* 0b01..32 bit bus
* 0b10..64 bit bus
* 0b11..128 bit bus
*/
#define VPU_G1_SWREG50_SW_DEC_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_SHIFT)) & VPU_G1_SWREG50_SW_DEC_BUS_WIDTH_MASK)
#define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_MASK (0xC000U)
#define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_SHIFT (14U)
/*! SW_DEC_SYNTH_LAN
* 0b00..error
* 0b01..vhdl
* 0b10..verilog
*/
#define VPU_G1_SWREG50_SW_DEC_SYNTH_LAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_SHIFT)) & VPU_G1_SWREG50_SW_DEC_SYNTH_LAN_MASK)
#define VPU_G1_SWREG50_SW_DEC_BUS_STRD_MASK (0xF0000U)
#define VPU_G1_SWREG50_SW_DEC_BUS_STRD_SHIFT (16U)
/*! SW_DEC_BUS_STRD - Connected to standard bus:
* 0b0000..error
* 0b0001..AHB master, AHB slave
* 0b0010..OCP master, OCP slave
* 0b0011..AXI master, AXI slave
* 0b0100..AXI master, APB slave
* 0b0101..AXI master, AHB slave
*/
#define VPU_G1_SWREG50_SW_DEC_BUS_STRD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_BUS_STRD_SHIFT)) & VPU_G1_SWREG50_SW_DEC_BUS_STRD_MASK)
#define VPU_G1_SWREG50_SW_REF_BUFF_EXIST_MASK (0x100000U)
#define VPU_G1_SWREG50_SW_REF_BUFF_EXIST_SHIFT (20U)
/*! SW_REF_BUFF_EXIST - Reference picture buffer usage:
* 0b0..not supported
* 0b1..reference buffer is used
*/
#define VPU_G1_SWREG50_SW_REF_BUFF_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_REF_BUFF_EXIST_SHIFT)) & VPU_G1_SWREG50_SW_REF_BUFF_EXIST_MASK)
#define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_MASK (0x200000U)
#define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_SHIFT (21U)
/*! SW_DEC_OBUFF_LEVEL - Decoder output buffer level:
* 0b0..1 MB buffering is used
* 0b1..4 MB buffering is used
*/
#define VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG50_SW_DEC_OBUFF_LEVEL_MASK)
#define VPU_G1_SWREG50_SW_DEC_H264_PROF_MASK (0x3000000U)
#define VPU_G1_SWREG50_SW_DEC_H264_PROF_SHIFT (24U)
/*! SW_DEC_H264_PROF - Decoding format support, H.264
* 0b00..not supported
* 0b01..supported up to baseline profile
* 0b10..supported up to high profile labeled stream with restricted high profile tools (Tools that are used in Hantro 7280, 8270 encoder)
* 0b11..supported up to high profile
*/
#define VPU_G1_SWREG50_SW_DEC_H264_PROF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG50_SW_DEC_H264_PROF_SHIFT)) & VPU_G1_SWREG50_SW_DEC_H264_PROF_MASK)
/*! @} */
/*! @name SWREG51 - Reference picture buffer control register */
/*! @{ */
#define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_MASK (0x1FFU)
#define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_SHIFT (0U)
/*! SW_REFBU_Y_OFFSET - Y offset for refbufferd. This coordinate is used to compensate the global motion of the video for better buffer hit rate
*/
#define VPU_G1_SWREG51_SW_REFBU_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_Y_OFFSET_MASK)
#define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_MASK (0x1000U)
#define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_SHIFT (12U)
/*! SW_REFBU_FPARMOD_E - Field parity mode enable. Used in refbufferd evaluation mode.
* 0b0..use the result field of the evaluation
* 0b1..use the parity mode field
*/
#define VPU_G1_SWREG51_SW_REFBU_FPARMOD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_FPARMOD_E_MASK)
#define VPU_G1_SWREG51_SW_REFBU_EVAL_E_MASK (0x2000U)
#define VPU_G1_SWREG51_SW_REFBU_EVAL_E_SHIFT (13U)
/*! SW_REFBU_EVAL_E - Enable for HW internal reference ID calculation. If given threshold level is
* reached by any picture_id after first MB row, that picture_id is used for reference buffer fill
* for rest of the picture
*/
#define VPU_G1_SWREG51_SW_REFBU_EVAL_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_EVAL_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_EVAL_E_MASK)
#define VPU_G1_SWREG51_SW_REFBU_PICID_MASK (0x7C000U)
#define VPU_G1_SWREG51_SW_REFBU_PICID_SHIFT (14U)
/*! SW_REFBU_PICID - The used reference picture ID for reference buffer usage
*/
#define VPU_G1_SWREG51_SW_REFBU_PICID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_PICID_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_PICID_MASK)
#define VPU_G1_SWREG51_SW_REFBU_THR_MASK (0x7FF80000U)
#define VPU_G1_SWREG51_SW_REFBU_THR_SHIFT (19U)
/*! SW_REFBU_THR - Reference buffer disable threshold value (cache miss amount). Used to buffer shut down (if more misses than allowed)
*/
#define VPU_G1_SWREG51_SW_REFBU_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_THR_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_THR_MASK)
#define VPU_G1_SWREG51_SW_REFBU_E_MASK (0x80000000U)
#define VPU_G1_SWREG51_SW_REFBU_E_SHIFT (31U)
/*! SW_REFBU_E - Refer picture buffer enable:
* 0b0..refer picture buffer disabled
* 0b1..refer picture buffer enabled. Valid if picture size is QVGA or more.
*/
#define VPU_G1_SWREG51_SW_REFBU_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG51_SW_REFBU_E_SHIFT)) & VPU_G1_SWREG51_SW_REFBU_E_MASK)
/*! @} */
/*! @name SWREG52 - Reference picture buffer information register 1 */
/*! @{ */
#define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_MASK (0xFFFFU)
#define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_SHIFT (0U)
/*! SW_REFBU_INTRA_SUM - The sum of the luminance 8x8 intra partitions of the picture. The
* proceeding of the HW calculation can be read during HW decoding.
*/
#define VPU_G1_SWREG52_SW_REFBU_INTRA_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_SHIFT)) & VPU_G1_SWREG52_SW_REFBU_INTRA_SUM_MASK)
#define VPU_G1_SWREG52_SW_REFBU_HIT_SUM_MASK (0xFFFF0000U)
#define VPU_G1_SWREG52_SW_REFBU_HIT_SUM_SHIFT (16U)
/*! SW_REFBU_HIT_SUM - The sum of the refbufferd hits of the picture. Determined for each 8x8
* luminance partition of the picture. The proceeding of the HW calculation can be read during HW
* decoding.
*/
#define VPU_G1_SWREG52_SW_REFBU_HIT_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG52_SW_REFBU_HIT_SUM_SHIFT)) & VPU_G1_SWREG52_SW_REFBU_HIT_SUM_MASK)
/*! @} */
/*! @name SWREG53 - Reference picture buffer information register 2 */
/*! @{ */
#define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_MASK (0x3FFFFFU)
#define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_SHIFT (0U)
/*! SW_REFBU_Y_MV_SUM - The sum of the decoded motion vector y-components of the picture. The first
* luminance motion vector of each MB is used in calculation. Other motion vectors of the MB are
* discarded. Each motion vector is saturated between -256 - 255 before calculation. The
* proceeding of the HW calculation can be read during HW decoding.
*/
#define VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_SHIFT)) & VPU_G1_SWREG53_SW_REFBU_Y_MV_SUM_MASK)
/*! @} */
/*! @name SWREG54 - Synthesis configuration register decoder 1 */
/*! @{ */
#define VPU_G1_SWREG54_SW_DEC_CORE_AM_MASK (0x380U)
#define VPU_G1_SWREG54_SW_DEC_CORE_AM_SHIFT (7U)
/*! SW_DEC_CORE_AM - Decoder core amount. If other than 0, the multicore can be used. Each
* individual cores can be identified from corresponding core ID register:
* 0b000..single core decoder
* 0b001..dual core decoder
* 0b010..3 core decoder
* 0b011..4 core decoder
* 0b100..5 core decoder
* 0b101..6 core decoder
* 0b110..7 core decoder
* 0b111..8 core decoder
*/
#define VPU_G1_SWREG54_SW_DEC_CORE_AM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_CORE_AM_SHIFT)) & VPU_G1_SWREG54_SW_DEC_CORE_AM_MASK)
#define VPU_G1_SWREG54_SW_DPB_FIELD_E_MASK (0x400U)
#define VPU_G1_SWREG54_SW_DPB_FIELD_E_SHIFT (10U)
/*! SW_DPB_FIELD_E - DPB field separate mode support for ilaced content:
* 0b0..Not supported. For ilaced content, DPB is ilaced frame order.
* 0b1..Supported. For ilaced content, DPB can consist of ilaced frames or separate fields (TOP/BOT).
*/
#define VPU_G1_SWREG54_SW_DPB_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DPB_FIELD_E_SHIFT)) & VPU_G1_SWREG54_SW_DPB_FIELD_E_MASK)
#define VPU_G1_SWREG54_SW_VP8_STRIDE_E_MASK (0x800U)
#define VPU_G1_SWREG54_SW_VP8_STRIDE_E_SHIFT (11U)
/*! SW_VP8_STRIDE_E - Decoder output stride support for VP8. Separate base addresses for Y/C data
* and possibility to set scanline bigger than picture width:
* 0b0..not supported, Y and C tables attached.
* 0b1..supported, Y and C tables can be set freely.
*/
#define VPU_G1_SWREG54_SW_VP8_STRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_VP8_STRIDE_E_SHIFT)) & VPU_G1_SWREG54_SW_VP8_STRIDE_E_MASK)
#define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_MASK (0x3000U)
#define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_SHIFT (12U)
/*! SW_DEC_ERRCO_LEVEL - Decoder error concealment support level:
* 0b00..Error concealment not supported (only error detection)
* 0b01..VP8 direct mode motion vector error concealment supported
*/
#define VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_SHIFT)) & VPU_G1_SWREG54_SW_DEC_ERRCO_LEVEL_MASK)
#define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_MASK (0xC000U)
#define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT (14U)
/*! SW_DEC_MAX_OW_EXT - Max configured decoder video resolution that can be decoded. This is the MSB part of the configuration signal
*/
#define VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT)) & VPU_G1_SWREG54_SW_DEC_MAX_OW_EXT_MASK)
#define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_MASK (0x10000U)
#define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_SHIFT (16U)
/*! SW_DEC_VP8S_ARCH - VP8 Architecture type (for prediction)
* 0b0..Same prediction architecture as for other decoding formats
* 0b1..Dedicated small architecture for VP8 (refbuffer cannot be used either)
*/
#define VPU_G1_SWREG54_SW_DEC_VP8S_ARCH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_SHIFT)) & VPU_G1_SWREG54_SW_DEC_VP8S_ARCH_MASK)
#define VPU_G1_SWREG54_SW_DEC_TILED_L_MASK (0x60000U)
#define VPU_G1_SWREG54_SW_DEC_TILED_L_SHIFT (17U)
/*! SW_DEC_TILED_L - Tiled mode support level
* 0b00..not supported
* 0b01..supported with 8x4 tile size for progressive content
* 0b10..supported with 8x4 tile size for progressive/ilaced content
*/
#define VPU_G1_SWREG54_SW_DEC_TILED_L(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_TILED_L_SHIFT)) & VPU_G1_SWREG54_SW_DEC_TILED_L_MASK)
#define VPU_G1_SWREG54_SW_DEC_WEBP_E_MASK (0x80000U)
#define VPU_G1_SWREG54_SW_DEC_WEBP_E_SHIFT (19U)
/*! SW_DEC_WEBP_E - Decoding format support, Web-p
* 0b0..not supported bigger than 1080p resolution
* 0b1..supported upto 16kx16k pixel resolution (defined max)
*/
#define VPU_G1_SWREG54_SW_DEC_WEBP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_WEBP_E_SHIFT)) & VPU_G1_SWREG54_SW_DEC_WEBP_E_MASK)
#define VPU_G1_SWREG54_SW_DEC_MVC_PROF_MASK (0x100000U)
#define VPU_G1_SWREG54_SW_DEC_MVC_PROF_SHIFT (20U)
/*! SW_DEC_MVC_PROF - Decoding format support, MVC
* 0b0..not supported
* 0b1..supported
*/
#define VPU_G1_SWREG54_SW_DEC_MVC_PROF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_MVC_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_MVC_PROF_MASK)
#define VPU_G1_SWREG54_SW_DEC_VP8_PROF_MASK (0x800000U)
#define VPU_G1_SWREG54_SW_DEC_VP8_PROF_SHIFT (23U)
/*! SW_DEC_VP8_PROF - Decoding format support, VP8
* 0b0..not supported
* 0b1..supported
*/
#define VPU_G1_SWREG54_SW_DEC_VP8_PROF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_VP8_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_VP8_PROF_MASK)
#define VPU_G1_SWREG54_SW_DEC_RTL_ROM_MASK (0x2000000U)
#define VPU_G1_SWREG54_SW_DEC_RTL_ROM_SHIFT (25U)
/*! SW_DEC_RTL_ROM - ROM implementation type (If design includes ROMs)
* 0b0..ROMs are implemented from actual ROM units
* 0b1..ROMs are implemented from RTL
*/
#define VPU_G1_SWREG54_SW_DEC_RTL_ROM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_RTL_ROM_SHIFT)) & VPU_G1_SWREG54_SW_DEC_RTL_ROM_MASK)
#define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_MASK (0x10000000U)
#define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_SHIFT (28U)
/*! SW_REF_BUFF2_EXIST - Reference picture buffer 2 usage:
* 0b0..not supported
* 0b1..reference buffer 2 is used
*/
#define VPU_G1_SWREG54_SW_REF_BUFF2_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_SHIFT)) & VPU_G1_SWREG54_SW_REF_BUFF2_EXIST_MASK)
#define VPU_G1_SWREG54_SW_DEC_DIVX_PROF_MASK (0x20000000U)
#define VPU_G1_SWREG54_SW_DEC_DIVX_PROF_SHIFT (29U)
/*! SW_DEC_DIVX_PROF - DIVX Support:
* 0b0..not supported
* 0b1..supported
*/
#define VPU_G1_SWREG54_SW_DEC_DIVX_PROF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_DIVX_PROF_SHIFT)) & VPU_G1_SWREG54_SW_DEC_DIVX_PROF_MASK)
#define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_MASK (0x40000000U)
#define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_SHIFT (30U)
/*! SW_DEC_REFBU_ILACE - Refbufferd support for interlaced content:
* 0b0..not supported
* 0b1..supported
*/
#define VPU_G1_SWREG54_SW_DEC_REFBU_ILACE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_SHIFT)) & VPU_G1_SWREG54_SW_DEC_REFBU_ILACE_MASK)
/*! @} */
/*! @name SWREG55 - Reference picture buffer 2 / Advanced prefetch control register */
/*! @{ */
#define VPU_G1_SWREG55_SW_APF_THRESHOLD_MASK (0x3FFFU)
#define VPU_G1_SWREG55_SW_APF_THRESHOLD_SHIFT (0U)
/*! SW_APF_THRESHOLD - G1 decoder and later :Advanced prefetch threshold value. If current MB
* exceeds the threshold the advanced mode is not used. Value 0 disables threshold usage and advanced
* prefetch usage is restricted by internal memory limitation only
*/
#define VPU_G1_SWREG55_SW_APF_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_APF_THRESHOLD_SHIFT)) & VPU_G1_SWREG55_SW_APF_THRESHOLD_MASK)
#define VPU_G1_SWREG55_SW_REFBU2_PICID_MASK (0x7C000U)
#define VPU_G1_SWREG55_SW_REFBU2_PICID_SHIFT (14U)
/*! SW_REFBU2_PICID - The used reference picture ID for reference buffer usage
*/
#define VPU_G1_SWREG55_SW_REFBU2_PICID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_PICID_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_PICID_MASK)
#define VPU_G1_SWREG55_SW_REFBU2_THR_MASK (0x7FF80000U)
#define VPU_G1_SWREG55_SW_REFBU2_THR_SHIFT (19U)
/*! SW_REFBU2_THR - Reference buffer disable threshold value (buffer miss amount). Used to buffer shut down (if more misses than allowed)
*/
#define VPU_G1_SWREG55_SW_REFBU2_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_THR_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_THR_MASK)
#define VPU_G1_SWREG55_SW_REFBU2_BUF_E_MASK (0x80000000U)
#define VPU_G1_SWREG55_SW_REFBU2_BUF_E_SHIFT (31U)
/*! SW_REFBU2_BUF_E - Refer picture buffer 2 enable:
* 0b0..refer picture buffer disabled
* 0b1..refer picture buffer enabled. Valid if picture size is QVGA or more (can be turned of by HW if threshold value reached).
*/
#define VPU_G1_SWREG55_SW_REFBU2_BUF_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG55_SW_REFBU2_BUF_E_SHIFT)) & VPU_G1_SWREG55_SW_REFBU2_BUF_E_MASK)
/*! @} */
/*! @name SWREG56 - Reference buffer information register 3 */
/*! @{ */
#define VPU_G1_SWREG56_SW_REFBU_BOT_SUM_MASK (0xFFFFU)
#define VPU_G1_SWREG56_SW_REFBU_BOT_SUM_SHIFT (0U)
/*! SW_REFBU_BOT_SUM - The sum of the bottom partitions of the picture
*/
#define VPU_G1_SWREG56_SW_REFBU_BOT_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG56_SW_REFBU_BOT_SUM_SHIFT)) & VPU_G1_SWREG56_SW_REFBU_BOT_SUM_MASK)
#define VPU_G1_SWREG56_SW_REFBU_TOP_SUM_MASK (0xFFFF0000U)
#define VPU_G1_SWREG56_SW_REFBU_TOP_SUM_SHIFT (16U)
/*! SW_REFBU_TOP_SUM - The sum of the top partitions of the picture
*/
#define VPU_G1_SWREG56_SW_REFBU_TOP_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG56_SW_REFBU_TOP_SUM_SHIFT)) & VPU_G1_SWREG56_SW_REFBU_TOP_SUM_MASK)
/*! @} */
/*! @name SWREG57 - Decoder fuse register */
/*! @{ */
#define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_MASK (0x80U)
#define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_SHIFT (7U)
/*! FUSE_DEC_REFBUFFER - 1 = reference buffer used
*/
#define VPU_G1_SWREG57_FUSE_DEC_REFBUFFER(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_REFBUFFER_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_352_MASK (0x1000U)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_352_SHIFT (12U)
/*! FUSE_DEC_MAXW_352 - 1 = Max video width up to 352 pixels enabled. Priority coded with priority 5.
*/
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_352(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_352_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_352_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_720_MASK (0x2000U)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_720_SHIFT (13U)
/*! FUSE_DEC_MAXW_720 - 1 = Max video width up to 720 pixels enabled. Priority coded with priority 4.
*/
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_720(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_720_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_720_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_MASK (0x4000U)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_SHIFT (14U)
/*! FUSE_DEC_MAXW_1280 - 1 = Max video width up to 1280 pixels enabled. Priority coded with priority 3.
*/
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1280(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_1280_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_MASK (0x8000U)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_SHIFT (15U)
/*! FUSE_DEC_MAXW_1920 - 1 = Max video width up to 1920 pixels enabled. Priority coded with priority 2.
*/
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_1920(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_1920_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_MASK (0x10000U)
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_SHIFT (16U)
/*! FUSE_DEC_MAXW_4K - 1 = Max video width up to 4096 pixels enabled. Priority coded with priority 1.
*/
#define VPU_G1_SWREG57_FUSE_DEC_MAXW_4K(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MAXW_4K_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_MVC_MASK (0x40000U)
#define VPU_G1_SWREG57_FUSE_DEC_MVC_SHIFT (18U)
/*! FUSE_DEC_MVC - 1 = MVC enabled (requires also H264 to be enabled)
*/
#define VPU_G1_SWREG57_FUSE_DEC_MVC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_MVC_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_MVC_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_VP8_MASK (0x100000U)
#define VPU_G1_SWREG57_FUSE_DEC_VP8_SHIFT (20U)
/*! FUSE_DEC_VP8 - 1 = VP8 enabled
*/
#define VPU_G1_SWREG57_FUSE_DEC_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_VP8_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_VP8_MASK)
#define VPU_G1_SWREG57_FUSE_DEC_H264_MASK (0x80000000U)
#define VPU_G1_SWREG57_FUSE_DEC_H264_SHIFT (31U)
/*! FUSE_DEC_H264 - 1 = H.264 enabled
*/
#define VPU_G1_SWREG57_FUSE_DEC_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG57_FUSE_DEC_H264_SHIFT)) & VPU_G1_SWREG57_FUSE_DEC_H264_MASK)
/*! @} */
/*! @name SWREG58 - Device configuration register decoder 2 + Multi core control register */
/*! @{ */
#define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_MASK (0x7FE0000U)
#define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_SHIFT (17U)
/*! SW_DEC_MC_POLLTIME - sw_dec_mc_polltime definition depends on sw_dec_mc_mode.
*/
#define VPU_G1_SWREG58_SW_DEC_MC_POLLTIME(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MC_POLLTIME_MASK)
#define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_MASK (0x18000000U)
#define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_SHIFT (27U)
/*! SW_DEC_MC_POLLMODE - Decoder multicore status reading mode:
* 0b00..HW internal status polling mechanism is used. Status of reference picture is read only when required
* coordinate for the reference picture is not big enough. If the status is still not big enough after reading
* it the HW waits N clock cycles per pixel from the coordinate difference. The N is defined by the
* sw_dec_mc_polltime (range 0...4).
* 0b01..Dummy status polling mechanism is used for all reference pictures. HW reads status of all reference
* pictures at frequency defined by sw_dec_mc_polltime.
*/
#define VPU_G1_SWREG58_SW_DEC_MC_POLLMODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MC_POLLMODE_MASK)
#define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_MASK (0x20000000U)
#define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_SHIFT (29U)
/*! SW_DEC_WRITESTAT_E - Decoder write statusword enable. Must be high if multi core decoding
* enabled. HW writes output picture data proceeding to external memory after picture data (and after
* H264 direct mode MVS if they exist)
*/
#define VPU_G1_SWREG58_SW_DEC_WRITESTAT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_SHIFT)) & VPU_G1_SWREG58_SW_DEC_WRITESTAT_E_MASK)
#define VPU_G1_SWREG58_SW_DEC_MULTICORE_E_MASK (0x40000000U)
#define VPU_G1_SWREG58_SW_DEC_MULTICORE_E_SHIFT (30U)
/*! SW_DEC_MULTICORE_E - Decoder multi core enable:
* 0b0..Multi core disabled or only one core exists in design.
* 0b1..Multi core enable. Each reference picture status must be verified from external memory status field
* before usage. 128 bits status word exists after each reference picture and include picture proceeding
* coordinates Y and X.
*/
#define VPU_G1_SWREG58_SW_DEC_MULTICORE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_DEC_MULTICORE_E_SHIFT)) & VPU_G1_SWREG58_SW_DEC_MULTICORE_E_MASK)
#define VPU_G1_SWREG58_SW_SERV_MERGE_DIS_MASK (0x80000000U)
#define VPU_G1_SWREG58_SW_SERV_MERGE_DIS_SHIFT (31U)
/*! SW_SERV_MERGE_DIS - Decoder service merge disable:
* 0b0..HW merges simultaneous sub-block requests internally if they are same type (read or write).
* 0b1..decoder serves one sub-block per service and merging is disabled.
*/
#define VPU_G1_SWREG58_SW_SERV_MERGE_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG58_SW_SERV_MERGE_DIS_SHIFT)) & VPU_G1_SWREG58_SW_SERV_MERGE_DIS_MASK)
/*! @} */
/*! @name SWREG59 - H264 Chrominance 8 pixel interleaved data base */
/*! @{ */
#define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_SHIFT (2U)
/*! SW_DEC_CH8PIX_BASE - Base address for additional chrominance data format where chrominance is
* interleaved in group of 8 pixels. The usage is enabled by sw_ch_8pix_ileav_e
*/
#define VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_SHIFT)) & VPU_G1_SWREG59_SW_DEC_CH8PIX_BASE_MASK)
/*! @} */
/*! @name SWREG60 - Interrupt register post-processor */
/*! @{ */
#define VPU_G1_SWREG60_SW_PP_E_MASK (0x1U)
#define VPU_G1_SWREG60_SW_PP_E_SHIFT (0U)
/*! SW_PP_E - External mode post-processing enable. This bit will start the post-processing
* operation. Not to be used if PP is in pipeline with decoder (sw_pp_pipeline_e = 1). HW will reset this
* when picture is post-processed.
*/
#define VPU_G1_SWREG60_SW_PP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_E_SHIFT)) & VPU_G1_SWREG60_SW_PP_E_MASK)
#define VPU_G1_SWREG60_SW_PP_PIPELINE_E_MASK (0x2U)
#define VPU_G1_SWREG60_SW_PP_PIPELINE_E_SHIFT (1U)
/*! SW_PP_PIPELINE_E - Decoder - post-processing pipeline enable:
* 0b0..Post-processing is processing different picture than decoder or is disabled
* 0b1..Post-processing is performed in pipeline with decoder
*/
#define VPU_G1_SWREG60_SW_PP_PIPELINE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_PIPELINE_E_SHIFT)) & VPU_G1_SWREG60_SW_PP_PIPELINE_E_MASK)
#define VPU_G1_SWREG60_SW_PP_IRQ_DIS_MASK (0x10U)
#define VPU_G1_SWREG60_SW_PP_IRQ_DIS_SHIFT (4U)
/*! SW_PP_IRQ_DIS - Post-processor IRQ disable. When high, there are no interrupts from HW
* concerning post processing. Polling must be used to see the interrupt
*/
#define VPU_G1_SWREG60_SW_PP_IRQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_IRQ_DIS_SHIFT)) & VPU_G1_SWREG60_SW_PP_IRQ_DIS_MASK)
#define VPU_G1_SWREG60_SW_PP_IRQ_MASK (0x100U)
#define VPU_G1_SWREG60_SW_PP_IRQ_SHIFT (8U)
/*! SW_PP_IRQ - Post-processor IRQ. SW will reset this after interrupt is handled. HINTpp is not
* used for pp if IRQ disable pp is high (sw_pp_irq_n_e = 1). In pipeline mode this bit is not used
*/
#define VPU_G1_SWREG60_SW_PP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_IRQ_SHIFT)) & VPU_G1_SWREG60_SW_PP_IRQ_MASK)
#define VPU_G1_SWREG60_SW_PP_RDY_INT_MASK (0x1000U)
#define VPU_G1_SWREG60_SW_PP_RDY_INT_SHIFT (12U)
/*! SW_PP_RDY_INT - Interrupt status bit pp. When this bit is high post processor has processed a
* picture in external mode. In pipeline mode this bit is not used.
*/
#define VPU_G1_SWREG60_SW_PP_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_RDY_INT_SHIFT)) & VPU_G1_SWREG60_SW_PP_RDY_INT_MASK)
#define VPU_G1_SWREG60_SW_PP_BUS_INT_MASK (0x2000U)
#define VPU_G1_SWREG60_SW_PP_BUS_INT_SHIFT (13U)
/*! SW_PP_BUS_INT - Interrupt status bit bus. Error response from bus. In pipeline mode this bit is not used
*/
#define VPU_G1_SWREG60_SW_PP_BUS_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG60_SW_PP_BUS_INT_SHIFT)) & VPU_G1_SWREG60_SW_PP_BUS_INT_MASK)
/*! @} */
/*! @name SWREG61 - Device configuration register post-processor */
/*! @{ */
#define VPU_G1_SWREG61_SW_PP_MAX_BURST_MASK (0x1FU)
#define VPU_G1_SWREG61_SW_PP_MAX_BURST_SHIFT (0U)
/*! SW_PP_MAX_BURST - Maximum burst length for PP bus transactions.
*/
#define VPU_G1_SWREG61_SW_PP_MAX_BURST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_MAX_BURST_SHIFT)) & VPU_G1_SWREG61_SW_PP_MAX_BURST_MASK)
#define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_MASK (0x20U)
#define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_SHIFT (5U)
/*! SW_PP_OUT_SWAP32_E - PP output data word swap (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order (also little endian should be enabled))
*/
#define VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_OUT_SWAP32_E_MASK)
#define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_MASK (0x40U)
#define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_SHIFT (6U)
/*! SW_PP_OUT_ENDIAN - PP output picture endian mode for YCbCr data or for any data if config value SW_PP_OEN_VERSION = 1.
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG61_SW_PP_OUT_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_OUT_ENDIAN_MASK)
#define VPU_G1_SWREG61_SW_PP_IN_ENDIAN_MASK (0x80U)
#define VPU_G1_SWREG61_SW_PP_IN_ENDIAN_SHIFT (7U)
/*! SW_PP_IN_ENDIAN - PP input picture byte endian mode. Used only if PP is in standalone mode. If
* PP is running pipelined with the decoder, this bit has no effect.
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG61_SW_PP_IN_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_ENDIAN_MASK)
#define VPU_G1_SWREG61_SW_PP_CLK_GATE_E_MASK (0x100U)
#define VPU_G1_SWREG61_SW_PP_CLK_GATE_E_SHIFT (8U)
/*! SW_PP_CLK_GATE_E - PP dynamic clock gating enable.
* 0b1..Clock is gated from PP structures that are not used
* 0b0..Clock is running for all PP structures
*/
#define VPU_G1_SWREG61_SW_PP_CLK_GATE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_CLK_GATE_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_CLK_GATE_E_MASK)
#define VPU_G1_SWREG61_SW_PP_DATA_DISC_E_MASK (0x200U)
#define VPU_G1_SWREG61_SW_PP_DATA_DISC_E_SHIFT (9U)
/*! SW_PP_DATA_DISC_E - PP data discard enable. Precise burst lengths are used with reading
* services. Extra data is discarded internally. Note. If AHB maxburst 17 is used data discard cannot be
* enabled (causes conflict)
*/
#define VPU_G1_SWREG61_SW_PP_DATA_DISC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_DATA_DISC_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_DATA_DISC_E_MASK)
#define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_MASK (0x400U)
#define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_SHIFT (10U)
/*! SW_PP_IN_SWAP32_E - PP input 32bit data swap (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
*/
#define VPU_G1_SWREG61_SW_PP_IN_SWAP32_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_SWAP32_E_MASK)
#define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_MASK (0x800U)
#define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_SHIFT (11U)
/*! SW_PP_IN_A1_ENDIAN - Alpha blend source 1 input data byte endian mode.
* 0b0..Big endian (0-1-2-3 order)
* 0b1..Little endian (3-2-1-0 order)
*/
#define VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A1_ENDIAN_MASK)
#define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_MASK (0x1000U)
#define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_SHIFT (12U)
/*! SW_PP_IN_A1_SWAP32 - Alpha blend source 1 input 32bit data swap (may be used for 64 bit environment):
* 0b0..no swapping of 32 bit words
* 0b1..32 bit data words are swapped (needed in 64 bit environment to achieve 7-6-5-4-3-2-1-0 byte order(also little endian should be enabled))
*/
#define VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A1_SWAP32_MASK)
#define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_MASK (0x2000U)
#define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_SHIFT (13U)
/*! SW_PP_IN_A2_ENDSEL - Endian/swap select for Alpha blend input source 2:
* 0b0..Use PP in endian/swap definitions (sw_pp_in_endian, sw_pp_in_swap)
* 0b1..Use Ablend source 1 endian/swap definitions (sw_pp_in_a1_endian, sw_pp_in_a1_swap)
*/
#define VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_SHIFT)) & VPU_G1_SWREG61_SW_PP_IN_A2_ENDSEL_MASK)
#define VPU_G1_SWREG61_SW_PP_SCMD_DIS_MASK (0x4000U)
#define VPU_G1_SWREG61_SW_PP_SCMD_DIS_SHIFT (14U)
/*! SW_PP_SCMD_DIS - 9170 decoder: AXI Single Command Multiple Data disable. 9170 axi wrapper
* supports this mode by default (where only the first addresses of the burst are given from address
* generator). This bit is used to disable the feature (possible SW workaround if something is not
* working correctly)
*/
#define VPU_G1_SWREG61_SW_PP_SCMD_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_SCMD_DIS_SHIFT)) & VPU_G1_SWREG61_SW_PP_SCMD_DIS_MASK)
#define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_MASK (0x8000U)
#define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_SHIFT (15U)
/*! SW_PP_AHB_HLOCK_E - AHB master HLOCK enable. When high the service is locked to pp as long as it
* needs the bus (whenever pp requests the bus it will be granted)
*/
#define VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_SHIFT)) & VPU_G1_SWREG61_SW_PP_AHB_HLOCK_E_MASK)
#define VPU_G1_SWREG61_SW_PP_AXI_WR_ID_MASK (0xFF0000U)
#define VPU_G1_SWREG61_SW_PP_AXI_WR_ID_SHIFT (16U)
/*! SW_PP_AXI_WR_ID - Write ID used for AXI PP write services (if connected to AXI)
*/
#define VPU_G1_SWREG61_SW_PP_AXI_WR_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AXI_WR_ID_SHIFT)) & VPU_G1_SWREG61_SW_PP_AXI_WR_ID_MASK)
#define VPU_G1_SWREG61_SW_PP_AXI_RD_ID_MASK (0xFF000000U)
#define VPU_G1_SWREG61_SW_PP_AXI_RD_ID_SHIFT (24U)
/*! SW_PP_AXI_RD_ID - Read ID used for AXI PP read services (if connected to AXI)
*/
#define VPU_G1_SWREG61_SW_PP_AXI_RD_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG61_SW_PP_AXI_RD_ID_SHIFT)) & VPU_G1_SWREG61_SW_PP_AXI_RD_ID_MASK)
/*! @} */
/*! @name SWREG62 - Deinterlace control register */
/*! @{ */
#define VPU_G1_SWREG62_SW_DEINT_EDGE_DET_MASK (0x7FFFU)
#define VPU_G1_SWREG62_SW_DEINT_EDGE_DET_SHIFT (0U)
/*! SW_DEINT_EDGE_DET - Edge detect value used for deinterlacing
*/
#define VPU_G1_SWREG62_SW_DEINT_EDGE_DET(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_EDGE_DET_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_EDGE_DET_MASK)
#define VPU_G1_SWREG62_SW_DEINT_BLEND_E_MASK (0x8000U)
#define VPU_G1_SWREG62_SW_DEINT_BLEND_E_SHIFT (15U)
/*! SW_DEINT_BLEND_E - Blend enable for de-interlacing
*/
#define VPU_G1_SWREG62_SW_DEINT_BLEND_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_BLEND_E_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_BLEND_E_MASK)
#define VPU_G1_SWREG62_SW_DEINT_THRESHOLD_MASK (0x3FFF0000U)
#define VPU_G1_SWREG62_SW_DEINT_THRESHOLD_SHIFT (16U)
/*! SW_DEINT_THRESHOLD - Threshold value used in deinterlacing
*/
#define VPU_G1_SWREG62_SW_DEINT_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_THRESHOLD_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_THRESHOLD_MASK)
#define VPU_G1_SWREG62_SW_DEINT_E_MASK (0x80000000U)
#define VPU_G1_SWREG62_SW_DEINT_E_SHIFT (31U)
/*! SW_DEINT_E - De-interlace enable. Input data is in interlaced format and deinterlacing needs to be performed
*/
#define VPU_G1_SWREG62_SW_DEINT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG62_SW_DEINT_E_SHIFT)) & VPU_G1_SWREG62_SW_DEINT_E_MASK)
/*! @} */
/*! @name SWREG63 - Base address for reading post-processing input picture luminance (top field/frame) */
/*! @{ */
#define VPU_G1_SWREG63_SW_PP_IN_LU_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG63_SW_PP_IN_LU_BASE_SHIFT (2U)
/*! SW_PP_IN_LU_BASE - Base address for post-processing input luminance picture. If PP input picture
* is fetched from fields this base address is used to point to top field of the picture. Used
* in external mode only.
*/
#define VPU_G1_SWREG63_SW_PP_IN_LU_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG63_SW_PP_IN_LU_BASE_SHIFT)) & VPU_G1_SWREG63_SW_PP_IN_LU_BASE_MASK)
/*! @} */
/*! @name SWREG64 - Base address for reading post-processing input picture Cb/Ch (top field/frame) */
/*! @{ */
#define VPU_G1_SWREG64_SW_PP_IN_CB_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG64_SW_PP_IN_CB_BASE_SHIFT (2U)
/*! SW_PP_IN_CB_BASE - Base address for post-processing input Cb picture or for both chrominance
* pictures (if chrominances interleaved). If PP input picture is fetched from fields this base
* address is used to point to top field of the picture. Used in external mode only
*/
#define VPU_G1_SWREG64_SW_PP_IN_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG64_SW_PP_IN_CB_BASE_SHIFT)) & VPU_G1_SWREG64_SW_PP_IN_CB_BASE_MASK)
/*! @} */
/*! @name SWREG65 - Base address for reading post-processing input picture Cr */
/*! @{ */
#define VPU_G1_SWREG65_SW_PP_IN_CR_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG65_SW_PP_IN_CR_BASE_SHIFT (2U)
/*! SW_PP_IN_CR_BASE - Base address for post-processing input cr picture. Used in external mode only
*/
#define VPU_G1_SWREG65_SW_PP_IN_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG65_SW_PP_IN_CR_BASE_SHIFT)) & VPU_G1_SWREG65_SW_PP_IN_CR_BASE_MASK)
/*! @} */
/*! @name SWREG66 - Base address for writing post-processed picture luminance/RGB */
/*! @{ */
#define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_SHIFT (0U)
/*! SW_PP_OUT_LU_BASE - Base address for post-processing output picture (luminance/YUYV/RGB). NOTE:
* Bits 2:0 are used to adjust the post-processor output to start from zertain byte (1:0 for 32
* bit bus). These bits can be other than zero only if Pixel Accurate PP output configuration is
* enabled
*/
#define VPU_G1_SWREG66_SW_PP_OUT_LU_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_SHIFT)) & VPU_G1_SWREG66_SW_PP_OUT_LU_BASE_MASK)
/*! @} */
/*! @name SWREG67 - Base address for writing post-processed picture Ch */
/*! @{ */
#define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_SHIFT (0U)
/*! SW_PP_OUT_CH_BASE - Base address for post-processing output chrominance picture (interleaved
* chrominance). NOTE: Bits 2:0 are used to adjust the post-processor output to start from zertain
* byte (1:0 for 32 bit bus). These bits can be other than zero only if Pixel Accurate PP output
* configuration is enabled
*/
#define VPU_G1_SWREG67_SW_PP_OUT_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_SHIFT)) & VPU_G1_SWREG67_SW_PP_OUT_CH_BASE_MASK)
/*! @} */
/*! @name SWREG68 - Register for contrast adjusting */
/*! @{ */
#define VPU_G1_SWREG68_SW_CONTRAST_OFF1_MASK (0x3FFU)
#define VPU_G1_SWREG68_SW_CONTRAST_OFF1_SHIFT (0U)
/*! SW_CONTRAST_OFF1 - Offset value 1, used with contrast adjusting
*/
#define VPU_G1_SWREG68_SW_CONTRAST_OFF1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_OFF1_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_OFF1_MASK)
#define VPU_G1_SWREG68_SW_CONTRAST_OFF2_MASK (0xFFC00U)
#define VPU_G1_SWREG68_SW_CONTRAST_OFF2_SHIFT (10U)
/*! SW_CONTRAST_OFF2 - Offset value 2, used with contrast adjusting
*/
#define VPU_G1_SWREG68_SW_CONTRAST_OFF2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_OFF2_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_OFF2_MASK)
#define VPU_G1_SWREG68_SW_CONTRAST_THR1_MASK (0xFF000000U)
#define VPU_G1_SWREG68_SW_CONTRAST_THR1_SHIFT (24U)
/*! SW_CONTRAST_THR1 - Threshold value 1, used with contrast adjusting
*/
#define VPU_G1_SWREG68_SW_CONTRAST_THR1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG68_SW_CONTRAST_THR1_SHIFT)) & VPU_G1_SWREG68_SW_CONTRAST_THR1_MASK)
/*! @} */
/*! @name SWREG69 - Register for colour conversion and contrast adjusting/YUYV 422 channel orders */
/*! @{ */
#define VPU_G1_SWREG69_SW_CONTRAST_THR2_MASK (0xFFU)
#define VPU_G1_SWREG69_SW_CONTRAST_THR2_SHIFT (0U)
/*! SW_CONTRAST_THR2 - Threshold value 2, used with contrast adjusting
*/
#define VPU_G1_SWREG69_SW_CONTRAST_THR2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_CONTRAST_THR2_SHIFT)) & VPU_G1_SWREG69_SW_CONTRAST_THR2_MASK)
#define VPU_G1_SWREG69_SW_COLOR_COEFFA1_MASK (0x3FF00U)
#define VPU_G1_SWREG69_SW_COLOR_COEFFA1_SHIFT (8U)
/*! SW_COLOR_COEFFA1 - Coefficient a1, used with Y pixel to calculate all color components
*/
#define VPU_G1_SWREG69_SW_COLOR_COEFFA1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_COLOR_COEFFA1_SHIFT)) & VPU_G1_SWREG69_SW_COLOR_COEFFA1_MASK)
#define VPU_G1_SWREG69_SW_COLOR_COEFFA2_MASK (0xFFC0000U)
#define VPU_G1_SWREG69_SW_COLOR_COEFFA2_SHIFT (18U)
/*! SW_COLOR_COEFFA2 - Coefficient a2, used with Y pixel to calculate all color components
*/
#define VPU_G1_SWREG69_SW_COLOR_COEFFA2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_COLOR_COEFFA2_SHIFT)) & VPU_G1_SWREG69_SW_COLOR_COEFFA2_MASK)
#define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_MASK (0x10000000U)
#define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_SHIFT (28U)
/*! SW_PP_OUT_CR_FIRST - For YUYV 422 output format. Enable for Cr first (before Cb).
* 0b0..the order is Y0CbY0Cr or CbY0CrY0
* 0b1..the order is Y0CrY0Cb or CrY0CbY0
*/
#define VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_SHIFT)) & VPU_G1_SWREG69_SW_PP_OUT_CR_FIRST_MASK)
#define VPU_G1_SWREG69_SW_PP_OUT_START_CH_MASK (0x20000000U)
#define VPU_G1_SWREG69_SW_PP_OUT_START_CH_SHIFT (29U)
/*! SW_PP_OUT_START_CH - For YUYV 422 output format. Enable for start_with_chrominance.
* 0b0..the order is Y0CbY0Cr or Y0CrY0Cb
* 0b1..the order is CbY0CrY0 or CrY0CbY0
*/
#define VPU_G1_SWREG69_SW_PP_OUT_START_CH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_OUT_START_CH_SHIFT)) & VPU_G1_SWREG69_SW_PP_OUT_START_CH_MASK)
#define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_MASK (0x40000000U)
#define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_SHIFT (30U)
/*! SW_PP_IN_CR_FIRST - For YUYV 422 input format. Enable for Cr first (before Cb).
* 0b0..the order is Y0CbY0Cr or CbY0CrY0 (if 420 semiplanar chrominance: CbCrCbCr)
* 0b1..the order is Y0CrY0Cb or CrY0CbY0 (if 420 semiplanar chrominance: CrCbCrCb)
*/
#define VPU_G1_SWREG69_SW_PP_IN_CR_FIRST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_SHIFT)) & VPU_G1_SWREG69_SW_PP_IN_CR_FIRST_MASK)
#define VPU_G1_SWREG69_SW_PP_IN_START_CH_MASK (0x80000000U)
#define VPU_G1_SWREG69_SW_PP_IN_START_CH_SHIFT (31U)
/*! SW_PP_IN_START_CH - For YUYV 422 input format. Enable for start_with_chrominance.
* 0b0..the order is Y0CbY0Cr or Y0CrY0Cb
* 0b1..the order is CbY0CrY0 or CrY0CbY0
*/
#define VPU_G1_SWREG69_SW_PP_IN_START_CH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG69_SW_PP_IN_START_CH_SHIFT)) & VPU_G1_SWREG69_SW_PP_IN_START_CH_MASK)
/*! @} */
/*! @name SWREG70 - Register for colour conversion 0 */
/*! @{ */
#define VPU_G1_SWREG70_SW_COLOR_COEFFB_MASK (0x3FFU)
#define VPU_G1_SWREG70_SW_COLOR_COEFFB_SHIFT (0U)
/*! SW_COLOR_COEFFB - Coefficient b, used with Cr to calculate red component value
*/
#define VPU_G1_SWREG70_SW_COLOR_COEFFB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFB_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFB_MASK)
#define VPU_G1_SWREG70_SW_COLOR_COEFFC_MASK (0xFFC00U)
#define VPU_G1_SWREG70_SW_COLOR_COEFFC_SHIFT (10U)
/*! SW_COLOR_COEFFC - Coefficient c, used with Cr to calculate green component value
*/
#define VPU_G1_SWREG70_SW_COLOR_COEFFC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFC_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFC_MASK)
#define VPU_G1_SWREG70_SW_COLOR_COEFFD_MASK (0x3FF00000U)
#define VPU_G1_SWREG70_SW_COLOR_COEFFD_SHIFT (20U)
/*! SW_COLOR_COEFFD - Coefficient d, used with Cb to calculate green component value
*/
#define VPU_G1_SWREG70_SW_COLOR_COEFFD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_COLOR_COEFFD_SHIFT)) & VPU_G1_SWREG70_SW_COLOR_COEFFD_MASK)
#define VPU_G1_SWREG70_SW_PP_OUT_H_EXT_MASK (0xC0000000U)
#define VPU_G1_SWREG70_SW_PP_OUT_H_EXT_SHIFT (30U)
/*! SW_PP_OUT_H_EXT - Extended output height for 4k resolution
*/
#define VPU_G1_SWREG70_SW_PP_OUT_H_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG70_SW_PP_OUT_H_EXT_SHIFT)) & VPU_G1_SWREG70_SW_PP_OUT_H_EXT_MASK)
/*! @} */
/*! @name SWREG71 - Register for colour conversion 1 + rotation mode */
/*! @{ */
#define VPU_G1_SWREG71_SW_COLOR_COEFFE_MASK (0x3FFU)
#define VPU_G1_SWREG71_SW_COLOR_COEFFE_SHIFT (0U)
/*! SW_COLOR_COEFFE - Coefficient e, used with Cb to calculate blue component value
*/
#define VPU_G1_SWREG71_SW_COLOR_COEFFE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_COLOR_COEFFE_SHIFT)) & VPU_G1_SWREG71_SW_COLOR_COEFFE_MASK)
#define VPU_G1_SWREG71_SW_COLOR_COEFFF_MASK (0x3FC00U)
#define VPU_G1_SWREG71_SW_COLOR_COEFFF_SHIFT (10U)
/*! SW_COLOR_COEFFF - Coefficient f, used with Y to adjust brightness
*/
#define VPU_G1_SWREG71_SW_COLOR_COEFFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_COLOR_COEFFF_SHIFT)) & VPU_G1_SWREG71_SW_COLOR_COEFFF_MASK)
#define VPU_G1_SWREG71_SW_ROTATION_MODE_MASK (0x1C0000U)
#define VPU_G1_SWREG71_SW_ROTATION_MODE_SHIFT (18U)
/*! SW_ROTATION_MODE - Rotation mode:
* 0b000..rotation disabled
* 0b001..rotate + 90
* 0b010..rotate - 90
* 0b011..horizontal flip (mirror)
* 0b100..vertical flip
* 0b101..rotate 180
*/
#define VPU_G1_SWREG71_SW_ROTATION_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_ROTATION_MODE_SHIFT)) & VPU_G1_SWREG71_SW_ROTATION_MODE_MASK)
#define VPU_G1_SWREG71_SW_CROP_STARTX_MASK (0x3FE00000U)
#define VPU_G1_SWREG71_SW_CROP_STARTX_SHIFT (21U)
/*! SW_CROP_STARTX - Start coordinate x for the cropped area in macroblocks.
*/
#define VPU_G1_SWREG71_SW_CROP_STARTX(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_CROP_STARTX_SHIFT)) & VPU_G1_SWREG71_SW_CROP_STARTX_MASK)
#define VPU_G1_SWREG71_SW_PP_OUT_W_EXT_MASK (0xC0000000U)
#define VPU_G1_SWREG71_SW_PP_OUT_W_EXT_SHIFT (30U)
/*! SW_PP_OUT_W_EXT - Extended output width for 4k resolution
*/
#define VPU_G1_SWREG71_SW_PP_OUT_W_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG71_SW_PP_OUT_W_EXT_SHIFT)) & VPU_G1_SWREG71_SW_PP_OUT_W_EXT_MASK)
/*! @} */
/*! @name SWREG72 - PP input size and -cropping register */
/*! @{ */
#define VPU_G1_SWREG72_SW_PP_IN_WIDTH_MASK (0x1FFU)
#define VPU_G1_SWREG72_SW_PP_IN_WIDTH_SHIFT (0U)
/*! SW_PP_IN_WIDTH - PP input picture width in MBs. Can be cropped from a bigger input picture in external mode
*/
#define VPU_G1_SWREG72_SW_PP_IN_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_PP_IN_WIDTH_SHIFT)) & VPU_G1_SWREG72_SW_PP_IN_WIDTH_MASK)
#define VPU_G1_SWREG72_SW_PP_IN_HEIGHT_MASK (0x1FE00U)
#define VPU_G1_SWREG72_SW_PP_IN_HEIGHT_SHIFT (9U)
/*! SW_PP_IN_HEIGHT - PP input picture height in MBs. Can be cropped from a bigger input picture in external mode
*/
#define VPU_G1_SWREG72_SW_PP_IN_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_PP_IN_HEIGHT_SHIFT)) & VPU_G1_SWREG72_SW_PP_IN_HEIGHT_MASK)
#define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_MASK (0x7C0000U)
#define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_SHIFT (18U)
/*! SW_RANGEMAP_COEF_Y - Range map value for Y component
*/
#define VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_SHIFT)) & VPU_G1_SWREG72_SW_RANGEMAP_COEF_Y_MASK)
#define VPU_G1_SWREG72_SW_CROP_STARTY_MASK (0xFF000000U)
#define VPU_G1_SWREG72_SW_CROP_STARTY_SHIFT (24U)
/*! SW_CROP_STARTY - Start coordinate y for the cropped area in macroblocks.
*/
#define VPU_G1_SWREG72_SW_CROP_STARTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG72_SW_CROP_STARTY_SHIFT)) & VPU_G1_SWREG72_SW_CROP_STARTY_MASK)
/*! @} */
/*! @name SWREG73 - PP input picture base address for Y bottom field */
/*! @{ */
#define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_SHIFT (2U)
/*! SW_PP_BOT_YIN_BASE - PP input Y base for bottom field
*/
#define VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_SHIFT)) & VPU_G1_SWREG73_SW_PP_BOT_YIN_BASE_MASK)
/*! @} */
/*! @name SWREG74 - PP input picture base for Ch bottom field */
/*! @{ */
#define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_SHIFT (2U)
/*! SW_PP_BOT_CIN_BASE - PP input C base for bottom field (mixed chrominance)
*/
#define VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_SHIFT)) & VPU_G1_SWREG74_SW_PP_BOT_CIN_BASE_MASK)
/*! @} */
/*! @name SWREG79 - Scaling register 0 ratio and padding for R and G */
/*! @{ */
#define VPU_G1_SWREG79_SW_SCALE_WRATIO_MASK (0x3FFFFU)
#define VPU_G1_SWREG79_SW_SCALE_WRATIO_SHIFT (0U)
/*! SW_SCALE_WRATIO - Scaling ratio for width (outputw-1/inputw-1)
*/
#define VPU_G1_SWREG79_SW_SCALE_WRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_SCALE_WRATIO_SHIFT)) & VPU_G1_SWREG79_SW_SCALE_WRATIO_MASK)
#define VPU_G1_SWREG79_SW_RGB_G_PADD_MASK (0x7C0000U)
#define VPU_G1_SWREG79_SW_RGB_G_PADD_SHIFT (18U)
/*! SW_RGB_G_PADD - Amount of ones that will be padded in front of the G-component
*/
#define VPU_G1_SWREG79_SW_RGB_G_PADD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_G_PADD_SHIFT)) & VPU_G1_SWREG79_SW_RGB_G_PADD_MASK)
#define VPU_G1_SWREG79_SW_RGB_R_PADD_MASK (0xF800000U)
#define VPU_G1_SWREG79_SW_RGB_R_PADD_SHIFT (23U)
/*! SW_RGB_R_PADD - Amount of ones that will be padded in front of the R-component
*/
#define VPU_G1_SWREG79_SW_RGB_R_PADD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_R_PADD_SHIFT)) & VPU_G1_SWREG79_SW_RGB_R_PADD_MASK)
#define VPU_G1_SWREG79_SW_RGB_PIX_IN32_MASK (0x10000000U)
#define VPU_G1_SWREG79_SW_RGB_PIX_IN32_SHIFT (28U)
/*! SW_RGB_PIX_IN32 - RGB pixel amount/ 32 bit word
* 0b0..1 RGB pixel/32 bit
* 0b1..2 RGB pixels/32 bit
*/
#define VPU_G1_SWREG79_SW_RGB_PIX_IN32(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RGB_PIX_IN32_SHIFT)) & VPU_G1_SWREG79_SW_RGB_PIX_IN32_MASK)
#define VPU_G1_SWREG79_SW_YCBCR_RANGE_MASK (0x20000000U)
#define VPU_G1_SWREG79_SW_YCBCR_RANGE_SHIFT (29U)
/*! SW_YCBCR_RANGE - Defines the YCbCr range in RGB conversion:
* 0b0..16...235 for Y, 16...240 for Chrominance.
* 0b1..0...255 for all components
*/
#define VPU_G1_SWREG79_SW_YCBCR_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_YCBCR_RANGE_SHIFT)) & VPU_G1_SWREG79_SW_YCBCR_RANGE_MASK)
#define VPU_G1_SWREG79_SW_RANGEMAP_C_E_MASK (0x40000000U)
#define VPU_G1_SWREG79_SW_RANGEMAP_C_E_SHIFT (30U)
/*! SW_RANGEMAP_C_E - Range map enable for chrominance component
*/
#define VPU_G1_SWREG79_SW_RANGEMAP_C_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RANGEMAP_C_E_SHIFT)) & VPU_G1_SWREG79_SW_RANGEMAP_C_E_MASK)
#define VPU_G1_SWREG79_SW_RANGEMAP_Y_E_MASK (0x80000000U)
#define VPU_G1_SWREG79_SW_RANGEMAP_Y_E_SHIFT (31U)
/*! SW_RANGEMAP_Y_E - Range map enable for Y component
*/
#define VPU_G1_SWREG79_SW_RANGEMAP_Y_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG79_SW_RANGEMAP_Y_E_SHIFT)) & VPU_G1_SWREG79_SW_RANGEMAP_Y_E_MASK)
/*! @} */
/*! @name SWREG80 - Scaling ratio register 1 and padding for B */
/*! @{ */
#define VPU_G1_SWREG80_SW_SCALE_HRATIO_MASK (0x3FFFFU)
#define VPU_G1_SWREG80_SW_SCALE_HRATIO_SHIFT (0U)
/*! SW_SCALE_HRATIO - Scaling ratio for height (outputh-1/inputh-1)
*/
#define VPU_G1_SWREG80_SW_SCALE_HRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_SCALE_HRATIO_SHIFT)) & VPU_G1_SWREG80_SW_SCALE_HRATIO_MASK)
#define VPU_G1_SWREG80_SW_RGB_B_PADD_MASK (0x7C0000U)
#define VPU_G1_SWREG80_SW_RGB_B_PADD_SHIFT (18U)
/*! SW_RGB_B_PADD - Amount of ones that will be padded in front of the B-component
*/
#define VPU_G1_SWREG80_SW_RGB_B_PADD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_RGB_B_PADD_SHIFT)) & VPU_G1_SWREG80_SW_RGB_B_PADD_MASK)
#define VPU_G1_SWREG80_SW_VER_SCALE_MODE_MASK (0x1800000U)
#define VPU_G1_SWREG80_SW_VER_SCALE_MODE_SHIFT (23U)
/*! SW_VER_SCALE_MODE - Vertical scaling mode:
* 0b00..Off
* 0b01..Upscale
* 0b10..Downscale
*/
#define VPU_G1_SWREG80_SW_VER_SCALE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_VER_SCALE_MODE_SHIFT)) & VPU_G1_SWREG80_SW_VER_SCALE_MODE_MASK)
#define VPU_G1_SWREG80_SW_HOR_SCALE_MODE_MASK (0x6000000U)
#define VPU_G1_SWREG80_SW_HOR_SCALE_MODE_SHIFT (25U)
/*! SW_HOR_SCALE_MODE - Horizontal scaling mode:
* 0b00..Off
* 0b01..Upscale
* 0b10..Downscale
*/
#define VPU_G1_SWREG80_SW_HOR_SCALE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_HOR_SCALE_MODE_SHIFT)) & VPU_G1_SWREG80_SW_HOR_SCALE_MODE_MASK)
#define VPU_G1_SWREG80_SW_PP_IN_STRUCT_MASK (0x38000000U)
#define VPU_G1_SWREG80_SW_PP_IN_STRUCT_SHIFT (27U)
/*! SW_PP_IN_STRUCT - PP input data picture structure:
* 0b000..Top field / progressive frame structure: Read input data from top field base address /frame base address and read every line.
* 0b001..Bottom field structure: Read input data from bottom field base address and read every line.
* 0b010..Interlaced field structure: Read input data from both top and bottom field base address and take every line from each field.
* 0b011..Interlaced frame structure: Read input data from both top and bottom field base address and take every second line from each field.
* 0b100..Ripped top field structure: Read input data from top field base address and read every second line.
* 0b101..Ripped bottom field structure: Read input data from bottom field base address and read every second line.
*/
#define VPU_G1_SWREG80_SW_PP_IN_STRUCT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_PP_IN_STRUCT_SHIFT)) & VPU_G1_SWREG80_SW_PP_IN_STRUCT_MASK)
#define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_MASK (0x40000000U)
#define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_SHIFT (30U)
/*! SW_PP_FAST_SCALE_E
* 0b0..fast downscaling is not enabled
* 0b1..fast downscaling is enabled. The quality of the picture is decreased but performance is improved.
*/
#define VPU_G1_SWREG80_SW_PP_FAST_SCALE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_SHIFT)) & VPU_G1_SWREG80_SW_PP_FAST_SCALE_E_MASK)
/*! @} */
/*! @name SWREG81 - Scaling ratio register 2 */
/*! @{ */
#define VPU_G1_SWREG81_SW_HSCALE_INVRA_MASK (0xFFFFU)
#define VPU_G1_SWREG81_SW_HSCALE_INVRA_SHIFT (0U)
/*! SW_HSCALE_INVRA - Inverse scaling ratio for height or cv (inputh-1 / outputh-1)
*/
#define VPU_G1_SWREG81_SW_HSCALE_INVRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG81_SW_HSCALE_INVRA_SHIFT)) & VPU_G1_SWREG81_SW_HSCALE_INVRA_MASK)
#define VPU_G1_SWREG81_SW_WSCALE_INVRA_MASK (0xFFFF0000U)
#define VPU_G1_SWREG81_SW_WSCALE_INVRA_SHIFT (16U)
/*! SW_WSCALE_INVRA - Inverse scaling ratio for width, or ch (inputw-1 / outputw-1)
*/
#define VPU_G1_SWREG81_SW_WSCALE_INVRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG81_SW_WSCALE_INVRA_SHIFT)) & VPU_G1_SWREG81_SW_WSCALE_INVRA_MASK)
/*! @} */
/*! @name SWREG82 - Rmask register */
/*! @{ */
#define VPU_G1_SWREG82_SW_R_MASK_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG82_SW_R_MASK_SHIFT (0U)
/*! SW_R_MASK - Bit mask for R component (and alpha channel)
*/
#define VPU_G1_SWREG82_SW_R_MASK(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG82_SW_R_MASK_SHIFT)) & VPU_G1_SWREG82_SW_R_MASK_MASK)
/*! @} */
/*! @name SWREG83 - Gmask register */
/*! @{ */
#define VPU_G1_SWREG83_SW_G_MASK_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG83_SW_G_MASK_SHIFT (0U)
/*! SW_G_MASK - Bit mask for G component (and alpha channel)
*/
#define VPU_G1_SWREG83_SW_G_MASK(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG83_SW_G_MASK_SHIFT)) & VPU_G1_SWREG83_SW_G_MASK_MASK)
/*! @} */
/*! @name SWREG84 - Bmask register */
/*! @{ */
#define VPU_G1_SWREG84_SW_B_MASK_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG84_SW_B_MASK_SHIFT (0U)
/*! SW_B_MASK - Bit mask for B component (and alpha channel)
*/
#define VPU_G1_SWREG84_SW_B_MASK(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG84_SW_B_MASK_SHIFT)) & VPU_G1_SWREG84_SW_B_MASK_MASK)
/*! @} */
/*! @name SWREG85 - Post-processor control register */
/*! @{ */
#define VPU_G1_SWREG85_SW_PP_CROP8_D_E_MASK (0x1U)
#define VPU_G1_SWREG85_SW_PP_CROP8_D_E_SHIFT (0U)
/*! SW_PP_CROP8_D_E - PP input picture height is not 16 pixels multiple. Only 8 pixel rows of the
* most down MB of the unrotated input picture is used for PP input.
*/
#define VPU_G1_SWREG85_SW_PP_CROP8_D_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_CROP8_D_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_CROP8_D_E_MASK)
#define VPU_G1_SWREG85_SW_PP_CROP8_R_E_MASK (0x2U)
#define VPU_G1_SWREG85_SW_PP_CROP8_R_E_SHIFT (1U)
/*! SW_PP_CROP8_R_E - PP input picture width is not 16 pixels multiple. Only 8 pixels of the most
* right MB of the unrotated input picture is used for PP input.
*/
#define VPU_G1_SWREG85_SW_PP_CROP8_R_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_CROP8_R_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_CROP8_R_E_MASK)
#define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_MASK (0x4U)
#define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_SHIFT (2U)
/*! SW_PP_OUT_SWAP16_E - PP output swap 16, swaps 16 bit half inside of 32 bit word. Can be used for
* 16 bit RGB to change pixel orders but is valid also for any output format. NOTE: requires
* that configuration of SW_PPD_OEN_VERSION=1
*/
#define VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_SWAP16_E_MASK)
#define VPU_G1_SWREG85_SW_PP_OUT_TILED_E_MASK (0x8U)
#define VPU_G1_SWREG85_SW_PP_OUT_TILED_E_SHIFT (3U)
/*! SW_PP_OUT_TILED_E - Tiled mode enable for PP output. Can be used only for YCbYCr 422 output
* format. Can be used only if corresponding configuration supports this feature. Tile size is 4x4
* pixels.
*/
#define VPU_G1_SWREG85_SW_PP_OUT_TILED_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_TILED_E_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_TILED_E_MASK)
#define VPU_G1_SWREG85_SW_PP_OUT_WIDTH_MASK (0x7FF0U)
#define VPU_G1_SWREG85_SW_PP_OUT_WIDTH_SHIFT (4U)
/*! SW_PP_OUT_WIDTH - Scaled picture width in pixels. Must be dividable by 8 or by any if Pixel
* Accurate PP output configuration is enabled. Max scaled picture width is 1920 pixels or maximum
* three times the input source width minus 8 pixels
*/
#define VPU_G1_SWREG85_SW_PP_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_WIDTH_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_WIDTH_MASK)
#define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_MASK (0x3FF8000U)
#define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_SHIFT (15U)
/*! SW_PP_OUT_HEIGHT - Scaled picture height in pixels (Must be dividable by 2 or by any if Pixel
* Accurate PP output configuration is enabled) Max scaled picture height is 1920 pixels or maximum
* three times the input source height minus 8 pixels
*/
#define VPU_G1_SWREG85_SW_PP_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_HEIGHT_MASK)
#define VPU_G1_SWREG85_SW_PP_OUT_FORMAT_MASK (0x1C000000U)
#define VPU_G1_SWREG85_SW_PP_OUT_FORMAT_SHIFT (26U)
/*! SW_PP_OUT_FORMAT - PP output picture data format:
* 0b000..RGB
* 0b001..YCbCr 4:2:0 planar (Not supported)
* 0b010..YCbCr 4:2:2 planar (Not supported)
* 0b011..YUYV 4:2:2 interleaved
* 0b100..YCbCr 4:4:4 planar (Not supported)
* 0b101..YCh 4:2:0 chrominance interleaved
* 0b110..YCh 4:2:2 (Not supported)
* 0b111..YCh 4:4:4 (Not supported)
*/
#define VPU_G1_SWREG85_SW_PP_OUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_OUT_FORMAT_SHIFT)) & VPU_G1_SWREG85_SW_PP_OUT_FORMAT_MASK)
#define VPU_G1_SWREG85_SW_PP_IN_FORMAT_MASK (0xE0000000U)
#define VPU_G1_SWREG85_SW_PP_IN_FORMAT_SHIFT (29U)
/*! SW_PP_IN_FORMAT - PP input picture data format
* 0b000..YUYV 4:2:2 interleaved (supported only in external mode)
* 0b001..YCbCr 4:2:0 Semi-planar in linear raster-scan format
* 0b010..YCbCr 4:2:0 planar (supported only in external mode)
* 0b011..YCbCr 4:0:0 (supported only in pipelined mode)
* 0b100..YCbCr 4:2:2 Semi-planar (supported only in pipelined mode)
* 0b101..YCbCr 4:2:0 Semi-planar in tiled format (supported only in external mode (8170 decoder only)
* 0b110..Reserved
* 0b111..Escape pp input data format. Defined in swreg86.
*/
#define VPU_G1_SWREG85_SW_PP_IN_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG85_SW_PP_IN_FORMAT_SHIFT)) & VPU_G1_SWREG85_SW_PP_IN_FORMAT_MASK)
/*! @} */
/*! @name SWREG86 - Mask 1 start coordinate register */
/*! @{ */
#define VPU_G1_SWREG86_SW_MASK1_STARTX_MASK (0x7FFU)
#define VPU_G1_SWREG86_SW_MASK1_STARTX_SHIFT (0U)
/*! SW_MASK1_STARTX - Horizontal start pixel for mask area 1. Defines the x coordinate. Coordinate
* 0,0 means the up-left corner in PP output luminance picture. See Table 47 for restrictions
*/
#define VPU_G1_SWREG86_SW_MASK1_STARTX(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_STARTX_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_STARTX_MASK)
#define VPU_G1_SWREG86_SW_MASK1_STARTY_MASK (0x3FF800U)
#define VPU_G1_SWREG86_SW_MASK1_STARTY_SHIFT (11U)
/*! SW_MASK1_STARTY - Vertical start pixel for mask area 1. Defines the y coordinate. Coordinate 0,0
* means the up-left corner in PP output luminance picture. See Table 47 for restrictions
*/
#define VPU_G1_SWREG86_SW_MASK1_STARTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_STARTY_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_STARTY_MASK)
#define VPU_G1_SWREG86_SW_MASK1_ABLEND_E_MASK (0x400000U)
#define VPU_G1_SWREG86_SW_MASK1_ABLEND_E_SHIFT (22U)
/*! SW_MASK1_ABLEND_E - Mask 1 alpha blending enable. Instead of masking the output picture the
* alpha blending is performed. Alpha blending source can be found from alpha blend 1 base address.
* Alpha blending can be enabled only for RGB/ YUYV 422 data.
*/
#define VPU_G1_SWREG86_SW_MASK1_ABLEND_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_MASK1_ABLEND_E_SHIFT)) & VPU_G1_SWREG86_SW_MASK1_ABLEND_E_MASK)
#define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_MASK (0xF800000U)
#define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_SHIFT (23U)
/*! SW_RANGEMAP_COEF_C - Range map value for chrominance component
*/
#define VPU_G1_SWREG86_SW_RANGEMAP_COEF_C(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_SHIFT)) & VPU_G1_SWREG86_SW_RANGEMAP_COEF_C_MASK)
#define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_MASK (0xE0000000U)
#define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_SHIFT (29U)
/*! SW_PP_IN_FORMAT_ES - Escape PP in format. Used if sw_pp_in_format is defined to 7.
* 0b000..YCbCr 4:4:4
* 0b001..YCbCr 4:1:1
*/
#define VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_SHIFT)) & VPU_G1_SWREG86_SW_PP_IN_FORMAT_ES_MASK)
/*! @} */
/*! @name SWREG87 - Mask 2 start coordinate register + Mask extensions */
/*! @{ */
#define VPU_G1_SWREG87_SW_MASK2_STARTX_MASK (0x7FFU)
#define VPU_G1_SWREG87_SW_MASK2_STARTX_SHIFT (0U)
/*! SW_MASK2_STARTX - Horizontal start pixel for mask area 2. Defines the x coordinate. Coordinate
* 0,0 means the up-left corner in PP output Y picture. See Table 47 for restrictions
*/
#define VPU_G1_SWREG87_SW_MASK2_STARTX(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTX_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTX_MASK)
#define VPU_G1_SWREG87_SW_MASK2_STARTY_MASK (0x3FF800U)
#define VPU_G1_SWREG87_SW_MASK2_STARTY_SHIFT (11U)
/*! SW_MASK2_STARTY - Vertical start pixel for mask area 2. Defines the y coordinate. Coordinate 0,0
* means the up-left corner in PP output Y picture. See Table 47 for restrictions
*/
#define VPU_G1_SWREG87_SW_MASK2_STARTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTY_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTY_MASK)
#define VPU_G1_SWREG87_SW_MASK2_ABLEND_E_MASK (0x400000U)
#define VPU_G1_SWREG87_SW_MASK2_ABLEND_E_SHIFT (22U)
/*! SW_MASK2_ABLEND_E - Mask 2 alpha blending enable. Instead of masking the output picture the
* alpha blending is performed. Alpha blending source can be found from alpha blend 2 base address.
* Alpha blending can be enabled only for RGB/YUYV 422 data.
*/
#define VPU_G1_SWREG87_SW_MASK2_ABLEND_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_ABLEND_E_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_ABLEND_E_MASK)
#define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_MASK (0x1800000U)
#define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_SHIFT (23U)
/*! SW_MASK2_STARTY_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG87_SW_MASK2_STARTY_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTY_EXT_MASK)
#define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_MASK (0x6000000U)
#define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_SHIFT (25U)
/*! SW_MASK2_STARTX_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG87_SW_MASK2_STARTX_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK2_STARTX_EXT_MASK)
#define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_MASK (0x18000000U)
#define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_SHIFT (27U)
/*! SW_MASK1_STARTY_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG87_SW_MASK1_STARTY_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK1_STARTY_EXT_MASK)
#define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_MASK (0x60000000U)
#define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_SHIFT (29U)
/*! SW_MASK1_STARTX_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG87_SW_MASK1_STARTX_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_SHIFT)) & VPU_G1_SWREG87_SW_MASK1_STARTX_EXT_MASK)
/*! @} */
/*! @name SWREG88 - Mask 1 size and PP original width register */
/*! @{ */
#define VPU_G1_SWREG88_SW_MASK1_ENDX_MASK (0x7FFU)
#define VPU_G1_SWREG88_SW_MASK1_ENDX_SHIFT (0U)
/*! SW_MASK1_ENDX - Mask 1 end coordinate x in pixels (inside of PPD output picture). Range must be
* between [Mask1StartCoordinateX, ScaledWidth]
*/
#define VPU_G1_SWREG88_SW_MASK1_ENDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_ENDX_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_ENDX_MASK)
#define VPU_G1_SWREG88_SW_MASK1_ENDY_MASK (0x3FF800U)
#define VPU_G1_SWREG88_SW_MASK1_ENDY_SHIFT (11U)
/*! SW_MASK1_ENDY - Mask 1 end coordinate y in pixels (inside of PPD output picture). Range must be
* between [Mask1StartCoordinateY, ScaledHeight].
*/
#define VPU_G1_SWREG88_SW_MASK1_ENDY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_ENDY_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_ENDY_MASK)
#define VPU_G1_SWREG88_SW_MASK1_E_MASK (0x400000U)
#define VPU_G1_SWREG88_SW_MASK1_E_SHIFT (22U)
/*! SW_MASK1_E - Mask 1 enable. If mask 1 is used this bit is high
*/
#define VPU_G1_SWREG88_SW_MASK1_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_MASK1_E_SHIFT)) & VPU_G1_SWREG88_SW_MASK1_E_MASK)
#define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_MASK (0xFF800000U)
#define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_SHIFT (23U)
/*! SW_EXT_ORIG_WIDTH - PP input picture original width in macro blocks.
*/
#define VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_SHIFT)) & VPU_G1_SWREG88_SW_EXT_ORIG_WIDTH_MASK)
/*! @} */
/*! @name SWREG89 - Mask 2 size register + mask extensions */
/*! @{ */
#define VPU_G1_SWREG89_SW_MASK2_ENDX_MASK (0x7FFU)
#define VPU_G1_SWREG89_SW_MASK2_ENDX_SHIFT (0U)
/*! SW_MASK2_ENDX - Mask 2 end coordinate x in pixels (inside of PP output picture). Range must be
* between [Mask2StartCoordinateX, ScaledWidth].
*/
#define VPU_G1_SWREG89_SW_MASK2_ENDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDX_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDX_MASK)
#define VPU_G1_SWREG89_SW_MASK2_ENDY_MASK (0x3FF800U)
#define VPU_G1_SWREG89_SW_MASK2_ENDY_SHIFT (11U)
/*! SW_MASK2_ENDY - Mask 2 end coordinate y in pixels (inside of PP output picture). Range must be
* between [Mask2StartCoordinateY, ScaledHeight].
*/
#define VPU_G1_SWREG89_SW_MASK2_ENDY(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDY_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDY_MASK)
#define VPU_G1_SWREG89_SW_MASK2_E_MASK (0x400000U)
#define VPU_G1_SWREG89_SW_MASK2_E_SHIFT (22U)
/*! SW_MASK2_E - Mask 2 enable. If mask 1 is used this bit is high
*/
#define VPU_G1_SWREG89_SW_MASK2_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_E_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_E_MASK)
#define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_MASK (0x1800000U)
#define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_SHIFT (23U)
/*! SW_MASK2_ENDY_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG89_SW_MASK2_ENDY_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDY_EXT_MASK)
#define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_MASK (0x6000000U)
#define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_SHIFT (25U)
/*! SW_MASK2_ENDX_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG89_SW_MASK2_ENDX_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK2_ENDX_EXT_MASK)
#define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_MASK (0x18000000U)
#define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_SHIFT (27U)
/*! SW_MASK1_ENDY_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG89_SW_MASK1_ENDY_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK1_ENDY_EXT_MASK)
#define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_MASK (0x60000000U)
#define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_SHIFT (29U)
/*! SW_MASK1_ENDX_EXT - Extended coordinate upto 4k resolution
*/
#define VPU_G1_SWREG89_SW_MASK1_ENDX_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_SHIFT)) & VPU_G1_SWREG89_SW_MASK1_ENDX_EXT_MASK)
/*! @} */
/*! @name SWREG90 - PiP register 0 */
/*! @{ */
#define VPU_G1_SWREG90_SW_DOWN_CROSS_MASK (0x7FFU)
#define VPU_G1_SWREG90_SW_DOWN_CROSS_SHIFT (0U)
/*! SW_DOWN_CROSS - Amount of downward overcross (vertical pixels outside of display from the down
* side). Range must be between [0, ScaledHeight].
*/
#define VPU_G1_SWREG90_SW_DOWN_CROSS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_MASK)
#define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_MASK (0x1800U)
#define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_SHIFT (11U)
/*! SW_DOWN_CROSS_EXT - Extended coordinate for 4k resolution
*/
#define VPU_G1_SWREG90_SW_DOWN_CROSS_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_EXT_MASK)
#define VPU_G1_SWREG90_SW_UP_CROSS_MASK (0x3FF8000U)
#define VPU_G1_SWREG90_SW_UP_CROSS_SHIFT (15U)
/*! SW_UP_CROSS - Amount of upward overcross (vertical pixels outside of display from the upper
* side). Range must be between [0, ScaledHeight].
*/
#define VPU_G1_SWREG90_SW_UP_CROSS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_UP_CROSS_SHIFT)) & VPU_G1_SWREG90_SW_UP_CROSS_MASK)
#define VPU_G1_SWREG90_SW_DOWN_CROSS_E_MASK (0x4000000U)
#define VPU_G1_SWREG90_SW_DOWN_CROSS_E_SHIFT (26U)
/*! SW_DOWN_CROSS_E - Downward overcross enable.
* 0b0..No downward overcross
* 0b1..Downward overcross
*/
#define VPU_G1_SWREG90_SW_DOWN_CROSS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_DOWN_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_DOWN_CROSS_E_MASK)
#define VPU_G1_SWREG90_SW_UP_CROSS_E_MASK (0x8000000U)
#define VPU_G1_SWREG90_SW_UP_CROSS_E_SHIFT (27U)
/*! SW_UP_CROSS_E - Upward overcross enable.
* 0b0..No upward overcross
* 0b1..Upward overcross
*/
#define VPU_G1_SWREG90_SW_UP_CROSS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_UP_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_UP_CROSS_E_MASK)
#define VPU_G1_SWREG90_SW_LEFT_CROSS_E_MASK (0x10000000U)
#define VPU_G1_SWREG90_SW_LEFT_CROSS_E_SHIFT (28U)
/*! SW_LEFT_CROSS_E - Left side overcross enable.
* 0b0..No left side overcross
* 0b1..Left side overcross
*/
#define VPU_G1_SWREG90_SW_LEFT_CROSS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_LEFT_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_LEFT_CROSS_E_MASK)
#define VPU_G1_SWREG90_SW_RIGHT_CROSS_E_MASK (0x20000000U)
#define VPU_G1_SWREG90_SW_RIGHT_CROSS_E_SHIFT (29U)
/*! SW_RIGHT_CROSS_E - Right side overcross enable.
* 0b0..No right side overcross
* 0b1..Right side overcross
*/
#define VPU_G1_SWREG90_SW_RIGHT_CROSS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG90_SW_RIGHT_CROSS_E_SHIFT)) & VPU_G1_SWREG90_SW_RIGHT_CROSS_E_MASK)
/*! @} */
/*! @name SWREG91 - PiP register 1 and dithering control */
/*! @{ */
#define VPU_G1_SWREG91_SW_LEFT_CROSS_MASK (0x7FFU)
#define VPU_G1_SWREG91_SW_LEFT_CROSS_SHIFT (0U)
/*! SW_LEFT_CROSS - Amount of left side overcross (Horizontal pixels outside of display from the
* left side). Range must be between [0, ScaledWidth].
*/
#define VPU_G1_SWREG91_SW_LEFT_CROSS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_LEFT_CROSS_SHIFT)) & VPU_G1_SWREG91_SW_LEFT_CROSS_MASK)
#define VPU_G1_SWREG91_SW_RIGHT_CROSS_MASK (0x3FF800U)
#define VPU_G1_SWREG91_SW_RIGHT_CROSS_SHIFT (11U)
/*! SW_RIGHT_CROSS - Amount of right side overcross (Horizontal pixels outside of display from the
* right side). Range must be between [0, ScaledWidth].
*/
#define VPU_G1_SWREG91_SW_RIGHT_CROSS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_RIGHT_CROSS_SHIFT)) & VPU_G1_SWREG91_SW_RIGHT_CROSS_MASK)
#define VPU_G1_SWREG91_SW_PP_TILED_MODE_MASK (0xC00000U)
#define VPU_G1_SWREG91_SW_PP_TILED_MODE_SHIFT (22U)
/*! SW_PP_TILED_MODE - Input data is in tiled mode (at the moment valid only for YCbCr 420 data, pipeline or external mode):
* 0b00..Tiled mode not used
* 0b01..Tiled mode enabled for 8x4 sized tiles
*/
#define VPU_G1_SWREG91_SW_PP_TILED_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_PP_TILED_MODE_SHIFT)) & VPU_G1_SWREG91_SW_PP_TILED_MODE_MASK)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_B_MASK (0xC000000U)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_B_SHIFT (26U)
/*! SW_DITHER_SELECT_B - Dithering control for B channel:
* 0b00..dithering disabled
* 0b01..use four-bit dither matrix
* 0b10..use five-bit dither matrix
* 0b11..use six-bit dither matrix
*/
#define VPU_G1_SWREG91_SW_DITHER_SELECT_B(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_B_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_B_MASK)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_G_MASK (0x30000000U)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_G_SHIFT (28U)
/*! SW_DITHER_SELECT_G - Dithering control for G channel:
* 0b00..dithering disabled
* 0b01..use four-bit dither matrix
* 0b10..use five-bit dither matrix
* 0b11..use six-bit dither matrix
*/
#define VPU_G1_SWREG91_SW_DITHER_SELECT_G(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_G_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_G_MASK)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_R_MASK (0xC0000000U)
#define VPU_G1_SWREG91_SW_DITHER_SELECT_R_SHIFT (30U)
/*! SW_DITHER_SELECT_R - Dithering control for R channel:
* 0b00..dithering disabled
* 0b01..use four-bit dither matrix
* 0b10..use five-bit dither matrix
* 0b11..use six-bit dither matrix
*/
#define VPU_G1_SWREG91_SW_DITHER_SELECT_R(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG91_SW_DITHER_SELECT_R_SHIFT)) & VPU_G1_SWREG91_SW_DITHER_SELECT_R_MASK)
/*! @} */
/*! @name SWREG92 - Display width and PP input size extension register */
/*! @{ */
#define VPU_G1_SWREG92_SW_DISPLAY_WIDTH_MASK (0x1FFFU)
#define VPU_G1_SWREG92_SW_DISPLAY_WIDTH_SHIFT (0U)
/*! SW_DISPLAY_WIDTH - Width of the display in pixels. Max 4k (depends on HW config support)
*/
#define VPU_G1_SWREG92_SW_DISPLAY_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_DISPLAY_WIDTH_SHIFT)) & VPU_G1_SWREG92_SW_DISPLAY_WIDTH_MASK)
#define VPU_G1_SWREG92_SW_UP_CROSS_EXT_MASK (0xC000U)
#define VPU_G1_SWREG92_SW_UP_CROSS_EXT_SHIFT (14U)
/*! SW_UP_CROSS_EXT - Extended coordinate for 4k resolution
*/
#define VPU_G1_SWREG92_SW_UP_CROSS_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_UP_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_UP_CROSS_EXT_MASK)
#define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_MASK (0x30000U)
#define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_SHIFT (16U)
/*! SW_LEFT_CROSS_EXT - Extended coordinate for 4k resolution
*/
#define VPU_G1_SWREG92_SW_LEFT_CROSS_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_LEFT_CROSS_EXT_MASK)
#define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_MASK (0xC0000U)
#define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_SHIFT (18U)
/*! SW_RIGHT_CROSS_EXT - Extended coordinate for 4k resolution
*/
#define VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_SHIFT)) & VPU_G1_SWREG92_SW_RIGHT_CROSS_EXT_MASK)
#define VPU_G1_SWREG92_SW_CROP_STARTX_EXT_MASK (0x700000U)
#define VPU_G1_SWREG92_SW_CROP_STARTX_EXT_SHIFT (20U)
/*! SW_CROP_STARTX_EXT - Extended PP input crop start coordinate y. Used with WEBP
*/
#define VPU_G1_SWREG92_SW_CROP_STARTX_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_CROP_STARTX_EXT_SHIFT)) & VPU_G1_SWREG92_SW_CROP_STARTX_EXT_MASK)
#define VPU_G1_SWREG92_SW_CROP_STARTY_EXT_MASK (0x3800000U)
#define VPU_G1_SWREG92_SW_CROP_STARTY_EXT_SHIFT (23U)
/*! SW_CROP_STARTY_EXT - Extended PP input crop start coordinate x. Used with WEBP
*/
#define VPU_G1_SWREG92_SW_CROP_STARTY_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_CROP_STARTY_EXT_SHIFT)) & VPU_G1_SWREG92_SW_CROP_STARTY_EXT_MASK)
#define VPU_G1_SWREG92_SW_PP_IN_W_EXT_MASK (0x1C000000U)
#define VPU_G1_SWREG92_SW_PP_IN_W_EXT_SHIFT (26U)
/*! SW_PP_IN_W_EXT - Extended PP input width. Used with WEBP
*/
#define VPU_G1_SWREG92_SW_PP_IN_W_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_PP_IN_W_EXT_SHIFT)) & VPU_G1_SWREG92_SW_PP_IN_W_EXT_MASK)
#define VPU_G1_SWREG92_SW_PP_IN_H_EXT_MASK (0xE0000000U)
#define VPU_G1_SWREG92_SW_PP_IN_H_EXT_SHIFT (29U)
/*! SW_PP_IN_H_EXT - Extended PP input height. Used with WEBP
*/
#define VPU_G1_SWREG92_SW_PP_IN_H_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG92_SW_PP_IN_H_EXT_SHIFT)) & VPU_G1_SWREG92_SW_PP_IN_H_EXT_MASK)
/*! @} */
/*! @name SWREG93 - Base address for alpha blend 1 gui component */
/*! @{ */
#define VPU_G1_SWREG93_SW_ABLEND1_BASE_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG93_SW_ABLEND1_BASE_SHIFT (0U)
/*! SW_ABLEND1_BASE - Base address for alpha blending input 1 (if mask1 is used in alpha blending
* mode). Format of data is 24 bit RGB/ YCbCr and endian/swap -mode is as in PP input. Amount of
* data is informed with mask 1 size or with ablend1_scanline if ablend cropping is supported in
* configuration.
*/
#define VPU_G1_SWREG93_SW_ABLEND1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG93_SW_ABLEND1_BASE_SHIFT)) & VPU_G1_SWREG93_SW_ABLEND1_BASE_MASK)
/*! @} */
/*! @name SWREG94 - Base address for alpha blend 2 gui component */
/*! @{ */
#define VPU_G1_SWREG94_SW_ABLEND2_BASE_MASK (0xFFFFFFFFU)
#define VPU_G1_SWREG94_SW_ABLEND2_BASE_SHIFT (0U)
/*! SW_ABLEND2_BASE - Base address for alpha blending input 2 (if mask2 is used in alpha blending
* mode). Format of data is 24 bit RGB/ YCbCr and endian/swap -mode is as in PP input. Amount of
* data is informed with mask 2 size or with ablend2_scanline if ablend cropping is supported in
* configuration.
*/
#define VPU_G1_SWREG94_SW_ABLEND2_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG94_SW_ABLEND2_BASE_SHIFT)) & VPU_G1_SWREG94_SW_ABLEND2_BASE_MASK)
/*! @} */
/*! @name SWREG95 - Alpha blend input cropping register (scanline for cropping) */
/*! @{ */
#define VPU_G1_SWREG95_SW_ABLEND1_SCANL_MASK (0x1FFFU)
#define VPU_G1_SWREG95_SW_ABLEND1_SCANL_SHIFT (0U)
/*! SW_ABLEND1_SCANL - Scanline width in pixels for Ablend 1. Usage enabled if corresponding configuration bit is enabled
*/
#define VPU_G1_SWREG95_SW_ABLEND1_SCANL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG95_SW_ABLEND1_SCANL_SHIFT)) & VPU_G1_SWREG95_SW_ABLEND1_SCANL_MASK)
#define VPU_G1_SWREG95_SW_ABLEND2_SCANL_MASK (0x3FFE000U)
#define VPU_G1_SWREG95_SW_ABLEND2_SCANL_SHIFT (13U)
/*! SW_ABLEND2_SCANL - Scanline width in pixels for Ablend 2. Usage enabled if corresponding configuration bit is enabled
*/
#define VPU_G1_SWREG95_SW_ABLEND2_SCANL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG95_SW_ABLEND2_SCANL_SHIFT)) & VPU_G1_SWREG95_SW_ABLEND2_SCANL_MASK)
/*! @} */
/*! @name SWREG99 - PP fuse register */
/*! @{ */
#define VPU_G1_SWREG99_FUSE_PP_MAXW_352_MASK (0x1000U)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_352_SHIFT (12U)
/*! FUSE_PP_MAXW_352 - 1 = Max PP output width up to 352 pixels enabled. Priority coded with priority 5
*/
#define VPU_G1_SWREG99_FUSE_PP_MAXW_352(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_352_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_352_MASK)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_720_MASK (0x2000U)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_720_SHIFT (13U)
/*! FUSE_PP_MAXW_720 - 1 = Max PP output width up to 720 pixels enabled. Priority coded with priority 4
*/
#define VPU_G1_SWREG99_FUSE_PP_MAXW_720(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_720_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_720_MASK)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1280_MASK (0x4000U)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1280_SHIFT (14U)
/*! FUSE_PP_MAXW_1280 - 1 = Max PP output width up to 1280 pixels enabled. Priority coded with priority 3
*/
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1280(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_1280_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_1280_MASK)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1920_MASK (0x8000U)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1920_SHIFT (15U)
/*! FUSE_PP_MAXW_1920 - 1 = Max PP output width up to 1920 pixels enabled. Priority coded with priority 2
*/
#define VPU_G1_SWREG99_FUSE_PP_MAXW_1920(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_1920_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_1920_MASK)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_4K_MASK (0x10000U)
#define VPU_G1_SWREG99_FUSE_PP_MAXW_4K_SHIFT (16U)
/*! FUSE_PP_MAXW_4K - 1 = Max PP output width up to 4096 pixels enabled. Priority coded with priority 1
*/
#define VPU_G1_SWREG99_FUSE_PP_MAXW_4K(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_MAXW_4K_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_MAXW_4K_MASK)
#define VPU_G1_SWREG99_FUSE_PP_ABLEND_MASK (0x20000000U)
#define VPU_G1_SWREG99_FUSE_PP_ABLEND_SHIFT (29U)
/*! FUSE_PP_ABLEND - 1 = Alpha Blending enabled
*/
#define VPU_G1_SWREG99_FUSE_PP_ABLEND(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_ABLEND_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_ABLEND_MASK)
#define VPU_G1_SWREG99_FUSE_PP_DEINT_MASK (0x40000000U)
#define VPU_G1_SWREG99_FUSE_PP_DEINT_SHIFT (30U)
/*! FUSE_PP_DEINT - 1 = Deinterlacing enabled
*/
#define VPU_G1_SWREG99_FUSE_PP_DEINT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_DEINT_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_DEINT_MASK)
#define VPU_G1_SWREG99_FUSE_PP_PP_MASK (0x80000000U)
#define VPU_G1_SWREG99_FUSE_PP_PP_SHIFT (31U)
/*! FUSE_PP_PP - 1 = PP enabled
*/
#define VPU_G1_SWREG99_FUSE_PP_PP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG99_FUSE_PP_PP_SHIFT)) & VPU_G1_SWREG99_FUSE_PP_PP_MASK)
/*! @} */
/*! @name SWREG100 - Synthesis configuration register post-processor */
/*! @{ */
#define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_MASK (0x1FFFU)
#define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_SHIFT (0U)
/*! SW_PPD_MAX_OWIDTH - Max supported PP output width in pixels
*/
#define VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_SHIFT)) & VPU_G1_SWREG100_SW_PPD_MAX_OWIDTH_MASK)
#define VPU_G1_SWREG100_SW_PPD_IN_TILED_L_MASK (0xC000U)
#define VPU_G1_SWREG100_SW_PPD_IN_TILED_L_SHIFT (14U)
/*! SW_PPD_IN_TILED_L - PPD input tiled mode support level
* 0b00..not supported
* 0b01..8x4 tile size supported
*/
#define VPU_G1_SWREG100_SW_PPD_IN_TILED_L(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_IN_TILED_L_SHIFT)) & VPU_G1_SWREG100_SW_PPD_IN_TILED_L_MASK)
#define VPU_G1_SWREG100_SW_PPD_PP_EXIST_MASK (0x10000U)
#define VPU_G1_SWREG100_SW_PPD_PP_EXIST_SHIFT (16U)
/*! SW_PPD_PP_EXIST - PPD exists:
* 0b0..No
* 0b1..Yes
*/
#define VPU_G1_SWREG100_SW_PPD_PP_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_PP_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_PP_EXIST_MASK)
#define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_MASK (0x20000U)
#define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_SHIFT (17U)
/*! SW_PPD_OBUFF_LEVEL - PP output buffering level:
* 0b0..1 unit output buffering is used
* 0b1..4 unit output buffering is used
*/
#define VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_OBUFF_LEVEL_MASK)
#define VPU_G1_SWREG100_SW_PPD_OEN_VERSION_MASK (0x40000U)
#define VPU_G1_SWREG100_SW_PPD_OEN_VERSION_SHIFT (18U)
/*! SW_PPD_OEN_VERSION - PP output endian version:
* 0b0..Endian mode supported for other than RGB
* 0b1..Endian mode supported for any output format
*/
#define VPU_G1_SWREG100_SW_PPD_OEN_VERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_OEN_VERSION_SHIFT)) & VPU_G1_SWREG100_SW_PPD_OEN_VERSION_MASK)
#define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_MASK (0x800000U)
#define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_SHIFT (23U)
/*! SW_PPD_IBUFF_LEVEL - PP input buffering level:
* 0b0..1 MB input buffering is used
* 0b1..4 MB input buffering is used
*/
#define VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_IBUFF_LEVEL_MASK)
#define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_MASK (0x1000000U)
#define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_SHIFT (24U)
/*! SW_PPD_BLEND_EXIST - Alpha blending exists:
* 0b0..No
* 0b1..Yes
*/
#define VPU_G1_SWREG100_SW_PPD_BLEND_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_BLEND_EXIST_MASK)
#define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_MASK (0x2000000U)
#define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_SHIFT (25U)
/*! SW_PPD_DEINT_EXIST - De-interlacing exits:
* 0b0..No
* 0b1..Yes
*/
#define VPU_G1_SWREG100_SW_PPD_DEINT_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_DEINT_EXIST_MASK)
#define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_MASK (0xC000000U)
#define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_SHIFT (26U)
/*! SW_PPD_SCALE_LEVEL - Scaling support:
* 0b00..No scaling
* 0b01..Scaling with lo performance architecture
* 0b10..Scaling with high performance architecture
* 0b11..Scaling with high performance architecture + fast downscaling enabled
*/
#define VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_SHIFT)) & VPU_G1_SWREG100_SW_PPD_SCALE_LEVEL_MASK)
#define VPU_G1_SWREG100_SW_PPD_DITH_EXIST_MASK (0x10000000U)
#define VPU_G1_SWREG100_SW_PPD_DITH_EXIST_SHIFT (28U)
/*! SW_PPD_DITH_EXIST - Dithering exists:
* 0b0..No
* 0b1..Yes
*/
#define VPU_G1_SWREG100_SW_PPD_DITH_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_DITH_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_DITH_EXIST_MASK)
#define VPU_G1_SWREG100_SW_PPD_TILED_EXIST_MASK (0x20000000U)
#define VPU_G1_SWREG100_SW_PPD_TILED_EXIST_SHIFT (29U)
/*! SW_PPD_TILED_EXIST - PP output YCbYCr 422 tiled support (4x4 pixel tiles)
* 0b0..Not supported
* 0b1..Supported
*/
#define VPU_G1_SWREG100_SW_PPD_TILED_EXIST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_TILED_EXIST_SHIFT)) & VPU_G1_SWREG100_SW_PPD_TILED_EXIST_MASK)
#define VPU_G1_SWREG100_SW_PPD_PIXAC_E_MASK (0x40000000U)
#define VPU_G1_SWREG100_SW_PPD_PIXAC_E_SHIFT (30U)
/*! SW_PPD_PIXAC_E - Pixel Accurate PP output mode exists:
* 0b0..PIP, Scaling and masks can be adjusted by steps of 8 pixels (width) or 2 pixels (height)
* 0b1..PIP, Scaling and masks can be adjusted by steps of 1 pixel for RGB and 2 pixels for subsampled chroma
* formats (by using bus specific write strobe functionality)
*/
#define VPU_G1_SWREG100_SW_PPD_PIXAC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_PPD_PIXAC_E_SHIFT)) & VPU_G1_SWREG100_SW_PPD_PIXAC_E_MASK)
#define VPU_G1_SWREG100_SW_ABLEND_CROP_E_MASK (0x80000000U)
#define VPU_G1_SWREG100_SW_ABLEND_CROP_E_SHIFT (31U)
/*! SW_ABLEND_CROP_E - Alpha blending support for input cropping:
* 0b0..Not supported. External memory must include the exact image of the area being alpha blended.
* 0b1..Supported. External memory can include a picture from blended area can be cropped. Requires usage of swreg95.
*/
#define VPU_G1_SWREG100_SW_ABLEND_CROP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG100_SW_ABLEND_CROP_E_SHIFT)) & VPU_G1_SWREG100_SW_ABLEND_CROP_E_MASK)
/*! @} */
/*! @name SWREG102 - Base address for H264 decoded chroma picture */
/*! @{ */
#define VPU_G1_SWREG102_SW_CH_BASE_E_MASK (0x1U)
#define VPU_G1_SWREG102_SW_CH_BASE_E_SHIFT (0U)
/*! SW_CH_BASE_E - chroma address separate mode enable:
* 0b1..HW outputs decoded chroma picture to independent memory address
* 0b0..HW outputs decoded chroma picture to the end of decoded luma picture. HW calculates the chroma picture
* address according to sw_dec_base and luma data length.
*/
#define VPU_G1_SWREG102_SW_CH_BASE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG102_SW_CH_BASE_E_SHIFT)) & VPU_G1_SWREG102_SW_CH_BASE_E_MASK)
#define VPU_G1_SWREG102_SW_DEC_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG102_SW_DEC_CH_BASE_SHIFT (2U)
/*! SW_DEC_CH_BASE - Valid only if chroma address separate mode is enabled. H264: Base address for
* decoder output chroma picture. Points directly to start of decoder output chroma picture or
* field.
*/
#define VPU_G1_SWREG102_SW_DEC_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG102_SW_DEC_CH_BASE_SHIFT)) & VPU_G1_SWREG102_SW_DEC_CH_BASE_MASK)
/*! @} */
/*! @name SWREG103 - Base address for reference chroma picture index 0 */
/*! @{ */
#define VPU_G1_SWREG103_SW_REFER0_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG103_SW_REFER0_CH_BASE_SHIFT (2U)
/*! SW_REFER0_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 0.
*/
#define VPU_G1_SWREG103_SW_REFER0_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG103_SW_REFER0_CH_BASE_SHIFT)) & VPU_G1_SWREG103_SW_REFER0_CH_BASE_MASK)
/*! @} */
/*! @name SWREG104 - Base address for reference chroma picture index 1 */
/*! @{ */
#define VPU_G1_SWREG104_SW_REFER1_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG104_SW_REFER1_CH_BASE_SHIFT (2U)
/*! SW_REFER1_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 1.
*/
#define VPU_G1_SWREG104_SW_REFER1_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG104_SW_REFER1_CH_BASE_SHIFT)) & VPU_G1_SWREG104_SW_REFER1_CH_BASE_MASK)
/*! @} */
/*! @name SWREG105 - Base address for reference chroma picture index 2 */
/*! @{ */
#define VPU_G1_SWREG105_SW_REFER2_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG105_SW_REFER2_CH_BASE_SHIFT (2U)
/*! SW_REFER2_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 2.
*/
#define VPU_G1_SWREG105_SW_REFER2_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG105_SW_REFER2_CH_BASE_SHIFT)) & VPU_G1_SWREG105_SW_REFER2_CH_BASE_MASK)
/*! @} */
/*! @name SWREG106 - Base address for reference chroma picture index 3 */
/*! @{ */
#define VPU_G1_SWREG106_SW_REFER3_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG106_SW_REFER3_CH_BASE_SHIFT (2U)
/*! SW_REFER3_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 3.
*/
#define VPU_G1_SWREG106_SW_REFER3_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG106_SW_REFER3_CH_BASE_SHIFT)) & VPU_G1_SWREG106_SW_REFER3_CH_BASE_MASK)
/*! @} */
/*! @name SWREG107 - Base address for reference chroma picture index 4 */
/*! @{ */
#define VPU_G1_SWREG107_SW_REFER4_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG107_SW_REFER4_CH_BASE_SHIFT (2U)
/*! SW_REFER4_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 4.
*/
#define VPU_G1_SWREG107_SW_REFER4_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG107_SW_REFER4_CH_BASE_SHIFT)) & VPU_G1_SWREG107_SW_REFER4_CH_BASE_MASK)
/*! @} */
/*! @name SWREG108 - Base address for reference chroma picture index 5 */
/*! @{ */
#define VPU_G1_SWREG108_SW_REFER5_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG108_SW_REFER5_CH_BASE_SHIFT (2U)
/*! SW_REFER5_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 5.
*/
#define VPU_G1_SWREG108_SW_REFER5_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG108_SW_REFER5_CH_BASE_SHIFT)) & VPU_G1_SWREG108_SW_REFER5_CH_BASE_MASK)
/*! @} */
/*! @name SWREG109 - Base address for reference chroma picture index 6 */
/*! @{ */
#define VPU_G1_SWREG109_SW_REFER6_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG109_SW_REFER6_CH_BASE_SHIFT (2U)
/*! SW_REFER6_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 6.
*/
#define VPU_G1_SWREG109_SW_REFER6_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG109_SW_REFER6_CH_BASE_SHIFT)) & VPU_G1_SWREG109_SW_REFER6_CH_BASE_MASK)
/*! @} */
/*! @name SWREG110 - Base address for reference chroma picture index 7 */
/*! @{ */
#define VPU_G1_SWREG110_SW_REFER7_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG110_SW_REFER7_CH_BASE_SHIFT (2U)
/*! SW_REFER7_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 7.
*/
#define VPU_G1_SWREG110_SW_REFER7_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG110_SW_REFER7_CH_BASE_SHIFT)) & VPU_G1_SWREG110_SW_REFER7_CH_BASE_MASK)
/*! @} */
/*! @name SWREG111 - Base address for reference chroma picture index 8 */
/*! @{ */
#define VPU_G1_SWREG111_SW_REFER8_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG111_SW_REFER8_CH_BASE_SHIFT (2U)
/*! SW_REFER8_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 8.
*/
#define VPU_G1_SWREG111_SW_REFER8_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG111_SW_REFER8_CH_BASE_SHIFT)) & VPU_G1_SWREG111_SW_REFER8_CH_BASE_MASK)
/*! @} */
/*! @name SWREG112 - Base address for reference chroma picture index 9 */
/*! @{ */
#define VPU_G1_SWREG112_SW_REFER9_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG112_SW_REFER9_CH_BASE_SHIFT (2U)
/*! SW_REFER9_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 9.
*/
#define VPU_G1_SWREG112_SW_REFER9_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG112_SW_REFER9_CH_BASE_SHIFT)) & VPU_G1_SWREG112_SW_REFER9_CH_BASE_MASK)
/*! @} */
/*! @name SWREG113 - Base address for reference chroma picture index 10 */
/*! @{ */
#define VPU_G1_SWREG113_SW_REFER10_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG113_SW_REFER10_CH_BASE_SHIFT (2U)
/*! SW_REFER10_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 10.
*/
#define VPU_G1_SWREG113_SW_REFER10_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG113_SW_REFER10_CH_BASE_SHIFT)) & VPU_G1_SWREG113_SW_REFER10_CH_BASE_MASK)
/*! @} */
/*! @name SWREG114 - Base address for reference chroma picture index 11 */
/*! @{ */
#define VPU_G1_SWREG114_SW_REFER11_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG114_SW_REFER11_CH_BASE_SHIFT (2U)
/*! SW_REFER11_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 11.
*/
#define VPU_G1_SWREG114_SW_REFER11_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG114_SW_REFER11_CH_BASE_SHIFT)) & VPU_G1_SWREG114_SW_REFER11_CH_BASE_MASK)
/*! @} */
/*! @name SWREG115 - Base address for reference chroma picture index 12 */
/*! @{ */
#define VPU_G1_SWREG115_SW_REFER12_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG115_SW_REFER12_CH_BASE_SHIFT (2U)
/*! SW_REFER12_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 12.
*/
#define VPU_G1_SWREG115_SW_REFER12_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG115_SW_REFER12_CH_BASE_SHIFT)) & VPU_G1_SWREG115_SW_REFER12_CH_BASE_MASK)
/*! @} */
/*! @name SWREG116 - Base address for reference chroma picture index 13 */
/*! @{ */
#define VPU_G1_SWREG116_SW_REFER13_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG116_SW_REFER13_CH_BASE_SHIFT (2U)
/*! SW_REFER13_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 13.
*/
#define VPU_G1_SWREG116_SW_REFER13_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG116_SW_REFER13_CH_BASE_SHIFT)) & VPU_G1_SWREG116_SW_REFER13_CH_BASE_MASK)
/*! @} */
/*! @name SWREG117 - Base address for reference chroma picture index 14 */
/*! @{ */
#define VPU_G1_SWREG117_SW_REFER14_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG117_SW_REFER14_CH_BASE_SHIFT (2U)
/*! SW_REFER14_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 14.
*/
#define VPU_G1_SWREG117_SW_REFER14_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG117_SW_REFER14_CH_BASE_SHIFT)) & VPU_G1_SWREG117_SW_REFER14_CH_BASE_MASK)
/*! @} */
/*! @name SWREG118 - Base address for reference chroma picture index 15 */
/*! @{ */
#define VPU_G1_SWREG118_SW_REFER15_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_SWREG118_SW_REFER15_CH_BASE_SHIFT (2U)
/*! SW_REFER15_CH_BASE - Valid only if chroma address separate mode is enabled. Base address for reference chroma picture index 15.
*/
#define VPU_G1_SWREG118_SW_REFER15_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_SWREG118_SW_REFER15_CH_BASE_SHIFT)) & VPU_G1_SWREG118_SW_REFER15_CH_BASE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_G1_Register_Masks */
/* VPU_G1 - Peripheral instance base addresses */
/** Peripheral VPU_G1 base address */
#define VPU_G1_BASE (0x38300000u)
/** Peripheral VPU_G1 base pointer */
#define VPU_G1 ((VPU_G1_Type *)VPU_G1_BASE)
/** Array initializer of VPU_G1 peripheral base addresses */
#define VPU_G1_BASE_ADDRS { VPU_G1_BASE }
/** Array initializer of VPU_G1 peripheral base pointers */
#define VPU_G1_BASE_PTRS { VPU_G1 }
/*!
* @}
*/ /* end of group VPU_G1_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_G1_H264 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_H264_Peripheral_Access_Layer VPU_G1_H264 Peripheral Access Layer
* @{
*/
/** VPU_G1_H264 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t SWREG4; /**< Decoder control register 1 (picture parameters), offset: 0x10 */
__IO uint32_t SWREG5; /**< Decoder control register 2 (stream decoding table selects), offset: 0x14 */
__IO uint32_t SWREG6; /**< Decoder control register 3 (stream buffer information), offset: 0x18 */
__IO uint32_t SWREG7; /**< Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control), offset: 0x1C */
__IO uint32_t SWREG8; /**< Decoder control register 5 (H264, VC-1, VP6, Progressive JPEG and RV control), offset: 0x20 */
__IO uint32_t SWREG9; /**< Decoder control register 6 / base address for MB-control (RLC) / VC-1 intensity control 0/ VP6,VP7,VP8 ctrl-stream length/ RV pic slice amount, offset: 0x24 */
__IO uint32_t SWREG10; /**< Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register, offset: 0x28 */
__IO uint32_t SWREG11; /**< Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2, offset: 0x2C */
uint8_t RESERVED_1[8];
__IO uint32_t SWREG14; /**< Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture, offset: 0x38 */
__IO uint32_t SWREG15; /**< Base address for reference picture index 1 / JPEG control, offset: 0x3C */
__IO uint32_t SWREG16; /**< Base address for reference picture index 2 / List of VLC code lengths in first JPEG AC table, offset: 0x40 */
__IO uint32_t SWREG17; /**< Base address for reference picture index 3 / List of VLC code lengths in first JPEG AC table, offset: 0x44 */
__IO uint32_t SWREG18; /**< Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base, offset: 0x48 */
__IO uint32_t SWREG19; /**< Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps, offset: 0x4C */
__IO uint32_t SWREG20; /**< Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x50 */
__IO uint32_t SWREG21; /**< Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x54 */
__IO uint32_t SWREG22; /**< Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base, offset: 0x58 */
__IO uint32_t SWREG23; /**< Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base, offset: 0x5C */
__IO uint32_t SWREG24; /**< Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base, offset: 0x60 */
__IO uint32_t SWREG25; /**< Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base, offset: 0x64 */
__IO uint32_t SWREG26; /**< Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base, offset: 0x68 */
__IO uint32_t SWREG27; /**< Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table, offset: 0x6C */
__IO uint32_t SWREG28; /**< Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base, offset: 0x70 */
__IO uint32_t SWREG29; /**< Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base, offset: 0x74 */
__IO uint32_t SWREG30; /**< Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts, offset: 0x78 */
__IO uint32_t SWREG31; /**< Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts, offset: 0x7C */
__IO uint32_t SWREG32; /**< Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels, offset: 0x80 */
__IO uint32_t SWREG33; /**< Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values, offset: 0x84 */
__IO uint32_t SWREG34; /**< Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps, offset: 0x88 */
__IO uint32_t SWREG35; /**< Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x8C */
__IO uint32_t SWREG36; /**< Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x90 */
__IO uint32_t SWREG37; /**< Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps, offset: 0x94 */
__IO uint32_t SWREG38; /**< Reference picture long term flags (H264 VLC) / VPx prediction filter taps, offset: 0x98 */
__IO uint32_t SWREG39; /**< Reference picture valid flags (H264 VLC) / VPx prediction filter taps, offset: 0x9C */
uint8_t RESERVED_2[8];
__IO uint32_t SWREG42_H264; /**< bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base, offset: 0xA8 */
__IO uint32_t SWREG43_H264; /**< bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base, offset: 0xAC */
__IO uint32_t SWREG44_H264; /**< bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps, offset: 0xB0 */
__IO uint32_t SWREG45; /**< bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps, offset: 0xB4 */
__IO uint32_t SWREG46; /**< bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values, offset: 0xB8 */
__IO uint32_t SWREG47; /**< bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values, offset: 0xBC */
} VPU_G1_H264_Type;
/* ----------------------------------------------------------------------------
-- VPU_G1_H264 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_H264_Register_Masks VPU_G1_H264 Register Masks
* @{
*/
/*! @name SWREG4 - Decoder control register 1 (picture parameters) */
/*! @{ */
#define VPU_G1_H264_SWREG4_SW_REF_FRAMES_MASK (0x1FU)
#define VPU_G1_H264_SWREG4_SW_REF_FRAMES_SHIFT (0U)
/*! SW_REF_FRAMES - H.264: num_ref_frames, maximum number of short and long term reference frames in
* decoded picture buffer VC-1: num_ref semantics
*/
#define VPU_G1_H264_SWREG4_SW_REF_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_REF_FRAMES_SHIFT)) & VPU_G1_H264_SWREG4_SW_REF_FRAMES_MASK)
#define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_MASK (0x40U)
#define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_SHIFT (6U)
/*! SW_ALT_SCAN_E - indicates alternative vertical scan method used for interlaced frames
*/
#define VPU_G1_H264_SWREG4_SW_ALT_SCAN_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_SHIFT)) & VPU_G1_H264_SWREG4_SW_ALT_SCAN_E_MASK)
#define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_MASK (0x780U)
#define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_SHIFT (7U)
/*! SW_MB_HEIGHT_OFF - The amount of meaningful vertical pixels in last MB (height offset 0 if
* exactly 16 pixels multiple picture and all the vertical pixels in last MB are meaningfull
*/
#define VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_SHIFT)) & VPU_G1_H264_SWREG4_SW_MB_HEIGHT_OFF_MASK)
#define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_MASK (0x7F800U)
#define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_SHIFT (11U)
/*! SW_PIC_MB_HEIGHT_P - Picture height in macroblocks =((height in pixels+15)/16). Picture height
* is informed as size of the (progressive) frame also for single field (of interlaced content) is
* being decoded
*/
#define VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_SHIFT)) & VPU_G1_H264_SWREG4_SW_PIC_MB_HEIGHT_P_MASK)
#define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_MASK (0x780000U)
#define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_SHIFT (19U)
/*! SW_MB_WIDTH_OFF - The amount of meaningfull horizontal pixels in last MB (width offset) 0 if
* exactly 16 pixels multiple picture and all the horizontal pixels in last MB are meaningfull
*/
#define VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_SHIFT)) & VPU_G1_H264_SWREG4_SW_MB_WIDTH_OFF_MASK)
#define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_MASK (0xFF800000U)
#define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_SHIFT (23U)
/*! SW_PIC_MB_WIDTH - Picture width in macroblocks = ((width in pixels + 15) /16)
*/
#define VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_SHIFT)) & VPU_G1_H264_SWREG4_SW_PIC_MB_WIDTH_MASK)
/*! @} */
/*! @name SWREG5 - Decoder control register 2 (stream decoding table selects) */
/*! @{ */
#define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_MASK (0x1U)
#define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_SHIFT (0U)
/*! SW_FIELDPIC_FLAG_E - Flag for streamd that field_pic_flag exists in stream
*/
#define VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_FIELDPIC_FLAG_E_MASK)
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_MASK (0x7C000U)
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_SHIFT (14U)
/*! SW_CH_QP_OFFSET2 - Chroma Qp filter offset for cr type
*/
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_SHIFT)) & VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET2_MASK)
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_MASK (0xF80000U)
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_SHIFT (19U)
/*! SW_CH_QP_OFFSET - Chroma Qp filter offset. (For H.264 this offset concerns Cb only)
*/
#define VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_SHIFT)) & VPU_G1_H264_SWREG5_SW_CH_QP_OFFSET_MASK)
#define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_MASK (0x1000000U)
#define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_SHIFT (24U)
#define VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_TYPE1_QUANT_E_MASK)
#define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_MASK (0x2000000U)
#define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_SHIFT (25U)
/*! SW_SYNC_MARKER_E - Sync markers enable
* 0b0..synch markers are not used
* 0b1..synch markers are used.
*/
#define VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_SHIFT)) & VPU_G1_H264_SWREG5_SW_SYNC_MARKER_E_MASK)
#define VPU_G1_H264_SWREG5_SW_STRM_START_BIT_MASK (0xFC000000U)
#define VPU_G1_H264_SWREG5_SW_STRM_START_BIT_SHIFT (26U)
/*! SW_STRM_START_BIT - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)
*/
#define VPU_G1_H264_SWREG5_SW_STRM_START_BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG5_SW_STRM_START_BIT_SHIFT)) & VPU_G1_H264_SWREG5_SW_STRM_START_BIT_MASK)
/*! @} */
/*! @name SWREG6 - Decoder control register 3 (stream buffer information) */
/*! @{ */
#define VPU_G1_H264_SWREG6_SW_STREAM_LEN_MASK (0xFFFFFFU)
#define VPU_G1_H264_SWREG6_SW_STREAM_LEN_SHIFT (0U)
/*! SW_STREAM_LEN - Amount of stream data bytes in input buffer. If the given buffer size is not
* enough for finishing the picture the corresponding interrupt is given and new stream buffer base
* address and stream buffer size information should be given (assosiates with sw_rlc_vlc_base).
* For VC-1/VP6 the buffer must include data for one picture/slice of the picture For
* H264/MPEG4/H263/MPEG2/MPEG1 the buffer must include at least data for one slice/VP of the picture For
* JPEG the buffer size must be a multiple of 256 bytes or the amount of data for one picture.
*/
#define VPU_G1_H264_SWREG6_SW_STREAM_LEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_STREAM_LEN_SHIFT)) & VPU_G1_H264_SWREG6_SW_STREAM_LEN_MASK)
#define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_MASK (0x1000000U)
#define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_SHIFT (24U)
/*! SW_CH_8PIX_ILEAV_E - Enable for additional chrominance data format writing where decoder writes
* chrominance in group of 8 pixels of Cb and then corresponding 8 pixels of Cr. Data is written
* to sw_dec_ch8pix_base. Cannot be used if tiled mode is enabled
*/
#define VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_SHIFT)) & VPU_G1_H264_SWREG6_SW_CH_8PIX_ILEAV_E_MASK)
#define VPU_G1_H264_SWREG6_SW_INIT_QP_MASK (0x7E000000U)
#define VPU_G1_H264_SWREG6_SW_INIT_QP_SHIFT (25U)
/*! SW_INIT_QP - Initial value for quantization parameter (picture quantizer).
*/
#define VPU_G1_H264_SWREG6_SW_INIT_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_INIT_QP_SHIFT)) & VPU_G1_H264_SWREG6_SW_INIT_QP_MASK)
#define VPU_G1_H264_SWREG6_SW_START_CODE_E_MASK (0x80000000U)
#define VPU_G1_H264_SWREG6_SW_START_CODE_E_SHIFT (31U)
/*! SW_START_CODE_E - Bit for indicating stream start code existence:
* 0b0..stream doesn't contain start codes
* 0b1..stream contains start codes
*/
#define VPU_G1_H264_SWREG6_SW_START_CODE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG6_SW_START_CODE_E_SHIFT)) & VPU_G1_H264_SWREG6_SW_START_CODE_E_MASK)
/*! @} */
/*! @name SWREG7 - Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control) */
/*! @{ */
#define VPU_G1_H264_SWREG7_SW_FRAMENUM_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG7_SW_FRAMENUM_SHIFT (0U)
/*! SW_FRAMENUM - current frame_num, used to identify short-term reference frames. Used in reference picture reordering
*/
#define VPU_G1_H264_SWREG7_SW_FRAMENUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_FRAMENUM_SHIFT)) & VPU_G1_H264_SWREG7_SW_FRAMENUM_MASK)
#define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_MASK (0x1F0000U)
#define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_SHIFT (16U)
/*! SW_FRAMENUM_LEN - H.264: Bit length of frame_num in data stream RV: frame size length. Informs
* how many bits in stream are used for frame size (HW discards these bits)
*/
#define VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_SHIFT)) & VPU_G1_H264_SWREG7_SW_FRAMENUM_LEN_MASK)
#define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_MASK (0x2000000U)
#define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_SHIFT (25U)
/*! SW_AVS_H264_H_EXT - Resolution extension to support 4k resolution for AVS/H264. Used as MSB of sw_pic_mb_height
*/
#define VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_SHIFT)) & VPU_G1_H264_SWREG7_SW_AVS_H264_H_EXT_MASK)
#define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_MASK (0xC000000U)
#define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT (26U)
/*! SW_WEIGHT_BIPR_IDC - weighted prediction specification for B slices:
* 0b00..default weighted prediction is applied to B slices
* 0b01..explicit weighted prediction shall be applied to B slices
* 0b10..implicit weighted prediction shall be applied to B slices
*/
#define VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT)) & VPU_G1_H264_SWREG7_SW_WEIGHT_BIPR_IDC_MASK)
#define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_MASK (0x10000000U)
#define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_SHIFT (28U)
/*! SW_WEIGHT_PRED_E - Weighted prediction enable for P slices
*/
#define VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_WEIGHT_PRED_E_MASK)
#define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_MASK (0x20000000U)
#define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_SHIFT (29U)
/*! SW_DIR_8X8_INFER_E - Specifies the method to use to derive luma motion vectors in B_skip,
* B_Direct_16x16 and B_direct_8x8_inference_flag (see direct_8x8_inference flag)
*/
#define VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_DIR_8X8_INFER_E_MASK)
#define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_MASK (0x40000000U)
#define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_SHIFT (30U)
/*! SW_BLACKWHITE_E
* 0b0..4:2:0 sampling format
* 0b1..4:0:0 sampling format (H264 monochroma)
*/
#define VPU_G1_H264_SWREG7_SW_BLACKWHITE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_BLACKWHITE_E_MASK)
#define VPU_G1_H264_SWREG7_SW_CABAC_E_MASK (0x80000000U)
#define VPU_G1_H264_SWREG7_SW_CABAC_E_SHIFT (31U)
/*! SW_CABAC_E - CABAC enable
*/
#define VPU_G1_H264_SWREG7_SW_CABAC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG7_SW_CABAC_E_SHIFT)) & VPU_G1_H264_SWREG7_SW_CABAC_E_MASK)
/*! @} */
/*! @name SWREG8 - Decoder control register 5 (H264, VC-1, VP6, Progressive JPEG and RV control) */
/*! @{ */
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_SHIFT (0U)
/*! SW_IDR_PIC_ID - idr_pic_id, identifies IDR (instantaneous decoding refresh) picture
*/
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_SHIFT)) & VPU_G1_H264_SWREG8_SW_IDR_PIC_ID_MASK)
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_E_MASK (0x10000U)
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_E_SHIFT (16U)
/*! SW_IDR_PIC_E - IDR (instantaneous decoding refresh) picture flag.
*/
#define VPU_G1_H264_SWREG8_SW_IDR_PIC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_IDR_PIC_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_IDR_PIC_E_MASK)
#define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_MASK (0xFFE0000U)
#define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_SHIFT (17U)
/*! SW_REFPIC_MK_LEN - Length of decoded reference picture marking bits
*/
#define VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_SHIFT)) & VPU_G1_H264_SWREG8_SW_REFPIC_MK_LEN_MASK)
#define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_MASK (0x10000000U)
#define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_SHIFT (28U)
/*! SW_8X8TRANS_FLAG_E - 8x8 transform flag enable for stream decoding
*/
#define VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_8X8TRANS_FLAG_E_MASK)
#define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_MASK (0x20000000U)
#define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_SHIFT (29U)
/*! SW_RDPIC_CNT_PRES - redundant_pic_cnt_present_flag specifies whether redundant_pic_cnt syntax elements are present in the slice header.
*/
#define VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_SHIFT)) & VPU_G1_H264_SWREG8_SW_RDPIC_CNT_PRES_MASK)
#define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_MASK (0x40000000U)
#define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_SHIFT (30U)
/*! SW_FILT_CTRL_PRES - deblocking_filter_control_present_flag indicates whether extra variables
* controlling characteristics of the deblocking filter are present in the slice header.
*/
#define VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_SHIFT)) & VPU_G1_H264_SWREG8_SW_FILT_CTRL_PRES_MASK)
#define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_MASK (0x80000000U)
#define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_SHIFT (31U)
/*! SW_CONST_INTRA_E - constrained_intra_pred_flag equal to 1 specifies that intra prediction uses
* only neighbouring intra macroblocks in prediction. When equal to 0 also neighbouring inter
* macroblocks are used in intra prediction process.
*/
#define VPU_G1_H264_SWREG8_SW_CONST_INTRA_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_SHIFT)) & VPU_G1_H264_SWREG8_SW_CONST_INTRA_E_MASK)
/*! @} */
/*! @name SWREG9 - Decoder control register 6 / base address for MB-control (RLC) / VC-1 intensity control 0/ VP6,VP7,VP8 ctrl-stream length/ RV pic slice amount */
/*! @{ */
#define VPU_G1_H264_SWREG9_SW_POC_LENGTH_MASK (0xFFU)
#define VPU_G1_H264_SWREG9_SW_POC_LENGTH_SHIFT (0U)
/*! SW_POC_LENGTH - Length of picture order count field in stream
*/
#define VPU_G1_H264_SWREG9_SW_POC_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_POC_LENGTH_SHIFT)) & VPU_G1_H264_SWREG9_SW_POC_LENGTH_MASK)
#define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_MASK (0x7C000U)
#define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_SHIFT (14U)
/*! SW_REFIDX0_ACTIVE - Specifies the maximum reference index that can be used while decoding inter
* predicted macro blocks. This is same as in previous decoders (width increased with q bit)
*/
#define VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_SHIFT)) & VPU_G1_H264_SWREG9_SW_REFIDX0_ACTIVE_MASK)
#define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_MASK (0xF80000U)
#define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_SHIFT (19U)
/*! SW_REFIDX1_ACTIVE - Specifies the maximum reference index that can be used while decoding inter predicted macro blocks.
*/
#define VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_SHIFT)) & VPU_G1_H264_SWREG9_SW_REFIDX1_ACTIVE_MASK)
#define VPU_G1_H264_SWREG9_SW_PPS_ID_MASK (0xFF000000U)
#define VPU_G1_H264_SWREG9_SW_PPS_ID_SHIFT (24U)
/*! SW_PPS_ID - pic_parameter_set_id, identifies the picture parameter set that is referred to in the slice header.
*/
#define VPU_G1_H264_SWREG9_SW_PPS_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG9_SW_PPS_ID_SHIFT)) & VPU_G1_H264_SWREG9_SW_PPS_ID_MASK)
/*! @} */
/*! @name SWREG10 - Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register */
/*! @{ */
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_MASK (0x1FU)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_SHIFT (0U)
/*! SW_PINIT_RLIST_F4 - Initial reference picture list for P forward picid 4
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F4_MASK)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_MASK (0x3E0U)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_SHIFT (5U)
/*! SW_PINIT_RLIST_F5 - Initial reference picture list for P forward picid 5
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F5_MASK)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_MASK (0x7C00U)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_SHIFT (10U)
/*! SW_PINIT_RLIST_F6 - Initial reference picture list for P forward picid 6
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F6_MASK)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_MASK (0xF8000U)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_SHIFT (15U)
/*! SW_PINIT_RLIST_F7 - Initial reference picture list for P forward picid 7
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F7_MASK)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_SHIFT (20U)
/*! SW_PINIT_RLIST_F8 - Initial reference picture list for P forward picid 8
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F8_MASK)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_SHIFT (25U)
/*! SW_PINIT_RLIST_F9 - Initial reference picture list for P forward picid 9
*/
#define VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_SHIFT)) & VPU_G1_H264_SWREG10_SW_PINIT_RLIST_F9_MASK)
/*! @} */
/*! @name SWREG11 - Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2 */
/*! @{ */
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_MASK (0x1FU)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_SHIFT (0U)
/*! SW_PINIT_RLIST_F10 - Initial reference picture list for P forward picid 10
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F10_MASK)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_MASK (0x3E0U)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_SHIFT (5U)
/*! SW_PINIT_RLIST_F11 - Initial reference picture list for P forward picid 11
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F11_MASK)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_MASK (0x7C00U)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_SHIFT (10U)
/*! SW_PINIT_RLIST_F12 - Initial reference picture list for P forward picid 12
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F12_MASK)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_MASK (0xF8000U)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_SHIFT (15U)
/*! SW_PINIT_RLIST_F13 - Initial reference picture list for P forward picid 13
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F13_MASK)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_SHIFT (20U)
/*! SW_PINIT_RLIST_F14 - Initial reference picture list for P forward picid 14
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F14_MASK)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_SHIFT (25U)
/*! SW_PINIT_RLIST_F15 - Initial reference picture list for P forward picid 15
*/
#define VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_SHIFT)) & VPU_G1_H264_SWREG11_SW_PINIT_RLIST_F15_MASK)
/*! @} */
/*! @name SWREG14 - Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture */
/*! @{ */
#define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_SHIFT (0U)
/*! SW_REFER0_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..Bottom field is closer to current picture
* 0b1..Top field is closer to current picture
*/
#define VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_TOPC_E_MASK)
#define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_SHIFT (1U)
/*! SW_REFER0_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_FIELD_E_MASK)
#define VPU_G1_H264_SWREG14_SW_REFER0_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG14_SW_REFER0_BASE_SHIFT (2U)
/*! SW_REFER0_BASE - Base address for reference picture index 0. See picture index definition from toplevel_sp
*/
#define VPU_G1_H264_SWREG14_SW_REFER0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG14_SW_REFER0_BASE_SHIFT)) & VPU_G1_H264_SWREG14_SW_REFER0_BASE_MASK)
/*! @} */
/*! @name SWREG15 - Base address for reference picture index 1 / JPEG control */
/*! @{ */
#define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_SHIFT (0U)
/*! SW_REFER1_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_TOPC_E_MASK)
#define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_SHIFT (1U)
/*! SW_REFER1_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_FIELD_E_MASK)
#define VPU_G1_H264_SWREG15_SW_REFER1_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG15_SW_REFER1_BASE_SHIFT (2U)
/*! SW_REFER1_BASE - Base address for reference picture index 1. See picture index definition from
* toplevel_sp. For VP8 this base address is used as Chrominance base address for reference
* picture 0 (if vp8 stride configuration is enabled)
*/
#define VPU_G1_H264_SWREG15_SW_REFER1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG15_SW_REFER1_BASE_SHIFT)) & VPU_G1_H264_SWREG15_SW_REFER1_BASE_MASK)
/*! @} */
/*! @name SWREG16 - Base address for reference picture index 2 / List of VLC code lengths in first JPEG AC table */
/*! @{ */
#define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_SHIFT (0U)
/*! SW_REFER2_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_TOPC_E_MASK)
#define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_SHIFT (1U)
/*! SW_REFER2_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_FIELD_E_MASK)
#define VPU_G1_H264_SWREG16_SW_REFER2_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG16_SW_REFER2_BASE_SHIFT (2U)
/*! SW_REFER2_BASE - Base address for reference picture index 2. See picture index definition from
* toplevel_sp. For VP8 video this base address is used as Golden reference chrominance base
* address (if vp8 stride configuration is enabled)
*/
#define VPU_G1_H264_SWREG16_SW_REFER2_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG16_SW_REFER2_BASE_SHIFT)) & VPU_G1_H264_SWREG16_SW_REFER2_BASE_MASK)
/*! @} */
/*! @name SWREG17 - Base address for reference picture index 3 / List of VLC code lengths in first JPEG AC table */
/*! @{ */
#define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_SHIFT (0U)
/*! SW_REFER3_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_TOPC_E_MASK)
#define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_SHIFT (1U)
/*! SW_REFER3_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_FIELD_E_MASK)
#define VPU_G1_H264_SWREG17_SW_REFER3_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG17_SW_REFER3_BASE_SHIFT (2U)
/*! SW_REFER3_BASE - Base address for reference picture index 3. See picture index definition from
* toplevel_sp. For VP8 video this base address is used as Alternate reference chrominance base
* address (if vp8 stride configuration is enabled)
*/
#define VPU_G1_H264_SWREG17_SW_REFER3_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG17_SW_REFER3_BASE_SHIFT)) & VPU_G1_H264_SWREG17_SW_REFER3_BASE_MASK)
/*! @} */
/*! @name SWREG18 - Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base */
/*! @{ */
#define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_SHIFT (0U)
/*! SW_REFER4_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_TOPC_E_MASK)
#define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_SHIFT (1U)
/*! SW_REFER4_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_FIELD_E_MASK)
#define VPU_G1_H264_SWREG18_SW_REFER4_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG18_SW_REFER4_BASE_SHIFT (2U)
/*! SW_REFER4_BASE - H264: Base address for reference picture index 4 VP6/VP7/VP8: Base address for
* Golden reference picture (corresponds picid 4)
*/
#define VPU_G1_H264_SWREG18_SW_REFER4_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG18_SW_REFER4_BASE_SHIFT)) & VPU_G1_H264_SWREG18_SW_REFER4_BASE_MASK)
/*! @} */
/*! @name SWREG19 - Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_SHIFT (0U)
/*! SW_REFER5_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_TOPC_E_MASK)
#define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_SHIFT (1U)
/*! SW_REFER5_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_FIELD_E_MASK)
#define VPU_G1_H264_SWREG19_SW_REFER5_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG19_SW_REFER5_BASE_SHIFT (2U)
/*! SW_REFER5_BASE - H.264: Base address for reference picture index 5 VP8: Base address for
* alternate reference picture (corresponds picid 5)
*/
#define VPU_G1_H264_SWREG19_SW_REFER5_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG19_SW_REFER5_BASE_SHIFT)) & VPU_G1_H264_SWREG19_SW_REFER5_BASE_MASK)
/*! @} */
/*! @name SWREG20 - Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_SHIFT (0U)
/*! SW_REFER6_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_TOPC_E_MASK)
#define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_SHIFT (1U)
/*! SW_REFER6_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_FIELD_E_MASK)
#define VPU_G1_H264_SWREG20_SW_REFER6_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG20_SW_REFER6_BASE_SHIFT (2U)
/*! SW_REFER6_BASE - Base address for reference picture index 6. For VP8 video this base address is
* used as decoder output chrominance base address (if vp8 stride configuration is enabled)
*/
#define VPU_G1_H264_SWREG20_SW_REFER6_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG20_SW_REFER6_BASE_SHIFT)) & VPU_G1_H264_SWREG20_SW_REFER6_BASE_MASK)
/*! @} */
/*! @name SWREG21 - Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_SHIFT (0U)
/*! SW_REFER7_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_TOPC_E_MASK)
#define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_SHIFT (1U)
/*! SW_REFER7_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_FIELD_E_MASK)
#define VPU_G1_H264_SWREG21_SW_REFER7_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG21_SW_REFER7_BASE_SHIFT (2U)
/*! SW_REFER7_BASE - Base address for reference picture index 7
*/
#define VPU_G1_H264_SWREG21_SW_REFER7_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG21_SW_REFER7_BASE_SHIFT)) & VPU_G1_H264_SWREG21_SW_REFER7_BASE_MASK)
/*! @} */
/*! @name SWREG22 - Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base */
/*! @{ */
#define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_SHIFT (0U)
/*! SW_REFER8_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_TOPC_E_MASK)
#define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_SHIFT (1U)
/*! SW_REFER8_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_FIELD_E_MASK)
#define VPU_G1_H264_SWREG22_SW_REFER8_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG22_SW_REFER8_BASE_SHIFT (2U)
/*! SW_REFER8_BASE - Base address for reference picture index 8
*/
#define VPU_G1_H264_SWREG22_SW_REFER8_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG22_SW_REFER8_BASE_SHIFT)) & VPU_G1_H264_SWREG22_SW_REFER8_BASE_MASK)
/*! @} */
/*! @name SWREG23 - Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base */
/*! @{ */
#define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_SHIFT (0U)
/*! SW_REFER9_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_TOPC_E_MASK)
#define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_SHIFT (1U)
/*! SW_REFER9_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_FIELD_E_MASK)
#define VPU_G1_H264_SWREG23_SW_REFER9_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG23_SW_REFER9_BASE_SHIFT (2U)
/*! SW_REFER9_BASE - Base address for reference picture index 9
*/
#define VPU_G1_H264_SWREG23_SW_REFER9_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG23_SW_REFER9_BASE_SHIFT)) & VPU_G1_H264_SWREG23_SW_REFER9_BASE_MASK)
/*! @} */
/*! @name SWREG24 - Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base */
/*! @{ */
#define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_SHIFT (0U)
/*! SW_REFER10_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_TOPC_E_MASK)
#define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_SHIFT (1U)
/*! SW_REFER10_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_FIELD_E_MASK)
#define VPU_G1_H264_SWREG24_SW_REFER10_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG24_SW_REFER10_BASE_SHIFT (2U)
/*! SW_REFER10_BASE - Base address for reference picture index 10
*/
#define VPU_G1_H264_SWREG24_SW_REFER10_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG24_SW_REFER10_BASE_SHIFT)) & VPU_G1_H264_SWREG24_SW_REFER10_BASE_MASK)
/*! @} */
/*! @name SWREG25 - Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base */
/*! @{ */
#define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_SHIFT (0U)
/*! SW_REFER11_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_TOPC_E_MASK)
#define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_SHIFT (1U)
/*! SW_REFER11_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_FIELD_E_MASK)
#define VPU_G1_H264_SWREG25_SW_REFER11_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG25_SW_REFER11_BASE_SHIFT (2U)
/*! SW_REFER11_BASE - Base address for reference picture index 11
*/
#define VPU_G1_H264_SWREG25_SW_REFER11_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG25_SW_REFER11_BASE_SHIFT)) & VPU_G1_H264_SWREG25_SW_REFER11_BASE_MASK)
/*! @} */
/*! @name SWREG26 - Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base */
/*! @{ */
#define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_SHIFT (0U)
/*! SW_REFER12_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_TOPC_E_MASK)
#define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_SHIFT (1U)
/*! SW_REFER12_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_FIELD_E_MASK)
#define VPU_G1_H264_SWREG26_SW_REFER12_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG26_SW_REFER12_BASE_SHIFT (2U)
/*! SW_REFER12_BASE - Base address for reference picture index 12
*/
#define VPU_G1_H264_SWREG26_SW_REFER12_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG26_SW_REFER12_BASE_SHIFT)) & VPU_G1_H264_SWREG26_SW_REFER12_BASE_MASK)
/*! @} */
/*! @name SWREG27 - Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table */
/*! @{ */
#define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_SHIFT (0U)
/*! SW_REFER13_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_TOPC_E_MASK)
#define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_SHIFT (1U)
/*! SW_REFER13_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_FIELD_E_MASK)
#define VPU_G1_H264_SWREG27_SW_REFER13_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG27_SW_REFER13_BASE_SHIFT (2U)
/*! SW_REFER13_BASE - Base address for reference picture index 13
*/
#define VPU_G1_H264_SWREG27_SW_REFER13_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG27_SW_REFER13_BASE_SHIFT)) & VPU_G1_H264_SWREG27_SW_REFER13_BASE_MASK)
/*! @} */
/*! @name SWREG28 - Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base */
/*! @{ */
#define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_SHIFT (0U)
/*! SW_REFER14_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_TOPC_E_MASK)
#define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_SHIFT (1U)
/*! SW_REFER14_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_FIELD_E_MASK)
#define VPU_G1_H264_SWREG28_SW_REFER14_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG28_SW_REFER14_BASE_SHIFT (2U)
/*! SW_REFER14_BASE - Base address for reference picture index 14
*/
#define VPU_G1_H264_SWREG28_SW_REFER14_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG28_SW_REFER14_BASE_SHIFT)) & VPU_G1_H264_SWREG28_SW_REFER14_BASE_MASK)
/*! @} */
/*! @name SWREG29 - Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base */
/*! @{ */
#define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_MASK (0x1U)
#define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_SHIFT (0U)
/*! SW_REFER15_TOPC_E - Which field of reference picture is closer to current picture:
* 0b0..bottom field is closer to current picture
* 0b1..top field is closer to current picture
*/
#define VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_TOPC_E_MASK)
#define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_MASK (0x2U)
#define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_SHIFT (1U)
/*! SW_REFER15_FIELD_E - Refer picture consist of single fields or frame:
* 0b0..reference picture consists of frame
* 0b1..reference picture consists of fields
*/
#define VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_FIELD_E_MASK)
#define VPU_G1_H264_SWREG29_SW_REFER15_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_H264_SWREG29_SW_REFER15_BASE_SHIFT (2U)
/*! SW_REFER15_BASE - Base address for reference picture index 15. For Multi View Coding this base address refers to inter view base address
*/
#define VPU_G1_H264_SWREG29_SW_REFER15_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG29_SW_REFER15_BASE_SHIFT)) & VPU_G1_H264_SWREG29_SW_REFER15_BASE_MASK)
/*! @} */
/*! @name SWREG30 - Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts */
/*! @{ */
#define VPU_G1_H264_SWREG30_SW_REFER0_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG30_SW_REFER0_NBR_SHIFT (0U)
/*! SW_REFER0_NBR - Number for reference picture index 0
*/
#define VPU_G1_H264_SWREG30_SW_REFER0_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG30_SW_REFER0_NBR_SHIFT)) & VPU_G1_H264_SWREG30_SW_REFER0_NBR_MASK)
#define VPU_G1_H264_SWREG30_SW_REFER1_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG30_SW_REFER1_NBR_SHIFT (16U)
/*! SW_REFER1_NBR - Number for reference picture index 1
*/
#define VPU_G1_H264_SWREG30_SW_REFER1_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG30_SW_REFER1_NBR_SHIFT)) & VPU_G1_H264_SWREG30_SW_REFER1_NBR_MASK)
/*! @} */
/*! @name SWREG31 - Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts */
/*! @{ */
#define VPU_G1_H264_SWREG31_SW_REFER2_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG31_SW_REFER2_NBR_SHIFT (0U)
/*! SW_REFER2_NBR - Number for reference picture index 2
*/
#define VPU_G1_H264_SWREG31_SW_REFER2_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG31_SW_REFER2_NBR_SHIFT)) & VPU_G1_H264_SWREG31_SW_REFER2_NBR_MASK)
#define VPU_G1_H264_SWREG31_SW_REFER3_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG31_SW_REFER3_NBR_SHIFT (16U)
/*! SW_REFER3_NBR - Number for reference picture index 3
*/
#define VPU_G1_H264_SWREG31_SW_REFER3_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG31_SW_REFER3_NBR_SHIFT)) & VPU_G1_H264_SWREG31_SW_REFER3_NBR_MASK)
/*! @} */
/*! @name SWREG32 - Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels */
/*! @{ */
#define VPU_G1_H264_SWREG32_SW_REFER4_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG32_SW_REFER4_NBR_SHIFT (0U)
/*! SW_REFER4_NBR - Number for reference picture index 4
*/
#define VPU_G1_H264_SWREG32_SW_REFER4_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG32_SW_REFER4_NBR_SHIFT)) & VPU_G1_H264_SWREG32_SW_REFER4_NBR_MASK)
#define VPU_G1_H264_SWREG32_SW_REFER5_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG32_SW_REFER5_NBR_SHIFT (16U)
/*! SW_REFER5_NBR - Number for reference picture index 5
*/
#define VPU_G1_H264_SWREG32_SW_REFER5_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG32_SW_REFER5_NBR_SHIFT)) & VPU_G1_H264_SWREG32_SW_REFER5_NBR_MASK)
/*! @} */
/*! @name SWREG33 - Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_H264_SWREG33_SW_REFER6_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG33_SW_REFER6_NBR_SHIFT (0U)
/*! SW_REFER6_NBR - Number for reference picture index 6
*/
#define VPU_G1_H264_SWREG33_SW_REFER6_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG33_SW_REFER6_NBR_SHIFT)) & VPU_G1_H264_SWREG33_SW_REFER6_NBR_MASK)
#define VPU_G1_H264_SWREG33_SW_REFER7_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG33_SW_REFER7_NBR_SHIFT (16U)
/*! SW_REFER7_NBR - Number for reference picture index 7
*/
#define VPU_G1_H264_SWREG33_SW_REFER7_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG33_SW_REFER7_NBR_SHIFT)) & VPU_G1_H264_SWREG33_SW_REFER7_NBR_MASK)
/*! @} */
/*! @name SWREG34 - Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG34_SW_REFER8_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG34_SW_REFER8_NBR_SHIFT (0U)
/*! SW_REFER8_NBR - Number for reference picture index 8
*/
#define VPU_G1_H264_SWREG34_SW_REFER8_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG34_SW_REFER8_NBR_SHIFT)) & VPU_G1_H264_SWREG34_SW_REFER8_NBR_MASK)
#define VPU_G1_H264_SWREG34_SW_REFER9_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG34_SW_REFER9_NBR_SHIFT (16U)
/*! SW_REFER9_NBR - Number for reference picture index 9
*/
#define VPU_G1_H264_SWREG34_SW_REFER9_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG34_SW_REFER9_NBR_SHIFT)) & VPU_G1_H264_SWREG34_SW_REFER9_NBR_MASK)
/*! @} */
/*! @name SWREG35 - Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG35_SW_REFER10_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG35_SW_REFER10_NBR_SHIFT (0U)
/*! SW_REFER10_NBR - Number for reference picture index 10
*/
#define VPU_G1_H264_SWREG35_SW_REFER10_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG35_SW_REFER10_NBR_SHIFT)) & VPU_G1_H264_SWREG35_SW_REFER10_NBR_MASK)
#define VPU_G1_H264_SWREG35_SW_REFER11_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG35_SW_REFER11_NBR_SHIFT (16U)
/*! SW_REFER11_NBR - Number for reference picture index 11
*/
#define VPU_G1_H264_SWREG35_SW_REFER11_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG35_SW_REFER11_NBR_SHIFT)) & VPU_G1_H264_SWREG35_SW_REFER11_NBR_MASK)
/*! @} */
/*! @name SWREG36 - Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG36_SW_REFER12_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG36_SW_REFER12_NBR_SHIFT (0U)
/*! SW_REFER12_NBR - Number for reference picture index 12
*/
#define VPU_G1_H264_SWREG36_SW_REFER12_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG36_SW_REFER12_NBR_SHIFT)) & VPU_G1_H264_SWREG36_SW_REFER12_NBR_MASK)
#define VPU_G1_H264_SWREG36_SW_REFER13_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG36_SW_REFER13_NBR_SHIFT (16U)
/*! SW_REFER13_NBR - Number for reference picture index 13
*/
#define VPU_G1_H264_SWREG36_SW_REFER13_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG36_SW_REFER13_NBR_SHIFT)) & VPU_G1_H264_SWREG36_SW_REFER13_NBR_MASK)
/*! @} */
/*! @name SWREG37 - Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG37_SW_REFER14_NBR_MASK (0xFFFFU)
#define VPU_G1_H264_SWREG37_SW_REFER14_NBR_SHIFT (0U)
/*! SW_REFER14_NBR - Number for reference picture index 14
*/
#define VPU_G1_H264_SWREG37_SW_REFER14_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG37_SW_REFER14_NBR_SHIFT)) & VPU_G1_H264_SWREG37_SW_REFER14_NBR_MASK)
#define VPU_G1_H264_SWREG37_SW_REFER15_NBR_MASK (0xFFFF0000U)
#define VPU_G1_H264_SWREG37_SW_REFER15_NBR_SHIFT (16U)
/*! SW_REFER15_NBR - Number for reference picture index 15
*/
#define VPU_G1_H264_SWREG37_SW_REFER15_NBR(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG37_SW_REFER15_NBR_SHIFT)) & VPU_G1_H264_SWREG37_SW_REFER15_NBR_MASK)
/*! @} */
/*! @name SWREG38 - Reference picture long term flags (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_MASK (0xFFFFFFFFU)
#define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_SHIFT (0U)
/*! SW_REFER_LTERM_E - Long term flag for reference picture index [31:0]. Definition: If frame is
* being decoded the bits 31:15 are used, Bit 31 for picture index 0, Bit 30 for picture index 1
* etc... IF field is being decoded the bits 31:0 are used, Bit 31 for reference picture 0 top
* field, bit 30 for reference picture 0 bottom field etc...
*/
#define VPU_G1_H264_SWREG38_SW_REFER_LTERM_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_SHIFT)) & VPU_G1_H264_SWREG38_SW_REFER_LTERM_E_MASK)
/*! @} */
/*! @name SWREG39 - Reference picture valid flags (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG39_SW_REFER_VALID_E_MASK (0xFFFFFFFFU)
#define VPU_G1_H264_SWREG39_SW_REFER_VALID_E_SHIFT (0U)
/*! SW_REFER_VALID_E - Valid flag for reference picture index [31:0].Definition: If frame is being
* decoded the bits 31:15 are used, Bit 31 for picture index 0, Bit 30 for picture index 1 etc...
* IF field is being decoded the bits 31:0 are used, Bit 31 for reference picture 0 top field,
* bit 30 for reference picture 0 bottom field etc...
*/
#define VPU_G1_H264_SWREG39_SW_REFER_VALID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG39_SW_REFER_VALID_E_SHIFT)) & VPU_G1_H264_SWREG39_SW_REFER_VALID_E_MASK)
/*! @} */
/*! @name SWREG42_H264 - bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base */
/*! @{ */
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_MASK (0x1FU)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_SHIFT (0U)
/*! SW_BINIT_RLIST_F0_H264 - Initial reference picture list for bi-direct forward picid 0
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F0_H264_MASK)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_MASK (0x3E0U)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_SHIFT (5U)
/*! SW_BINIT_RLIST_B0_H264 - Initial reference picture list for bi-direct backward picid 0
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B0_H264_MASK)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_MASK (0x7C00U)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_SHIFT (10U)
/*! SW_BINIT_RLIST_F1_H264 - Initial reference picture list for bi-direct forward picid 1
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F1_H264_MASK)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_MASK (0xF8000U)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_SHIFT (15U)
/*! SW_BINIT_RLIST_B1_H264 - Initial reference picture list for bi-direct backward picid 1
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B1_H264_MASK)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_SHIFT (20U)
/*! SW_BINIT_RLIST_F2_H264 - Initial reference picture list for bi-direct forward picid 2
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_F2_H264_MASK)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_SHIFT (25U)
/*! SW_BINIT_RLIST_B2_H264 - Initial reference picture list for bi-direct backward picid 2
*/
#define VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_SHIFT)) & VPU_G1_H264_SWREG42_H264_SW_BINIT_RLIST_B2_H264_MASK)
/*! @} */
/*! @name SWREG43_H264 - bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base */
/*! @{ */
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_MASK (0x1FU)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_SHIFT (0U)
/*! SW_BINIT_RLIST_F3_H264 - Initial reference picture list for bi-direct forward picid 3
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F3_H264_MASK)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_MASK (0x3E0U)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_SHIFT (5U)
/*! SW_BINIT_RLIST_B3_H264 - Initial reference picture list for bi-direct backward picid 3
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B3_H264_MASK)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_MASK (0x7C00U)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_SHIFT (10U)
/*! SW_BINIT_RLIST_F4_H264 - Initial reference picture list for bi-direct forward picid 4
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F4_H264_MASK)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_MASK (0xF8000U)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_SHIFT (15U)
/*! SW_BINIT_RLIST_B4_H264 - Initial reference picture list for bi-direct backward picid 4
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B4_H264_MASK)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_SHIFT (20U)
/*! SW_BINIT_RLIST_F5_H264 - Initial reference picture list for bi-direct forward picid 5
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_F5_H264_MASK)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_SHIFT (25U)
/*! SW_BINIT_RLIST_B5_H264 - Initial reference picture list for bi-direct backward picid 5
*/
#define VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_SHIFT)) & VPU_G1_H264_SWREG43_H264_SW_BINIT_RLIST_B5_H264_MASK)
/*! @} */
/*! @name SWREG44_H264 - bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_MASK (0x1FU)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_SHIFT (0U)
/*! SW_BINIT_RLIST_F6_H264 - Initial reference picture list for bi-direct forward picid 6
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F6_H264_MASK)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_MASK (0x3E0U)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_SHIFT (5U)
/*! SW_BINIT_RLIST_B6_H264 - Initial reference picture list for bi-direct backward picid 6
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B6_H264_MASK)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_MASK (0x7C00U)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_SHIFT (10U)
/*! SW_BINIT_RLIST_F7_H264 - Initial reference picture list for bi-direct forward picid 7
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F7_H264_MASK)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_MASK (0xF8000U)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_SHIFT (15U)
/*! SW_BINIT_RLIST_B7_H264 - Initial reference picture list for bi-direct backward picid 7
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B7_H264_MASK)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_SHIFT (20U)
/*! SW_BINIT_RLIST_F8_H264 - Initial reference picture list for bi-direct forward picid 8
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_F8_H264_MASK)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_SHIFT (25U)
/*! SW_BINIT_RLIST_B8_H264 - Initial reference picture list for bi-direct backward picid 8
*/
#define VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_SHIFT)) & VPU_G1_H264_SWREG44_H264_SW_BINIT_RLIST_B8_H264_MASK)
/*! @} */
/*! @name SWREG45 - bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps */
/*! @{ */
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_MASK (0x1FU)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_SHIFT (0U)
/*! SW_BINIT_RLIST_F9 - Initial reference picture list for bi-direct forward picid 9
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F9_MASK)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_MASK (0x3E0U)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_SHIFT (5U)
/*! SW_BINIT_RLIST_B9 - Initial reference picture list for bi-direct backward picid 9
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B9_MASK)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_MASK (0x7C00U)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_SHIFT (10U)
/*! SW_BINIT_RLIST_F10 - Initial reference picture list for bi-direct forward picid 10
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F10_MASK)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_MASK (0xF8000U)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_SHIFT (15U)
/*! SW_BINIT_RLIST_B10 - Initial reference picture list for bi-direct backward picid 10
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B10_MASK)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_SHIFT (20U)
/*! SW_BINIT_RLIST_F11 - Initial reference picture list for bi-direct forward picid 11
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_F11_MASK)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_SHIFT (25U)
/*! SW_BINIT_RLIST_B11 - Initial reference picture list for bi-direct backward picid 11
*/
#define VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_SHIFT)) & VPU_G1_H264_SWREG45_SW_BINIT_RLIST_B11_MASK)
/*! @} */
/*! @name SWREG46 - bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_MASK (0x1FU)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_SHIFT (0U)
/*! SW_BINIT_RLIST_F12 - Initial reference picture list for bi-direct forward picid 12
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F12_MASK)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_MASK (0x3E0U)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_SHIFT (5U)
/*! SW_BINIT_RLIST_B12 - Initial reference picture list for bi-direct backward picid 12
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B12_MASK)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_MASK (0x7C00U)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_SHIFT (10U)
/*! SW_BINIT_RLIST_F13 - Initial reference picture list for bi-direct forward picid 13
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F13_MASK)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_MASK (0xF8000U)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_SHIFT (15U)
/*! SW_BINIT_RLIST_B13 - Initial reference picture list for bi-direct backward picid 13
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B13_MASK)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_SHIFT (20U)
/*! SW_BINIT_RLIST_F14 - Initial reference picture list for bi-direct forward picid 14
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_F14_MASK)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_SHIFT (25U)
/*! SW_BINIT_RLIST_B14 - Initial reference picture list for bi-direct backward picid 14
*/
#define VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_SHIFT)) & VPU_G1_H264_SWREG46_SW_BINIT_RLIST_B14_MASK)
/*! @} */
/*! @name SWREG47 - bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_MASK (0x1FU)
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_SHIFT (0U)
/*! SW_BINIT_RLIST_F15 - Initial reference picture list for bi-direct forward picid 15
*/
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_SHIFT)) & VPU_G1_H264_SWREG47_SW_BINIT_RLIST_F15_MASK)
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_MASK (0x3E0U)
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_SHIFT (5U)
/*! SW_BINIT_RLIST_B15 - Initial reference picture list for bi-direct backward picid 15
*/
#define VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_SHIFT)) & VPU_G1_H264_SWREG47_SW_BINIT_RLIST_B15_MASK)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_MASK (0x7C00U)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_SHIFT (10U)
/*! SW_PINIT_RLIST_F0 - Initial reference picture list for P forward picid 0
*/
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F0_MASK)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_MASK (0xF8000U)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_SHIFT (15U)
/*! SW_PINIT_RLIST_F1 - Initial reference picture list for P forward picid 1
*/
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F1_MASK)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_MASK (0x1F00000U)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_SHIFT (20U)
/*! SW_PINIT_RLIST_F2 - Initial reference picture list for P forward picid 2
*/
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F2_MASK)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_MASK (0x3E000000U)
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_SHIFT (25U)
/*! SW_PINIT_RLIST_F3 - Initial reference picture list for P forward picid 3
*/
#define VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_SHIFT)) & VPU_G1_H264_SWREG47_SW_PINIT_RLIST_F3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_G1_H264_Register_Masks */
/* VPU_G1_H264 - Peripheral instance base addresses */
/** Peripheral VPU_G1_H264 base address */
#define VPU_G1_H264_BASE (0x38300000u)
/** Peripheral VPU_G1_H264 base pointer */
#define VPU_G1_H264 ((VPU_G1_H264_Type *)VPU_G1_H264_BASE)
/** Array initializer of VPU_G1_H264 peripheral base addresses */
#define VPU_G1_H264_BASE_ADDRS { VPU_G1_H264_BASE }
/** Array initializer of VPU_G1_H264 peripheral base pointers */
#define VPU_G1_H264_BASE_PTRS { VPU_G1_H264 }
/*!
* @}
*/ /* end of group VPU_G1_H264_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_G1_VP7_VP8 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_VP7_VP8_Peripheral_Access_Layer VPU_G1_VP7_VP8 Peripheral Access Layer
* @{
*/
/** VPU_G1_VP7_VP8 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t SWREG4_JPEG_VP7_VP8; /**< Decoder control register 1 (picture parameters), offset: 0x10 */
__IO uint32_t SWREG5_VP7_VP8; /**< Decoder control register 2 (stream decoding table selects), offset: 0x14 */
__IO uint32_t SWREG6_VP7_VP8; /**< Decoder control register 3 (stream buffer information), offset: 0x18 */
__IO uint32_t SWREG7_VP7_VP8; /**< Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control), offset: 0x1C */
uint8_t RESERVED_1[8];
__IO uint32_t SWREG10_VP7_VP8; /**< Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register, offset: 0x28 */
__IO uint32_t SWREG11_VP7_VP8; /**< Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2, offset: 0x2C */
uint8_t RESERVED_2[8];
__IO uint32_t SWREG14_VP7_VP8; /**< Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture, offset: 0x38 */
__IO uint32_t SWREG15_VP7_VP8; /**< Base address for reference picture index 1 / JPEG control, offset: 0x3C */
uint8_t RESERVED_3[8];
__IO uint32_t SWREG18_VP7_VP8; /**< Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base, offset: 0x48 */
uint8_t RESERVED_4[12];
__IO uint32_t SWREG22_VP7_VP8; /**< Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base, offset: 0x58 */
__IO uint32_t SWREG23_VP7_VP8; /**< Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base, offset: 0x5C */
__IO uint32_t SWREG24_VP7_VP8; /**< Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base, offset: 0x60 */
__IO uint32_t SWREG25_VP7_VP8; /**< Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base, offset: 0x64 */
__IO uint32_t SWREG26_VP7_VP8; /**< Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base, offset: 0x68 */
__IO uint32_t SWREG27_VC1; /**< Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table, offset: 0x6C */
__IO uint32_t SWREG28_VP7_VP8; /**< Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base, offset: 0x70 */
__IO uint32_t SWREG29_VP7_VP8; /**< Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base, offset: 0x74 */
__IO uint32_t SWREG30_VP7_VP8; /**< Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts, offset: 0x78 */
__IO uint32_t SWREG31_VP7_VP8; /**< Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts, offset: 0x7C */
__IO uint32_t SWREG32_VP7_VP8; /**< Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels, offset: 0x80 */
__IO uint32_t SWREG33_VP7_VP8; /**< Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values, offset: 0x84 */
__IO uint32_t SWREG34_H263; /**< Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps, offset: 0x88 */
__IO uint32_t SWREG35_VC1; /**< Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x8C */
__IO uint32_t SWREG36_VC1; /**< Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps, offset: 0x90 */
__IO uint32_t SWREG37_VP6_VP7_VP8; /**< Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps, offset: 0x94 */
__IO uint32_t SWREG38_VP6_VP7_VP8; /**< Reference picture long term flags (H264 VLC) / VPx prediction filter taps, offset: 0x98 */
__IO uint32_t SWREG39_VP6_VP7_VP8; /**< Reference picture valid flags (H264 VLC) / VPx prediction filter taps, offset: 0x9C */
uint8_t RESERVED_5[8];
__IO uint32_t SWREG42_VP6; /**< bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base, offset: 0xA8 */
__IO uint32_t SWREG43_VP7_VP8; /**< bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base, offset: 0xAC */
__IO uint32_t SWREG44_VP7_VP8; /**< bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps, offset: 0xB0 */
__IO uint32_t SWREG45_VP7_VP8; /**< bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps, offset: 0xB4 */
__IO uint32_t SWREG46_VP7_VP8; /**< bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values, offset: 0xB8 */
__IO uint32_t SWREG47_VP7_VP8; /**< bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values, offset: 0xBC */
} VPU_G1_VP7_VP8_Type;
/* ----------------------------------------------------------------------------
-- VPU_G1_VP7_VP8 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_VP7_VP8_Register_Masks VPU_G1_VP7_VP8 Register Masks
* @{
*/
/*! @name SWREG4_JPEG_VP7_VP8 - Decoder control register 1 (picture parameters) */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_MASK (0x7U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_SHIFT (0U)
/*! SW_PIC_MB_H_EXT_JPEG_VP7_VP6 - Picture mb height extension. If sw_pic_mb_height_p does not fit
* to 9 bits then these bits are used to increase the range upto 11 bits (used as 3 msb). For 4k
* video one bit is used for extension (bit 0)
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_H_EXT_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_MASK (0x38U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_SHIFT (3U)
/*! SW_PIC_MB_W_EXT_JPEG_VP7_VP6 - Picture mb width extension. If sw_pic_mb_width does not fit to 9
* bits then these bits are used to increase the range upto 11 bits (used as 3 msb)
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_W_EXT_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_MASK (0x40U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_SHIFT (6U)
/*! SW_ALT_SCAN_E_JPEG_VP7_VP6 - indicates alternative vertical scan method used for interlaced frames
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_ALT_SCAN_E_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_MASK (0x780U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_SHIFT (7U)
/*! SW_MB_HEIGHT_OFF_JPEG_VP7_VP6 - The amount of meaningful vertical pixels in last MB (height
* offset 0 if exactly 16 pixels multiple picture and all the vertical pixels in last MB are
* meaningfull
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_HEIGHT_OFF_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_MASK (0x7F800U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_SHIFT (11U)
/*! SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6 - Picture height in macroblocks =((height in pixels+15)/16).
* Picture height is informed as size of the (progressive) frame also for single field (of
* interlaced content) is being decoded
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_HEIGHT_P_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_MASK (0x780000U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_SHIFT (19U)
/*! SW_MB_WIDTH_OFF_JPEG_VP7_VP6 - The amount of meaningfull horizontal pixels in last MB (width
* offset) 0 if exactly 16 pixels multiple picture and all the horizontal pixels in last MB are
* meaningfull
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_MB_WIDTH_OFF_JPEG_VP7_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_MASK (0xFF800000U)
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_SHIFT (23U)
/*! SW_PIC_MB_WIDTH_JPEG_VP7_VP6 - Picture width in macroblocks = ((width in pixels + 15) /16)
*/
#define VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG4_JPEG_VP7_VP8_SW_PIC_MB_WIDTH_JPEG_VP7_VP6_MASK)
/*! @} */
/*! @name SWREG5_VP7_VP8 - Decoder control register 2 (stream decoding table selects) */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_MASK (0xFFU)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_SHIFT (0U)
/*! SW_BOOLEAN_RANGE_VP7_VP8 - Initial range for boolean dec
*/
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_RANGE_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_MASK (0xFF00U)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_SHIFT (8U)
/*! SW_BOOLEAN_VALUE_VP7_VP8 - Initial value for boolean dec
*/
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_BOOLEAN_VALUE_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_MASK (0xFC0000U)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_SHIFT (18U)
/*! SW_STRM1_START_BIT_VP7_VP8 - Start bit for ctrl-stream (needed if multistream is enabled, assosiates with sw_bitpl_ctrl_base)
*/
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM1_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_MASK (0xFC000000U)
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_SHIFT (26U)
/*! SW_STRM_START_BIT_VP7_VP8 - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)
*/
#define VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG5_VP7_VP8_SW_STRM_START_BIT_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG6_VP7_VP8 - Decoder control register 3 (stream buffer information) */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_MASK (0xFFFFFFU)
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_SHIFT (0U)
/*! SW_STREAM_LEN_VP7_VP8 - Amount of stream data bytes in input buffer. If the given buffer size is
* not enough for finishing the picture the corresponding interrupt is given and new stream
* buffer base address and stream buffer size information should be given (assosiates with
* sw_rlc_vlc_base). For VC-1/VP6 the buffer must include data for one picture/slice of the picture For
* H264/MPEG4/H263/MPEG2/MPEG1 the buffer must include at least data for one slice/VP of the picture
* For JPEG the buffer size must be a multiple of 256 bytes or the amount of data for one
* picture.
*/
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_MASK (0xFF000000U)
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_SHIFT (24U)
/*! SW_STREAM_LEN_EXT_VP7_VP8 - Extended stream length for WEBP/VP8
*/
#define VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG6_VP7_VP8_SW_STREAM_LEN_EXT_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG7_VP7_VP8 - Decoder control register 4 (H264, VC-1, VP6 and progressive JPEG control) */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_MASK (0x20U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_SHIFT (5U)
/*! SW_VP7_VERSION_VP7_VP8 - VP7 version information to streamd:
* 0b0..VP7 version 7.0
* 0b1..VP7 version 7.1 or better
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_VP7_VERSION_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_MASK (0x1C0U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_SHIFT (6U)
/*! SW_INIT_DC_MATCH1_VP7_VP8 - Initial DC prediction mach count 1. After HW has decoded a picture
* HW returns the final match count1 information which is read by SW
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_MASK (0xE00U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_SHIFT (9U)
/*! SW_INIT_DC_MATCH0_VP7_VP8 - Initial DC prediction mach count 0. After HW has decoded a picture
* HW returns the final match count0 information which is read by SW
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_INIT_DC_MATCH0_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_MASK (0x1000U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_SHIFT (12U)
/*! SW_BILIN_MC_E_VP7_VP8 - Bilinear motion compensation enable:
* 0b0..Bicubic interpolation used
* 0b1..Bilinear interpolation used
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_BILIN_MC_E_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_MASK (0x2000U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_SHIFT (13U)
/*! SW_CH_MV_RES_VP7_VP8 - VP7/VP8 Chrominance motion vector resolution:
* 0b0..Full pixel
* 0b1..1/8 pixel
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_CH_MV_RES_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_MASK (0x3F00000U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_SHIFT (20U)
/*! SW_DCT2_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 2
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT2_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_MASK (0xFC000000U)
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_SHIFT (26U)
/*! SW_DCT1_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 1
*/
#define VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG7_VP7_VP8_SW_DCT1_START_BIT_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG10_VP7_VP8 - Base address for differential motion vector base address (RLC-mode) /H264 P initial fwd ref pic list register (4-9)/ VC-1 intensity control 1/ VP7 and VP8 segmentation base register */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_MASK (0x1U)
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_SHIFT (0U)
/*! SW_SEGMENT_E_VP7_VP8 - Segmentation enable: '0': segmentation is not enabled '1': segmentation is enabled (sw_segment_upd_e value is used)
*/
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_E_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_MASK (0x2U)
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_SHIFT (1U)
/*! SW_SEGMENT_UPD_E_VP7_VP8 - VP7/VP8 Segmentation map update enable: '0': segmentation values are
* read from external memory (from segment_base) '1': segmentation update is included in stream
*/
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_UPD_E_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_SHIFT (2U)
/*! SW_SEGMENT_BASE_VP7_VP8 - VP7/VP8: base address for segmentation map values
*/
#define VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG10_VP7_VP8_SW_SEGMENT_BASE_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG11_VP7_VP8 - Decoder control register 7 (VLC) / base address for H.264 intra prediction 4x4 / base address for MPEG-4 DC component (RLC) / H264 P initial fwd ref pic list register (10-15) / VC-1 intensity control 2 */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_MASK (0x3FU)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_SHIFT (0U)
/*! SW_DCT7_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 7
*/
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT7_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_MASK (0xFC0U)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_SHIFT (6U)
/*! SW_DCT6_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 6
*/
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT6_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_MASK (0x3F000U)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_SHIFT (12U)
/*! SW_DCT5_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 5
*/
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT5_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_MASK (0xFC0000U)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_SHIFT (18U)
/*! SW_DCT4_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 4
*/
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT4_START_BIT_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_MASK (0x3F000000U)
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_SHIFT (24U)
/*! SW_DCT3_START_BIT_VP7_VP8 - Start bit for VP7/VP8 DCT stream partition index 3
*/
#define VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG11_VP7_VP8_SW_DCT3_START_BIT_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG14_VP7_VP8 - Base address for reference picture index 0 / base address for JPEG decoder output chrominance picture */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_SHIFT (2U)
/*! SW_JPG_CH_OUT_BASE_VP7_VP8 - Base address for decoder output chrominance picture. Used in JPEG
* and web-p picture mode (not needed if decoder output is not written)
*/
#define VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG14_VP7_VP8_SW_JPG_CH_OUT_BASE_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG15_VP7_VP8 - Base address for reference picture index 1 / JPEG control */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_MASK (0xFFU)
#define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_SHIFT (0U)
/*! SW_JPEG_SLICE_H_VP7_VP8 - JPEG/Web-p. Height of the slice (multiple of 16 pixels) that HW
* decodes before interrupt. When slice is decoded HW will rise an interrupt and reset external
* addresses back to base address. Note, value 0 disables slice mode. Slice mode must be used if picture
* size is more than 16 Mpixels. However for bigger than 4096 MBs the slice mode usage is
* recommended.
*/
#define VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG15_VP7_VP8_SW_JPEG_SLICE_H_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG18_VP7_VP8 - Base address for reference picture index 4 / VC1 control / MPEG4 MVD control/ List of VLC code lengths in first JPEG AC table / VC-1 intensity control 4 / VP6/VP7, VP8 Golden refer picture base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_MASK (0x1U)
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_SHIFT (0U)
/*! SW_GREF_SIGN_BIAS_VP7_VP8 - Reference picture sign bias for Golden reference frame
*/
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_GREF_SIGN_BIAS_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_SHIFT (2U)
/*! SW_REFER4_BASE_VP7_VP8 - H264: Base address for reference picture index 4 VP6/VP7/VP8: Base
* address for Golden reference picture (corresponds picid 4)
*/
#define VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG18_VP7_VP8_SW_REFER4_BASE_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG22_VP7_VP8 - Base address for reference picture index 8 / List of VLC code lengths in second JPEG AC table / VP6 scan maps / VP7,VP8 DCT stream 1 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_SHIFT (2U)
/*! SW_DCT_STRM1_BASE - Base address for VP7/VP8 DCT stream MB row 1,2n+1
*/
#define VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG22_VP7_VP8_SW_DCT_STRM1_BASE_MASK)
/*! @} */
/*! @name SWREG23_VP7_VP8 - Base address for reference picture index 9 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 2 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_SHIFT (2U)
/*! SW_DCT_STRM2_BASE - Base address for VP7/VP8 DCT stream MB row 2,2n+2
*/
#define VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG23_VP7_VP8_SW_DCT_STRM2_BASE_MASK)
/*! @} */
/*! @name SWREG24_VP7_VP8 - Base address for reference picture index 10 / List of VLC code lengths in first JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 3 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_SHIFT (2U)
/*! SW_DCT_STRM3_BASE - Base address for VP7/VP8 DCT stream MB row 3,2n+3
*/
#define VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG24_VP7_VP8_SW_DCT_STRM3_BASE_MASK)
/*! @} */
/*! @name SWREG25_VP7_VP8 - Base address for reference picture index 11 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 4 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_SHIFT (2U)
/*! SW_DCT_STRM4_BASE - Base address for VP7/VP8 DCT stream MB row 4,2n+4
*/
#define VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG25_VP7_VP8_SW_DCT_STRM4_BASE_MASK)
/*! @} */
/*! @name SWREG26_VP7_VP8 - Base address for reference picture index 12 / List of VLC code lengths in second JPEG DC table / VP6 scan maps / VP7,VP8 DCT stream 5 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_SHIFT (2U)
/*! SW_DCT_STRM5_BASE - Base address for VP7/VP8 DCT stream MB row 5,2n+5
*/
#define VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG26_VP7_VP8_SW_DCT_STRM5_BASE_MASK)
/*! @} */
/*! @name SWREG27_VC1 - Base address for reference picture index 13 / VC-1 bitpl mbctrl or VP6,VP7,VP8 ctrl stream base /Progressive JPEG DC table */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_SHIFT (2U)
/*! SW_BITPL_CTRL_BASE - VC-1: Base address for bitplane mb control VP6/VP7/VP8 : Base address for
* ctrl data stream. Used if multistream is enabled
*/
#define VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG27_VC1_SW_BITPL_CTRL_BASE_MASK)
/*! @} */
/*! @name SWREG28_VP7_VP8 - Base address for reference picture index 14 / VP6 scan maps /Progressive JPEG DC table / VP7,VP8 DCT stream 6 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_SHIFT (2U)
/*! SW_DCT_STRM6_BASE - Base address for VP7/VP8 DCT stream MB row 6,2n+6
*/
#define VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG28_VP7_VP8_SW_DCT_STRM6_BASE_MASK)
/*! @} */
/*! @name SWREG29_VP7_VP8 - Base address for reference picture index 15 / VP6 scan maps / VP7,VP8 DCT stream 7 base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_SHIFT (2U)
/*! SW_DCT_STRM7_BASE - Base address for VP7/VP8 DCT stream MB row 7,2n+7
*/
#define VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_SHIFT)) & VPU_G1_VP7_VP8_SWREG29_VP7_VP8_SW_DCT_STRM7_BASE_MASK)
/*! @} */
/*! @name SWREG30_VP7_VP8 - Reference picture numbers for index 0 and 1 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter mb level adjusts */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_MASK (0x7FU)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_SHIFT (0U)
/*! SW_FILT_MB_ADJ_3 - VP7/VP8 filter level adjustment for MB type 3
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_3_MASK)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_MASK (0x3F80U)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_SHIFT (7U)
/*! SW_FILT_MB_ADJ_2 - VP7/VP8 filter level adjustment for MB type 2
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_2_MASK)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_MASK (0x1FC000U)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_SHIFT (14U)
/*! SW_FILT_MB_ADJ_1 - VP7/VP8 filter level adjustment for MB type 1
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_1_MASK)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_MASK (0xFE00000U)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_SHIFT (21U)
/*! SW_FILT_MB_ADJ_0 - VP7/VP8 filter level adjustment for MB type 0
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_MB_ADJ_0_MASK)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_MASK (0x70000000U)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_SHIFT (28U)
/*! SW_FILT_SHARPNESS - VP7/VP8 loop filter sharpness
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_SHARPNESS_MASK)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_MASK (0x80000000U)
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_SHIFT (31U)
/*! SW_FILT_TYPE - VP7/VP8 loop filter type
*/
#define VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_SHIFT)) & VPU_G1_VP7_VP8_SWREG30_VP7_VP8_SW_FILT_TYPE_MASK)
/*! @} */
/*! @name SWREG31_VP7_VP8 - Reference picture numbers for index 2 and 3 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter ref pic level adjusts */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_MASK (0x7FU)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_SHIFT (0U)
/*! SW_FILT_REF_ADJ_3 - VP7/VP8 filter level adjustment for reference frame type 3
*/
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_3_MASK)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_MASK (0x3F80U)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_SHIFT (7U)
/*! SW_FILT_REF_ADJ_2 - VP7/VP8 filter level adjustment for reference frame type 2
*/
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_2_MASK)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_MASK (0x1FC000U)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_SHIFT (14U)
/*! SW_FILT_REF_ADJ_1 - VP7/VP8 filter level adjustment for reference frame type 1
*/
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_1_MASK)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_MASK (0xFE00000U)
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_SHIFT (21U)
/*! SW_FILT_REF_ADJ_0 - VP7/VP8 filter level adjustment for reference frame type 0
*/
#define VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG31_VP7_VP8_SW_FILT_REF_ADJ_0_MASK)
/*! @} */
/*! @name SWREG32_VP7_VP8 - Reference picture numbers for index 4 and 5 (H264 VLC) / VP6 scan maps / VP7,VP8 loop filter levels */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_MASK (0x3FU)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_SHIFT (0U)
/*! SW_FILT_LEVEL_3 - VP7/VP8 filter level value for reference frame type 3
*/
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_3_MASK)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_MASK (0xFC0U)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_SHIFT (6U)
/*! SW_FILT_LEVEL_2 - VP7/VP8 filter level value for reference frame type 2
*/
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_2_MASK)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_MASK (0x3F000U)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_SHIFT (12U)
/*! SW_FILT_LEVEL_1 - VP7/VP8 filter level value for reference frame type 1
*/
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_1_MASK)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_MASK (0xFC0000U)
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_SHIFT (18U)
/*! SW_FILT_LEVEL_0 - VP7/VP8 filter level value for reference frame type 0
*/
#define VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG32_VP7_VP8_SW_FILT_LEVEL_0_MASK)
/*! @} */
/*! @name SWREG33_VP7_VP8 - Reference picture numbers for index 6 and 7 (H264 VLC) / VP6 scan maps / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_MASK (0x7FFU)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_SHIFT (0U)
/*! SW_QUANT_1 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)
*/
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_1_MASK)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_MASK (0x3FF800U)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_SHIFT (11U)
/*! SW_QUANT_0 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)
*/
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_0_MASK)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_MASK (0x7C00000U)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_SHIFT (22U)
/*! SW_QUANT_DELTA_1 - VP8 quantisizer delta 1
*/
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_1_MASK)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_MASK (0xF8000000U)
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_SHIFT (27U)
/*! SW_QUANT_DELTA_0 - VP8 quantisizer delta 0
*/
#define VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG33_VP7_VP8_SW_QUANT_DELTA_0_MASK)
/*! @} */
/*! @name SWREG34_H263 - Reference picture numbers for index 8 and 9 (H264 VLC) / MPEG4, VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_SHIFT (2U)
/*! SW_PRED_BC_TAP_1_1 - Prediction filter set 1, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_1_MASK)
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_SHIFT (12U)
/*! SW_PRED_BC_TAP_1_0 - Prediction filter set 1, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_1_0_MASK)
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_SHIFT (22U)
/*! SW_PRED_BC_TAP_0_3 - Prediction filter set 0, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG34_H263_SW_PRED_BC_TAP_0_3_MASK)
/*! @} */
/*! @name SWREG35_VC1 - Reference picture numbers for index 10 and 11 (H264 VLC) / VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_SHIFT (2U)
/*! SW_PRED_BC_TAP_2_0 - Prediction filter set 2, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_2_0_MASK)
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_SHIFT (12U)
/*! SW_PRED_BC_TAP_1_3 - Prediction filter set 1, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_3_MASK)
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_SHIFT (22U)
/*! SW_PRED_BC_TAP_1_2 - Prediction filter set 1, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG35_VC1_SW_PRED_BC_TAP_1_2_MASK)
/*! @} */
/*! @name SWREG36_VC1 - Reference picture numbers for index 12 and 13 (H264 VLC) / VC1, VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_SHIFT (2U)
/*! SW_PRED_BC_TAP_2_3 - Prediction filter set 2, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_3_MASK)
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_SHIFT (12U)
/*! SW_PRED_BC_TAP_2_2 - Prediction filter set 2, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_2_MASK)
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_SHIFT (22U)
/*! SW_PRED_BC_TAP_2_1 - Prediction filter set 2, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG36_VC1_SW_PRED_BC_TAP_2_1_MASK)
/*! @} */
/*! @name SWREG37_VP6_VP7_VP8 - Reference picture numbers for index 14 and 15 (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_SHIFT (2U)
/*! SW_PRED_BC_TAP_3_2 - Prediction filter set 3, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_2_MASK)
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_SHIFT (12U)
/*! SW_PRED_BC_TAP_3_1 - Prediction filter set 3, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_1_MASK)
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_SHIFT (22U)
/*! SW_PRED_BC_TAP_3_0 - Prediction filter set 3, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG37_VP6_VP7_VP8_SW_PRED_BC_TAP_3_0_MASK)
/*! @} */
/*! @name SWREG38_VP6_VP7_VP8 - Reference picture long term flags (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_SHIFT (2U)
/*! SW_PRED_BC_TAP_4_1 - Prediction filter set 4, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_1_MASK)
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_SHIFT (12U)
/*! SW_PRED_BC_TAP_4_0 - Prediction filter set 4, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_4_0_MASK)
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_SHIFT (22U)
/*! SW_PRED_BC_TAP_3_3 - Prediction filter set 3, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG38_VP6_VP7_VP8_SW_PRED_BC_TAP_3_3_MASK)
/*! @} */
/*! @name SWREG39_VP6_VP7_VP8 - Reference picture valid flags (H264 VLC) / VPx prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_SHIFT (2U)
/*! SW_PRED_BC_TAP_5_0 - Prediction filter set 5, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_5_0_MASK)
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_SHIFT (12U)
/*! SW_PRED_BC_TAP_4_3 - Prediction filter set 4, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_3_MASK)
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_SHIFT (22U)
/*! SW_PRED_BC_TAP_4_2 - Prediction filter set 4, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_SHIFT)) & VPU_G1_VP7_VP8_SWREG39_VP6_VP7_VP8_SW_PRED_BC_TAP_4_2_MASK)
/*! @} */
/*! @name SWREG42_VP6 - bi_dir initial ref pic list register (0-2) / VP6 prediction filter taps / Progressive JPEG Cb ACDC coefficient base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_SHIFT (2U)
/*! SW_PRED_BC_TAP_5_3_VP6 - Prediction filter set 5, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_3_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_SHIFT (12U)
/*! SW_PRED_BC_TAP_5_2_VP6 - Prediction filter set 5, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_2_VP6_MASK)
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_SHIFT (22U)
/*! SW_PRED_BC_TAP_5_1_VP6 - Prediction filter set 5, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_SHIFT)) & VPU_G1_VP7_VP8_SWREG42_VP6_SW_PRED_BC_TAP_5_1_VP6_MASK)
/*! @} */
/*! @name SWREG43_VP7_VP8 - bi-dir initial ref pic list register (3-5) / VP6 prediction filter taps / Progressive JPEG Cr ACDC coefficient base */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_SHIFT (2U)
/*! SW_PRED_BC_TAP_6_2_VP7_VP8 - Prediction filter set 6, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_2_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_SHIFT (12U)
/*! SW_PRED_BC_TAP_6_1_VP7_VP8 - Prediction filter set 6, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_SHIFT (22U)
/*! SW_PRED_BC_TAP_6_0_VP7_VP8 - Prediction filter set 6, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG43_VP7_VP8_SW_PRED_BC_TAP_6_0_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG44_VP7_VP8 - bi-dir initial ref pic list register (6-8) / VP6 prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_MASK (0xFFCU)
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_SHIFT (2U)
/*! SW_PRED_BC_TAP_7_1_VP7_VP8 - Prediction filter set 7, tap 1
*/
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_SHIFT (12U)
/*! SW_PRED_BC_TAP_7_0_VP7_VP8 - Prediction filter set 7, tap 0
*/
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_7_0_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_SHIFT (22U)
/*! SW_PRED_BC_TAP_6_3_VP7_VP8 - Prediction filter set 6, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG44_VP7_VP8_SW_PRED_BC_TAP_6_3_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG45_VP7_VP8 - bi-dir initial ref pic list register (9-11) / VP6 prediction filter taps */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_MASK (0x3U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_SHIFT (0U)
/*! SW_PRED_TAP_6_4_VP7_VP8 - Additional Prediction filter tap 4 for set 6
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_4_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_MASK (0xCU)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_SHIFT (2U)
/*! SW_PRED_TAP_6_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 6
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_6_M1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_MASK (0x30U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_SHIFT (4U)
/*! SW_PRED_TAP_4_4_VP7_VP8 - Additional Prediction filter tap 4 for set 4
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_4_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_MASK (0xC0U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_SHIFT (6U)
/*! SW_PRED_TAP_4_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 4
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_4_M1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_MASK (0x300U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_SHIFT (8U)
/*! SW_PRED_TAP_2_4_VP7_VP8 - Additional Prediction filter tap 4 for set 2
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_4_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_MASK (0xC00U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_SHIFT (10U)
/*! SW_PRED_TAP_2_M1_VP7_VP8 - Additional Prediction filter tap -1 for set 2
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_TAP_2_M1_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_MASK (0x3FF000U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_SHIFT (12U)
/*! SW_PRED_BC_TAP_7_3_VP7_VP8 - Prediction filter set 7, tap 3
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_3_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_MASK (0xFFC00000U)
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_SHIFT (22U)
/*! SW_PRED_BC_TAP_7_2_VP7_VP8 - Prediction filter set 7, tap 2
*/
#define VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG45_VP7_VP8_SW_PRED_BC_TAP_7_2_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG46_VP7_VP8 - bi-dir initial ref pic list register (12-14) / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_MASK (0x7FFU)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_SHIFT (0U)
/*! SW_QUANT_3_VP7_VP8 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)
*/
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_3_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_MASK (0x3FF800U)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_SHIFT (11U)
/*! SW_QUANT_2_VP7_VP8 - VP7: QP (11 bit) VP8: quantisizer value for LUT (7 bit)
*/
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_2_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_MASK (0x7C00000U)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_SHIFT (22U)
/*! SW_QUANT_DELTA_3_VP7_VP8 - VP8 quantisizer delta 3
*/
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_3_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_MASK (0xF8000000U)
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_SHIFT (27U)
/*! SW_QUANT_DELTA_2_VP7_VP8 - VP8 quantisizer delta 2
*/
#define VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG46_VP7_VP8_SW_QUANT_DELTA_2_VP7_VP8_MASK)
/*! @} */
/*! @name SWREG47_VP7_VP8 - bi-dir and P fwd initial ref pic list register (15 and P 0-3) / VP7,VP8 quantization values */
/*! @{ */
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_MASK (0x7FFU)
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_SHIFT (0U)
/*! SW_QUANT_5_VP7_VP8 - VP7 QP (11 bit)
*/
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_5_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_MASK (0x3FF800U)
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_SHIFT (11U)
/*! SW_QUANT_4_VP7_VP8 - VP7 QP (11 bit)
*/
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_4_VP7_VP8_MASK)
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_MASK (0xF8000000U)
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_SHIFT (27U)
/*! SW_QUANT_DELTA_4_VP7_VP8 - VP8 quantisizer delta 4
*/
#define VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_SHIFT)) & VPU_G1_VP7_VP8_SWREG47_VP7_VP8_SW_QUANT_DELTA_4_VP7_VP8_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_G1_VP7_VP8_Register_Masks */
/* VPU_G1_VP7_VP8 - Peripheral instance base addresses */
/** Peripheral VPU_G1_VP7_VP8 base address */
#define VPU_G1_VP7_VP8_BASE (0x38300000u)
/** Peripheral VPU_G1_VP7_VP8 base pointer */
#define VPU_G1_VP7_VP8 ((VPU_G1_VP7_VP8_Type *)VPU_G1_VP7_VP8_BASE)
/** Array initializer of VPU_G1_VP7_VP8 peripheral base addresses */
#define VPU_G1_VP7_VP8_BASE_ADDRS { VPU_G1_VP7_VP8_BASE }
/** Array initializer of VPU_G1_VP7_VP8 peripheral base pointers */
#define VPU_G1_VP7_VP8_BASE_PTRS { VPU_G1_VP7_VP8 }
/*!
* @}
*/ /* end of group VPU_G1_VP7_VP8_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_G1_VP8 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_VP8_Peripheral_Access_Layer VPU_G1_VP8 Peripheral Access Layer
* @{
*/
/** VPU_G1_VP8 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[76];
__IO uint32_t SWREG19_VP8; /**< Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps, offset: 0x4C */
__IO uint32_t SWREG20_VP8; /**< Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x50 */
__IO uint32_t SWREG21_VP8; /**< Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps, offset: 0x54 */
} VPU_G1_VP8_Type;
/* ----------------------------------------------------------------------------
-- VPU_G1_VP8 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G1_VP8_Register_Masks VPU_G1_VP8 Register Masks
* @{
*/
/*! @name SWREG19_VP8 - Base address for reference picture index 5 / MPEG4 TRB/TRD delta 0 / VC-1 intensity control 3 List of VLC code lengths in first/second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_MASK (0x1U)
#define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_SHIFT (0U)
/*! SW_AREF_SIGN_BIAS - VP8 only: Reference picture sign bias for Alternate reference frame
*/
#define VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_SHIFT)) & VPU_G1_VP8_SWREG19_VP8_SW_AREF_SIGN_BIAS_MASK)
#define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_MASK (0xFFFFFFFCU)
#define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_SHIFT (2U)
/*! SW_REFER5_BASE_VP8 - H.264: Base address for reference picture index 5 VP8: Base address for
* alternate reference picture (corresponds picid 5)
*/
#define VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_SHIFT)) & VPU_G1_VP8_SWREG19_VP8_SW_REFER5_BASE_VP8_MASK)
/*! @} */
/*! @name SWREG20_VP8 - Base address for reference picture index 6 / / MPEG4 TRB/TRD delta -1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_MASK (0x1U)
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_SHIFT (0U)
/*! SW_VP8_CH_BASE_E - VP8 separate chrominance enable:
* 0b0..Write/Read chrominance data from internal offset after the luminance data
* 0b1..Write/Read chrominance data from separate base addresses given by SW
*/
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_CH_BASE_E_MASK)
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_MASK (0x2U)
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_SHIFT (1U)
/*! SW_VP8_STRIDE_E - VP8 stride enable. Can be set high only if HW configuration supports strides.
* Y and C strides are used instead of picture width. Separate chrominance base addresses are
* used instead of internal chrominance offsets.
* 0b0..Not enabled
* 0b1..Enabled
*/
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_STRIDE_E_MASK)
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_MASK (0xFFFFFFFCU)
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_SHIFT (2U)
/*! SW_VP8_DEC_CH_BASE - VP8 video base address for decoder output chrominance data (if vp8 stride configuration is enabled)
*/
#define VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_SHIFT)) & VPU_G1_VP8_SWREG20_VP8_SW_VP8_DEC_CH_BASE_MASK)
/*! @} */
/*! @name SWREG21_VP8 - Base address for reference picture index 7 / MPEG4 TRB/TRD delta 1 / List of VLC code lengths in second JPEG AC table / VP6/VP7 scan maps */
/*! @{ */
#define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_MASK (0x7C00000U)
#define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_SHIFT (22U)
/*! SW_C_STRIDE_POW2 - VP8 C stride length informed by 2^n (n=sw_c_stride_pow2). Valid range 10-17 for 32 bit bus and 10-18 for 64 bit bus
*/
#define VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_SHIFT)) & VPU_G1_VP8_SWREG21_VP8_SW_C_STRIDE_POW2_MASK)
#define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_MASK (0xF8000000U)
#define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_SHIFT (27U)
/*! SW_Y_STRIDE_POW2 - VP8 Y stride length informed by 2^n (n=sw_y_stride_pow2). Valid range 10-17 for 32 bit bus and 10-18 for 64 bit bus
*/
#define VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_SHIFT)) & VPU_G1_VP8_SWREG21_VP8_SW_Y_STRIDE_POW2_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_G1_VP8_Register_Masks */
/* VPU_G1_VP8 - Peripheral instance base addresses */
/** Peripheral VPU_G1_VP8 base address */
#define VPU_G1_VP8_BASE (0x38300000u)
/** Peripheral VPU_G1_VP8 base pointer */
#define VPU_G1_VP8 ((VPU_G1_VP8_Type *)VPU_G1_VP8_BASE)
/** Array initializer of VPU_G1_VP8 peripheral base addresses */
#define VPU_G1_VP8_BASE_ADDRS { VPU_G1_VP8_BASE }
/** Array initializer of VPU_G1_VP8 peripheral base pointers */
#define VPU_G1_VP8_BASE_PTRS { VPU_G1_VP8 }
/*!
* @}
*/ /* end of group VPU_G1_VP8_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_G2 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G2_Peripheral_Access_Layer VPU_G2 Peripheral Access Layer
* @{
*/
/** VPU_G2 - Register Layout Typedef */
typedef struct {
__I uint32_t SWREG0; /**< ID register (read only), offset: 0x0 */
__IO uint32_t SWREG1; /**< Interrupt register decoder, offset: 0x4 */
__IO uint32_t SWREG2; /**< Data configuration register decoder, offset: 0x8 */
__IO uint32_t SWREG3; /**< Decoder control register 0, offset: 0xC */
__IO uint32_t SWREG4; /**< Decoder control register 1, offset: 0x10 */
__IO uint32_t SWREG5; /**< Decoder control register 2, offset: 0x14 */
__IO uint32_t SWREG6; /**< Decoder control register 3, offset: 0x18 */
__IO uint32_t SWREG7; /**< Decoder control register 4, offset: 0x1C */
__IO uint32_t SWREG8; /**< Decoder control register 5, offset: 0x20 */
__IO uint32_t SWREG9; /**< Decoder control register 6, offset: 0x24 */
__IO uint32_t SWREG10; /**< Decoder control register 7, offset: 0x28 */
__IO uint32_t SWREG11; /**< Decoder control register 8, offset: 0x2C */
__IO uint32_t SWREG12; /**< Decoder control register 9, offset: 0x30 */
__IO uint32_t SWREG13; /**< Decoder control register 10, offset: 0x34 */
__IO uint32_t SWREG14; /**< Initial ref pic list register (0-2), offset: 0x38 */
__IO uint32_t SWREG15; /**< Initial ref pic list register (3-5), offset: 0x3C */
__IO uint32_t SWREG16; /**< Initial ref pic list register (6-8), offset: 0x40 */
__IO uint32_t SWREG17; /**< Initial ref pic list register (9-11), offset: 0x44 */
__IO uint32_t SWREG18; /**< Initial ref pic list register (12-14), offset: 0x48 */
__IO uint32_t SWREG19; /**< Initial ref pic list register (15 and P 0-3), offset: 0x4C */
__IO uint32_t SWREG20; /**< Decoder control register 11, offset: 0x50 */
uint32_t SWREG21; /**< Not used, offset: 0x54 */
uint32_t SWREG22; /**< Not used, offset: 0x58 */
__I uint32_t SWREG23; /**< Decoder configure status register, offset: 0x5C */
uint32_t SWREG24; /**< Not used, offset: 0x60 */
uint32_t SWREG25; /**< Not used, offset: 0x64 */
uint32_t SWREG26; /**< Not used, offset: 0x68 */
uint32_t SWREG27; /**< Not used, offset: 0x6C */
uint32_t SWREG28; /**< Not used, offset: 0x70 */
uint32_t SWREG29; /**< Not used, offset: 0x74 */
uint32_t SWREG30; /**< Not used, offset: 0x78 */
__IO uint32_t SWREG31; /**< VP9 segmentation values, offset: 0x7C */
__IO uint32_t SWREG32; /**< VP9 segmentation values, offset: 0x80 */
__IO uint32_t SWREG33; /**< VP9 reference picture scaling register 0, offset: 0x84 */
__IO uint32_t SWREG34; /**< VP9 reference picture scaling register 1, offset: 0x88 */
__IO uint32_t SWREG35; /**< VP9 reference picture scaling register 2, offset: 0x8C */
__IO uint32_t SWREG36; /**< VP9 reference picture scaling register 3, offset: 0x90 */
__IO uint32_t SWREG37; /**< VP9 reference picture scaling register 4, offset: 0x94 */
__IO uint32_t SWREG38; /**< VP9 reference picture scaling register 5, offset: 0x98 */
uint32_t SWREG39; /**< Not used, offset: 0x9C */
uint32_t SWREG40; /**< Not used, offset: 0xA0 */
uint32_t SWREG41; /**< Not used, offset: 0xA4 */
uint32_t SWREG42; /**< Not used, offset: 0xA8 */
uint32_t SWREG43; /**< Not used, offset: 0xAC */
uint32_t SWREG44; /**< Not used, offset: 0xB0 */
__IO uint32_t SWREG45; /**< Timeout control register, offset: 0xB4 */
__IO uint32_t SWREG46; /**< Picture order count from current pictures for index 0-3, offset: 0xB8 */
__IO uint32_t SWREG47; /**< Picture order count from current pictures for index 4-7, offset: 0xBC */
__IO uint32_t SWREG48; /**< Picture order count from current pictures for index 8-11, offset: 0xC0 */
__IO uint32_t SWREG49; /**< Picture order count from current pictures for index 12-15, offset: 0xC4 */
__I uint32_t SWREG50; /**< Synthesis configuration register decoder 0 (read only), offset: 0xC8 */
uint32_t SWREG51; /**< Reference picture buffer control register, offset: 0xCC */
uint32_t SWREG52; /**< Reference picture buffer information register 1 (read only), offset: 0xD0 */
uint32_t SWREG53; /**< Reference picture buffer information register 2 (read only), offset: 0xD4 */
__I uint32_t SWREG54; /**< Synthesis configuration register decoder 1 (read only), offset: 0xD8 */
__IO uint32_t SWREG55; /**< Advanced prefetch control register, offset: 0xDC */
__I uint32_t SWREG56; /**< Synthesis configuration register decoder 2 (read only), offset: 0xE0 */
uint32_t SWREG57; /**< Decoder fuse register (read only), offset: 0xE4 */
__IO uint32_t SWREG58; /**< Device configuration register decoder 2 + Multi core control register, offset: 0xE8 */
__IO uint32_t SWREG59; /**< Device configuration register AXI ID, offset: 0xEC */
__I uint32_t SWREG60; /**< Synthesis configuration register decoder 3 for PP (read only), offset: 0xF0 */
uint32_t SWREG61; /**< Not used, offset: 0xF4 */
__IO uint32_t SWREG62; /**< HW proceed register (CU location), offset: 0xF8 */
__I uint32_t SWREG63; /**< HW performance register (cycles running), offset: 0xFC */
__IO uint32_t SWREG64; /**< Base address MSB (bits 63:32) for decoded luminance picture, offset: 0x100 */
__IO uint32_t SWREG65; /**< Base address LSB (bits 31:0) for decoded luminance picture, offset: 0x104 */
__IO uint32_t SWREG66; /**< Base address MSB (bits 63:32) for reference luminance picture index 0, offset: 0x108 */
__IO uint32_t SWREG67; /**< Base address LSB (bits 31:0) for reference luminance picture index 0, offset: 0x10C */
__IO uint32_t SWREG68; /**< Base address MSB (bits 63:32) for reference luminance picture index 1, offset: 0x110 */
__IO uint32_t SWREG69; /**< Base address LSB (bits 31:0) for reference luminance picture index 1, offset: 0x114 */
__IO uint32_t SWREG70; /**< Base address MSB (bits 63:32) for reference luminance picture index 2, offset: 0x118 */
__IO uint32_t SWREG71; /**< Base address LSB (bits 31:0) for reference luminance picture index 2, offset: 0x11C */
__IO uint32_t SWREG72; /**< Base address MSB (bits 63:32) for reference luminance picture index 3, offset: 0x120 */
__IO uint32_t SWREG73; /**< Base address LSB (bits 31:0) for reference luminance picture index 3, offset: 0x124 */
__IO uint32_t SWREG74; /**< Base address MSB (bits 63:32) for reference luminance picture index 4, offset: 0x128 */
__IO uint32_t SWREG75; /**< Base address LSB (bits 31:0) for reference luminance picture index 4, offset: 0x12C */
__IO uint32_t SWREG76; /**< Base address MSB (bits 63:32) for reference luminance picture index 5, offset: 0x130 */
__IO uint32_t SWREG77; /**< Base address LSB (bits 31:0) for reference luminance picture index 5, offset: 0x134 */
__IO uint32_t SWREG78; /**< Base address MSB (bits 63:32) for reference luminance picture index 6 /VP9 segment write base MSB, offset: 0x138 */
__IO uint32_t SWREG79; /**< Base address LSB (bits 31:0) for reference luminance picture index 6 /VP9 segment write base LSB, offset: 0x13C */
__IO uint32_t SWREG80; /**< Base address MSB (bits 63:32) for reference luminance picture index 7 /VP9 segment read base MSB, offset: 0x140 */
__IO uint32_t SWREG81; /**< Base address LSB (bits 31:0) for reference luminance picture index 7 /VP9 segment read base LSB, offset: 0x144 */
__IO uint32_t SWREG82; /**< Base address MSB (bits 63:32) for reference luminance picture index 8, offset: 0x148 */
__IO uint32_t SWREG83; /**< Base address LSB (bits 31:0) for reference luminance picture index 8, offset: 0x14C */
__IO uint32_t SWREG84; /**< Base address MSB (bits 63:32) for reference luminance picture index 9, offset: 0x150 */
__IO uint32_t SWREG85; /**< Base address LSB (bits 31:0) for reference luminance picture index 9, offset: 0x154 */
__IO uint32_t SWREG86; /**< Base address MSB (bits 63:32) for reference luminance picture index 10, offset: 0x158 */
__IO uint32_t SWREG87; /**< Base address LSB (bits 31:0) for reference luminance picture index 10, offset: 0x15C */
__IO uint32_t SWREG88; /**< Base address MSB (bits 63:32) for reference luminance picture index 11, offset: 0x160 */
__IO uint32_t SWREG89; /**< Base address LSB (bits 31:0) for reference luminance picture index 11, offset: 0x164 */
__IO uint32_t SWREG90; /**< Base address MSB (bits 63:32) for reference luminance picture index 12, offset: 0x168 */
__IO uint32_t SWREG91; /**< Base address LSB (bits 31:0) for reference luminance picture index 12, offset: 0x16C */
__IO uint32_t SWREG92; /**< Base address MSB (bits 63:32) for reference luminance picture index 13, offset: 0x170 */
__IO uint32_t SWREG93; /**< Base address LSB (bits 31:0) for reference luminance picture index 13, offset: 0x174 */
__IO uint32_t SWREG94; /**< Base address MSB (bits 63:32) for reference luminance picture index 14, offset: 0x178 */
__IO uint32_t SWREG95; /**< Base address LSB (bits 31:0) for reference luminance picture index 14, offset: 0x17C */
__IO uint32_t SWREG96; /**< Base address MSB (bits 63:32) for reference luminance picture index 15, offset: 0x180 */
__IO uint32_t SWREG97; /**< Base address LSB (bits 31:0) for reference luminance picture index 15, offset: 0x184 */
__IO uint32_t SWREG98; /**< Base address MSB (bits 63:32) for decoded chrominance picture, offset: 0x188 */
__IO uint32_t SWREG99; /**< Base address LSB (bits 31:0) for decoded chrominance picture, offset: 0x18C */
__IO uint32_t SWREG100; /**< Base address MSB (bits 63:32) for reference chrominance picture index 0, offset: 0x190 */
__IO uint32_t SWREG101; /**< Base address LSB (bits 31:0) for reference chrominance picture index 0, offset: 0x194 */
__IO uint32_t SWREG102; /**< Base address MSB (bits 63:32) for reference chrominance picture index 1, offset: 0x198 */
__IO uint32_t SWREG103; /**< Base address LSB (bits 31:0) for reference chrominance picture index 1, offset: 0x19C */
__IO uint32_t SWREG104; /**< Base address MSB (bits 63:32) for reference chrominance picture index 2, offset: 0x1A0 */
__IO uint32_t SWREG105; /**< Base address LSB (bits 31:0) for reference chrominance picture index 2, offset: 0x1A4 */
__IO uint32_t SWREG106; /**< Base address MSB (bits 63:32) for reference chrominance picture index 3, offset: 0x1A8 */
__IO uint32_t SWREG107; /**< Base address LSB (bits 31:0) for reference chrominance picture index 3, offset: 0x1AC */
__IO uint32_t SWREG108; /**< Base address MSB (bits 63:32) for reference chrominance picture index 4, offset: 0x1B0 */
__IO uint32_t SWREG109; /**< Base address LSB (bits 31:0) for reference chrominance picture index 4, offset: 0x1B4 */
__IO uint32_t SWREG110; /**< Base address MSB (bits 63:32) for reference chrominance picture index 5, offset: 0x1B8 */
__IO uint32_t SWREG111; /**< Base address LSB (bits 31:0) for reference chrominance picture index 5, offset: 0x1BC */
__IO uint32_t SWREG112; /**< Base address MSB (bits 63:32) for reference chrominance picture index 6, offset: 0x1C0 */
__IO uint32_t SWREG113; /**< Base address LSB (bits 31:0) for reference chrominance picture index 6, offset: 0x1C4 */
__IO uint32_t SWREG114; /**< Base address MSB (bits 63:32) for reference chrominance picture index 7, offset: 0x1C8 */
__IO uint32_t SWREG115; /**< Base address LSB (bits 31:0) for reference chrominance picture index 7, offset: 0x1CC */
__IO uint32_t SWREG116; /**< Base address MSB (bits 63:32) for reference chrominance picture index 8, offset: 0x1D0 */
__IO uint32_t SWREG117; /**< Base address LSB (bits 31:0) for reference chrominance picture index 8, offset: 0x1D4 */
__IO uint32_t SWREG118; /**< Base address MSB (bits 63:32) for reference chrominance picture index 9, offset: 0x1D8 */
__IO uint32_t SWREG119; /**< Base address LSB (bits 31:0) for reference chrominance picture index 9, offset: 0x1DC */
__IO uint32_t SWREG120; /**< Base address MSB (bits 63:32) for reference chrominance picture index 10, offset: 0x1E0 */
__IO uint32_t SWREG121; /**< Base address LSB (bits 31:0) for reference chrominance picture index 10, offset: 0x1E4 */
__IO uint32_t SWREG122; /**< Base address MSB (bits 63:32) for reference chrominance picture index 11, offset: 0x1E8 */
__IO uint32_t SWREG123; /**< Base address LSB (bits 31:0) for reference chrominance picture index 11, offset: 0x1EC */
__IO uint32_t SWREG124; /**< Base address MSB (bits 63:32) for reference chrominance picture index 12, offset: 0x1F0 */
__IO uint32_t SWREG125; /**< Base address LSB (bits 31:0) for reference chrominance picture index 12, offset: 0x1F4 */
__IO uint32_t SWREG126; /**< Base address MSB (bits 63:32) for reference chrominance picture index 13, offset: 0x1F8 */
__IO uint32_t SWREG127; /**< Base address LSB (bits 31:0) for reference chrominance picture index 13, offset: 0x1FC */
__IO uint32_t SWREG128; /**< Base address MSB (bits 63:32) for reference chrominance picture index 14, offset: 0x200 */
__IO uint32_t SWREG129; /**< Base address LSB (bits 31:0) for reference chrominance picture index 14, offset: 0x204 */
__IO uint32_t SWREG130; /**< Base address MSB (bits 63:32) for reference chrominance picture index 15, offset: 0x208 */
__IO uint32_t SWREG131; /**< Base address LSB (bits 31:0) for reference chrominance picture index 15, offset: 0x20C */
__IO uint32_t SWREG132; /**< Base address MSB (bits 63:32) for decoded direct mode MVS, offset: 0x210 */
__IO uint32_t SWREG133; /**< Base address LSB (bits 31:0) for decoded direct mode MVS, offset: 0x214 */
__IO uint32_t SWREG134; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 0, offset: 0x218 */
__IO uint32_t SWREG135; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 0, offset: 0x21C */
__IO uint32_t SWREG136; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 1, offset: 0x220 */
__IO uint32_t SWREG137; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 1, offset: 0x224 */
__IO uint32_t SWREG138; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 2, offset: 0x228 */
__IO uint32_t SWREG139; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 2, offset: 0x22C */
__IO uint32_t SWREG140; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 3, offset: 0x230 */
__IO uint32_t SWREG141; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 3, offset: 0x234 */
__IO uint32_t SWREG142; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 4, offset: 0x238 */
__IO uint32_t SWREG143; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 4, offset: 0x23C */
__IO uint32_t SWREG144; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 5, offset: 0x240 */
__IO uint32_t SWREG145; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 5, offset: 0x244 */
__IO uint32_t SWREG146; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 6, offset: 0x248 */
__IO uint32_t SWREG147; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 6, offset: 0x24C */
__IO uint32_t SWREG148; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 7, offset: 0x250 */
__IO uint32_t SWREG149; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 7, offset: 0x254 */
__IO uint32_t SWREG150; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 8, offset: 0x258 */
__IO uint32_t SWREG151; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 8, offset: 0x25C */
__IO uint32_t SWREG152; /**< Base address MSB (bits 63:32) for reference direct mode mode MVS index 9, offset: 0x260 */
__IO uint32_t SWREG153; /**< Base address LSB (bits 31:0) for reference direct mode mode MVS index 9, offset: 0x264 */
__IO uint32_t SWREG154; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 10, offset: 0x268 */
__IO uint32_t SWREG155; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 10, offset: 0x26C */
__IO uint32_t SWREG156; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 11, offset: 0x270 */
__IO uint32_t SWREG157; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 11, offset: 0x274 */
__IO uint32_t SWREG158; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 12, offset: 0x278 */
__IO uint32_t SWREG159; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 12, offset: 0x27C */
__IO uint32_t SWREG160; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 13, offset: 0x280 */
__IO uint32_t SWREG161; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 13, offset: 0x284 */
__IO uint32_t SWREG162; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 14, offset: 0x288 */
__IO uint32_t SWREG163; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 14, offset: 0x28C */
__IO uint32_t SWREG164; /**< Base address MSB (bits 63:32) for reference direct mode MVS index 15, offset: 0x290 */
__IO uint32_t SWREG165; /**< Base address LSB (bits 31:0) for reference direct mode MVS index 15, offset: 0x294 */
__IO uint32_t SWREG166; /**< Base address MSB (bits 63:32) for tile sizes, offset: 0x298 */
__IO uint32_t SWREG167; /**< Base address LSB (bits 31:0) for tile sizes, offset: 0x29C */
__IO uint32_t SWREG168; /**< Base address MSB (bits 63:32) for / stream start address/decoded end addr register, offset: 0x2A0 */
__IO uint32_t SWREG169; /**< Base address LSB (bits 31:0) for / stream start address/decoded end addr register, offset: 0x2A4 */
__IO uint32_t SWREG170; /**< Base address MSB (bits 63:32) for scaling lists / VP9 CTX counter values, offset: 0x2A8 */
__IO uint32_t SWREG171; /**< Base address LSB (bits 31:0) for scaling lists / VP9 CTX counter values, offset: 0x2AC */
__IO uint32_t SWREG172; /**< Base address MSB (bits 63:32) for stream propability tables, offset: 0x2B0 */
__IO uint32_t SWREG173; /**< Base address LSB (bits 31:0) for stream propability tables, offset: 0x2B4 */
__IO uint32_t SWREG174; /**< Base address MSB (bits 63:32) for decoder output raster scan Y picture, offset: 0x2B8 */
__IO uint32_t SWREG175; /**< Base address LSB (bits 31:0) for decoder output raster scan Y picture, offset: 0x2BC */
__IO uint32_t SWREG176; /**< Base address MSB (bits 63:32) for decoder output raster scan C picture, offset: 0x2C0 */
__IO uint32_t SWREG177; /**< Base address LSB (bits 31:0) for decoder output raster scan C picture, offset: 0x2C4 */
__IO uint32_t SWREG178; /**< Base address MSB (bits 63:32) for tile border coeffients of filter, offset: 0x2C8 */
__IO uint32_t SWREG179; /**< Base address LSB (bits 31:0) for tile border coeffients of filter, offset: 0x2CC */
__IO uint32_t SWREG180; /**< Base address MSB (bits 63:32) for tile border coeffients of sao, offset: 0x2D0 */
__IO uint32_t SWREG181; /**< Base address LSB (bits 31:0) for tile border coeffients of sao, offset: 0x2D4 */
__IO uint32_t SWREG182; /**< Base address MSB (bits 63:32) for tile border bsd control data, offset: 0x2D8 */
__IO uint32_t SWREG183; /**< Base address LSB (bits 31:0) for tile border bsd control data, offset: 0x2DC */
__IO uint32_t SWREG184; /**< Raster scan down scale control register MSM, offset: 0x2E0 */
__IO uint32_t SWREG185; /**< Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture, offset: 0x2E4 */
__IO uint32_t SWREG186; /**< Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture, offset: 0x2E8 */
__IO uint32_t SWREG187; /**< Base address MSB (bits 63:32) for decoder output raster scan down scale C picture, offset: 0x2EC */
__IO uint32_t SWREG188; /**< Base address LSB (bits 31:0) for decoder output raster scan down scale C picture, offset: 0x2F0 */
__IO uint32_t SWREG189; /**< Base address MSB (bits 63:32) for decoder output compress luminance table, offset: 0x2F4 */
__IO uint32_t SWREG190; /**< Base address LSB (bits 31:0) for decoder output compress luminance table, offset: 0x2F8 */
__IO uint32_t SWREG191; /**< Base address MSB (bits 63:32) for reference compress luminance table index 0, offset: 0x2FC */
__IO uint32_t SWREG192; /**< Base address LSB (bits 31:0) for reference compress luminance table index 0, offset: 0x300 */
__IO uint32_t SWREG193; /**< Base address MSB (bits 63:32) for reference compress luminance table index 1, offset: 0x304 */
__IO uint32_t SWREG194; /**< Base address LSB (bits 31:0) for reference compress luminance table index 1, offset: 0x308 */
__IO uint32_t SWREG195; /**< Base address MSB (bits 63:32) for reference compress luminance table index 2, offset: 0x30C */
__IO uint32_t SWREG196; /**< Base address LSB (bits 31:0) for reference compress luminance table index 2, offset: 0x310 */
__IO uint32_t SWREG197; /**< Base address MSB (bits 63:32) for reference compress luminance table index 3, offset: 0x314 */
__IO uint32_t SWREG198; /**< Base address LSB (bits 31:0) for reference compress luminance table index 3, offset: 0x318 */
__IO uint32_t SWREG199; /**< Base address MSB (bits 63:32) for reference compress luminance table index 4, offset: 0x31C */
__IO uint32_t SWREG200; /**< Base address LSB (bits 31:0) for reference compress luminance table index 4, offset: 0x320 */
__IO uint32_t SWREG201; /**< Base address MSB (bits 63:32) for reference compress luminance table index 5, offset: 0x324 */
__IO uint32_t SWREG202; /**< Base address LSB (bits 31:0) for reference compress luminance table index 5, offset: 0x328 */
__IO uint32_t SWREG203; /**< Base address MSB (bits 63:32) for reference compress luminance table index 6, offset: 0x32C */
__IO uint32_t SWREG204; /**< Base address LSB (bits 31:0) for reference compress luminance table index 6, offset: 0x330 */
__IO uint32_t SWREG205; /**< Base address MSB (bits 63:32) for reference compress luminance table index 7, offset: 0x334 */
__IO uint32_t SWREG206; /**< Base address LSB (bits 31:0) for reference compress luminance table index 7, offset: 0x338 */
__IO uint32_t SWREG207; /**< Base address MSB (bits 63:32) for reference compress luminance table index 8, offset: 0x33C */
__IO uint32_t SWREG208; /**< Base address LSB (bits 31:0) for reference compress luminance table index 8, offset: 0x340 */
__IO uint32_t SWREG209; /**< Base address MSB (bits 63:32) for reference compress luminance table index 9, offset: 0x344 */
__IO uint32_t SWREG210; /**< Base address LSB (bits 31:0) for reference compress luminance table index 9, offset: 0x348 */
__IO uint32_t SWREG211; /**< Base address MSB (bits 63:32) for reference compress luminance table index 10, offset: 0x34C */
__IO uint32_t SWREG212; /**< Base address LSB (bits 31:0) for reference compress luminance table index 10, offset: 0x350 */
__IO uint32_t SWREG213; /**< Base address MSB (bits 63:32) for reference compress luminance table index 11, offset: 0x354 */
__IO uint32_t SWREG214; /**< Base address LSB (bits 31:0) for reference compress luminance table index 11, offset: 0x358 */
__IO uint32_t SWREG215; /**< Base address MSB (bits 63:32) for reference compress luminance table index 12, offset: 0x35C */
__IO uint32_t SWREG216; /**< Base address LSB (bits 31:0) for reference compress luminance table index 12, offset: 0x360 */
__IO uint32_t SWREG217; /**< Base address MSB (bits 63:32) for reference compress luminance table index 13, offset: 0x364 */
__IO uint32_t SWREG218; /**< Base address LSB (bits 31:0) for reference compress luminance table index 13, offset: 0x368 */
__IO uint32_t SWREG219; /**< Base address MSB (bits 63:32) for reference compress luminance table index 14, offset: 0x36C */
__IO uint32_t SWREG220; /**< Base address LSB (bits 31:0) for reference compress luminance table index 14, offset: 0x370 */
__IO uint32_t SWREG221; /**< Base address MSB (bits 63:32) for reference compress luminance table index 15, offset: 0x374 */
__IO uint32_t SWREG222; /**< Base address LSB (bits 31:0) for reference compress luminance table index 15, offset: 0x378 */
__IO uint32_t SWREG223; /**< Base address MSB (bits 63:32) for decoder output compress chrominance table, offset: 0x37C */
__IO uint32_t SWREG224; /**< Base address LSB (bits 31:0) for decoder output compress chrominance table, offset: 0x380 */
__IO uint32_t SWREG225; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 0, offset: 0x384 */
__IO uint32_t SWREG226; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 0, offset: 0x388 */
__IO uint32_t SWREG227; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 1, offset: 0x38C */
__IO uint32_t SWREG228; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 1, offset: 0x390 */
__IO uint32_t SWREG229; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 2, offset: 0x394 */
__IO uint32_t SWREG230; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 2, offset: 0x398 */
__IO uint32_t SWREG231; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 3, offset: 0x39C */
__IO uint32_t SWREG232; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 3, offset: 0x3A0 */
__IO uint32_t SWREG233; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 4, offset: 0x3A4 */
__IO uint32_t SWREG234; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 4, offset: 0x3A8 */
__IO uint32_t SWREG235; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 5, offset: 0x3AC */
__IO uint32_t SWREG236; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 5, offset: 0x3B0 */
__IO uint32_t SWREG237; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 6, offset: 0x3B4 */
__IO uint32_t SWREG238; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 6, offset: 0x3B8 */
__IO uint32_t SWREG239; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 7, offset: 0x3BC */
__IO uint32_t SWREG240; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 7, offset: 0x3C0 */
__IO uint32_t SWREG241; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 8, offset: 0x3C4 */
__IO uint32_t SWREG242; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 8, offset: 0x3C8 */
__IO uint32_t SWREG243; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 9, offset: 0x3CC */
__IO uint32_t SWREG244; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 9, offset: 0x3D0 */
__IO uint32_t SWREG245; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 10, offset: 0x3D4 */
__IO uint32_t SWREG246; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 10, offset: 0x3D8 */
__IO uint32_t SWREG247; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 11, offset: 0x3DC */
__IO uint32_t SWREG248; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 11, offset: 0x3E0 */
__IO uint32_t SWREG249; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 12, offset: 0x3E4 */
__IO uint32_t SWREG250; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 12, offset: 0x3E8 */
__IO uint32_t SWREG251; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 13, offset: 0x3EC */
__IO uint32_t SWREG252; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 13, offset: 0x3F0 */
__IO uint32_t SWREG253; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 14, offset: 0x3F4 */
__IO uint32_t SWREG254; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 14, offset: 0x3F8 */
__IO uint32_t SWREG255; /**< Base address MSB (bits 63:32) for reference compress chrominance table index 15, offset: 0x3FC */
__IO uint32_t SWREG256; /**< Base address LSB (bits 31:0) for reference compress chrominance table index 15, offset: 0x400 */
uint32_t SWREG257; /**< Not used, offset: 0x404 */
__IO uint32_t SWREG258; /**< input stream buffer length, offset: 0x408 */
__IO uint32_t SWREG259; /**< input stream buffer start offset, offset: 0x40C */
} VPU_G2_Type;
/* ----------------------------------------------------------------------------
-- VPU_G2 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_G2_Register_Masks VPU_G2 Register Masks
* @{
*/
/*! @name SWREG0 - ID register (read only) */
/*! @{ */
#define VPU_G2_SWREG0_SW_BUILD_VERSION_MASK (0x7U)
#define VPU_G2_SWREG0_SW_BUILD_VERSION_SHIFT (0U)
/*! SW_BUILD_VERSION - Build version (core number)
*/
#define VPU_G2_SWREG0_SW_BUILD_VERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_BUILD_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_BUILD_VERSION_MASK)
#define VPU_G2_SWREG0_SW_PRODUCT_ID_EN_MASK (0x8U)
#define VPU_G2_SWREG0_SW_PRODUCT_ID_EN_SHIFT (3U)
/*! SW_PRODUCT_ID_EN - ASCII type product ID enable
*/
#define VPU_G2_SWREG0_SW_PRODUCT_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_PRODUCT_ID_EN_SHIFT)) & VPU_G2_SWREG0_SW_PRODUCT_ID_EN_MASK)
#define VPU_G2_SWREG0_SW_MINOR_VERSION_MASK (0xFF0U)
#define VPU_G2_SWREG0_SW_MINOR_VERSION_SHIFT (4U)
/*! SW_MINOR_VERSION - Minor version
*/
#define VPU_G2_SWREG0_SW_MINOR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_MINOR_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_MINOR_VERSION_MASK)
#define VPU_G2_SWREG0_SW_MAJOR_VERSION_MASK (0xF000U)
#define VPU_G2_SWREG0_SW_MAJOR_VERSION_SHIFT (12U)
/*! SW_MAJOR_VERSION - Major version
*/
#define VPU_G2_SWREG0_SW_MAJOR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_MAJOR_VERSION_SHIFT)) & VPU_G2_SWREG0_SW_MAJOR_VERSION_MASK)
#define VPU_G2_SWREG0_SW_PRODUCT_NUMBER_MASK (0xFFFF0000U)
#define VPU_G2_SWREG0_SW_PRODUCT_NUMBER_SHIFT (16U)
/*! SW_PRODUCT_NUMBER - Product number (g2)
*/
#define VPU_G2_SWREG0_SW_PRODUCT_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG0_SW_PRODUCT_NUMBER_SHIFT)) & VPU_G2_SWREG0_SW_PRODUCT_NUMBER_MASK)
/*! @} */
/*! @name SWREG1 - Interrupt register decoder */
/*! @{ */
#define VPU_G2_SWREG1_SW_DEC_E_MASK (0x1U)
#define VPU_G2_SWREG1_SW_DEC_E_SHIFT (0U)
/*! SW_DEC_E - Decoder enable. Setting this bit high will start the decoding operation. HW will
* reset this when picture is processed or ASO or stream error is detected or bus error or timeout
* interrupt is given.
*/
#define VPU_G2_SWREG1_SW_DEC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_E_SHIFT)) & VPU_G2_SWREG1_SW_DEC_E_MASK)
#define VPU_G2_SWREG1_SW_DEC_IRQ_DIS_MASK (0x10U)
#define VPU_G2_SWREG1_SW_DEC_IRQ_DIS_SHIFT (4U)
/*! SW_DEC_IRQ_DIS - Decoder IRQ disable. When high there are no interrupts concerning decoder from
* HW. Polling must be used to see the interrupt statuses.
*/
#define VPU_G2_SWREG1_SW_DEC_IRQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_IRQ_DIS_SHIFT)) & VPU_G2_SWREG1_SW_DEC_IRQ_DIS_MASK)
#define VPU_G2_SWREG1_SW_DEC_ABORT_E_MASK (0x20U)
#define VPU_G2_SWREG1_SW_DEC_ABORT_E_SHIFT (5U)
/*! SW_DEC_ABORT_E - Abort decoding enable. Setting this bit high will cause HW to abort decoding
* and safely to reset itself down. After abort is complete the corresponding interrupt status is
* set and this bit is set low as well as the decoder enable.
*/
#define VPU_G2_SWREG1_SW_DEC_ABORT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ABORT_E_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ABORT_E_MASK)
#define VPU_G2_SWREG1_SW_DEC_IRQ_MASK (0x100U)
#define VPU_G2_SWREG1_SW_DEC_IRQ_SHIFT (8U)
/*! SW_DEC_IRQ - Decoder IRQ. When high decoder requests an interrupt. SW will reset this after interrupt is handled.
*/
#define VPU_G2_SWREG1_SW_DEC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_IRQ_SHIFT)) & VPU_G2_SWREG1_SW_DEC_IRQ_MASK)
#define VPU_G2_SWREG1_SW_DEC_ABORT_INT_MASK (0x800U)
#define VPU_G2_SWREG1_SW_DEC_ABORT_INT_SHIFT (11U)
/*! SW_DEC_ABORT_INT - Interrupt status bit decoding aborted. When this bit is high decoder has
* aborted the current picture decoding as SW requested (sw_dec_abort_e). Decoder self reset and
* sw_dec_abort_e written low
*/
#define VPU_G2_SWREG1_SW_DEC_ABORT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ABORT_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ABORT_INT_MASK)
#define VPU_G2_SWREG1_SW_DEC_RDY_INT_MASK (0x1000U)
#define VPU_G2_SWREG1_SW_DEC_RDY_INT_SHIFT (12U)
/*! SW_DEC_RDY_INT - Interrupt status bit decoder. When this bit is high decoder has decoded a picture. HW will self reset.
*/
#define VPU_G2_SWREG1_SW_DEC_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_RDY_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_RDY_INT_MASK)
#define VPU_G2_SWREG1_SW_DEC_BUS_INT_MASK (0x2000U)
#define VPU_G2_SWREG1_SW_DEC_BUS_INT_SHIFT (13U)
/*! SW_DEC_BUS_INT - Interrupt status bit bus. Error response from bus. HW will self reset.
*/
#define VPU_G2_SWREG1_SW_DEC_BUS_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_BUS_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_BUS_INT_MASK)
#define VPU_G2_SWREG1_SW_DEC_BUFFER_INT_MASK (0x4000U)
#define VPU_G2_SWREG1_SW_DEC_BUFFER_INT_SHIFT (14U)
/*! SW_DEC_BUFFER_INT - Interrupt status bit input buffer empty. When high input stream buffer is
* empty but picture is not ready. HW will not self reset.
*/
#define VPU_G2_SWREG1_SW_DEC_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_BUFFER_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_BUFFER_INT_MASK)
#define VPU_G2_SWREG1_SW_DEC_ERROR_INT_MASK (0x10000U)
#define VPU_G2_SWREG1_SW_DEC_ERROR_INT_SHIFT (16U)
/*! SW_DEC_ERROR_INT - Interrupt status bit input stream error. When high an error is found in input data stream decoding. HW will self reset.
*/
#define VPU_G2_SWREG1_SW_DEC_ERROR_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_ERROR_INT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_ERROR_INT_MASK)
#define VPU_G2_SWREG1_SW_DEC_TIMEOUT_MASK (0x40000U)
#define VPU_G2_SWREG1_SW_DEC_TIMEOUT_SHIFT (18U)
/*! SW_DEC_TIMEOUT - Interrupt status bit decoder timeout. When high the decoder has been idling for
* too long. HW will self reset. Possible only if timeout interrupt is enabled
*/
#define VPU_G2_SWREG1_SW_DEC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG1_SW_DEC_TIMEOUT_SHIFT)) & VPU_G2_SWREG1_SW_DEC_TIMEOUT_MASK)
/*! @} */
/*! @name SWREG2 - Data configuration register decoder */
/*! @{ */
#define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_MASK (0xFU)
#define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_SHIFT (0U)
/*! SW_DEC_RSCAN_SWAP - Byte swap for raster scan output picture data
*/
#define VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_RSCAN_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_MASK (0xF0U)
#define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_SHIFT (4U)
/*! SW_DEC_TAB3_SWAP - Byte swap configuration for tile sizes
*/
#define VPU_G2_SWREG2_SW_DEC_TAB3_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB3_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_MASK (0xF00U)
#define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_SHIFT (8U)
/*! SW_DEC_TAB2_SWAP - Byte swap configuration for VP9 CTX counter values
*/
#define VPU_G2_SWREG2_SW_DEC_TAB2_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB2_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_MASK (0xF000U)
#define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_SHIFT (12U)
/*! SW_DEC_TAB1_SWAP - Byte swap configuration for HEVC scaling lists / VP9 segmentation map read/write
*/
#define VPU_G2_SWREG2_SW_DEC_TAB1_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB1_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_MASK (0xF0000U)
#define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_SHIFT (16U)
/*! SW_DEC_TAB0_SWAP - Byte swap configuration for VP9 stream propability tables
*/
#define VPU_G2_SWREG2_SW_DEC_TAB0_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_TAB0_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_MASK (0xF00000U)
#define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_SHIFT (20U)
/*! SW_DEC_DIRMV_SWAP - Byte swap configuration for direct mode MV data (read/write)
*/
#define VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_DIRMV_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_PIC_SWAP_MASK (0xF000000U)
#define VPU_G2_SWREG2_SW_DEC_PIC_SWAP_SHIFT (24U)
/*! SW_DEC_PIC_SWAP - Byte swap configuration for decoder reference output picture data
*/
#define VPU_G2_SWREG2_SW_DEC_PIC_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_PIC_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_PIC_SWAP_MASK)
#define VPU_G2_SWREG2_SW_DEC_STRM_SWAP_MASK (0xF0000000U)
#define VPU_G2_SWREG2_SW_DEC_STRM_SWAP_SHIFT (28U)
/*! SW_DEC_STRM_SWAP - Byte swap configuration for stream data 4 Bit byte order vector to control
* byte locations inside HW internal 128 bit data vector. For 64 and 32 bit external bus widths,
* the data is first gathered to 128 bit width and then bytes swapped accordingly:
*/
#define VPU_G2_SWREG2_SW_DEC_STRM_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG2_SW_DEC_STRM_SWAP_SHIFT)) & VPU_G2_SWREG2_SW_DEC_STRM_SWAP_MASK)
/*! @} */
/*! @name SWREG3 - Decoder control register 0 */
/*! @{ */
#define VPU_G2_SWREG3_SW_APF_ONE_PID_MASK (0x800U)
#define VPU_G2_SWREG3_SW_APF_ONE_PID_SHIFT (11U)
/*! SW_APF_ONE_PID - Prefetch partitions that have the same pic_id together
*/
#define VPU_G2_SWREG3_SW_APF_ONE_PID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_APF_ONE_PID_SHIFT)) & VPU_G2_SWREG3_SW_APF_ONE_PID_MASK)
#define VPU_G2_SWREG3_SW_WRITE_MVS_E_MASK (0x1000U)
#define VPU_G2_SWREG3_SW_WRITE_MVS_E_SHIFT (12U)
/*! SW_WRITE_MVS_E - Direct mode motion vector write enable for current picture
* 0b0..Writing disabled for current picture.
* 0b1..The direct mode motion vectors are written to external memory. HEVC/VP9 direct mode motion vectors are
* written to DPB aside with the corresponding reference picture. Other decoding mode dir mode mvs are written
* to external memory starting from sw_dir_mv_base.
*/
#define VPU_G2_SWREG3_SW_WRITE_MVS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_WRITE_MVS_E_SHIFT)) & VPU_G2_SWREG3_SW_WRITE_MVS_E_MASK)
#define VPU_G2_SWREG3_SW_FILTERING_DIS_MASK (0x4000U)
#define VPU_G2_SWREG3_SW_FILTERING_DIS_SHIFT (14U)
/*! SW_FILTERING_DIS - De-block filtering disable
* 0b1..Filtering is disabled for current picture
* 0b0..Filtering is enabled for current picture
*/
#define VPU_G2_SWREG3_SW_FILTERING_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_FILTERING_DIS_SHIFT)) & VPU_G2_SWREG3_SW_FILTERING_DIS_MASK)
#define VPU_G2_SWREG3_SW_DEC_OUT_DIS_MASK (0x8000U)
#define VPU_G2_SWREG3_SW_DEC_OUT_DIS_SHIFT (15U)
/*! SW_DEC_OUT_DIS - Disable decoder output picture writing
* 0b0..Decoder output picture is written to external memory
* 0b1..Decoder output picture is not written to external memory
*/
#define VPU_G2_SWREG3_SW_DEC_OUT_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_DIS_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_DIS_MASK)
#define VPU_G2_SWREG3_SW_DEC_OUT_RS_E_MASK (0x10000U)
#define VPU_G2_SWREG3_SW_DEC_OUT_RS_E_SHIFT (16U)
/*! SW_DEC_OUT_RS_E - Raster scan output enable. If high decoder writes the raster scan output if
* the configuration of Decoder includes PP raster scan output
*/
#define VPU_G2_SWREG3_SW_DEC_OUT_RS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_RS_E_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_RS_E_MASK)
#define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_MASK (0x20000U)
#define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_SHIFT (17U)
/*! SW_DEC_OUT_EC_BYPASS - Compress bypass
*/
#define VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_SHIFT)) & VPU_G2_SWREG3_SW_DEC_OUT_EC_BYPASS_MASK)
#define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_MASK (0xF00000U)
#define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_SHIFT (20U)
/*! SW_DEC_COMP_TABLE_SWAP - Byte swap configuration for compress table data
*/
#define VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_SHIFT)) & VPU_G2_SWREG3_SW_DEC_COMP_TABLE_SWAP_MASK)
#define VPU_G2_SWREG3_SW_DEC_MODE_MASK (0xF8000000U)
#define VPU_G2_SWREG3_SW_DEC_MODE_SHIFT (27U)
/*! SW_DEC_MODE - Decoding mode:
* 0b00000-0b01011..Reserved
* 0b01100..HEVC
* 0b01101..VP9
* 0b01110-0b11111..Reserved
*/
#define VPU_G2_SWREG3_SW_DEC_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG3_SW_DEC_MODE_SHIFT)) & VPU_G2_SWREG3_SW_DEC_MODE_MASK)
/*! @} */
/*! @name SWREG4 - Decoder control register 1 */
/*! @{ */
#define VPU_G2_SWREG4_SW_REF_FRAMES_MASK (0x1FU)
#define VPU_G2_SWREG4_SW_REF_FRAMES_SHIFT (0U)
/*! SW_REF_FRAMES - HEVC: num_ref_frames maximum number of short and long term reference frames in decoded picture buffer
*/
#define VPU_G2_SWREG4_SW_REF_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_REF_FRAMES_SHIFT)) & VPU_G2_SWREG4_SW_REF_FRAMES_MASK)
#define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_MASK (0x7FFC0U)
#define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_SHIFT (6U)
/*! SW_PIC_HEIGHT_IN_CBS - Picture height in min coded blocks (min = 8pix)
*/
#define VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_SHIFT)) & VPU_G2_SWREG4_SW_PIC_HEIGHT_IN_CBS_MASK)
#define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_MASK (0xFFF80000U)
#define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_SHIFT (19U)
/*! SW_PIC_WIDTH_IN_CBS - Picture width in min coded blocks (min = 8pix)
*/
#define VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_SHIFT)) & VPU_G2_SWREG4_SW_PIC_WIDTH_IN_CBS_MASK)
/*! @} */
/*! @name SWREG5 - Decoder control register 2 */
/*! @{ */
#define VPU_G2_SWREG5_SW_CU_QPD_E_MASK (0x10U)
#define VPU_G2_SWREG5_SW_CU_QPD_E_SHIFT (4U)
/*! SW_CU_QPD_E - CU qp delta enable
*/
#define VPU_G2_SWREG5_SW_CU_QPD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CU_QPD_E_SHIFT)) & VPU_G2_SWREG5_SW_CU_QPD_E_MASK)
#define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_MASK (0x7E0U)
#define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_SHIFT (5U)
/*! SW_MAX_CU_QPD_DEPTH - Max CU qp delta depth
*/
#define VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_SHIFT)) & VPU_G2_SWREG5_SW_MAX_CU_QPD_DEPTH_MASK)
#define VPU_G2_SWREG5_SW_TEMPOR_MVP_E_MASK (0x800U)
#define VPU_G2_SWREG5_SW_TEMPOR_MVP_E_SHIFT (11U)
/*! SW_TEMPOR_MVP_E - Temporal mvp enable
*/
#define VPU_G2_SWREG5_SW_TEMPOR_MVP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_TEMPOR_MVP_E_SHIFT)) & VPU_G2_SWREG5_SW_TEMPOR_MVP_E_MASK)
#define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_MASK (0x1000U)
#define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_SHIFT (12U)
/*! SW_SIGN_DATA_HIDE - Flag for stream decoding
*/
#define VPU_G2_SWREG5_SW_SIGN_DATA_HIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_SHIFT)) & VPU_G2_SWREG5_SW_SIGN_DATA_HIDE_MASK)
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET2_MASK (0x7C000U)
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET2_SHIFT (14U)
/*! SW_CH_QP_OFFSET2 - Chroma Qp filter offset for cr type
*/
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CH_QP_OFFSET2_SHIFT)) & VPU_G2_SWREG5_SW_CH_QP_OFFSET2_MASK)
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET_MASK (0xF80000U)
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET_SHIFT (19U)
/*! SW_CH_QP_OFFSET - Chroma Qp filter offset. (For HEVC this offset concerns Cb only)
*/
#define VPU_G2_SWREG5_SW_CH_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_CH_QP_OFFSET_SHIFT)) & VPU_G2_SWREG5_SW_CH_QP_OFFSET_MASK)
#define VPU_G2_SWREG5_SW_SCALING_LIST_E_MASK (0x1000000U)
#define VPU_G2_SWREG5_SW_SCALING_LIST_E_SHIFT (24U)
/*! SW_SCALING_LIST_E - Scaling matrix enable
* 0b0..Normal transform
* 0b1..Use scaling matrix for transform (read from external memory)
*/
#define VPU_G2_SWREG5_SW_SCALING_LIST_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_SCALING_LIST_E_SHIFT)) & VPU_G2_SWREG5_SW_SCALING_LIST_E_MASK)
#define VPU_G2_SWREG5_SW_STRM_START_BIT_MASK (0xFE000000U)
#define VPU_G2_SWREG5_SW_STRM_START_BIT_SHIFT (25U)
/*! SW_STRM_START_BIT - Exact bit of stream start word where decoding can be started (assosiates with sw_rlc_vlc_base)
*/
#define VPU_G2_SWREG5_SW_STRM_START_BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG5_SW_STRM_START_BIT_SHIFT)) & VPU_G2_SWREG5_SW_STRM_START_BIT_MASK)
/*! @} */
/*! @name SWREG6 - Decoder control register 3 */
/*! @{ */
#define VPU_G2_SWREG6_SW_STREAM_LEN_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG6_SW_STREAM_LEN_SHIFT (0U)
/*! SW_STREAM_LEN - Amount of stream data bytes in input buffer. If the given buffer size is not
* enough for finishing the picture the corresponding interrupt is given and new stream buffer base
* address and stream buffer size information should be given (assosiates with sw_rlc_vlc_base).
* For HEVC the buffer must include at least data for one slice/VP of the picture
*/
#define VPU_G2_SWREG6_SW_STREAM_LEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG6_SW_STREAM_LEN_SHIFT)) & VPU_G2_SWREG6_SW_STREAM_LEN_MASK)
/*! @} */
/*! @name SWREG7 - Decoder control register 4 */
/*! @{ */
#define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_MASK (0x38U)
#define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_SHIFT (3U)
/*! SW_SLICE_HDR_EBITS - Number of extra slice header bits (if enabled slice header extension)
*/
#define VPU_G2_SWREG7_SW_SLICE_HDR_EBITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_HDR_EBITS_MASK)
#define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_MASK (0x40U)
#define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_SHIFT (6U)
/*! SW_SLICE_HDR_EXT_E - Slice header extension enable. Reserved for future use
*/
#define VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_HDR_EXT_E_MASK)
#define VPU_G2_SWREG7_SW_FILT_OFFSET_TC_MASK (0xF80U)
#define VPU_G2_SWREG7_SW_FILT_OFFSET_TC_SHIFT (7U)
/*! SW_FILT_OFFSET_TC - Filter tc offset (declared as div2)
*/
#define VPU_G2_SWREG7_SW_FILT_OFFSET_TC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OFFSET_TC_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OFFSET_TC_MASK)
#define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_MASK (0x1F000U)
#define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_SHIFT (12U)
/*! SW_FILT_OFFSET_BETA - Filter beta offset (declared as div2)
*/
#define VPU_G2_SWREG7_SW_FILT_OFFSET_BETA(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OFFSET_BETA_MASK)
#define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_MASK (0x20000U)
#define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_SHIFT (17U)
/*! SW_STRONG_SMOOTH_E - Strong smoothing enable
*/
#define VPU_G2_SWREG7_SW_STRONG_SMOOTH_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_SHIFT)) & VPU_G2_SWREG7_SW_STRONG_SMOOTH_E_MASK)
#define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_MASK (0x40000U)
#define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_SHIFT (18U)
/*! SW_FILT_OVERRIDE_E - Filter override enable
*/
#define VPU_G2_SWREG7_SW_FILT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_SHIFT)) & VPU_G2_SWREG7_SW_FILT_OVERRIDE_E_MASK)
#define VPU_G2_SWREG7_SW_DEPEND_SLICE_E_MASK (0x80000U)
#define VPU_G2_SWREG7_SW_DEPEND_SLICE_E_SHIFT (19U)
/*! SW_DEPEND_SLICE_E - Dependent slice enable
*/
#define VPU_G2_SWREG7_SW_DEPEND_SLICE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_DEPEND_SLICE_E_SHIFT)) & VPU_G2_SWREG7_SW_DEPEND_SLICE_E_MASK)
#define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_MASK (0x100000U)
#define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_SHIFT (20U)
/*! SW_SLICE_CHQP_FLAG - Slice header flag for chroma QP present (if it is included in slice header)
*/
#define VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_SHIFT)) & VPU_G2_SWREG7_SW_SLICE_CHQP_FLAG_MASK)
#define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_MASK (0x200000U)
#define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_SHIFT (21U)
/*! SW_PCM_FILT_DISABLE - Disable for PCM loop filtering
*/
#define VPU_G2_SWREG7_SW_PCM_FILT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_SHIFT)) & VPU_G2_SWREG7_SW_PCM_FILT_DISABLE_MASK)
#define VPU_G2_SWREG7_SW_SAO_E_MASK (0x400000U)
#define VPU_G2_SWREG7_SW_SAO_E_SHIFT (22U)
/*! SW_SAO_E - Sample Adaptive Offset enable for stream decoding
*/
#define VPU_G2_SWREG7_SW_SAO_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_SAO_E_SHIFT)) & VPU_G2_SWREG7_SW_SAO_E_MASK)
#define VPU_G2_SWREG7_SW_ASYM_PRED_E_MASK (0x800000U)
#define VPU_G2_SWREG7_SW_ASYM_PRED_E_SHIFT (23U)
/*! SW_ASYM_PRED_E - Asymmetric prediction flag for stream decoding
*/
#define VPU_G2_SWREG7_SW_ASYM_PRED_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_ASYM_PRED_E_SHIFT)) & VPU_G2_SWREG7_SW_ASYM_PRED_E_MASK)
#define VPU_G2_SWREG7_SW_FILT_TILE_BORDER_MASK (0x1000000U)
#define VPU_G2_SWREG7_SW_FILT_TILE_BORDER_SHIFT (24U)
/*! SW_FILT_TILE_BORDER - Filter enable over tile border
*/
#define VPU_G2_SWREG7_SW_FILT_TILE_BORDER(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_TILE_BORDER_SHIFT)) & VPU_G2_SWREG7_SW_FILT_TILE_BORDER_MASK)
#define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_MASK (0x2000000U)
#define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_SHIFT (25U)
/*! SW_FILT_SLICE_BORDER - Filter enable over slice border
*/
#define VPU_G2_SWREG7_SW_FILT_SLICE_BORDER(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_SHIFT)) & VPU_G2_SWREG7_SW_FILT_SLICE_BORDER_MASK)
#define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_MASK (0xC000000U)
#define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT (26U)
/*! SW_WEIGHT_BIPR_IDC - Weighted prediction specification
* 0b00..Default weighted prediction is applied to B slices
* 0b01..Explicit weighted prediction shall be applied to B slices
* 0b10..NA
* 0b11..NA
*/
#define VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_SHIFT)) & VPU_G2_SWREG7_SW_WEIGHT_BIPR_IDC_MASK)
#define VPU_G2_SWREG7_SW_WEIGHT_PRED_E_MASK (0x10000000U)
#define VPU_G2_SWREG7_SW_WEIGHT_PRED_E_SHIFT (28U)
/*! SW_WEIGHT_PRED_E - Weighted prediction enable for P slices
*/
#define VPU_G2_SWREG7_SW_WEIGHT_PRED_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_WEIGHT_PRED_E_SHIFT)) & VPU_G2_SWREG7_SW_WEIGHT_PRED_E_MASK)
#define VPU_G2_SWREG7_SW_BLACKWHITE_E_MASK (0x40000000U)
#define VPU_G2_SWREG7_SW_BLACKWHITE_E_SHIFT (30U)
/*! SW_BLACKWHITE_E - Sampling
* 0b0..4:2:0 sampling format
* 0b1..4:0:0 sampling format (H264 monochroma)
*/
#define VPU_G2_SWREG7_SW_BLACKWHITE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_BLACKWHITE_E_SHIFT)) & VPU_G2_SWREG7_SW_BLACKWHITE_E_MASK)
#define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_MASK (0x80000000U)
#define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_SHIFT (31U)
/*! SW_CABAC_INIT_PRESENT - CABAC init present enable for stream decoding
*/
#define VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_SHIFT)) & VPU_G2_SWREG7_SW_CABAC_INIT_PRESENT_MASK)
/*! @} */
/*! @name SWREG8 - Decoder control register 5 */
/*! @{ */
#define VPU_G2_SWREG8_SW_OUTPUT_FORMAT_MASK (0x7U)
#define VPU_G2_SWREG8_SW_OUTPUT_FORMAT_SHIFT (0U)
/*! SW_OUTPUT_FORMAT - Raster scan and down scale output data format
* 0b000..Each pixel in 10 bits when luma or chroma pixel bit depth is larger than 8; or 8 bits when both luma
* and chroma pixel bit depth are 8 bits. (default)
* 0b001..Store in P010 format when luma or chroma pixel bit depth is larger than 8.
* 0b010..A customized format: please refer to register SWREG23[6].
*/
#define VPU_G2_SWREG8_SW_OUTPUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_OUTPUT_FORMAT_SHIFT)) & VPU_G2_SWREG8_SW_OUTPUT_FORMAT_MASK)
#define VPU_G2_SWREG8_SW_OUTPUT_8_BITS_MASK (0x8U)
#define VPU_G2_SWREG8_SW_OUTPUT_8_BITS_SHIFT (3U)
/*! SW_OUTPUT_8_BITS - enable rasterscan output force to 8 bit(only for hevc main10 and vp9 10bit)
*/
#define VPU_G2_SWREG8_SW_OUTPUT_8_BITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_OUTPUT_8_BITS_SHIFT)) & VPU_G2_SWREG8_SW_OUTPUT_8_BITS_MASK)
#define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_MASK (0x30U)
#define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_SHIFT (4U)
/*! SW_BIT_DEPTH_C_MINUS8 - Bit depth of chroma samples minus 8
*/
#define VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_SHIFT)) & VPU_G2_SWREG8_SW_BIT_DEPTH_C_MINUS8_MASK)
#define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_MASK (0xC0U)
#define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_SHIFT (6U)
/*! SW_BIT_DEPTH_Y_MINUS8 - Bit depth of luma samples minus 8
*/
#define VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_SHIFT)) & VPU_G2_SWREG8_SW_BIT_DEPTH_Y_MINUS8_MASK)
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_MASK (0xF00U)
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_SHIFT (8U)
/*! SW_PCM_BITDEPTH_C - Bit depth for PCM C data
*/
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_C(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_SHIFT)) & VPU_G2_SWREG8_SW_PCM_BITDEPTH_C_MASK)
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_MASK (0xF000U)
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_SHIFT (12U)
/*! SW_PCM_BITDEPTH_Y - Bit depth for PCM Y data
*/
#define VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_SHIFT)) & VPU_G2_SWREG8_SW_PCM_BITDEPTH_Y_MASK)
#define VPU_G2_SWREG8_SW_IDR_PIC_E_MASK (0x10000U)
#define VPU_G2_SWREG8_SW_IDR_PIC_E_SHIFT (16U)
/*! SW_IDR_PIC_E - IDR (instantaneous decoding refresh) picture flag.
*/
#define VPU_G2_SWREG8_SW_IDR_PIC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_IDR_PIC_E_SHIFT)) & VPU_G2_SWREG8_SW_IDR_PIC_E_MASK)
#define VPU_G2_SWREG8_SW_FILT_CTRL_PRES_MASK (0x40000000U)
#define VPU_G2_SWREG8_SW_FILT_CTRL_PRES_SHIFT (30U)
/*! SW_FILT_CTRL_PRES - deblocking_filter_control_present_flag indicates whether extra variables
* controlling characteristics of the deblocking filter are present in the slice header.
*/
#define VPU_G2_SWREG8_SW_FILT_CTRL_PRES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_FILT_CTRL_PRES_SHIFT)) & VPU_G2_SWREG8_SW_FILT_CTRL_PRES_MASK)
#define VPU_G2_SWREG8_SW_CONST_INTRA_E_MASK (0x80000000U)
#define VPU_G2_SWREG8_SW_CONST_INTRA_E_SHIFT (31U)
/*! SW_CONST_INTRA_E - constrained_intra_pred_flag equal to 1 specifies that intra prediction uses
* only neighbouring intra macroblocks in prediction. When equal to 0 also neighbouring inter
* macroblocks are used in intra prediction process.
*/
#define VPU_G2_SWREG8_SW_CONST_INTRA_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG8_SW_CONST_INTRA_E_SHIFT)) & VPU_G2_SWREG8_SW_CONST_INTRA_E_MASK)
/*! @} */
/*! @name SWREG9 - Decoder control register 6 */
/*! @{ */
#define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_MASK (0x3FFFU)
#define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_SHIFT (0U)
/*! SW_HDR_SKIP_LENGTH - Length of slice header skip length (bytes used by sw)
*/
#define VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_SHIFT)) & VPU_G2_SWREG9_SW_HDR_SKIP_LENGTH_MASK)
#define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_MASK (0x7C000U)
#define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_SHIFT (14U)
/*! SW_REFIDX0_ACTIVE - Specifies the maximum reference index that can be used while decoding inter
* predicted macro blocks. This is same as in previous decoders (width increased with q bit)
*/
#define VPU_G2_SWREG9_SW_REFIDX0_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_SHIFT)) & VPU_G2_SWREG9_SW_REFIDX0_ACTIVE_MASK)
#define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_MASK (0xF80000U)
#define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_SHIFT (19U)
/*! SW_REFIDX1_ACTIVE - Specifies the maximum reference index that can be used while decoding inter predicted macro blocks.
*/
#define VPU_G2_SWREG9_SW_REFIDX1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_SHIFT)) & VPU_G2_SWREG9_SW_REFIDX1_ACTIVE_MASK)
/*! @} */
/*! @name SWREG10 - Decoder control register 7 */
/*! @{ */
#define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_MASK (0x1U)
#define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_SHIFT (0U)
/*! SW_ENTR_CODE_SYNCH_E - Entropy coding synchronization enable (Possible parallel cabac decoding)
*/
#define VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_SHIFT)) & VPU_G2_SWREG10_SW_ENTR_CODE_SYNCH_E_MASK)
#define VPU_G2_SWREG10_SW_TILE_ENABLE_MASK (0x2U)
#define VPU_G2_SWREG10_SW_TILE_ENABLE_SHIFT (1U)
/*! SW_TILE_ENABLE - Tile enable
*/
#define VPU_G2_SWREG10_SW_TILE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_TILE_ENABLE_SHIFT)) & VPU_G2_SWREG10_SW_TILE_ENABLE_MASK)
#define VPU_G2_SWREG10_SW_NUM_TILE_ROWS_MASK (0x7C000U)
#define VPU_G2_SWREG10_SW_NUM_TILE_ROWS_SHIFT (14U)
/*! SW_NUM_TILE_ROWS - Number of tile rows in picture
*/
#define VPU_G2_SWREG10_SW_NUM_TILE_ROWS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_NUM_TILE_ROWS_SHIFT)) & VPU_G2_SWREG10_SW_NUM_TILE_ROWS_MASK)
#define VPU_G2_SWREG10_SW_NUM_TILE_COLS_MASK (0xF80000U)
#define VPU_G2_SWREG10_SW_NUM_TILE_COLS_SHIFT (19U)
/*! SW_NUM_TILE_COLS - Number of tile columns in picture
*/
#define VPU_G2_SWREG10_SW_NUM_TILE_COLS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_NUM_TILE_COLS_SHIFT)) & VPU_G2_SWREG10_SW_NUM_TILE_COLS_MASK)
#define VPU_G2_SWREG10_SW_INIT_QP_MASK (0x7F000000U)
#define VPU_G2_SWREG10_SW_INIT_QP_SHIFT (24U)
/*! SW_INIT_QP - Initial value for quantization parameter (picture quantizer).
*/
#define VPU_G2_SWREG10_SW_INIT_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_INIT_QP_SHIFT)) & VPU_G2_SWREG10_SW_INIT_QP_MASK)
#define VPU_G2_SWREG10_SW_START_CODE_E_MASK (0x80000000U)
#define VPU_G2_SWREG10_SW_START_CODE_E_SHIFT (31U)
/*! SW_START_CODE_E - Bit for indicating stream start code existence
* 0b0..Stream does not contain start codes
* 0b1..Stream contains start codes
*/
#define VPU_G2_SWREG10_SW_START_CODE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG10_SW_START_CODE_E_SHIFT)) & VPU_G2_SWREG10_SW_START_CODE_E_MASK)
/*! @} */
/*! @name SWREG11 - Decoder control register 8 */
/*! @{ */
#define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_MASK (0x1U)
#define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_SHIFT (0U)
/*! SW_AREF_SIGN_BIAS - Alternate reference picture sign bias used for motion vector decoding
*/
#define VPU_G2_SWREG11_SW_AREF_SIGN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_SHIFT)) & VPU_G2_SWREG11_SW_AREF_SIGN_BIAS_MASK)
#define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_MASK (0x4U)
#define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_SHIFT (2U)
/*! SW_GREF_SIGN_BIAS - Golden reference picture sign bias used for motion vector decoding
*/
#define VPU_G2_SWREG11_SW_GREF_SIGN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_SHIFT)) & VPU_G2_SWREG11_SW_GREF_SIGN_BIAS_MASK)
#define VPU_G2_SWREG11_SW_COMP_PRED_MODE_MASK (0x30U)
#define VPU_G2_SWREG11_SW_COMP_PRED_MODE_SHIFT (4U)
/*! SW_COMP_PRED_MODE - Prediction Comp Type
* 0b00..Single prediction only
* 0b01..COMP prediction only
* 0b10..Hybrid prediction
*/
#define VPU_G2_SWREG11_SW_COMP_PRED_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_COMP_PRED_MODE_SHIFT)) & VPU_G2_SWREG11_SW_COMP_PRED_MODE_MASK)
#define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_MASK (0x80U)
#define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_SHIFT (7U)
/*! SW_HIGH_PREC_MV_E - High precision MV prediction enable
*/
#define VPU_G2_SWREG11_SW_HIGH_PREC_MV_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_SHIFT)) & VPU_G2_SWREG11_SW_HIGH_PREC_MV_E_MASK)
#define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_MASK (0x700U)
#define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_SHIFT (8U)
/*! SW_MCOMP_FILT_TYPE - Inter prediction filter type to stream decoder
* 0b000..Eight tap smooth
* 0b001..Eight tap
* 0b010..Eight tap sharp
* 0b011..Bilinear
* 0b100..Switchable
*/
#define VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_SHIFT)) & VPU_G2_SWREG11_SW_MCOMP_FILT_TYPE_MASK)
#define VPU_G2_SWREG11_SW_FILT_TYPE_MASK (0x80000U)
#define VPU_G2_SWREG11_SW_FILT_TYPE_SHIFT (19U)
/*! SW_FILT_TYPE - Filter Type
*/
#define VPU_G2_SWREG11_SW_FILT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_FILT_TYPE_SHIFT)) & VPU_G2_SWREG11_SW_FILT_TYPE_MASK)
#define VPU_G2_SWREG11_SW_FILT_SHARPNESS_MASK (0xE00000U)
#define VPU_G2_SWREG11_SW_FILT_SHARPNESS_SHIFT (21U)
/*! SW_FILT_SHARPNESS - Filter sharpness value
*/
#define VPU_G2_SWREG11_SW_FILT_SHARPNESS(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_FILT_SHARPNESS_SHIFT)) & VPU_G2_SWREG11_SW_FILT_SHARPNESS_MASK)
#define VPU_G2_SWREG11_SW_TRANSFORM_MODE_MASK (0x38000000U)
#define VPU_G2_SWREG11_SW_TRANSFORM_MODE_SHIFT (27U)
/*! SW_TRANSFORM_MODE - Transform modes
* 0b000..4x4 only
* 0b001..Allow 8x8
* 0b010..Allow 16x16
* 0b011..Allow 32x32
* 0b100..TX mode select
*/
#define VPU_G2_SWREG11_SW_TRANSFORM_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG11_SW_TRANSFORM_MODE_SHIFT)) & VPU_G2_SWREG11_SW_TRANSFORM_MODE_MASK)
/*! @} */
/*! @name SWREG12 - Decoder control register 9 */
/*! @{ */
#define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_MASK (0x1U)
#define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_SHIFT (0U)
/*! SW_REFPICLIST_MOD_E - Refpic list reordering flag
*/
#define VPU_G2_SWREG12_SW_REFPICLIST_MOD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_SHIFT)) & VPU_G2_SWREG12_SW_REFPICLIST_MOD_E_MASK)
#define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_MASK (0x2U)
#define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_SHIFT (1U)
/*! SW_TRANSQ_BYPASS_E - Transform bypass flag (lossless mode)
*/
#define VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_SHIFT)) & VPU_G2_SWREG12_SW_TRANSQ_BYPASS_E_MASK)
#define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_MASK (0x4U)
#define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_SHIFT (2U)
/*! SW_TRANSFORM_SKIP_E - Transform skipping flag
*/
#define VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_SHIFT)) & VPU_G2_SWREG12_SW_TRANSFORM_SKIP_E_MASK)
#define VPU_G2_SWREG12_SW_PCM_E_MASK (0x8U)
#define VPU_G2_SWREG12_SW_PCM_E_SHIFT (3U)
/*! SW_PCM_E - IPCM MBs flag
*/
#define VPU_G2_SWREG12_SW_PCM_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_PCM_E_SHIFT)) & VPU_G2_SWREG12_SW_PCM_E_MASK)
#define VPU_G2_SWREG12_SW_MAX_PCM_SIZE_MASK (0x70U)
#define VPU_G2_SWREG12_SW_MAX_PCM_SIZE_SHIFT (4U)
/*! SW_MAX_PCM_SIZE - PCM max size (2^N):
* 0b011..8 pix
* 0b100..16 pix
* 0b101..32 pix
* 0b110..64 pix
*/
#define VPU_G2_SWREG12_SW_MAX_PCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MAX_PCM_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MAX_PCM_SIZE_MASK)
#define VPU_G2_SWREG12_SW_MIN_PCM_SIZE_MASK (0x380U)
#define VPU_G2_SWREG12_SW_MIN_PCM_SIZE_SHIFT (7U)
/*! SW_MIN_PCM_SIZE - PCM min size (2^N):
* 0b011..8 pix
* 0b100..16 pix
* 0b101..32 pix
* 0b110..64 pix
*/
#define VPU_G2_SWREG12_SW_MIN_PCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MIN_PCM_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MIN_PCM_SIZE_MASK)
#define VPU_G2_SWREG12_SW_MAX_CB_SIZE_MASK (0x1C00U)
#define VPU_G2_SWREG12_SW_MAX_CB_SIZE_SHIFT (10U)
/*! SW_MAX_CB_SIZE - CodedBlock max size (2^N):
* 0b011..8 pix
* 0b100..16 pix
* 0b101..32 pix
* 0b110..64 pix
*/
#define VPU_G2_SWREG12_SW_MAX_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MAX_CB_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MAX_CB_SIZE_MASK)
#define VPU_G2_SWREG12_SW_MIN_CB_SIZE_MASK (0xE000U)
#define VPU_G2_SWREG12_SW_MIN_CB_SIZE_SHIFT (13U)
/*! SW_MIN_CB_SIZE - CodedBlock min size (2^N):
* 0b011..8 pix
* 0b100..16 pix
* 0b101..32 pix
* 0b110..64 pix
*/
#define VPU_G2_SWREG12_SW_MIN_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_MIN_CB_SIZE_SHIFT)) & VPU_G2_SWREG12_SW_MIN_CB_SIZE_MASK)
#define VPU_G2_SWREG12_SW_REFER_LTERM_E_MASK (0xFFFF0000U)
#define VPU_G2_SWREG12_SW_REFER_LTERM_E_SHIFT (16U)
/*! SW_REFER_LTERM_E - Long term flag for reference picture index Definition: Bit 31 for picture index 0 Bit 30 for picture index 1 etc.
*/
#define VPU_G2_SWREG12_SW_REFER_LTERM_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG12_SW_REFER_LTERM_E_SHIFT)) & VPU_G2_SWREG12_SW_REFER_LTERM_E_MASK)
/*! @} */
/*! @name SWREG13 - Decoder control register 10 */
/*! @{ */
#define VPU_G2_SWREG13_DEC_CTRL_REG10_BF_MASK (0x1FFFFFFFU)
#define VPU_G2_SWREG13_DEC_CTRL_REG10_BF_SHIFT (0U)
#define VPU_G2_SWREG13_DEC_CTRL_REG10_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG13_DEC_CTRL_REG10_BF_SHIFT)) & VPU_G2_SWREG13_DEC_CTRL_REG10_BF_MASK)
/*! @} */
/*! @name SWREG14 - Initial ref pic list register (0-2) */
/*! @{ */
#define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_SHIFT (0U)
#define VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_SHIFT)) & VPU_G2_SWREG14_INIT_REF_PIC_0_2_BF_MASK)
/*! @} */
/*! @name SWREG15 - Initial ref pic list register (3-5) */
/*! @{ */
#define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_SHIFT (0U)
#define VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_SHIFT)) & VPU_G2_SWREG15_INIT_REF_PIC_3_5_BF_MASK)
/*! @} */
/*! @name SWREG16 - Initial ref pic list register (6-8) */
/*! @{ */
#define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_SHIFT (0U)
#define VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_SHIFT)) & VPU_G2_SWREG16_INIT_REF_PIC_6_8_BF_MASK)
/*! @} */
/*! @name SWREG17 - Initial ref pic list register (9-11) */
/*! @{ */
#define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_SHIFT (0U)
#define VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_SHIFT)) & VPU_G2_SWREG17_INIT_REF_PIC_9_11_BF_MASK)
/*! @} */
/*! @name SWREG18 - Initial ref pic list register (12-14) */
/*! @{ */
#define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_SHIFT (0U)
#define VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_SHIFT)) & VPU_G2_SWREG18_INIT_REF_PIC_12_14_BF_MASK)
/*! @} */
/*! @name SWREG19 - Initial ref pic list register (15 and P 0-3) */
/*! @{ */
#define VPU_G2_SWREG19_INIT_REF_PIC_15_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG19_INIT_REF_PIC_15_BF_SHIFT (0U)
#define VPU_G2_SWREG19_INIT_REF_PIC_15_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG19_INIT_REF_PIC_15_BF_SHIFT)) & VPU_G2_SWREG19_INIT_REF_PIC_15_BF_MASK)
/*! @} */
/*! @name SWREG20 - Decoder control register 11 */
/*! @{ */
#define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_MASK (0xFFFU)
#define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_SHIFT (0U)
/*! SW_PIC_HEIGHT_4X4 - Current picture height in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks)
*/
#define VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_SHIFT)) & VPU_G2_SWREG20_SW_PIC_HEIGHT_4X4_MASK)
#define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_MASK (0xFFF0000U)
#define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_SHIFT (16U)
/*! SW_PIC_WIDTH_4X4 - Current picture width in 4x4 blocks (Needed to reduce overlapping HW conditions in various blocks)
*/
#define VPU_G2_SWREG20_SW_PIC_WIDTH_4X4(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_SHIFT)) & VPU_G2_SWREG20_SW_PIC_WIDTH_4X4_MASK)
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_MASK (0x40000000U)
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_SHIFT (30U)
/*! SW_PARTIAL_CTB_Y - Picture height not multiple of CTB size
*/
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_SHIFT)) & VPU_G2_SWREG20_SW_PARTIAL_CTB_Y_MASK)
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_X_MASK (0x80000000U)
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_X_SHIFT (31U)
/*! SW_PARTIAL_CTB_X - Picture width not multiple of CTB size
*/
#define VPU_G2_SWREG20_SW_PARTIAL_CTB_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG20_SW_PARTIAL_CTB_X_SHIFT)) & VPU_G2_SWREG20_SW_PARTIAL_CTB_X_MASK)
/*! @} */
/*! @name SWREG23 - Decoder configure status register */
/*! @{ */
#define VPU_G2_SWREG23_SW_HEVC_SUPPORT_MASK (0x1U)
#define VPU_G2_SWREG23_SW_HEVC_SUPPORT_SHIFT (0U)
/*! SW_HEVC_SUPPORT - HEVC support
* 0b0..Do not support HEVC
* 0b1..Support HEVC
*/
#define VPU_G2_SWREG23_SW_HEVC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_HEVC_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_HEVC_SUPPORT_MASK)
#define VPU_G2_SWREG23_SW_VP9_SUPPORT_MASK (0x2U)
#define VPU_G2_SWREG23_SW_VP9_SUPPORT_SHIFT (1U)
/*! SW_VP9_SUPPORT - VP9 support
* 0b0..Do not support VP9
* 0b1..Support VP9
*/
#define VPU_G2_SWREG23_SW_VP9_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_VP9_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_VP9_SUPPORT_MASK)
#define VPU_G2_SWREG23_SW_RFC_SUPPORT_MASK (0x4U)
#define VPU_G2_SWREG23_SW_RFC_SUPPORT_SHIFT (2U)
/*! SW_RFC_SUPPORT - RFC support
* 0b0..Do not support RFC
* 0b1..Support RFC
*/
#define VPU_G2_SWREG23_SW_RFC_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_RFC_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_RFC_SUPPORT_MASK)
#define VPU_G2_SWREG23_SW_DOWN_SUPPORT_MASK (0x8U)
#define VPU_G2_SWREG23_SW_DOWN_SUPPORT_SHIFT (3U)
/*! SW_DOWN_SUPPORT - Downscale support
* 0b0..Do not support downscale
* 0b1..Support downscale
*/
#define VPU_G2_SWREG23_SW_DOWN_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DOWN_SUPPORT_SHIFT)) & VPU_G2_SWREG23_SW_DOWN_SUPPORT_MASK)
#define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_MASK (0x10U)
#define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_SHIFT (4U)
/*! SW_DEC_64BIT_AD_E - 64 bit addressing of master interface support
* 0b0..Not supported (32 bit addressing)
* 0b1..Supported
*/
#define VPU_G2_SWREG23_SW_DEC_64BIT_AD_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_64BIT_AD_E_MASK)
#define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_MASK (0x20U)
#define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_SHIFT (5U)
/*! SW_DEC_FORMAT_P010_E - P010 output format support
* 0b0..Not supported
* 0b1..Supported
*/
#define VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_FORMAT_P010_E_MASK)
#define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_MASK (0x40U)
#define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_SHIFT (6U)
/*! SW_DEC_FORMAT_CUSTOMER1_E - Customized output format support
* 0b0..Not supported
* 0b1..Supported
*/
#define VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_SHIFT)) & VPU_G2_SWREG23_SW_DEC_FORMAT_CUSTOMER1_E_MASK)
#define VPU_G2_SWREG23_SW_MULTI_PREFETCH_MASK (0x80U)
#define VPU_G2_SWREG23_SW_MULTI_PREFETCH_SHIFT (7U)
/*! SW_MULTI_PREFETCH - Multi-Reference Blocks Prefetch
* 0b0..Not supported
* 0b1..Supported
*/
#define VPU_G2_SWREG23_SW_MULTI_PREFETCH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_MULTI_PREFETCH_SHIFT)) & VPU_G2_SWREG23_SW_MULTI_PREFETCH_MASK)
#define VPU_G2_SWREG23_SW_HEVC_VERSION_MASK (0xF00U)
#define VPU_G2_SWREG23_SW_HEVC_VERSION_SHIFT (8U)
/*! SW_HEVC_VERSION - HEVC version
* 0b0000..main8
* 0b0001..main10
*/
#define VPU_G2_SWREG23_SW_HEVC_VERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_HEVC_VERSION_SHIFT)) & VPU_G2_SWREG23_SW_HEVC_VERSION_MASK)
#define VPU_G2_SWREG23_SW_VP9_PROFILE_MASK (0xF000U)
#define VPU_G2_SWREG23_SW_VP9_PROFILE_SHIFT (12U)
/*! SW_VP9_PROFILE - VP9 version
* 0b0000..vp9 profile 0
* 0b0001..vp9 profile 2 - 10bits
*/
#define VPU_G2_SWREG23_SW_VP9_PROFILE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG23_SW_VP9_PROFILE_SHIFT)) & VPU_G2_SWREG23_SW_VP9_PROFILE_MASK)
/*! @} */
/*! @name SWREG31 - VP9 segmentation values */
/*! @{ */
#define VPU_G2_SWREG31_SW_QUANT_SEG6_MASK (0xFFU)
#define VPU_G2_SWREG31_SW_QUANT_SEG6_SHIFT (0U)
/*! SW_QUANT_SEG6 - Segment quantization parameter
*/
#define VPU_G2_SWREG31_SW_QUANT_SEG6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_QUANT_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_QUANT_SEG6_MASK)
#define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_MASK (0x3F00U)
#define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_SHIFT (8U)
/*! SW_FILT_LEVEL_SEG6 - Segment filter level
*/
#define VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_FILT_LEVEL_SEG6_MASK)
#define VPU_G2_SWREG31_SW_SKIP_SEG6_MASK (0x4000U)
#define VPU_G2_SWREG31_SW_SKIP_SEG6_SHIFT (14U)
/*! SW_SKIP_SEG6 - Segment skip enable
*/
#define VPU_G2_SWREG31_SW_SKIP_SEG6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_SKIP_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_SKIP_SEG6_MASK)
#define VPU_G2_SWREG31_SW_REFPIC_SEG6_MASK (0x38000U)
#define VPU_G2_SWREG31_SW_REFPIC_SEG6_SHIFT (15U)
/*! SW_REFPIC_SEG6 - Segment refer picture
*/
#define VPU_G2_SWREG31_SW_REFPIC_SEG6(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG31_SW_REFPIC_SEG6_SHIFT)) & VPU_G2_SWREG31_SW_REFPIC_SEG6_MASK)
/*! @} */
/*! @name SWREG32 - VP9 segmentation values */
/*! @{ */
#define VPU_G2_SWREG32_SW_QUANT_SEG7_MASK (0xFFU)
#define VPU_G2_SWREG32_SW_QUANT_SEG7_SHIFT (0U)
/*! SW_QUANT_SEG7 - Segment quantization parameter
*/
#define VPU_G2_SWREG32_SW_QUANT_SEG7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_QUANT_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_QUANT_SEG7_MASK)
#define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_MASK (0x3F00U)
#define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_SHIFT (8U)
/*! SW_FILT_LEVEL_SEG7 - Segment filter level
*/
#define VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_FILT_LEVEL_SEG7_MASK)
#define VPU_G2_SWREG32_SW_SKIP_SEG7_MASK (0x4000U)
#define VPU_G2_SWREG32_SW_SKIP_SEG7_SHIFT (14U)
/*! SW_SKIP_SEG7 - Segment skip enable
*/
#define VPU_G2_SWREG32_SW_SKIP_SEG7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_SKIP_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_SKIP_SEG7_MASK)
#define VPU_G2_SWREG32_SW_REFPIC_SEG7_MASK (0x38000U)
#define VPU_G2_SWREG32_SW_REFPIC_SEG7_SHIFT (15U)
/*! SW_REFPIC_SEG7 - Segment refer picture
*/
#define VPU_G2_SWREG32_SW_REFPIC_SEG7(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG32_SW_REFPIC_SEG7_SHIFT)) & VPU_G2_SWREG32_SW_REFPIC_SEG7_MASK)
/*! @} */
/*! @name SWREG33 - VP9 reference picture scaling register 0 */
/*! @{ */
#define VPU_G2_SWREG33_SW_LREF_HEIGHT_MASK (0xFFFFU)
#define VPU_G2_SWREG33_SW_LREF_HEIGHT_SHIFT (0U)
/*! SW_LREF_HEIGHT - Accurate height of last (previous) reference picture in pixels
*/
#define VPU_G2_SWREG33_SW_LREF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG33_SW_LREF_HEIGHT_SHIFT)) & VPU_G2_SWREG33_SW_LREF_HEIGHT_MASK)
#define VPU_G2_SWREG33_SW_LREF_WIDTH_MASK (0xFFFF0000U)
#define VPU_G2_SWREG33_SW_LREF_WIDTH_SHIFT (16U)
/*! SW_LREF_WIDTH - Accurate width of last (previous) reference picture in pixels
*/
#define VPU_G2_SWREG33_SW_LREF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG33_SW_LREF_WIDTH_SHIFT)) & VPU_G2_SWREG33_SW_LREF_WIDTH_MASK)
/*! @} */
/*! @name SWREG34 - VP9 reference picture scaling register 1 */
/*! @{ */
#define VPU_G2_SWREG34_SW_GREF_HEIGHT_MASK (0xFFFFU)
#define VPU_G2_SWREG34_SW_GREF_HEIGHT_SHIFT (0U)
/*! SW_GREF_HEIGHT - Accurate height of golden reference picture in pixels
*/
#define VPU_G2_SWREG34_SW_GREF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG34_SW_GREF_HEIGHT_SHIFT)) & VPU_G2_SWREG34_SW_GREF_HEIGHT_MASK)
#define VPU_G2_SWREG34_SW_GREF_WIDTH_MASK (0xFFFF0000U)
#define VPU_G2_SWREG34_SW_GREF_WIDTH_SHIFT (16U)
/*! SW_GREF_WIDTH - Accurate width of golden reference picture in pixels
*/
#define VPU_G2_SWREG34_SW_GREF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG34_SW_GREF_WIDTH_SHIFT)) & VPU_G2_SWREG34_SW_GREF_WIDTH_MASK)
/*! @} */
/*! @name SWREG35 - VP9 reference picture scaling register 2 */
/*! @{ */
#define VPU_G2_SWREG35_SW_AREF_HEIGHT_MASK (0xFFFFU)
#define VPU_G2_SWREG35_SW_AREF_HEIGHT_SHIFT (0U)
/*! SW_AREF_HEIGHT - Accurate height of alternate reference picture in pixels
*/
#define VPU_G2_SWREG35_SW_AREF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG35_SW_AREF_HEIGHT_SHIFT)) & VPU_G2_SWREG35_SW_AREF_HEIGHT_MASK)
#define VPU_G2_SWREG35_SW_AREF_WIDTH_MASK (0xFFFF0000U)
#define VPU_G2_SWREG35_SW_AREF_WIDTH_SHIFT (16U)
/*! SW_AREF_WIDTH - Accurate width of alternate reference picture in pixels
*/
#define VPU_G2_SWREG35_SW_AREF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG35_SW_AREF_WIDTH_SHIFT)) & VPU_G2_SWREG35_SW_AREF_WIDTH_MASK)
/*! @} */
/*! @name SWREG36 - VP9 reference picture scaling register 3 */
/*! @{ */
#define VPU_G2_SWREG36_SW_LREF_VER_SCALE_MASK (0xFFFFU)
#define VPU_G2_SWREG36_SW_LREF_VER_SCALE_SHIFT (0U)
/*! SW_LREF_VER_SCALE - Vertical scaling factor for last (previous) reference picture
*/
#define VPU_G2_SWREG36_SW_LREF_VER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG36_SW_LREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG36_SW_LREF_VER_SCALE_MASK)
#define VPU_G2_SWREG36_SW_LREF_HOR_SCALE_MASK (0xFFFF0000U)
#define VPU_G2_SWREG36_SW_LREF_HOR_SCALE_SHIFT (16U)
/*! SW_LREF_HOR_SCALE - Horizontal scaling factor for last (previous) reference picture
*/
#define VPU_G2_SWREG36_SW_LREF_HOR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG36_SW_LREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG36_SW_LREF_HOR_SCALE_MASK)
/*! @} */
/*! @name SWREG37 - VP9 reference picture scaling register 4 */
/*! @{ */
#define VPU_G2_SWREG37_SW_GREF_VER_SCALE_MASK (0xFFFFU)
#define VPU_G2_SWREG37_SW_GREF_VER_SCALE_SHIFT (0U)
/*! SW_GREF_VER_SCALE - Vertical scaling factor for golden reference picture
*/
#define VPU_G2_SWREG37_SW_GREF_VER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG37_SW_GREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG37_SW_GREF_VER_SCALE_MASK)
#define VPU_G2_SWREG37_SW_GREF_HOR_SCALE_MASK (0xFFFF0000U)
#define VPU_G2_SWREG37_SW_GREF_HOR_SCALE_SHIFT (16U)
/*! SW_GREF_HOR_SCALE - Horizontal scaling factor for golden reference picture
*/
#define VPU_G2_SWREG37_SW_GREF_HOR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG37_SW_GREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG37_SW_GREF_HOR_SCALE_MASK)
/*! @} */
/*! @name SWREG38 - VP9 reference picture scaling register 5 */
/*! @{ */
#define VPU_G2_SWREG38_SW_AREF_VER_SCALE_MASK (0xFFFFU)
#define VPU_G2_SWREG38_SW_AREF_VER_SCALE_SHIFT (0U)
/*! SW_AREF_VER_SCALE - Vertical scaling factor for alternate reference picture
*/
#define VPU_G2_SWREG38_SW_AREF_VER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG38_SW_AREF_VER_SCALE_SHIFT)) & VPU_G2_SWREG38_SW_AREF_VER_SCALE_MASK)
#define VPU_G2_SWREG38_SW_AREF_HOR_SCALE_MASK (0xFFFF0000U)
#define VPU_G2_SWREG38_SW_AREF_HOR_SCALE_SHIFT (16U)
/*! SW_AREF_HOR_SCALE - Horizontal scaling factor for alternate reference picture
*/
#define VPU_G2_SWREG38_SW_AREF_HOR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG38_SW_AREF_HOR_SCALE_SHIFT)) & VPU_G2_SWREG38_SW_AREF_HOR_SCALE_MASK)
/*! @} */
/*! @name SWREG45 - Timeout control register */
/*! @{ */
#define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_MASK (0x7FFFFFFFU)
#define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_SHIFT (0U)
/*! SW_TIMEOUT_CYCLES - Amount of clock cycles to trigger timeout interrupt if no external master
* activity acknowledged. Used if sw_timeout_override_e is set
*/
#define VPU_G2_SWREG45_SW_TIMEOUT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_G2_SWREG45_SW_TIMEOUT_CYCLES_MASK)
#define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_MASK (0x80000000U)
#define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_SHIFT (31U)
/*! SW_TIMEOUT_OVERRIDE_E - Enable for SW controlled timeout. If enabled the sw_timeout_cycles is
* used to detect HW timeout instead of hard coded HW value
*/
#define VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_G2_SWREG45_SW_TIMEOUT_OVERRIDE_E_MASK)
/*! @} */
/*! @name SWREG46 - Picture order count from current pictures for index 0-3 */
/*! @{ */
#define VPU_G2_SWREG46_PIC_ORD_0_3_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG46_PIC_ORD_0_3_BF_SHIFT (0U)
#define VPU_G2_SWREG46_PIC_ORD_0_3_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG46_PIC_ORD_0_3_BF_SHIFT)) & VPU_G2_SWREG46_PIC_ORD_0_3_BF_MASK)
/*! @} */
/*! @name SWREG47 - Picture order count from current pictures for index 4-7 */
/*! @{ */
#define VPU_G2_SWREG47_PIC_ORD_4_7_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG47_PIC_ORD_4_7_BF_SHIFT (0U)
#define VPU_G2_SWREG47_PIC_ORD_4_7_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG47_PIC_ORD_4_7_BF_SHIFT)) & VPU_G2_SWREG47_PIC_ORD_4_7_BF_MASK)
/*! @} */
/*! @name SWREG48 - Picture order count from current pictures for index 8-11 */
/*! @{ */
#define VPU_G2_SWREG48_SW_CUR_POC_11_MASK (0xFFU)
#define VPU_G2_SWREG48_SW_CUR_POC_11_SHIFT (0U)
/*! SW_CUR_POC_11 - Picture order count from current picture 11
*/
#define VPU_G2_SWREG48_SW_CUR_POC_11(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_11_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_11_MASK)
#define VPU_G2_SWREG48_SW_CUR_POC_10_MASK (0xFF00U)
#define VPU_G2_SWREG48_SW_CUR_POC_10_SHIFT (8U)
/*! SW_CUR_POC_10 - Picture order count from current picture 10
*/
#define VPU_G2_SWREG48_SW_CUR_POC_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_10_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_10_MASK)
#define VPU_G2_SWREG48_SW_CUR_POC_09_MASK (0xFF0000U)
#define VPU_G2_SWREG48_SW_CUR_POC_09_SHIFT (16U)
/*! SW_CUR_POC_09 - Picture order count from current picture 9
*/
#define VPU_G2_SWREG48_SW_CUR_POC_09(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_09_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_09_MASK)
#define VPU_G2_SWREG48_SW_CUR_POC_08_MASK (0xFF000000U)
#define VPU_G2_SWREG48_SW_CUR_POC_08_SHIFT (24U)
/*! SW_CUR_POC_08 - Picture order count from current picture 8
*/
#define VPU_G2_SWREG48_SW_CUR_POC_08(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG48_SW_CUR_POC_08_SHIFT)) & VPU_G2_SWREG48_SW_CUR_POC_08_MASK)
/*! @} */
/*! @name SWREG49 - Picture order count from current pictures for index 12-15 */
/*! @{ */
#define VPU_G2_SWREG49_SW_CUR_POC_15_MASK (0xFFU)
#define VPU_G2_SWREG49_SW_CUR_POC_15_SHIFT (0U)
/*! SW_CUR_POC_15 - Picture order count from current picture 15
*/
#define VPU_G2_SWREG49_SW_CUR_POC_15(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_15_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_15_MASK)
#define VPU_G2_SWREG49_SW_CUR_POC_14_MASK (0xFF00U)
#define VPU_G2_SWREG49_SW_CUR_POC_14_SHIFT (8U)
/*! SW_CUR_POC_14 - Picture order count from current picture 14
*/
#define VPU_G2_SWREG49_SW_CUR_POC_14(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_14_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_14_MASK)
#define VPU_G2_SWREG49_SW_CUR_POC_13_MASK (0xFF0000U)
#define VPU_G2_SWREG49_SW_CUR_POC_13_SHIFT (16U)
/*! SW_CUR_POC_13 - Picture order count from current picture 13
*/
#define VPU_G2_SWREG49_SW_CUR_POC_13(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_13_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_13_MASK)
#define VPU_G2_SWREG49_SW_CUR_POC_12_MASK (0xFF000000U)
#define VPU_G2_SWREG49_SW_CUR_POC_12_SHIFT (24U)
/*! SW_CUR_POC_12 - Picture order count from current picture 12
*/
#define VPU_G2_SWREG49_SW_CUR_POC_12(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG49_SW_CUR_POC_12_SHIFT)) & VPU_G2_SWREG49_SW_CUR_POC_12_MASK)
/*! @} */
/*! @name SWREG50 - Synthesis configuration register decoder 0 (read only) */
/*! @{ */
#define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_MASK (0x7FFU)
#define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT (0U)
/*! SW_DEC_MAX_OWIDTH - Max configured decoder video resolution that can be decoded. Informed as width of the picture in pixels
*/
#define VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_SHIFT)) & VPU_G2_SWREG50_SW_DEC_MAX_OWIDTH_MASK)
/*! @} */
/*! @name SWREG54 - Synthesis configuration register decoder 1 (read only) */
/*! @{ */
#define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_MASK (0xC000U)
#define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT (14U)
/*! SW_DEC_MAX_OW_EXT - Max configured decoder video resolution that can be decoded. This is the MSB part of the configuration signal
*/
#define VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_SHIFT)) & VPU_G2_SWREG54_SW_DEC_MAX_OW_EXT_MASK)
/*! @} */
/*! @name SWREG55 - Advanced prefetch control register */
/*! @{ */
#define VPU_G2_SWREG55_SW_APF_THRESHOLD_MASK (0xFFFFU)
#define VPU_G2_SWREG55_SW_APF_THRESHOLD_SHIFT (0U)
/*! SW_APF_THRESHOLD - Advanced prefetch threshold. If current buffered unit exceeds the threshold
* the advanced mode is not used. Value 0 disables threshold usage and advanced prefetch usage is
* restricted by internal memory limitation only
*/
#define VPU_G2_SWREG55_SW_APF_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_THRESHOLD_SHIFT)) & VPU_G2_SWREG55_SW_APF_THRESHOLD_MASK)
#define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_MASK (0x40000000U)
#define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_SHIFT (30U)
/*! SW_APF_SINGLE_PU_MODE - APF amount of buffered Pus: can be restricted to buffer one PU at a time
*/
#define VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_SHIFT)) & VPU_G2_SWREG55_SW_APF_SINGLE_PU_MODE_MASK)
#define VPU_G2_SWREG55_SW_APF_DISABLE_MASK (0x80000000U)
#define VPU_G2_SWREG55_SW_APF_DISABLE_SHIFT (31U)
/*! SW_APF_DISABLE - Advanced prefetch disable. If hight each partition is read separately
*/
#define VPU_G2_SWREG55_SW_APF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG55_SW_APF_DISABLE_SHIFT)) & VPU_G2_SWREG55_SW_APF_DISABLE_MASK)
/*! @} */
/*! @name SWREG56 - Synthesis configuration register decoder 2 (read only) */
/*! @{ */
#define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_MASK (0x1FFFU)
#define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_SHIFT (0U)
/*! SW_DEC_MAX_OHEIGHT - Max supported picture height in pixels
*/
#define VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_SHIFT)) & VPU_G2_SWREG56_SW_DEC_MAX_OHEIGHT_MASK)
/*! @} */
/*! @name SWREG58 - Device configuration register decoder 2 + Multi core control register */
/*! @{ */
#define VPU_G2_SWREG58_SW_DEC_MAX_BURST_MASK (0xFFU)
#define VPU_G2_SWREG58_SW_DEC_MAX_BURST_SHIFT (0U)
/*! SW_DEC_MAX_BURST - Maximum burst length for decoder bus transactions. Valid values: AXI: 1-256
*/
#define VPU_G2_SWREG58_SW_DEC_MAX_BURST(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_MAX_BURST_SHIFT)) & VPU_G2_SWREG58_SW_DEC_MAX_BURST_MASK)
#define VPU_G2_SWREG58_SW_DEC_BUSWIDTH_MASK (0x700U)
#define VPU_G2_SWREG58_SW_DEC_BUSWIDTH_SHIFT (8U)
/*! SW_DEC_BUSWIDTH - Decoder master interface buswidth
* 0b000..32 bit bus
* 0b001..64 bit bus
* 0b010..128 bit bus
*/
#define VPU_G2_SWREG58_SW_DEC_BUSWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_BUSWIDTH_SHIFT)) & VPU_G2_SWREG58_SW_DEC_BUSWIDTH_MASK)
#define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_MASK (0x2000U)
#define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_SHIFT (13U)
/*! SW_DEC_AXI_WD_ID_E - SW axi ID enable. When enabled the given sw_dec_axi_wd_id is used as ID base and each sub-block will use offsets 0...max
*/
#define VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_AXI_WD_ID_E_MASK)
#define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_MASK (0x4000U)
#define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_SHIFT (14U)
/*! SW_DEC_AXI_RD_ID_E - SW axi ID enable. When enabled the given sw_dec_axi_rd_id is used as ID base and each sub-block will use offsets 0...max
*/
#define VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_AXI_RD_ID_E_MASK)
#define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_MASK (0x8000U)
#define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_SHIFT (15U)
/*! SW_DEC_REFER_DOUBLEBUFFER_E - HW internal double buffering enable for reference data. This
* enable requires that there are two buffers available at the configured decoder (see configuration
* register values)
*/
#define VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_REFER_DOUBLEBUFFER_E_MASK)
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_MASK (0x10000U)
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_SHIFT (16U)
/*! SW_DEC_CLK_GATE_E - Clock gating enable for picture-wise/decoding format clock gating. Between
* each picture the clock is gated from HW if this bit is high
*/
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_CLK_GATE_E_MASK)
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_MASK (0x20000U)
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_SHIFT (17U)
/*! SW_DEC_CLK_GATE_IDLE_E - Clock gating enable for decoder run-time. Generated separate clocks for each block by its own IDLE signal.
*/
#define VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_SHIFT)) & VPU_G2_SWREG58_SW_DEC_CLK_GATE_IDLE_E_MASK)
/*! @} */
/*! @name SWREG59 - Device configuration register AXI ID */
/*! @{ */
#define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_MASK (0xFFFFU)
#define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_SHIFT (0U)
/*! SW_DEC_AXI_RD_ID - Write ID base for HW write accesses. Each writing device use AXI ID of
* base+deviceoffset (where device offset is 0 1 2 3...Number of writing sub-blocks)
*/
#define VPU_G2_SWREG59_SW_DEC_AXI_RD_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_SHIFT)) & VPU_G2_SWREG59_SW_DEC_AXI_RD_ID_MASK)
#define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_MASK (0xFFFF0000U)
#define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_SHIFT (16U)
/*! SW_DEC_AXI_WR_ID - Read ID base for HW write accesses. Each writing device use AXI ID of
* base+deviceoffset (where device offset is 0 1 2 3...Number of reading sub-blocks)
*/
#define VPU_G2_SWREG59_SW_DEC_AXI_WR_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_SHIFT)) & VPU_G2_SWREG59_SW_DEC_AXI_WR_ID_MASK)
/*! @} */
/*! @name SWREG60 - Synthesis configuration register decoder 3 for PP (read only) */
/*! @{ */
#define VPU_G2_SWREG60_SW_DEC_PP_RS_E_MASK (0x40000000U)
#define VPU_G2_SWREG60_SW_DEC_PP_RS_E_SHIFT (30U)
/*! SW_DEC_PP_RS_E - Decoder PP raster scan output support
* 0b0..Raster scan output not supported
* 0b1..Raster scan output supported
*/
#define VPU_G2_SWREG60_SW_DEC_PP_RS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG60_SW_DEC_PP_RS_E_SHIFT)) & VPU_G2_SWREG60_SW_DEC_PP_RS_E_MASK)
#define VPU_G2_SWREG60_SW_DEC_PP_E_MASK (0x80000000U)
#define VPU_G2_SWREG60_SW_DEC_PP_E_SHIFT (31U)
/*! SW_DEC_PP_E - Decoder include PP
* 0b0..PP does not exist. None of the PP features can be enabled.
* 0b1..PP exists
*/
#define VPU_G2_SWREG60_SW_DEC_PP_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG60_SW_DEC_PP_E_SHIFT)) & VPU_G2_SWREG60_SW_DEC_PP_E_MASK)
/*! @} */
/*! @name SWREG62 - HW proceed register (CU location) */
/*! @{ */
#define VPU_G2_SWREG62_SW_CU_LOCATION_Y_MASK (0xFFFFU)
#define VPU_G2_SWREG62_SW_CU_LOCATION_Y_SHIFT (0U)
/*! SW_CU_LOCATION_Y - Cu vertical start location Y in pixels (returned HW internal position during interrupt)
*/
#define VPU_G2_SWREG62_SW_CU_LOCATION_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG62_SW_CU_LOCATION_Y_SHIFT)) & VPU_G2_SWREG62_SW_CU_LOCATION_Y_MASK)
#define VPU_G2_SWREG62_SW_CU_LOCATION_X_MASK (0xFFFF0000U)
#define VPU_G2_SWREG62_SW_CU_LOCATION_X_SHIFT (16U)
/*! SW_CU_LOCATION_X - Cu horizontal start location X in pixels (returned HW internal position during interrupt)
*/
#define VPU_G2_SWREG62_SW_CU_LOCATION_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG62_SW_CU_LOCATION_X_SHIFT)) & VPU_G2_SWREG62_SW_CU_LOCATION_X_MASK)
/*! @} */
/*! @name SWREG63 - HW performance register (cycles running) */
/*! @{ */
#define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_SHIFT (0U)
/*! SW_PERF_CYCLE_COUNT - HW clock cycle counter return value. Amount of consumed clock cycles
* returned to this register when interrupt is being made (any kind of interrupt)
*/
#define VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_SHIFT)) & VPU_G2_SWREG63_SW_PERF_CYCLE_COUNT_MASK)
/*! @} */
/*! @name SWREG64 - Base address MSB (bits 63:32) for decoded luminance picture */
/*! @{ */
#define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_SHIFT (0U)
/*! SW_DEC_OUT_YBASE_MSB - Base address MSB (bits 63:32) for decoded luminance picture
*/
#define VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_SHIFT)) & VPU_G2_SWREG64_SW_DEC_OUT_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG65 - Base address LSB (bits 31:0) for decoded luminance picture */
/*! @{ */
#define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_SHIFT (0U)
/*! SW_DEC_OUT_YBASE_LSB - Base address LSB (bits 31:0) for decoded luminance picture
*/
#define VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_SHIFT)) & VPU_G2_SWREG65_SW_DEC_OUT_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG66 - Base address MSB (bits 63:32) for reference luminance picture index 0 */
/*! @{ */
#define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_SHIFT (0U)
/*! SW_REFER0_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 0
*/
#define VPU_G2_SWREG66_SW_REFER0_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_SHIFT)) & VPU_G2_SWREG66_SW_REFER0_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG67 - Base address LSB (bits 31:0) for reference luminance picture index 0 */
/*! @{ */
#define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_SHIFT (0U)
/*! SW_REFER0_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 0
*/
#define VPU_G2_SWREG67_SW_REFER0_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_SHIFT)) & VPU_G2_SWREG67_SW_REFER0_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG68 - Base address MSB (bits 63:32) for reference luminance picture index 1 */
/*! @{ */
#define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_SHIFT (0U)
/*! SW_REFER1_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 1
*/
#define VPU_G2_SWREG68_SW_REFER1_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_SHIFT)) & VPU_G2_SWREG68_SW_REFER1_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG69 - Base address LSB (bits 31:0) for reference luminance picture index 1 */
/*! @{ */
#define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_SHIFT (0U)
/*! SW_REFER1_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 1
*/
#define VPU_G2_SWREG69_SW_REFER1_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_SHIFT)) & VPU_G2_SWREG69_SW_REFER1_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG70 - Base address MSB (bits 63:32) for reference luminance picture index 2 */
/*! @{ */
#define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_SHIFT (0U)
/*! SW_REFER2_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 2
*/
#define VPU_G2_SWREG70_SW_REFER2_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_SHIFT)) & VPU_G2_SWREG70_SW_REFER2_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG71 - Base address LSB (bits 31:0) for reference luminance picture index 2 */
/*! @{ */
#define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_SHIFT (0U)
/*! SW_REFER2_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 2
*/
#define VPU_G2_SWREG71_SW_REFER2_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_SHIFT)) & VPU_G2_SWREG71_SW_REFER2_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG72 - Base address MSB (bits 63:32) for reference luminance picture index 3 */
/*! @{ */
#define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_SHIFT (0U)
/*! SW_REFER3_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 3
*/
#define VPU_G2_SWREG72_SW_REFER3_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_SHIFT)) & VPU_G2_SWREG72_SW_REFER3_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG73 - Base address LSB (bits 31:0) for reference luminance picture index 3 */
/*! @{ */
#define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_SHIFT (0U)
/*! SW_REFER3_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 3
*/
#define VPU_G2_SWREG73_SW_REFER3_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_SHIFT)) & VPU_G2_SWREG73_SW_REFER3_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG74 - Base address MSB (bits 63:32) for reference luminance picture index 4 */
/*! @{ */
#define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_SHIFT (0U)
/*! SW_REFER4_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 4
*/
#define VPU_G2_SWREG74_SW_REFER4_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_SHIFT)) & VPU_G2_SWREG74_SW_REFER4_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG75 - Base address LSB (bits 31:0) for reference luminance picture index 4 */
/*! @{ */
#define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_SHIFT (0U)
/*! SW_REFER4_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 4
*/
#define VPU_G2_SWREG75_SW_REFER4_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_SHIFT)) & VPU_G2_SWREG75_SW_REFER4_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG76 - Base address MSB (bits 63:32) for reference luminance picture index 5 */
/*! @{ */
#define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_SHIFT (0U)
/*! SW_REFER5_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 5
*/
#define VPU_G2_SWREG76_SW_REFER5_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_SHIFT)) & VPU_G2_SWREG76_SW_REFER5_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG77 - Base address LSB (bits 31:0) for reference luminance picture index 5 */
/*! @{ */
#define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_SHIFT (0U)
/*! SW_REFER5_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 5
*/
#define VPU_G2_SWREG77_SW_REFER5_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_SHIFT)) & VPU_G2_SWREG77_SW_REFER5_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG78 - Base address MSB (bits 63:32) for reference luminance picture index 6 /VP9 segment write base MSB */
/*! @{ */
#define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_SHIFT (0U)
#define VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_SHIFT)) & VPU_G2_SWREG78_BASE_ADDR_6_MSB_BF_MASK)
/*! @} */
/*! @name SWREG79 - Base address LSB (bits 31:0) for reference luminance picture index 6 /VP9 segment write base LSB */
/*! @{ */
#define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_SHIFT (0U)
#define VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_SHIFT)) & VPU_G2_SWREG79_BASE_ADDR_6_LSB_BF_MASK)
/*! @} */
/*! @name SWREG80 - Base address MSB (bits 63:32) for reference luminance picture index 7 /VP9 segment read base MSB */
/*! @{ */
#define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_SHIFT (0U)
#define VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_SHIFT)) & VPU_G2_SWREG80_BASE_ADDR_7_MSB_BF_MASK)
/*! @} */
/*! @name SWREG81 - Base address LSB (bits 31:0) for reference luminance picture index 7 /VP9 segment read base LSB */
/*! @{ */
#define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_SHIFT (0U)
#define VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_SHIFT)) & VPU_G2_SWREG81_BASE_ADDR_7_LSB_BF_MASK)
/*! @} */
/*! @name SWREG82 - Base address MSB (bits 63:32) for reference luminance picture index 8 */
/*! @{ */
#define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_SHIFT (0U)
/*! SW_REFER8_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 8
*/
#define VPU_G2_SWREG82_SW_REFER8_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_SHIFT)) & VPU_G2_SWREG82_SW_REFER8_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG83 - Base address LSB (bits 31:0) for reference luminance picture index 8 */
/*! @{ */
#define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_SHIFT (0U)
/*! SW_REFER8_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 8
*/
#define VPU_G2_SWREG83_SW_REFER8_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_SHIFT)) & VPU_G2_SWREG83_SW_REFER8_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG84 - Base address MSB (bits 63:32) for reference luminance picture index 9 */
/*! @{ */
#define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_SHIFT (0U)
/*! SW_REFER9_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 9
*/
#define VPU_G2_SWREG84_SW_REFER9_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_SHIFT)) & VPU_G2_SWREG84_SW_REFER9_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG85 - Base address LSB (bits 31:0) for reference luminance picture index 9 */
/*! @{ */
#define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_SHIFT (0U)
/*! SW_REFER9_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 9
*/
#define VPU_G2_SWREG85_SW_REFER9_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_SHIFT)) & VPU_G2_SWREG85_SW_REFER9_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG86 - Base address MSB (bits 63:32) for reference luminance picture index 10 */
/*! @{ */
#define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_SHIFT (0U)
/*! SW_REFER10_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 10
*/
#define VPU_G2_SWREG86_SW_REFER10_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_SHIFT)) & VPU_G2_SWREG86_SW_REFER10_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG87 - Base address LSB (bits 31:0) for reference luminance picture index 10 */
/*! @{ */
#define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_SHIFT (0U)
/*! SW_REFER10_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 10
*/
#define VPU_G2_SWREG87_SW_REFER10_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_SHIFT)) & VPU_G2_SWREG87_SW_REFER10_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG88 - Base address MSB (bits 63:32) for reference luminance picture index 11 */
/*! @{ */
#define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_SHIFT (0U)
/*! SW_REFER11_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 11
*/
#define VPU_G2_SWREG88_SW_REFER11_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_SHIFT)) & VPU_G2_SWREG88_SW_REFER11_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG89 - Base address LSB (bits 31:0) for reference luminance picture index 11 */
/*! @{ */
#define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_SHIFT (0U)
/*! SW_REFER11_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 11
*/
#define VPU_G2_SWREG89_SW_REFER11_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_SHIFT)) & VPU_G2_SWREG89_SW_REFER11_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG90 - Base address MSB (bits 63:32) for reference luminance picture index 12 */
/*! @{ */
#define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_SHIFT (0U)
/*! SW_REFER12_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 12
*/
#define VPU_G2_SWREG90_SW_REFER12_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_SHIFT)) & VPU_G2_SWREG90_SW_REFER12_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG91 - Base address LSB (bits 31:0) for reference luminance picture index 12 */
/*! @{ */
#define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_SHIFT (0U)
/*! SW_REFER12_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 12
*/
#define VPU_G2_SWREG91_SW_REFER12_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_SHIFT)) & VPU_G2_SWREG91_SW_REFER12_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG92 - Base address MSB (bits 63:32) for reference luminance picture index 13 */
/*! @{ */
#define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_SHIFT (0U)
/*! SW_REFER13_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 13
*/
#define VPU_G2_SWREG92_SW_REFER13_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_SHIFT)) & VPU_G2_SWREG92_SW_REFER13_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG93 - Base address LSB (bits 31:0) for reference luminance picture index 13 */
/*! @{ */
#define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_SHIFT (0U)
/*! SW_REFER13_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 13
*/
#define VPU_G2_SWREG93_SW_REFER13_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_SHIFT)) & VPU_G2_SWREG93_SW_REFER13_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG94 - Base address MSB (bits 63:32) for reference luminance picture index 14 */
/*! @{ */
#define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_SHIFT (0U)
/*! SW_REFER14_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 14
*/
#define VPU_G2_SWREG94_SW_REFER14_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_SHIFT)) & VPU_G2_SWREG94_SW_REFER14_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG95 - Base address LSB (bits 31:0) for reference luminance picture index 14 */
/*! @{ */
#define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_SHIFT (0U)
/*! SW_REFER14_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 14
*/
#define VPU_G2_SWREG95_SW_REFER14_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_SHIFT)) & VPU_G2_SWREG95_SW_REFER14_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG96 - Base address MSB (bits 63:32) for reference luminance picture index 15 */
/*! @{ */
#define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_SHIFT (0U)
/*! SW_REFER15_YBASE_MSB - Base address MSB (bits 63:32) for reference luminance picture index 15
*/
#define VPU_G2_SWREG96_SW_REFER15_YBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_SHIFT)) & VPU_G2_SWREG96_SW_REFER15_YBASE_MSB_MASK)
/*! @} */
/*! @name SWREG97 - Base address LSB (bits 31:0) for reference luminance picture index 15 */
/*! @{ */
#define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_SHIFT (0U)
/*! SW_REFER15_YBASE_LSB - Base address LSB (bits 31:0) for reference luminance picture index 15
*/
#define VPU_G2_SWREG97_SW_REFER15_YBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_SHIFT)) & VPU_G2_SWREG97_SW_REFER15_YBASE_LSB_MASK)
/*! @} */
/*! @name SWREG98 - Base address MSB (bits 63:32) for decoded chrominance picture */
/*! @{ */
#define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_SHIFT (0U)
/*! SW_DEC_OUT_CBASE_MSB - Base address MSB (bits 64:32) for decoded chrominance picture
*/
#define VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_SHIFT)) & VPU_G2_SWREG98_SW_DEC_OUT_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG99 - Base address LSB (bits 31:0) for decoded chrominance picture */
/*! @{ */
#define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_SHIFT (0U)
/*! SW_DEC_OUT_CBASE_LSB - Base address LSB (bits 31:0) for decoded chrominance picture
*/
#define VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_SHIFT)) & VPU_G2_SWREG99_SW_DEC_OUT_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG100 - Base address MSB (bits 63:32) for reference chrominance picture index 0 */
/*! @{ */
#define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_SHIFT (0U)
/*! SW_REFER0_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 0
*/
#define VPU_G2_SWREG100_SW_REFER0_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_SHIFT)) & VPU_G2_SWREG100_SW_REFER0_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG101 - Base address LSB (bits 31:0) for reference chrominance picture index 0 */
/*! @{ */
#define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_SHIFT (0U)
/*! SW_REFER0_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 0
*/
#define VPU_G2_SWREG101_SW_REFER0_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_SHIFT)) & VPU_G2_SWREG101_SW_REFER0_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG102 - Base address MSB (bits 63:32) for reference chrominance picture index 1 */
/*! @{ */
#define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_SHIFT (0U)
/*! SW_REFER1_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 1
*/
#define VPU_G2_SWREG102_SW_REFER1_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_SHIFT)) & VPU_G2_SWREG102_SW_REFER1_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG103 - Base address LSB (bits 31:0) for reference chrominance picture index 1 */
/*! @{ */
#define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_SHIFT (0U)
/*! SW_REFER1_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 1
*/
#define VPU_G2_SWREG103_SW_REFER1_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_SHIFT)) & VPU_G2_SWREG103_SW_REFER1_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG104 - Base address MSB (bits 63:32) for reference chrominance picture index 2 */
/*! @{ */
#define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_SHIFT (0U)
/*! SW_REFER2_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 2
*/
#define VPU_G2_SWREG104_SW_REFER2_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_SHIFT)) & VPU_G2_SWREG104_SW_REFER2_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG105 - Base address LSB (bits 31:0) for reference chrominance picture index 2 */
/*! @{ */
#define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_SHIFT (0U)
/*! SW_REFER2_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 2
*/
#define VPU_G2_SWREG105_SW_REFER2_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_SHIFT)) & VPU_G2_SWREG105_SW_REFER2_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG106 - Base address MSB (bits 63:32) for reference chrominance picture index 3 */
/*! @{ */
#define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_SHIFT (0U)
/*! SW_REFER3_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 3
*/
#define VPU_G2_SWREG106_SW_REFER3_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_SHIFT)) & VPU_G2_SWREG106_SW_REFER3_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG107 - Base address LSB (bits 31:0) for reference chrominance picture index 3 */
/*! @{ */
#define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_SHIFT (0U)
/*! SW_REFER3_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 3
*/
#define VPU_G2_SWREG107_SW_REFER3_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_SHIFT)) & VPU_G2_SWREG107_SW_REFER3_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG108 - Base address MSB (bits 63:32) for reference chrominance picture index 4 */
/*! @{ */
#define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_SHIFT (0U)
/*! SW_REFER4_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 4
*/
#define VPU_G2_SWREG108_SW_REFER4_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_SHIFT)) & VPU_G2_SWREG108_SW_REFER4_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG109 - Base address LSB (bits 31:0) for reference chrominance picture index 4 */
/*! @{ */
#define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_SHIFT (0U)
/*! SW_REFER4_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 4
*/
#define VPU_G2_SWREG109_SW_REFER4_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_SHIFT)) & VPU_G2_SWREG109_SW_REFER4_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG110 - Base address MSB (bits 63:32) for reference chrominance picture index 5 */
/*! @{ */
#define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_SHIFT (0U)
/*! SW_REFER5_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 5
*/
#define VPU_G2_SWREG110_SW_REFER5_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_SHIFT)) & VPU_G2_SWREG110_SW_REFER5_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG111 - Base address LSB (bits 31:0) for reference chrominance picture index 5 */
/*! @{ */
#define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_SHIFT (0U)
/*! SW_REFER5_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 5
*/
#define VPU_G2_SWREG111_SW_REFER5_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_SHIFT)) & VPU_G2_SWREG111_SW_REFER5_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG112 - Base address MSB (bits 63:32) for reference chrominance picture index 6 */
/*! @{ */
#define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_SHIFT (0U)
/*! SW_REFER6_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 6
*/
#define VPU_G2_SWREG112_SW_REFER6_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_SHIFT)) & VPU_G2_SWREG112_SW_REFER6_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG113 - Base address LSB (bits 31:0) for reference chrominance picture index 6 */
/*! @{ */
#define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_SHIFT (0U)
/*! SW_REFER6_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 6
*/
#define VPU_G2_SWREG113_SW_REFER6_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_SHIFT)) & VPU_G2_SWREG113_SW_REFER6_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG114 - Base address MSB (bits 63:32) for reference chrominance picture index 7 */
/*! @{ */
#define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_SHIFT (0U)
/*! SW_REFER7_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 7
*/
#define VPU_G2_SWREG114_SW_REFER7_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_SHIFT)) & VPU_G2_SWREG114_SW_REFER7_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG115 - Base address LSB (bits 31:0) for reference chrominance picture index 7 */
/*! @{ */
#define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_SHIFT (0U)
/*! SW_REFER7_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 7
*/
#define VPU_G2_SWREG115_SW_REFER7_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_SHIFT)) & VPU_G2_SWREG115_SW_REFER7_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG116 - Base address MSB (bits 63:32) for reference chrominance picture index 8 */
/*! @{ */
#define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_SHIFT (0U)
/*! SW_REFER8_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 8
*/
#define VPU_G2_SWREG116_SW_REFER8_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_SHIFT)) & VPU_G2_SWREG116_SW_REFER8_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG117 - Base address LSB (bits 31:0) for reference chrominance picture index 8 */
/*! @{ */
#define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_SHIFT (0U)
/*! SW_REFER8_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 8
*/
#define VPU_G2_SWREG117_SW_REFER8_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_SHIFT)) & VPU_G2_SWREG117_SW_REFER8_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG118 - Base address MSB (bits 63:32) for reference chrominance picture index 9 */
/*! @{ */
#define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_SHIFT (0U)
/*! SW_REFER9_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 9
*/
#define VPU_G2_SWREG118_SW_REFER9_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_SHIFT)) & VPU_G2_SWREG118_SW_REFER9_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG119 - Base address LSB (bits 31:0) for reference chrominance picture index 9 */
/*! @{ */
#define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_SHIFT (0U)
/*! SW_REFER9_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 9
*/
#define VPU_G2_SWREG119_SW_REFER9_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_SHIFT)) & VPU_G2_SWREG119_SW_REFER9_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG120 - Base address MSB (bits 63:32) for reference chrominance picture index 10 */
/*! @{ */
#define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_SHIFT (0U)
/*! SW_REFER10_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 10
*/
#define VPU_G2_SWREG120_SW_REFER10_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_SHIFT)) & VPU_G2_SWREG120_SW_REFER10_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG121 - Base address LSB (bits 31:0) for reference chrominance picture index 10 */
/*! @{ */
#define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_SHIFT (0U)
/*! SW_REFER10_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 10
*/
#define VPU_G2_SWREG121_SW_REFER10_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_SHIFT)) & VPU_G2_SWREG121_SW_REFER10_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG122 - Base address MSB (bits 63:32) for reference chrominance picture index 11 */
/*! @{ */
#define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_SHIFT (0U)
/*! SW_REFER11_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 11
*/
#define VPU_G2_SWREG122_SW_REFER11_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_SHIFT)) & VPU_G2_SWREG122_SW_REFER11_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG123 - Base address LSB (bits 31:0) for reference chrominance picture index 11 */
/*! @{ */
#define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_SHIFT (0U)
/*! SW_REFER11_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 11
*/
#define VPU_G2_SWREG123_SW_REFER11_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_SHIFT)) & VPU_G2_SWREG123_SW_REFER11_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG124 - Base address MSB (bits 63:32) for reference chrominance picture index 12 */
/*! @{ */
#define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_SHIFT (0U)
/*! SW_REFER12_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 12
*/
#define VPU_G2_SWREG124_SW_REFER12_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_SHIFT)) & VPU_G2_SWREG124_SW_REFER12_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG125 - Base address LSB (bits 31:0) for reference chrominance picture index 12 */
/*! @{ */
#define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_SHIFT (0U)
/*! SW_REFER12_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 12
*/
#define VPU_G2_SWREG125_SW_REFER12_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_SHIFT)) & VPU_G2_SWREG125_SW_REFER12_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG126 - Base address MSB (bits 63:32) for reference chrominance picture index 13 */
/*! @{ */
#define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_SHIFT (0U)
/*! SW_REFER13_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 13
*/
#define VPU_G2_SWREG126_SW_REFER13_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_SHIFT)) & VPU_G2_SWREG126_SW_REFER13_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG127 - Base address LSB (bits 31:0) for reference chrominance picture index 13 */
/*! @{ */
#define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_SHIFT (0U)
/*! SW_REFER13_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 13
*/
#define VPU_G2_SWREG127_SW_REFER13_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_SHIFT)) & VPU_G2_SWREG127_SW_REFER13_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG128 - Base address MSB (bits 63:32) for reference chrominance picture index 14 */
/*! @{ */
#define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_SHIFT (0U)
/*! SW_REFER14_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 14
*/
#define VPU_G2_SWREG128_SW_REFER14_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_SHIFT)) & VPU_G2_SWREG128_SW_REFER14_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG129 - Base address LSB (bits 31:0) for reference chrominance picture index 14 */
/*! @{ */
#define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_SHIFT (0U)
/*! SW_REFER14_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 14
*/
#define VPU_G2_SWREG129_SW_REFER14_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_SHIFT)) & VPU_G2_SWREG129_SW_REFER14_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG130 - Base address MSB (bits 63:32) for reference chrominance picture index 15 */
/*! @{ */
#define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_SHIFT (0U)
/*! SW_REFER15_CBASE_MSB - Base address MSB (bits 63:32) for reference chrominance picture index 15
*/
#define VPU_G2_SWREG130_SW_REFER15_CBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_SHIFT)) & VPU_G2_SWREG130_SW_REFER15_CBASE_MSB_MASK)
/*! @} */
/*! @name SWREG131 - Base address LSB (bits 31:0) for reference chrominance picture index 15 */
/*! @{ */
#define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_SHIFT (0U)
/*! SW_REFER15_CBASE_LSB - Base address LSB (bits 31:0) for reference chrominance picture index 15
*/
#define VPU_G2_SWREG131_SW_REFER15_CBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_SHIFT)) & VPU_G2_SWREG131_SW_REFER15_CBASE_LSB_MASK)
/*! @} */
/*! @name SWREG132 - Base address MSB (bits 63:32) for decoded direct mode MVS */
/*! @{ */
#define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_SHIFT (0U)
/*! SW_DEC_OUT_DBASE_MSB - Base address MSB (bits 63:32) for decoded direct mode MVS
*/
#define VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_SHIFT)) & VPU_G2_SWREG132_SW_DEC_OUT_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG133 - Base address LSB (bits 31:0) for decoded direct mode MVS */
/*! @{ */
#define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_SHIFT (0U)
/*! SW_DEC_OUT_DBASE_LSB - Base address LSB (bits 31:0) for decoded direct mode MVS
*/
#define VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_SHIFT)) & VPU_G2_SWREG133_SW_DEC_OUT_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG134 - Base address MSB (bits 63:32) for reference direct mode MVS index 0 */
/*! @{ */
#define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_SHIFT (0U)
/*! SW_REFER0_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 0
*/
#define VPU_G2_SWREG134_SW_REFER0_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_SHIFT)) & VPU_G2_SWREG134_SW_REFER0_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG135 - Base address LSB (bits 31:0) for reference direct mode MVS index 0 */
/*! @{ */
#define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_SHIFT (0U)
/*! SW_REFER0_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 0
*/
#define VPU_G2_SWREG135_SW_REFER0_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_SHIFT)) & VPU_G2_SWREG135_SW_REFER0_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG136 - Base address MSB (bits 63:32) for reference direct mode MVS index 1 */
/*! @{ */
#define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_SHIFT (0U)
/*! SW_REFER1_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 1
*/
#define VPU_G2_SWREG136_SW_REFER1_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_SHIFT)) & VPU_G2_SWREG136_SW_REFER1_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG137 - Base address LSB (bits 31:0) for reference direct mode MVS index 1 */
/*! @{ */
#define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_SHIFT (0U)
/*! SW_REFER1_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 1
*/
#define VPU_G2_SWREG137_SW_REFER1_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_SHIFT)) & VPU_G2_SWREG137_SW_REFER1_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG138 - Base address MSB (bits 63:32) for reference direct mode MVS index 2 */
/*! @{ */
#define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_SHIFT (0U)
/*! SW_REFER2_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 2
*/
#define VPU_G2_SWREG138_SW_REFER2_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_SHIFT)) & VPU_G2_SWREG138_SW_REFER2_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG139 - Base address LSB (bits 31:0) for reference direct mode MVS index 2 */
/*! @{ */
#define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_SHIFT (0U)
/*! SW_REFER2_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 2
*/
#define VPU_G2_SWREG139_SW_REFER2_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_SHIFT)) & VPU_G2_SWREG139_SW_REFER2_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG140 - Base address MSB (bits 63:32) for reference direct mode MVS index 3 */
/*! @{ */
#define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_SHIFT (0U)
/*! SW_REFER3_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 3
*/
#define VPU_G2_SWREG140_SW_REFER3_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_SHIFT)) & VPU_G2_SWREG140_SW_REFER3_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG141 - Base address LSB (bits 31:0) for reference direct mode MVS index 3 */
/*! @{ */
#define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_SHIFT (0U)
/*! SW_REFER3_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 3
*/
#define VPU_G2_SWREG141_SW_REFER3_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_SHIFT)) & VPU_G2_SWREG141_SW_REFER3_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG142 - Base address MSB (bits 63:32) for reference direct mode MVS index 4 */
/*! @{ */
#define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_SHIFT (0U)
/*! SW_REFER4_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 4
*/
#define VPU_G2_SWREG142_SW_REFER4_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_SHIFT)) & VPU_G2_SWREG142_SW_REFER4_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG143 - Base address LSB (bits 31:0) for reference direct mode MVS index 4 */
/*! @{ */
#define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_SHIFT (0U)
/*! SW_REFER4_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 4
*/
#define VPU_G2_SWREG143_SW_REFER4_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_SHIFT)) & VPU_G2_SWREG143_SW_REFER4_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG144 - Base address MSB (bits 63:32) for reference direct mode MVS index 5 */
/*! @{ */
#define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_SHIFT (0U)
/*! SW_REFER5_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 5
*/
#define VPU_G2_SWREG144_SW_REFER5_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_SHIFT)) & VPU_G2_SWREG144_SW_REFER5_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG145 - Base address LSB (bits 31:0) for reference direct mode MVS index 5 */
/*! @{ */
#define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_SHIFT (0U)
/*! SW_REFER5_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 5
*/
#define VPU_G2_SWREG145_SW_REFER5_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_SHIFT)) & VPU_G2_SWREG145_SW_REFER5_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG146 - Base address MSB (bits 63:32) for reference direct mode MVS index 6 */
/*! @{ */
#define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_SHIFT (0U)
/*! SW_REFER6_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 6
*/
#define VPU_G2_SWREG146_SW_REFER6_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_SHIFT)) & VPU_G2_SWREG146_SW_REFER6_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG147 - Base address LSB (bits 31:0) for reference direct mode MVS index 6 */
/*! @{ */
#define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_SHIFT (0U)
/*! SW_REFER6_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 6
*/
#define VPU_G2_SWREG147_SW_REFER6_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_SHIFT)) & VPU_G2_SWREG147_SW_REFER6_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG148 - Base address MSB (bits 63:32) for reference direct mode MVS index 7 */
/*! @{ */
#define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_SHIFT (0U)
/*! SW_REFER7_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 7
*/
#define VPU_G2_SWREG148_SW_REFER7_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_SHIFT)) & VPU_G2_SWREG148_SW_REFER7_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG149 - Base address LSB (bits 31:0) for reference direct mode MVS index 7 */
/*! @{ */
#define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_SHIFT (0U)
/*! SW_REFER7_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 7
*/
#define VPU_G2_SWREG149_SW_REFER7_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_SHIFT)) & VPU_G2_SWREG149_SW_REFER7_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG150 - Base address MSB (bits 63:32) for reference direct mode MVS index 8 */
/*! @{ */
#define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_SHIFT (0U)
/*! SW_REFER8_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 8
*/
#define VPU_G2_SWREG150_SW_REFER8_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_SHIFT)) & VPU_G2_SWREG150_SW_REFER8_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG151 - Base address LSB (bits 31:0) for reference direct mode MVS index 8 */
/*! @{ */
#define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_SHIFT (0U)
/*! SW_REFER8_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode mode MVS index 8
*/
#define VPU_G2_SWREG151_SW_REFER8_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_SHIFT)) & VPU_G2_SWREG151_SW_REFER8_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG152 - Base address MSB (bits 63:32) for reference direct mode mode MVS index 9 */
/*! @{ */
#define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_SHIFT (0U)
/*! SW_REFER9_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 9
*/
#define VPU_G2_SWREG152_SW_REFER9_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_SHIFT)) & VPU_G2_SWREG152_SW_REFER9_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG153 - Base address LSB (bits 31:0) for reference direct mode mode MVS index 9 */
/*! @{ */
#define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_SHIFT (0U)
/*! SW_REFER9_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode mode MVS index 9
*/
#define VPU_G2_SWREG153_SW_REFER9_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_SHIFT)) & VPU_G2_SWREG153_SW_REFER9_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG154 - Base address MSB (bits 63:32) for reference direct mode MVS index 10 */
/*! @{ */
#define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_SHIFT (0U)
/*! SW_REFER10_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 10
*/
#define VPU_G2_SWREG154_SW_REFER10_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_SHIFT)) & VPU_G2_SWREG154_SW_REFER10_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG155 - Base address LSB (bits 31:0) for reference direct mode MVS index 10 */
/*! @{ */
#define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_SHIFT (0U)
/*! SW_REFER10_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 10
*/
#define VPU_G2_SWREG155_SW_REFER10_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_SHIFT)) & VPU_G2_SWREG155_SW_REFER10_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG156 - Base address MSB (bits 63:32) for reference direct mode MVS index 11 */
/*! @{ */
#define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_SHIFT (0U)
/*! SW_REFER11_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 11
*/
#define VPU_G2_SWREG156_SW_REFER11_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_SHIFT)) & VPU_G2_SWREG156_SW_REFER11_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG157 - Base address LSB (bits 31:0) for reference direct mode MVS index 11 */
/*! @{ */
#define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_SHIFT (0U)
/*! SW_REFER11_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 11
*/
#define VPU_G2_SWREG157_SW_REFER11_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_SHIFT)) & VPU_G2_SWREG157_SW_REFER11_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG158 - Base address MSB (bits 63:32) for reference direct mode MVS index 12 */
/*! @{ */
#define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_SHIFT (0U)
/*! SW_REFER12_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 12
*/
#define VPU_G2_SWREG158_SW_REFER12_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_SHIFT)) & VPU_G2_SWREG158_SW_REFER12_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG159 - Base address LSB (bits 31:0) for reference direct mode MVS index 12 */
/*! @{ */
#define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_SHIFT (0U)
/*! SW_REFER12_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 12
*/
#define VPU_G2_SWREG159_SW_REFER12_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_SHIFT)) & VPU_G2_SWREG159_SW_REFER12_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG160 - Base address MSB (bits 63:32) for reference direct mode MVS index 13 */
/*! @{ */
#define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_SHIFT (0U)
/*! SW_REFER13_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 13
*/
#define VPU_G2_SWREG160_SW_REFER13_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_SHIFT)) & VPU_G2_SWREG160_SW_REFER13_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG161 - Base address LSB (bits 31:0) for reference direct mode MVS index 13 */
/*! @{ */
#define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_SHIFT (0U)
/*! SW_REFER13_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 13
*/
#define VPU_G2_SWREG161_SW_REFER13_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_SHIFT)) & VPU_G2_SWREG161_SW_REFER13_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG162 - Base address MSB (bits 63:32) for reference direct mode MVS index 14 */
/*! @{ */
#define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_SHIFT (0U)
/*! SW_REFER14_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 14
*/
#define VPU_G2_SWREG162_SW_REFER14_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_SHIFT)) & VPU_G2_SWREG162_SW_REFER14_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG163 - Base address LSB (bits 31:0) for reference direct mode MVS index 14 */
/*! @{ */
#define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_SHIFT (0U)
/*! SW_REFER14_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 14
*/
#define VPU_G2_SWREG163_SW_REFER14_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_SHIFT)) & VPU_G2_SWREG163_SW_REFER14_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG164 - Base address MSB (bits 63:32) for reference direct mode MVS index 15 */
/*! @{ */
#define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_SHIFT (0U)
/*! SW_REFER15_DBASE_MSB - Base address MSB (bits 63:32) for reference direct mode MVS index 15
*/
#define VPU_G2_SWREG164_SW_REFER15_DBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_SHIFT)) & VPU_G2_SWREG164_SW_REFER15_DBASE_MSB_MASK)
/*! @} */
/*! @name SWREG165 - Base address LSB (bits 31:0) for reference direct mode MVS index 15 */
/*! @{ */
#define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_SHIFT (0U)
/*! SW_REFER15_DBASE_LSB - Base address LSB (bits 31:0) for reference direct mode MVS index 15
*/
#define VPU_G2_SWREG165_SW_REFER15_DBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_SHIFT)) & VPU_G2_SWREG165_SW_REFER15_DBASE_LSB_MASK)
/*! @} */
/*! @name SWREG166 - Base address MSB (bits 63:32) for tile sizes */
/*! @{ */
#define VPU_G2_SWREG166_SW_TILE_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG166_SW_TILE_BASE_MSB_SHIFT (0U)
/*! SW_TILE_BASE_MSB - Base address MSB (bits 63:32) for tile sizes
*/
#define VPU_G2_SWREG166_SW_TILE_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG166_SW_TILE_BASE_MSB_SHIFT)) & VPU_G2_SWREG166_SW_TILE_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG167 - Base address LSB (bits 31:0) for tile sizes */
/*! @{ */
#define VPU_G2_SWREG167_SW_TILE_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG167_SW_TILE_BASE_LSB_SHIFT (0U)
/*! SW_TILE_BASE_LSB - Base address LSB (bits 31:0) for tile sizes
*/
#define VPU_G2_SWREG167_SW_TILE_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG167_SW_TILE_BASE_LSB_SHIFT)) & VPU_G2_SWREG167_SW_TILE_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG168 - Base address MSB (bits 63:32) for / stream start address/decoded end addr register */
/*! @{ */
#define VPU_G2_SWREG168_SW_STREAM_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG168_SW_STREAM_BASE_MSB_SHIFT (0U)
/*! SW_STREAM_BASE_MSB - Base address MSB (bits 63:32) for / stream start address/decoded end addr register
*/
#define VPU_G2_SWREG168_SW_STREAM_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG168_SW_STREAM_BASE_MSB_SHIFT)) & VPU_G2_SWREG168_SW_STREAM_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG169 - Base address LSB (bits 31:0) for / stream start address/decoded end addr register */
/*! @{ */
#define VPU_G2_SWREG169_SW_STREAM_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG169_SW_STREAM_BASE_LSB_SHIFT (0U)
/*! SW_STREAM_BASE_LSB - Base address LSB (bits 31:0) for / stream start address/decoded end addr register
*/
#define VPU_G2_SWREG169_SW_STREAM_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG169_SW_STREAM_BASE_LSB_SHIFT)) & VPU_G2_SWREG169_SW_STREAM_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG170 - Base address MSB (bits 63:32) for scaling lists / VP9 CTX counter values */
/*! @{ */
#define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_SHIFT (0U)
/*! SW_SCALE_LIST_CTX_COUNTER_BASE_MSB - HEVC: Base address MSB (bits 63:32) for scaling lists VP9: CTX counter values
*/
#define VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_SHIFT)) & VPU_G2_SWREG170_SW_SCALE_LIST_CTX_COUNTER_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG171 - Base address LSB (bits 31:0) for scaling lists / VP9 CTX counter values */
/*! @{ */
#define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_SHIFT (0U)
/*! SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB - HEVC: Base address LSB (bits 31:0) for scaling lists VP9: CTX counter values
*/
#define VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_SHIFT)) & VPU_G2_SWREG171_SW_SCALE_LISTT_CTX_COUNTER_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG172 - Base address MSB (bits 63:32) for stream propability tables */
/*! @{ */
#define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_SHIFT (0U)
/*! SW_PROB_TAB_BASE_MSB - Base address MSB (bits 63:32) for stream propability tables
*/
#define VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_SHIFT)) & VPU_G2_SWREG172_SW_PROB_TAB_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG173 - Base address LSB (bits 31:0) for stream propability tables */
/*! @{ */
#define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_SHIFT (0U)
/*! SW_PROB_TAB_BASE_LSB - Base address LSB (bits 31:0) for stream propability tables
*/
#define VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_SHIFT)) & VPU_G2_SWREG173_SW_PROB_TAB_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG174 - Base address MSB (bits 63:32) for decoder output raster scan Y picture */
/*! @{ */
#define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_SHIFT (0U)
/*! SW_DEC_RSY_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan Y picture
*/
#define VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_SHIFT)) & VPU_G2_SWREG174_SW_DEC_RSY_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG175 - Base address LSB (bits 31:0) for decoder output raster scan Y picture */
/*! @{ */
#define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_SHIFT (0U)
/*! SW_DEC_RSY_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan Y picture
*/
#define VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_SHIFT)) & VPU_G2_SWREG175_SW_DEC_RSY_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG176 - Base address MSB (bits 63:32) for decoder output raster scan C picture */
/*! @{ */
#define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_SHIFT (0U)
/*! SW_DEC_RSC_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan C picture
*/
#define VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_SHIFT)) & VPU_G2_SWREG176_SW_DEC_RSC_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG177 - Base address LSB (bits 31:0) for decoder output raster scan C picture */
/*! @{ */
#define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_SHIFT (0U)
/*! SW_DEC_RSC_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan C picture
*/
#define VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_SHIFT)) & VPU_G2_SWREG177_SW_DEC_RSC_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG178 - Base address MSB (bits 63:32) for tile border coeffients of filter */
/*! @{ */
#define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_SHIFT (0U)
/*! SW_DEC_VERT_FILT_BASE_MSB - Base address MSB to store/read filtering coeffients of current picture at tile border.
*/
#define VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_SHIFT)) & VPU_G2_SWREG178_SW_DEC_VERT_FILT_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG179 - Base address LSB (bits 31:0) for tile border coeffients of filter */
/*! @{ */
#define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_SHIFT (0U)
/*! SW_DEC_VERT_FILT_BASE_LSB - Base address LSB to store/read filtering coeffients of current picture at tile border.
*/
#define VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_SHIFT)) & VPU_G2_SWREG179_SW_DEC_VERT_FILT_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG180 - Base address MSB (bits 63:32) for tile border coeffients of sao */
/*! @{ */
#define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_SHIFT (0U)
/*! SW_DEC_VERT_SAO_BASE_MSB - Base address MSB to store/read sao coeffients of current picture at tile border.
*/
#define VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_SHIFT)) & VPU_G2_SWREG180_SW_DEC_VERT_SAO_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG181 - Base address LSB (bits 31:0) for tile border coeffients of sao */
/*! @{ */
#define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_SHIFT (0U)
/*! SW_DEC_VERT_SAO_BASE_LSB - Base address LSB to store/read sao coeffients of current picture at tile border.
*/
#define VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_SHIFT)) & VPU_G2_SWREG181_SW_DEC_VERT_SAO_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG182 - Base address MSB (bits 63:32) for tile border bsd control data */
/*! @{ */
#define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_SHIFT (0U)
/*! SW_DEC_BSD_CTRL_BASE_MSB - Base address MSB to store/read BSD control data of current picture at tile border.
*/
#define VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_SHIFT)) & VPU_G2_SWREG182_SW_DEC_BSD_CTRL_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG183 - Base address LSB (bits 31:0) for tile border bsd control data */
/*! @{ */
#define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_SHIFT (0U)
/*! SW_DEC_BSD_CTRL_BASE_LSB - Base address LSB to store/read BSD control data of current picture at tile border.
*/
#define VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_SHIFT)) & VPU_G2_SWREG183_SW_DEC_BSD_CTRL_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG184 - Raster scan down scale control register MSM */
/*! @{ */
#define VPU_G2_SWREG184_SW_DEC_DS_X_MASK (0x3U)
#define VPU_G2_SWREG184_SW_DEC_DS_X_SHIFT (0U)
/*! SW_DEC_DS_X - X coordinate down scale times for raster scan output picture data
* 0b00..1/2
* 0b01..1/4
* 0b10..1/8
*/
#define VPU_G2_SWREG184_SW_DEC_DS_X(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_X_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_X_MASK)
#define VPU_G2_SWREG184_SW_DEC_DS_Y_MASK (0xCU)
#define VPU_G2_SWREG184_SW_DEC_DS_Y_SHIFT (2U)
/*! SW_DEC_DS_Y - Y coordinate down scale times for raster scan output picture data
* 0b00..1/2
* 0b01..1/4
* 0b10..1/8
*/
#define VPU_G2_SWREG184_SW_DEC_DS_Y(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_Y_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_Y_MASK)
#define VPU_G2_SWREG184_SW_DEC_DS_E_MASK (0x80U)
#define VPU_G2_SWREG184_SW_DEC_DS_E_SHIFT (7U)
/*! SW_DEC_DS_E - Raster scan down scale enable
* 0b1..Enable
* 0b0..Disable
*/
#define VPU_G2_SWREG184_SW_DEC_DS_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG184_SW_DEC_DS_E_SHIFT)) & VPU_G2_SWREG184_SW_DEC_DS_E_MASK)
/*! @} */
/*! @name SWREG185 - Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture */
/*! @{ */
#define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_SHIFT (0U)
/*! SW_DEC_DSY_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan down scale Y picture
*/
#define VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_SHIFT)) & VPU_G2_SWREG185_SW_DEC_DSY_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG186 - Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture */
/*! @{ */
#define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_SHIFT (0U)
/*! SW_DEC_DSY_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan down scale Y picture
*/
#define VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_SHIFT)) & VPU_G2_SWREG186_SW_DEC_DSY_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG187 - Base address MSB (bits 63:32) for decoder output raster scan down scale C picture */
/*! @{ */
#define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_SHIFT (0U)
/*! SW_DEC_DSC_BASE_MSB - Base address MSB (bits 63:32) for decoder output raster scan down scale C picture
*/
#define VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_SHIFT)) & VPU_G2_SWREG187_SW_DEC_DSC_BASE_MSB_MASK)
/*! @} */
/*! @name SWREG188 - Base address LSB (bits 31:0) for decoder output raster scan down scale C picture */
/*! @{ */
#define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_SHIFT (0U)
/*! SW_DEC_DSC_BASE_LSB - Base address LSB (bits 31:0) for decoder output raster scan down scale C picture
*/
#define VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_SHIFT)) & VPU_G2_SWREG188_SW_DEC_DSC_BASE_LSB_MASK)
/*! @} */
/*! @name SWREG189 - Base address MSB (bits 63:32) for decoder output compress luminance table */
/*! @{ */
#define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_SHIFT (0U)
/*! SW_DEC_OUT_TYBASE_MSB - Base address MSB (bits 63:32) for decoder output compress luminance table
*/
#define VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG189_SW_DEC_OUT_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG190 - Base address LSB (bits 31:0) for decoder output compress luminance table */
/*! @{ */
#define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_SHIFT (0U)
/*! SW_DEC_OUT_TYBASE_LSB - Base address LSB (bits 31:0) for decoder output compress luminance table
*/
#define VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG190_SW_DEC_OUT_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG191 - Base address MSB (bits 63:32) for reference compress luminance table index 0 */
/*! @{ */
#define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER0_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 0
*/
#define VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG191_SW_REFER0_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG192 - Base address LSB (bits 31:0) for reference compress luminance table index 0 */
/*! @{ */
#define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER0_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 0
*/
#define VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG192_SW_REFER0_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG193 - Base address MSB (bits 63:32) for reference compress luminance table index 1 */
/*! @{ */
#define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER1_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 1
*/
#define VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG193_SW_REFER1_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG194 - Base address LSB (bits 31:0) for reference compress luminance table index 1 */
/*! @{ */
#define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER1_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 1
*/
#define VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG194_SW_REFER1_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG195 - Base address MSB (bits 63:32) for reference compress luminance table index 2 */
/*! @{ */
#define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER2_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 2
*/
#define VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG195_SW_REFER2_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG196 - Base address LSB (bits 31:0) for reference compress luminance table index 2 */
/*! @{ */
#define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER2_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 2
*/
#define VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG196_SW_REFER2_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG197 - Base address MSB (bits 63:32) for reference compress luminance table index 3 */
/*! @{ */
#define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER3_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 3
*/
#define VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG197_SW_REFER3_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG198 - Base address LSB (bits 31:0) for reference compress luminance table index 3 */
/*! @{ */
#define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER3_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 3
*/
#define VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG198_SW_REFER3_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG199 - Base address MSB (bits 63:32) for reference compress luminance table index 4 */
/*! @{ */
#define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER4_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 4
*/
#define VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG199_SW_REFER4_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG200 - Base address LSB (bits 31:0) for reference compress luminance table index 4 */
/*! @{ */
#define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER4_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 4
*/
#define VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG200_SW_REFER4_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG201 - Base address MSB (bits 63:32) for reference compress luminance table index 5 */
/*! @{ */
#define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER5_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 5
*/
#define VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG201_SW_REFER5_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG202 - Base address LSB (bits 31:0) for reference compress luminance table index 5 */
/*! @{ */
#define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER5_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 5
*/
#define VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG202_SW_REFER5_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG203 - Base address MSB (bits 63:32) for reference compress luminance table index 6 */
/*! @{ */
#define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER6_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 6
*/
#define VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG203_SW_REFER6_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG204 - Base address LSB (bits 31:0) for reference compress luminance table index 6 */
/*! @{ */
#define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER6_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 6
*/
#define VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG204_SW_REFER6_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG205 - Base address MSB (bits 63:32) for reference compress luminance table index 7 */
/*! @{ */
#define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER7_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 7
*/
#define VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG205_SW_REFER7_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG206 - Base address LSB (bits 31:0) for reference compress luminance table index 7 */
/*! @{ */
#define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER7_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 7
*/
#define VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG206_SW_REFER7_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG207 - Base address MSB (bits 63:32) for reference compress luminance table index 8 */
/*! @{ */
#define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER8_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 8
*/
#define VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG207_SW_REFER8_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG208 - Base address LSB (bits 31:0) for reference compress luminance table index 8 */
/*! @{ */
#define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER8_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 8
*/
#define VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG208_SW_REFER8_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG209 - Base address MSB (bits 63:32) for reference compress luminance table index 9 */
/*! @{ */
#define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER9_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 9
*/
#define VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG209_SW_REFER9_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG210 - Base address LSB (bits 31:0) for reference compress luminance table index 9 */
/*! @{ */
#define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER9_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 9
*/
#define VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG210_SW_REFER9_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG211 - Base address MSB (bits 63:32) for reference compress luminance table index 10 */
/*! @{ */
#define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER10_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 10
*/
#define VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG211_SW_REFER10_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG212 - Base address LSB (bits 31:0) for reference compress luminance table index 10 */
/*! @{ */
#define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER10_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 10
*/
#define VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG212_SW_REFER10_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG213 - Base address MSB (bits 63:32) for reference compress luminance table index 11 */
/*! @{ */
#define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER11_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 11
*/
#define VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG213_SW_REFER11_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG214 - Base address LSB (bits 31:0) for reference compress luminance table index 11 */
/*! @{ */
#define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER11_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 11
*/
#define VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG214_SW_REFER11_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG215 - Base address MSB (bits 63:32) for reference compress luminance table index 12 */
/*! @{ */
#define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER12_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 12
*/
#define VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG215_SW_REFER12_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG216 - Base address LSB (bits 31:0) for reference compress luminance table index 12 */
/*! @{ */
#define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER12_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 12
*/
#define VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG216_SW_REFER12_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG217 - Base address MSB (bits 63:32) for reference compress luminance table index 13 */
/*! @{ */
#define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER13_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 13
*/
#define VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG217_SW_REFER13_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG218 - Base address LSB (bits 31:0) for reference compress luminance table index 13 */
/*! @{ */
#define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER13_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 13
*/
#define VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG218_SW_REFER13_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG219 - Base address MSB (bits 63:32) for reference compress luminance table index 14 */
/*! @{ */
#define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER14_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 14
*/
#define VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG219_SW_REFER14_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG220 - Base address LSB (bits 31:0) for reference compress luminance table index 14 */
/*! @{ */
#define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER14_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 14
*/
#define VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG220_SW_REFER14_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG221 - Base address MSB (bits 63:32) for reference compress luminance table index 15 */
/*! @{ */
#define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_SHIFT (0U)
/*! SW_REFER15_TYBASE_MSB - Base address MSB (bits 63:32) for reference compress luminance table index 15
*/
#define VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_SHIFT)) & VPU_G2_SWREG221_SW_REFER15_TYBASE_MSB_MASK)
/*! @} */
/*! @name SWREG222 - Base address LSB (bits 31:0) for reference compress luminance table index 15 */
/*! @{ */
#define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_SHIFT (0U)
/*! SW_REFER15_TYBASE_LSB - Base address LSB (bits 31:0) for reference compress luminance table index 15
*/
#define VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_SHIFT)) & VPU_G2_SWREG222_SW_REFER15_TYBASE_LSB_MASK)
/*! @} */
/*! @name SWREG223 - Base address MSB (bits 63:32) for decoder output compress chrominance table */
/*! @{ */
#define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_SHIFT (0U)
/*! SW_DEC_OUT_TCBASE_MSB - Base address MSB (bits 63:32) for decoder output compress chrominance table
*/
#define VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG223_SW_DEC_OUT_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG224 - Base address LSB (bits 31:0) for decoder output compress chrominance table */
/*! @{ */
#define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_SHIFT (0U)
/*! SW_DEC_OUT_TCBASE_LSB - Base address LSB (bits 31:0) for decoder output compress chrominance table
*/
#define VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG224_SW_DEC_OUT_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG225 - Base address MSB (bits 63:32) for reference compress chrominance table index 0 */
/*! @{ */
#define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER0_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 0
*/
#define VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG225_SW_REFER0_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG226 - Base address LSB (bits 31:0) for reference compress chrominance table index 0 */
/*! @{ */
#define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER0_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 0
*/
#define VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG226_SW_REFER0_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG227 - Base address MSB (bits 63:32) for reference compress chrominance table index 1 */
/*! @{ */
#define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER1_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 1
*/
#define VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG227_SW_REFER1_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG228 - Base address LSB (bits 31:0) for reference compress chrominance table index 1 */
/*! @{ */
#define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER1_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 1
*/
#define VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG228_SW_REFER1_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG229 - Base address MSB (bits 63:32) for reference compress chrominance table index 2 */
/*! @{ */
#define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER2_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 2
*/
#define VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG229_SW_REFER2_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG230 - Base address LSB (bits 31:0) for reference compress chrominance table index 2 */
/*! @{ */
#define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER2_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 2
*/
#define VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG230_SW_REFER2_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG231 - Base address MSB (bits 63:32) for reference compress chrominance table index 3 */
/*! @{ */
#define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER3_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 3
*/
#define VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG231_SW_REFER3_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG232 - Base address LSB (bits 31:0) for reference compress chrominance table index 3 */
/*! @{ */
#define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER3_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 3
*/
#define VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG232_SW_REFER3_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG233 - Base address MSB (bits 63:32) for reference compress chrominance table index 4 */
/*! @{ */
#define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER4_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 4
*/
#define VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG233_SW_REFER4_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG234 - Base address LSB (bits 31:0) for reference compress chrominance table index 4 */
/*! @{ */
#define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER4_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 4
*/
#define VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG234_SW_REFER4_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG235 - Base address MSB (bits 63:32) for reference compress chrominance table index 5 */
/*! @{ */
#define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER5_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 5
*/
#define VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG235_SW_REFER5_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG236 - Base address LSB (bits 31:0) for reference compress chrominance table index 5 */
/*! @{ */
#define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER5_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 5
*/
#define VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG236_SW_REFER5_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG237 - Base address MSB (bits 63:32) for reference compress chrominance table index 6 */
/*! @{ */
#define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER6_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 6
*/
#define VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG237_SW_REFER6_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG238 - Base address LSB (bits 31:0) for reference compress chrominance table index 6 */
/*! @{ */
#define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER6_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 6
*/
#define VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG238_SW_REFER6_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG239 - Base address MSB (bits 63:32) for reference compress chrominance table index 7 */
/*! @{ */
#define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER7_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 7
*/
#define VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG239_SW_REFER7_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG240 - Base address LSB (bits 31:0) for reference compress chrominance table index 7 */
/*! @{ */
#define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER7_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 7
*/
#define VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG240_SW_REFER7_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG241 - Base address MSB (bits 63:32) for reference compress chrominance table index 8 */
/*! @{ */
#define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER8_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 8
*/
#define VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG241_SW_REFER8_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG242 - Base address LSB (bits 31:0) for reference compress chrominance table index 8 */
/*! @{ */
#define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER8_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 8
*/
#define VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG242_SW_REFER8_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG243 - Base address MSB (bits 63:32) for reference compress chrominance table index 9 */
/*! @{ */
#define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER9_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 9
*/
#define VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG243_SW_REFER9_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG244 - Base address LSB (bits 31:0) for reference compress chrominance table index 9 */
/*! @{ */
#define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER9_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 9
*/
#define VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG244_SW_REFER9_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG245 - Base address MSB (bits 63:32) for reference compress chrominance table index 10 */
/*! @{ */
#define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER10_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 10
*/
#define VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG245_SW_REFER10_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG246 - Base address LSB (bits 31:0) for reference compress chrominance table index 10 */
/*! @{ */
#define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER10_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 10
*/
#define VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG246_SW_REFER10_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG247 - Base address MSB (bits 63:32) for reference compress chrominance table index 11 */
/*! @{ */
#define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER11_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 11
*/
#define VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG247_SW_REFER11_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG248 - Base address LSB (bits 31:0) for reference compress chrominance table index 11 */
/*! @{ */
#define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER11_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 11
*/
#define VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG248_SW_REFER11_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG249 - Base address MSB (bits 63:32) for reference compress chrominance table index 12 */
/*! @{ */
#define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER12_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 12
*/
#define VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG249_SW_REFER12_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG250 - Base address LSB (bits 31:0) for reference compress chrominance table index 12 */
/*! @{ */
#define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER12_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 12
*/
#define VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG250_SW_REFER12_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG251 - Base address MSB (bits 63:32) for reference compress chrominance table index 13 */
/*! @{ */
#define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER13_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 13
*/
#define VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG251_SW_REFER13_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG252 - Base address LSB (bits 31:0) for reference compress chrominance table index 13 */
/*! @{ */
#define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER13_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 13
*/
#define VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG252_SW_REFER13_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG253 - Base address MSB (bits 63:32) for reference compress chrominance table index 14 */
/*! @{ */
#define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER14_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 14
*/
#define VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG253_SW_REFER14_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG254 - Base address LSB (bits 31:0) for reference compress chrominance table index 14 */
/*! @{ */
#define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER14_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 14
*/
#define VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG254_SW_REFER14_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG255 - Base address MSB (bits 63:32) for reference compress chrominance table index 15 */
/*! @{ */
#define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_SHIFT (0U)
/*! SW_REFER15_TCBASE_MSB - Base address MSB (bits 63:32) for reference compress chrominance table index 15
*/
#define VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_SHIFT)) & VPU_G2_SWREG255_SW_REFER15_TCBASE_MSB_MASK)
/*! @} */
/*! @name SWREG256 - Base address LSB (bits 31:0) for reference compress chrominance table index 15 */
/*! @{ */
#define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_SHIFT (0U)
/*! SW_REFER15_TCBASE_LSB - Base address LSB (bits 31:0) for reference compress chrominance table index 15
*/
#define VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_SHIFT)) & VPU_G2_SWREG256_SW_REFER15_TCBASE_LSB_MASK)
/*! @} */
/*! @name SWREG258 - input stream buffer length */
/*! @{ */
#define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_SHIFT (0U)
/*! SW_STRM_BUFFER_LEN - input stream buffer length
*/
#define VPU_G2_SWREG258_SW_STRM_BUFFER_LEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_SHIFT)) & VPU_G2_SWREG258_SW_STRM_BUFFER_LEN_MASK)
/*! @} */
/*! @name SWREG259 - input stream buffer start offset */
/*! @{ */
#define VPU_G2_SWREG259_SW_STRM_START_OFFSET_MASK (0xFFFFFFFFU)
#define VPU_G2_SWREG259_SW_STRM_START_OFFSET_SHIFT (0U)
/*! SW_STRM_START_OFFSET - input stream buffer start offset
*/
#define VPU_G2_SWREG259_SW_STRM_START_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_G2_SWREG259_SW_STRM_START_OFFSET_SHIFT)) & VPU_G2_SWREG259_SW_STRM_START_OFFSET_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_G2_Register_Masks */
/* VPU_G2 - Peripheral instance base addresses */
/** Peripheral VPU_G2 base address */
#define VPU_G2_BASE (0x38310000u)
/** Peripheral VPU_G2 base pointer */
#define VPU_G2 ((VPU_G2_Type *)VPU_G2_BASE)
/** Array initializer of VPU_G2 peripheral base addresses */
#define VPU_G2_BASE_ADDRS { VPU_G2_BASE }
/** Array initializer of VPU_G2 peripheral base pointers */
#define VPU_G2_BASE_PTRS { VPU_G2 }
/*!
* @}
*/ /* end of group VPU_G2_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_H264 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_H264_Peripheral_Access_Layer VPU_H264 Peripheral Access Layer
* @{
*/
/** VPU_H264 - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t SWREG1; /**< Interrupt register encoder, offset: 0x4 */
__IO uint32_t SWREG2; /**< Data configuration register0, offset: 0x8 */
__IO uint32_t SWREG3; /**< Data configuration register1, offset: 0xC */
__IO uint32_t SWREG4; /**< control register 0, offset: 0x10 */
__IO uint32_t SWREG5; /**< control register 1, offset: 0x14 */
__IO uint32_t SWREG6; /**< control register 2, offset: 0x18 */
__IO uint32_t SWREG7; /**< control register 3, offset: 0x1C */
__IO uint32_t SWREG8; /**< stream output buffer0 address, offset: 0x20 */
__IO uint32_t SWREG9; /**< stream output buffer0 limit size, offset: 0x24 */
__IO uint32_t SWREG10; /**< sizeTblBase, offset: 0x28 */
__IO uint32_t SWREG11; /**< encoded Picture order count, offset: 0x2C */
__IO uint32_t SWREG12; /**< input lum base address, offset: 0x30 */
__IO uint32_t SWREG13; /**< input cb base address, offset: 0x34 */
__IO uint32_t SWREG14; /**< input cr base address, offset: 0x38 */
__IO uint32_t SWREG15; /**< recon image luma base address, offset: 0x3C */
__IO uint32_t SWREG16; /**< recon image chroma base address, offset: 0x40 */
uint8_t RESERVED_1[4];
__IO uint32_t SWREG18; /**< reference picture reconstructed list0 luma0, offset: 0x48 */
__IO uint32_t SWREG19; /**< reference picture reconstructed list0 chroma0, offset: 0x4C */
uint8_t RESERVED_2[8];
__IO uint32_t SWREG22; /**< Cyclic Intra, offset: 0x58 */
__IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */
__IO uint32_t SWREG24; /**< ROI1 Area, offset: 0x60 */
__IO uint32_t SWREG25; /**< ROI2 Area, offset: 0x64 */
__IO uint32_t SWREG26_H2V2; /**< intra size factors. For H2V2 or later version., offset: 0x68 */
__IO uint32_t SWREG27_H2V2; /**< intra mode factors . For H2V2 or later version., offset: 0x6C */
__IO uint32_t SWREG28_H2V5; /**< inter me SATD lambda config 0. For H2V5 or later version., offset: 0x70 */
__IO uint32_t SWREG29_H2V5; /**< inter me SATD lambda config 1. For H2V5 or later version., offset: 0x74 */
__IO uint32_t SWREG30_H2V5; /**< inter me SATD lambda config 2. For H2V5 or later version., offset: 0x78 */
__IO uint32_t SWREG31_H2V5; /**< inter me SATD lambda config 3. For H2V5 or later version., offset: 0x7C */
__IO uint32_t SWREG32_H2V5; /**< inter me SATD lambda config 4. For H2V5 or later version., offset: 0x80 */
__IO uint32_t SWREG33_H2V5; /**< inter me SATD lambda config 5. For H2V5 or later version., offset: 0x84 */
__IO uint32_t SWREG34_H2V5; /**< inter me SATD lambda config 6. For H2V5 or later version., offset: 0x88 */
__IO uint32_t SWREG35; /**< inter prediction parameters1, offset: 0x8C */
__IO uint32_t SWREG36; /**< inter prediction parameters2, offset: 0x90 */
__IO uint32_t SWREG37; /**< SAO lambda parameter, offset: 0x94 */
__IO uint32_t SWREG38; /**< Pre-processor configuration, offset: 0x98 */
__IO uint32_t SWREG39; /**< Pre-processor color conversion parameters0, offset: 0x9C */
__IO uint32_t SWREG40; /**< Pre-processor color conversion parameters1, offset: 0xA0 */
__IO uint32_t SWREG41; /**< Pre-processor color conversion parameters2, offset: 0xA4 */
__IO uint32_t SWREG42; /**< Pre-processor Base address for down-scaled output, offset: 0xA8 */
__IO uint32_t SWREG43; /**< Pre-processor down-scaled configuration0, offset: 0xAC */
__IO uint32_t SWREG44; /**< Pre-processor down-scaled configuration1, offset: 0xB0 */
__IO uint32_t SWREG45; /**< Pre-processor down-scaled configuration2, offset: 0xB4 */
__IO uint32_t SWREG46; /**< compressed coefficients base address for SAN module., offset: 0xB8 */
uint8_t RESERVED_3[52];
__IO uint32_t SWREG60; /**< Base address for recon luma compress table LSB., offset: 0xF0 */
uint8_t RESERVED_4[4];
__IO uint32_t SWREG62; /**< Base address for recon Chroma compress table LSB, offset: 0xF8 */
uint8_t RESERVED_5[4];
__IO uint32_t SWREG64; /**< Base address for list 0 ref 0 luma compress table LSB., offset: 0x100 */
uint8_t RESERVED_6[4];
__IO uint32_t SWREG66; /**< Base address for list 0 ref 0 Chroma compress table LSB., offset: 0x108 */
uint8_t RESERVED_7[20];
__IO uint32_t SWREG72; /**< Base address for recon luma 4n base LSB., offset: 0x120 */
uint8_t RESERVED_8[4];
__IO uint32_t SWREG74; /**< reference picture reconstructed list0 4n 0, offset: 0x128 */
uint8_t RESERVED_9[12];
__IO uint32_t SWREG78_H2V5; /**< inter me SATD lambda config 7. For H2V5 or later version., offset: 0x138 */
__IO uint32_t SWREG79_H2V5; /**< inter me SSE lambda config 0. For H2V5 or later version., offset: 0x13C */
__I uint32_t SWREG80; /**< HW synthesis config register, read-only, offset: 0x140 */
__IO uint32_t SWREG81; /**< hardware configuation 0, offset: 0x144 */
__I uint32_t SWREG82; /**< record hardware performance, offset: 0x148 */
__IO uint32_t SWREG83; /**< reference picture reconstructed list1 luma0, offset: 0x14C */
__IO uint32_t SWREG84; /**< reference picture reconstructed list1 chroma0, offset: 0x150 */
uint8_t RESERVED_10[24];
__IO uint32_t SWREG91; /**< reference pictures list1 config, offset: 0x16C */
__IO uint32_t SWREG92; /**< reference picture reconstructed list1 4n 0, offset: 0x170 */
uint8_t RESERVED_11[12];
__IO uint32_t SWREG96; /**< Base address for list 1 ref 0 luma compress table LSB., offset: 0x180 */
uint8_t RESERVED_12[4];
__IO uint32_t SWREG98; /**< Base address for list 1 ref 0 Chroma compress table LSB., offset: 0x188 */
uint8_t RESERVED_13[28];
__IO uint32_t SWREG106; /**< Min picture size, offset: 0x1A8 */
__IO uint32_t SWREG107; /**< Max picture size, offset: 0x1AC */
uint8_t RESERVED_14[4];
__IO uint32_t SWREG109; /**< Qp delta map, offset: 0x1B4 */
uint8_t RESERVED_15[4];
__I uint32_t SWREG111; /**< adaptive GOP configuration1, offset: 0x1BC */
__I uint32_t SWREG112; /**< adaptive GOP configuration2, offset: 0x1C0 */
__IO uint32_t SWREG113; /**< adaptive GOP configuration3, offset: 0x1C4 */
__IO uint32_t SWREG114; /**< ctb rate control bit memory address of current frame, offset: 0x1C8 */
uint8_t RESERVED_16[4];
__IO uint32_t SWREG116; /**< ctb rate control bit memory address of previous frame, offset: 0x1D0 */
uint8_t RESERVED_17[8];
__IO uint32_t SWREG119; /**< min/max lcu bits number of last picture, offset: 0x1DC */
__IO uint32_t SWREG120; /**< total bits number of all lcus of last picture not including slice header bits, offset: 0x1E0 */
uint8_t RESERVED_18[4];
__IO uint32_t SWREG122_H2V5; /**< inter me SSE lambda config 1. For H2V5 or later version., offset: 0x1E8 */
__IO uint32_t SWREG123_H2V5; /**< inter me SSE lambda config 2. For H2V5 or later version., offset: 0x1EC */
__IO uint32_t SWREG124_H2V5; /**< inter me SSE lambda config 3. For H2V5 or later version., offset: 0x1F0 */
__IO uint32_t SWREG125; /**< intra SATD lambda config 0, offset: 0x1F4 */
__IO uint32_t SWREG126; /**< intra SATD lambda config 1, offset: 0x1F8 */
__IO uint32_t SWREG127; /**< intra SATD lambda config 2, offset: 0x1FC */
__IO uint32_t SWREG128; /**< intra SATD lambda config 3, offset: 0x200 */
__IO uint32_t SWREG129; /**< intra SATD lambda config 4, offset: 0x204 */
__IO uint32_t SWREG130; /**< intra SATD lambda config 5, offset: 0x208 */
__IO uint32_t SWREG131; /**< intra SATD lambda config 6, offset: 0x20C */
__IO uint32_t SWREG132; /**< intra SATD lambda config 7, offset: 0x210 */
__IO uint32_t SWREG133; /**< SSE devide 256, offset: 0x214 */
uint8_t RESERVED_19[16];
__IO uint32_t SWREG138_H2V5; /**< inter me SSE lambda config 4. For H2V5 or later version., offset: 0x228 */
__IO uint32_t SWREG139_H2V5; /**< inter me SSE lambda config 5. For H2V5 or later version., offset: 0x22C */
__IO uint32_t SWREG140_H2V5; /**< inter me SSE lambda config 6. For H2V5 or later version., offset: 0x230 */
__IO uint32_t SWREG141_H2V5; /**< inter me SSE lambda config 7. For H2V5 or later version., offset: 0x234 */
__IO uint32_t SWREG142_H2V5; /**< inter me SSE lambda config 8. For H2V5 or later version., offset: 0x238 */
__IO uint32_t SWREG143_H2V5; /**< inter me SSE lambda config 9. For H2V5 or later version., offset: 0x23C */
__IO uint32_t SWREG144_H2V5; /**< inter me SSE lambda config 10. For H2V5 or later version., offset: 0x240 */
__IO uint32_t SWREG145_H2V5; /**< inter me SSE lambda config 11. For H2V5 or later version., offset: 0x244 */
__IO uint32_t SWREG146_H2V5; /**< inter me SSE lambda config 12. For H2V5 or later version., offset: 0x248 */
__IO uint32_t SWREG147_H2V5; /**< inter me SSE lambda config 13. For H2V5 or later version., offset: 0x24C */
__IO uint32_t SWREG148_H2V5; /**< inter me SSE lambda config 14. For H2V5 or later version., offset: 0x250 */
__IO uint32_t SWREG149_H2V5; /**< inter me SSE lambda config 15. For H2V5 or later version., offset: 0x254 */
__IO uint32_t SWREG150; /**< inter me SATD lambda config 8, offset: 0x258 */
__IO uint32_t SWREG151; /**< inter me SATD lambda config 9, offset: 0x25C */
__IO uint32_t SWREG152; /**< inter me SATD lambda config 10, offset: 0x260 */
__IO uint32_t SWREG153; /**< inter me SATD lambda config 11, offset: 0x264 */
__IO uint32_t SWREG154; /**< inter me SATD lambda config 12, offset: 0x268 */
__IO uint32_t SWREG155; /**< inter me SATD lambda config 13, offset: 0x26C */
__IO uint32_t SWREG156; /**< inter me SATD lambda config 14, offset: 0x270 */
__IO uint32_t SWREG157; /**< inter me SATD lambda config 15, offset: 0x274 */
__IO uint32_t SWREG158; /**< inter me SSE lambda config 16, offset: 0x278 */
__IO uint32_t SWREG159; /**< inter me SSE lambda config 17, offset: 0x27C */
__IO uint32_t SWREG160; /**< inter me SSE lambda config 18, offset: 0x280 */
__IO uint32_t SWREG161; /**< inter me SSE lambda config 19, offset: 0x284 */
__IO uint32_t SWREG162; /**< inter me SSE lambda config 20, offset: 0x288 */
__IO uint32_t SWREG163; /**< inter me SSE lambda config 21, offset: 0x28C */
__IO uint32_t SWREG164; /**< inter me SSE lambda config 22, offset: 0x290 */
__IO uint32_t SWREG165; /**< inter me SSE lambda config 23, offset: 0x294 */
__IO uint32_t SWREG166; /**< inter me SSE lambda config 24, offset: 0x298 */
__IO uint32_t SWREG167; /**< inter me SSE lambda config 25, offset: 0x29C */
__IO uint32_t SWREG168; /**< inter me SSE lambda config 26, offset: 0x2A0 */
__IO uint32_t SWREG169; /**< inter me SSE lambda config 27, offset: 0x2A4 */
uint8_t RESERVED_20[8];
__IO uint32_t SWREG172; /**< inter me SSE lambda config 30, offset: 0x2B0 */
__IO uint32_t SWREG173; /**< inter me SSE lambda config 31, offset: 0x2B4 */
__IO uint32_t SWREG174; /**< intra SATD lambda config 8, offset: 0x2B8 */
__IO uint32_t SWREG175; /**< intra SATD lambda config 9, offset: 0x2BC */
__IO uint32_t SWREG176; /**< intra SATD lambda config 10, offset: 0x2C0 */
__IO uint32_t SWREG177; /**< intra SATD lambda config 11, offset: 0x2C4 */
__IO uint32_t SWREG178; /**< intra SATD lambda config 12, offset: 0x2C8 */
__IO uint32_t SWREG179; /**< intra SATD lambda config 13, offset: 0x2CC */
__IO uint32_t SWREG180; /**< intra SATD lambda config 14, offset: 0x2D0 */
__IO uint32_t SWREG181; /**< intra SATD lambda config 15, offset: 0x2D4 */
__IO uint32_t SWREG182; /**< qp fractional part, offset: 0x2D8 */
__I uint32_t SWREG183; /**< qp sum, offset: 0x2DC */
__I uint32_t SWREG184; /**< qp num, offset: 0x2E0 */
__IO uint32_t SWREG185; /**< picture complexity. Timeout cycles MSB., offset: 0x2E4 */
uint8_t RESERVED_21[16];
__IO uint32_t SWREG190; /**< Long-term reference pictures config, offset: 0x2F8 */
__IO uint32_t SWREG191; /**< Temporal scalable config, offset: 0x2FC */
__IO uint32_t SWREG192; /**< encoded Picture frame number (for H.264), offset: 0x300 */
__IO uint32_t SWREG193; /**< reference pictures list0 config (for H.264), offset: 0x304 */
__IO uint32_t SWREG194; /**< reference pictures list1 config (for H.264), offset: 0x308 */
__IO uint32_t SWREG195; /**< register extension for ctu_size=16, offset: 0x30C */
__IO uint32_t SWREG196; /**< Low Latency Controls, offset: 0x310 */
__IO uint32_t SWREG197; /**< Delta POC extension, offset: 0x314 */
__IO uint32_t SWREG198; /**< Long Term Reference Control, offset: 0x318 */
__IO uint32_t SWREG199; /**< Hash Code Control, offset: 0x31C */
__IO uint32_t SWREG200; /**< Hash Code Value, offset: 0x320 */
__IO uint32_t SWREG201; /**< Background SKIP Control 0, offset: 0x324 */
uint8_t RESERVED_22[4];
__IO uint32_t SWREG203; /**< Background SKIP Control 2, offset: 0x32C */
uint8_t RESERVED_23[16];
__IO uint32_t SWREG208; /**< Background SKIP Control 7, offset: 0x340 */
__IO uint32_t SWREG209; /**< IPCM Control 0, offset: 0x344 */
__IO uint32_t SWREG210; /**< IPCM Control 1, offset: 0x348 */
__IO uint32_t SWREG211; /**< IPCM Control 2, offset: 0x34C */
__IO uint32_t SWREG212; /**< IPCM Control 3, offset: 0x350 */
__IO uint32_t SWREG213; /**< IPCM Control 4, offset: 0x354 */
__I uint32_t SWREG214; /**< HW synthesis config register 2, read-only, offset: 0x358 */
__I uint32_t SWREG215; /**< AXI Information 0, offset: 0x35C */
__I uint32_t SWREG216; /**< AXI Information 1, offset: 0x360 */
__I uint32_t SWREG217; /**< AXI Information 2, offset: 0x364 */
__I uint32_t SWREG218; /**< AXI Information 3, offset: 0x368 */
__I uint32_t SWREG219; /**< AXI Information 4, offset: 0x36C */
__I uint32_t SWREG220; /**< AXI Information 5, offset: 0x370 */
__I uint32_t SWREG221; /**< AXI Information 6, offset: 0x374 */
__I uint32_t SWREG222; /**< AXI Information 7, offset: 0x378 */
__I uint32_t SWREG223; /**< AXI Information 8, offset: 0x37C */
__IO uint32_t SWREG224; /**< control register 4, offset: 0x380 */
__IO uint32_t SWREG225; /**< Tile Control, offset: 0x384 */
__I uint32_t SWREG226; /**< HW synthesis config register 3, read-only, offset: 0x388 */
uint8_t RESERVED_24[32];
__IO uint32_t SWREG235; /**< RPS encoding control 0, offset: 0x3AC */
__IO uint32_t SWREG236; /**< RPS encoding control 1, offset: 0x3B0 */
__IO uint32_t SWREG237; /**< Stride Control, offset: 0x3B4 */
__IO uint32_t SWREG238; /**< Dummy Read, offset: 0x3B8 */
__IO uint32_t SWREG239; /**< Base Address LSB of CTB MADs of current frame., offset: 0x3BC */
uint8_t RESERVED_25[4];
__IO uint32_t SWREG241; /**< Base Address LSB of CTB MADs of previous frame., offset: 0x3C4 */
uint8_t RESERVED_26[4];
__IO uint32_t SWREG243; /**< CTB RC Control 0, offset: 0x3CC */
__IO uint32_t SWREG244; /**< CTB RC Control 1, offset: 0x3D0 */
__IO uint32_t SWREG245; /**< CTB RC Control 2, offset: 0x3D4 */
__IO uint32_t SWREG246; /**< CTB RC Control 3, offset: 0x3D8 */
__IO uint32_t SWREG247; /**< CTB RC Control 4, offset: 0x3DC */
__IO uint32_t SWREG248; /**< CTB RC Control 5, offset: 0x3E0 */
__IO uint32_t SWREG249; /**< register extension for 8K width, offset: 0x3E4 */
__IO uint32_t SWREG250; /**< Global MV Control 0, offset: 0x3E8 */
__IO uint32_t SWREG251; /**< Global MV Control 1, offset: 0x3EC */
__IO uint32_t SWREG252; /**< ROI3 Area, offset: 0x3F0 */
__IO uint32_t SWREG253; /**< ROI3&4 Area, offset: 0x3F4 */
__IO uint32_t SWREG254; /**< ROI4&5 Area, offset: 0x3F8 */
__IO uint32_t SWREG255; /**< ROI5 Area, offset: 0x3FC */
__IO uint32_t SWREG256; /**< ROI6 Area, offset: 0x400 */
__IO uint32_t SWREG257; /**< ROI6&7 Area, offset: 0x404 */
__IO uint32_t SWREG258; /**< ROI7&8 Area, offset: 0x408 */
__IO uint32_t SWREG259; /**< ROI8 Area, offset: 0x40C */
__IO uint32_t SWREG260; /**< ROI qp, offset: 0x410 */
__IO uint32_t SWREG261; /**< Stride Control, offset: 0x414 */
uint8_t RESERVED_27[12];
__IO uint32_t SWREG265; /**< Multicore sync ctrl, offset: 0x424 */
__IO uint32_t SWREG266; /**< Multicore sync address L0 LSB, offset: 0x428 */
__IO uint32_t SWREG267; /**< Multicore sync address L0 MSB, offset: 0x42C */
__IO uint32_t SWREG268; /**< Multicore sync address L1 LSB, offset: 0x430 */
__IO uint32_t SWREG269; /**< Multicore sync address L1 MSB, offset: 0x434 */
__IO uint32_t SWREG270; /**< Multicore sync address recon LSB, offset: 0x438 */
__IO uint32_t SWREG271; /**< Multicore sync address recon MSB, offset: 0x43C */
__IO uint32_t SWREG272; /**< Programmable AXI urgent sideband signals, offset: 0x440 */
__IO uint32_t SWREG273; /**< roimap cu ctrl index address LSB, offset: 0x444 */
__IO uint32_t SWREG274; /**< roimap cu ctrl index address MSB, offset: 0x448 */
__IO uint32_t SWREG275; /**< roimap cu ctrl address LSB, offset: 0x44C */
__IO uint32_t SWREG276; /**< roimap cu ctrl address MSB, offset: 0x450 */
__IO uint32_t SWREG277; /**< poc type/bits setting, offset: 0x454 */
__IO uint32_t SWREG278; /**< stream output buffer1 address, offset: 0x458 */
uint8_t RESERVED_28[4];
__IO uint32_t SWREG280; /**< stream output buffer1 limit size, offset: 0x460 */
__IO uint32_t SWREG281; /**< poc type/bits setting, offset: 0x464 */
uint8_t RESERVED_29[20];
__I uint32_t SWREG287; /**< HW synthesis config register 4, read-only, offset: 0x47C */
uint8_t RESERVED_30[4];
__IO uint32_t SWREG289; /**< Pre-processor color conversion parameters1, offset: 0x484 */
} VPU_H264_Type;
/* ----------------------------------------------------------------------------
-- VPU_H264 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_H264_Register_Masks VPU_H264 Register Masks
* @{
*/
/*! @name SWREG1 - Interrupt register encoder */
/*! @{ */
#define VPU_H264_SWREG1_SW_ENC_IRQ_MASK (0x1U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT (0U)
#define VPU_H264_SWREG1_SW_ENC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_MASK)
#define VPU_H264_SWREG1_SW_ENC_IRQ_DIS_MASK (0x2U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_DIS_SHIFT (1U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_DIS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_DIS_MASK)
#define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK (0x4U)
#define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT (2U)
#define VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK)
#define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK (0x8U)
#define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT (3U)
#define VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK)
#define VPU_H264_SWREG1_SW_ENC_SW_RESET_MASK (0x10U)
#define VPU_H264_SWREG1_SW_ENC_SW_RESET_SHIFT (4U)
#define VPU_H264_SWREG1_SW_ENC_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_SW_RESET_SHIFT)) & VPU_H264_SWREG1_SW_ENC_SW_RESET_MASK)
#define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_MASK (0x20U)
#define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_SHIFT (5U)
#define VPU_H264_SWREG1_SW_ENC_BUFFER_FULL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_SHIFT)) & VPU_H264_SWREG1_SW_ENC_BUFFER_FULL_MASK)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT_MASK (0x40U)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT_SHIFT (6U)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_TIMEOUT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_TIMEOUT_MASK)
#define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK (0x80U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT (7U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK)
#define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK (0x100U)
#define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT (8U)
#define VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT)) & VPU_H264_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK)
#define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK (0x200U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT (9U)
#define VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT)) & VPU_H264_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_MASK (0x800U)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT (11U)
#define VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_TIMEOUT_INT_MASK)
#define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK (0x1000U)
#define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT (12U)
#define VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT)) & VPU_H264_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK)
/*! @} */
/*! @name SWREG2 - Data configuration register0 */
/*! @{ */
#define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK (0xFU)
#define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT (0U)
#define VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK)
#define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK (0xF0U)
#define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT (4U)
#define VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK)
#define VPU_H264_SWREG2_SW_ENC_PIC_SWAP_MASK (0xF00U)
#define VPU_H264_SWREG2_SW_ENC_PIC_SWAP_SHIFT (8U)
#define VPU_H264_SWREG2_SW_ENC_PIC_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_PIC_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_PIC_SWAP_MASK)
#define VPU_H264_SWREG2_SW_ENC_STRM_SWAP_MASK (0xF000U)
#define VPU_H264_SWREG2_SW_ENC_STRM_SWAP_SHIFT (12U)
#define VPU_H264_SWREG2_SW_ENC_STRM_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_STRM_SWAP_SHIFT)) & VPU_H264_SWREG2_SW_ENC_STRM_SWAP_MASK)
#define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_MASK (0xFF0000U)
#define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_SHIFT (16U)
#define VPU_H264_SWREG2_SW_ENC_AXI_READ_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_SHIFT)) & VPU_H264_SWREG2_SW_ENC_AXI_READ_ID_MASK)
#define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_MASK (0xFF000000U)
#define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT (24U)
#define VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT)) & VPU_H264_SWREG2_SW_ENC_AXI_WRITE_ID_MASK)
/*! @} */
/*! @name SWREG3 - Data configuration register1 */
/*! @{ */
#define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK (0x2U)
#define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT (1U)
#define VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK)
#define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK (0x4U)
#define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT (2U)
#define VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK)
#define VPU_H264_SWREG3_SW_ENC_SLICE_INT_MASK (0x8U)
#define VPU_H264_SWREG3_SW_ENC_SLICE_INT_SHIFT (3U)
#define VPU_H264_SWREG3_SW_ENC_SLICE_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_SLICE_INT_SHIFT)) & VPU_H264_SWREG3_SW_ENC_SLICE_INT_MASK)
#define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK (0xF00000U)
#define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT (20U)
#define VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK)
#define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_MASK (0x1000000U)
#define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT (24U)
/*! SW_ENC_AXI_RD_ID_E
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_AXI_RD_ID_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_MASK (0x2000000U)
#define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT (25U)
/*! SW_ENC_AXI_WR_ID_E
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_AXI_WR_ID_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK (0x4000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT (26U)
/*! SW_ENC_CLOCK_GATE_INTER_H264_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK (0x8000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT (27U)
/*! SW_ENC_CLOCK_GATE_INTER_H265_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK (0x10000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT (28U)
/*! SW_ENC_CLOCK_GATE_INTER_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK (0x20000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT (29U)
/*! SW_ENC_CLOCK_GATE_ENCODER_H264_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK (0x40000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT (30U)
/*! SW_ENC_CLOCK_GATE_ENCODER_H265_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK (0x80000000U)
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT (31U)
/*! SW_ENC_CLOCK_GATE_ENCODER_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT)) & VPU_H264_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK)
/*! @} */
/*! @name SWREG4 - control register 0 */
/*! @{ */
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK (0x7U)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT (0U)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK (0x38U)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT (3U)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK)
#define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK (0x100U)
#define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT (8U)
#define VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT)) & VPU_H264_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK)
#define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_MASK (0x800U)
#define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT (11U)
#define VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT)) & VPU_H264_SWREG4_SW_BW_LINEBUF_DISABLE_MASK)
#define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK (0x3E000U)
#define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT (13U)
#define VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT)) & VPU_H264_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK)
#define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK (0x40000U)
#define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT (18U)
/*! SW_ENC_OUTPUT_STRM_MODE
* 0b0..byte stream
* 0b1..Nal stream
*/
#define VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK (0x180000U)
#define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT (19U)
/*! SW_ENC_MAX_TRB_SIZE
* 0b00..4x4
* 0b01..8x8
* 0b10..16x16
* 0b11..32x32
*/
#define VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK)
#define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK (0x600000U)
#define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT (21U)
/*! SW_ENC_MIN_TRB_SIZE
* 0b00..4x4
* 0b01..8x8
* 0b10..16x16
* 0b11..32x32
*/
#define VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK)
#define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_MASK (0x1800000U)
#define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT (23U)
/*! SW_ENC_MAX_CB_SIZE
* 0b00..8x8
* 0b01..16x16
* 0b10..32x32
* 0b11..64x64
*/
#define VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MAX_CB_SIZE_MASK)
#define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_MASK (0x6000000U)
#define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT (25U)
/*! SW_ENC_MIN_CB_SIZE
* 0b00..8x8
* 0b01..16x16
* 0b10..32x32
* 0b11..64x64
*/
#define VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MIN_CB_SIZE_MASK)
#define VPU_H264_SWREG4_SW_ENC_MODE_MASK (0xE0000000U)
#define VPU_H264_SWREG4_SW_ENC_MODE_SHIFT (29U)
/*! SW_ENC_MODE
* 0b001..hevc.
* 0b010..h264.
* 0b100..jpeg
*/
#define VPU_H264_SWREG4_SW_ENC_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG4_SW_ENC_MODE_SHIFT)) & VPU_H264_SWREG4_SW_ENC_MODE_MASK)
/*! @} */
/*! @name SWREG5 - control register 1 */
/*! @{ */
#define VPU_H264_SWREG5_SW_ENC_E_MASK (0x1U)
#define VPU_H264_SWREG5_SW_ENC_E_SHIFT (0U)
#define VPU_H264_SWREG5_SW_ENC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_E_SHIFT)) & VPU_H264_SWREG5_SW_ENC_E_MASK)
#define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK (0x6U)
#define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT (1U)
#define VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT)) & VPU_H264_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK)
#define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK (0x100U)
#define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT (8U)
/*! SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG
* 0b0..no
* 0b1..yes
*/
#define VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT)) & VPU_H264_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK)
#define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK (0x200U)
#define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT (9U)
/*! SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG
* 0b0..disable
* 0b1..enable
*/
#define VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK)
#define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_MASK (0x3FF800U)
#define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT (11U)
#define VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PIC_HEIGHT_MASK)
#define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_MASK (0xFFC00000U)
#define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_SHIFT (22U)
#define VPU_H264_SWREG5_SW_ENC_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_SHIFT)) & VPU_H264_SWREG5_SW_ENC_PIC_WIDTH_MASK)
/*! @} */
/*! @name SWREG6 - control register 2 */
/*! @{ */
#define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_MASK (0x1U)
#define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_SHIFT (0U)
#define VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_SHIFT)) & VPU_H264_SWREG6_SW_ENC_CU_QP_DELTA_ENABLED_MASK)
#define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_MASK (0x2U)
#define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_SHIFT (1U)
#define VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_SHIFT)) & VPU_H264_SWREG6_SW_ENC_NAL_SIZE_WRITE_MASK)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_MASK (0x780U)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_SHIFT (7U)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_BETA_OFFSET_MASK)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_MASK (0x7800U)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_SHIFT (11U)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_TC_OFFSET_MASK)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_MASK (0x8000U)
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_SHIFT (15U)
/*! SW_ENC_DEBLOCKING_FILTER_CTRL
* 0b1..filtering is disabled for current picture.
* 0b0..filtering is enabled for current picture.
*/
#define VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_SHIFT)) & VPU_H264_SWREG6_SW_ENC_DEBLOCKING_FILTER_CTRL_MASK)
#define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_MASK (0xFE000000U)
#define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_SHIFT (25U)
#define VPU_H264_SWREG6_SW_ENC_SLICE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_SHIFT)) & VPU_H264_SWREG6_SW_ENC_SLICE_SIZE_MASK)
/*! @} */
/*! @name SWREG7 - control register 3 */
/*! @{ */
#define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK (0xFU)
#define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT (0U)
#define VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK)
#define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK (0xF0U)
#define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT (4U)
#define VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK)
#define VPU_H264_SWREG7_SW_ENC_PIC_QP_MASK (0x3F00U)
#define VPU_H264_SWREG7_SW_ENC_PIC_QP_SHIFT (8U)
#define VPU_H264_SWREG7_SW_ENC_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_PIC_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_PIC_QP_MASK)
#define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK (0xC000U)
#define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT (14U)
#define VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT)) & VPU_H264_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK)
#define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_MASK (0x1FE0000U)
#define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT (17U)
#define VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT)) & VPU_H264_SWREG7_SW_ENC_NUM_SLICES_READY_MASK)
#define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK (0x2000000U)
#define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT (25U)
#define VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT)) & VPU_H264_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK)
#define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_MASK (0xFC000000U)
#define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT (26U)
#define VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT)) & VPU_H264_SWREG7_SW_ENC_PIC_INIT_QP_MASK)
/*! @} */
/*! @name SWREG8 - stream output buffer0 address */
/*! @{ */
#define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT (0U)
#define VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT)) & VPU_H264_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK)
/*! @} */
/*! @name SWREG9 - stream output buffer0 limit size */
/*! @{ */
#define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT (0U)
#define VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT)) & VPU_H264_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK)
/*! @} */
/*! @name SWREG10 - sizeTblBase */
/*! @{ */
#define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT (0U)
#define VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT)) & VPU_H264_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK)
/*! @} */
/*! @name SWREG11 - encoded Picture order count */
/*! @{ */
#define VPU_H264_SWREG11_SW_ENC_POC_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG11_SW_ENC_POC_SHIFT (0U)
#define VPU_H264_SWREG11_SW_ENC_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG11_SW_ENC_POC_SHIFT)) & VPU_H264_SWREG11_SW_ENC_POC_MASK)
/*! @} */
/*! @name SWREG12 - input lum base address */
/*! @{ */
#define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT (0U)
#define VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT)) & VPU_H264_SWREG12_SW_ENC_INPUT_Y_BASE_MASK)
/*! @} */
/*! @name SWREG13 - input cb base address */
/*! @{ */
#define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT (0U)
#define VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT)) & VPU_H264_SWREG13_SW_ENC_INPUT_CB_BASE_MASK)
/*! @} */
/*! @name SWREG14 - input cr base address */
/*! @{ */
#define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT (0U)
#define VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT)) & VPU_H264_SWREG14_SW_ENC_INPUT_CR_BASE_MASK)
/*! @} */
/*! @name SWREG15 - recon image luma base address */
/*! @{ */
#define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT (0U)
#define VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT)) & VPU_H264_SWREG15_SW_ENC_RECON_Y_BASE_MASK)
/*! @} */
/*! @name SWREG16 - recon image chroma base address */
/*! @{ */
#define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT (0U)
#define VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT)) & VPU_H264_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK)
/*! @} */
/*! @name SWREG18 - reference picture reconstructed list0 luma0 */
/*! @{ */
#define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT (0U)
#define VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT)) & VPU_H264_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK)
/*! @} */
/*! @name SWREG19 - reference picture reconstructed list0 chroma0 */
/*! @{ */
#define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT (0U)
#define VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT)) & VPU_H264_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK)
/*! @} */
/*! @name SWREG22 - Cyclic Intra */
/*! @{ */
#define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_MASK (0xFU)
#define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT (0U)
#define VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT)) & VPU_H264_SWREG22_SW_ENC_RCROI_ENABLE_MASK)
#define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_MASK (0x3FFF0U)
#define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT (4U)
#define VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT)) & VPU_H264_SWREG22_SW_ENC_CIR_INTERVAL_MASK)
#define VPU_H264_SWREG22_SW_ENC_CIR_START_MASK (0xFFFC0000U)
#define VPU_H264_SWREG22_SW_ENC_CIR_START_SHIFT (18U)
#define VPU_H264_SWREG22_SW_ENC_CIR_START(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG22_SW_ENC_CIR_START_SHIFT)) & VPU_H264_SWREG22_SW_ENC_CIR_START_MASK)
/*! @} */
/*! @name SWREG23 - intra Area */
/*! @{ */
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK (0xFFU)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT (0U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK (0xFF00U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT (8U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK (0xFF0000U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT (16U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK (0xFF000000U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT (24U)
#define VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT)) & VPU_H264_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK)
/*! @} */
/*! @name SWREG24 - ROI1 Area */
/*! @{ */
#define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_MASK (0xFFU)
#define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT (0U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_BOTTOM_MASK)
#define VPU_H264_SWREG24_SW_ENC_ROI1_TOP_MASK (0xFF00U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_TOP_SHIFT (8U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_TOP_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_TOP_MASK)
#define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_MASK (0xFF0000U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT (16U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_RIGHT_MASK)
#define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_MASK (0xFF000000U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_SHIFT (24U)
#define VPU_H264_SWREG24_SW_ENC_ROI1_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_SHIFT)) & VPU_H264_SWREG24_SW_ENC_ROI1_LEFT_MASK)
/*! @} */
/*! @name SWREG25 - ROI2 Area */
/*! @{ */
#define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_MASK (0xFFU)
#define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT (0U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_BOTTOM_MASK)
#define VPU_H264_SWREG25_SW_ENC_ROI2_TOP_MASK (0xFF00U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_TOP_SHIFT (8U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_TOP_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_TOP_MASK)
#define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_MASK (0xFF0000U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT (16U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_RIGHT_MASK)
#define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_MASK (0xFF000000U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_SHIFT (24U)
#define VPU_H264_SWREG25_SW_ENC_ROI2_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_SHIFT)) & VPU_H264_SWREG25_SW_ENC_ROI2_LEFT_MASK)
/*! @} */
/*! @name SWREG26_H2V2 - intra size factors. For H2V2 or later version. */
/*! @{ */
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK (0xFFCU)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT (2U)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK (0x3FF000U)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT (12U)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK (0xFFC00000U)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT (22U)
#define VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT)) & VPU_H264_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK)
/*! @} */
/*! @name SWREG27_H2V2 - intra mode factors . For H2V2 or later version. */
/*! @{ */
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK (0x7F0U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT (4U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK (0x1F800U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT (11U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK (0x3E0000U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT (17U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK (0xFFC00000U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT (22U)
#define VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT)) & VPU_H264_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK)
/*! @} */
/*! @name SWREG28_H2V5 - inter me SATD lambda config 0. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK)
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG29_H2V5 - inter me SATD lambda config 1. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK)
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG30_H2V5 - inter me SATD lambda config 2. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK)
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG31_H2V5 - inter me SATD lambda config 3. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK)
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG32_H2V5 - inter me SATD lambda config 4. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK)
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG33_H2V5 - inter me SATD lambda config 5. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK)
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG34_H2V5 - inter me SATD lambda config 6. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK)
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG35 - inter prediction parameters1 */
/*! @{ */
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK (0xFFU)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT (0U)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK (0x7F00U)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT (8U)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK (0x38000U)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT (15U)
#define VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT)) & VPU_H264_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK)
#define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK (0xFFFC0000U)
#define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT (18U)
#define VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT)) & VPU_H264_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK)
/*! @} */
/*! @name SWREG36 - inter prediction parameters2 */
/*! @{ */
#define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK (0x3U)
#define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT (0U)
/*! SW_ENC_OUTPUT_BITWIDTH_CHROMA
* 0b00..8 bit.
* 0b01..9 bit.
* 0b10..10 bit.
*/
#define VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT)) & VPU_H264_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK (0x3CU)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT (2U)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK)
#define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK (0x1FC0U)
#define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT (6U)
#define VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT)) & VPU_H264_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK (0x7FE000U)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT (13U)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK (0xFF800000U)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT (23U)
#define VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT)) & VPU_H264_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK)
/*! @} */
/*! @name SWREG37 - SAO lambda parameter */
/*! @{ */
#define VPU_H264_SWREG37_SW_ENC_CHROFFSET_MASK (0xFU)
#define VPU_H264_SWREG37_SW_ENC_CHROFFSET_SHIFT (0U)
#define VPU_H264_SWREG37_SW_ENC_CHROFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG37_SW_ENC_CHROFFSET_SHIFT)) & VPU_H264_SWREG37_SW_ENC_CHROFFSET_MASK)
/*! @} */
/*! @name SWREG38 - Pre-processor configuration */
/*! @{ */
#define VPU_H264_SWREG38_SW_ENC_MIRROR_MASK (0x1U)
#define VPU_H264_SWREG38_SW_ENC_MIRROR_SHIFT (0U)
#define VPU_H264_SWREG38_SW_ENC_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_MIRROR_SHIFT)) & VPU_H264_SWREG38_SW_ENC_MIRROR_MASK)
#define VPU_H264_SWREG38_SW_ENC_YFILL_MASK (0xEU)
#define VPU_H264_SWREG38_SW_ENC_YFILL_SHIFT (1U)
#define VPU_H264_SWREG38_SW_ENC_YFILL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_YFILL_SHIFT)) & VPU_H264_SWREG38_SW_ENC_YFILL_MASK)
#define VPU_H264_SWREG38_SW_ENC_XFILL_MASK (0x30U)
#define VPU_H264_SWREG38_SW_ENC_XFILL_SHIFT (4U)
#define VPU_H264_SWREG38_SW_ENC_XFILL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_XFILL_SHIFT)) & VPU_H264_SWREG38_SW_ENC_XFILL_MASK)
#define VPU_H264_SWREG38_SW_ENC_ROWLENGTH_MASK (0xFFFC0U)
#define VPU_H264_SWREG38_SW_ENC_ROWLENGTH_SHIFT (6U)
#define VPU_H264_SWREG38_SW_ENC_ROWLENGTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_ROWLENGTH_SHIFT)) & VPU_H264_SWREG38_SW_ENC_ROWLENGTH_MASK)
#define VPU_H264_SWREG38_SW_ENC_LUMOFFSET_MASK (0xF00000U)
#define VPU_H264_SWREG38_SW_ENC_LUMOFFSET_SHIFT (20U)
#define VPU_H264_SWREG38_SW_ENC_LUMOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_LUMOFFSET_SHIFT)) & VPU_H264_SWREG38_SW_ENC_LUMOFFSET_MASK)
#define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK (0x3000000U)
#define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT (24U)
/*! SW_ENC_OUTPUT_BITWIDTH_LUM
* 0b00..8 bit.
* 0b01..9 bit.
* 0b10..10 bit.
*/
#define VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT)) & VPU_H264_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK)
#define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_MASK (0xC000000U)
#define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT (26U)
/*! SW_ENC_INPUT_ROTATION
* 0b00..disabled.
* 0b01..90 degrees right.
* 0b10..90 degrees left.
* 0b11..180 degree right.
*/
#define VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT)) & VPU_H264_SWREG38_SW_ENC_INPUT_ROTATION_MASK)
#define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_MASK (0xF0000000U)
#define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT (28U)
/*! SW_ENC_INPUT_FORMAT
* 0b0001..YUV420SP
* 0b0010..YUYV422
* 0b0011..UYVY422
* 0b0100..RGB565
* 0b0101..RGB555
* 0b0110..RGB444
* 0b0111..RGB888
* 0b1000..RGB101010
* 0b1001..I010
* 0b1010..P010
* 0b1011..PACKED10BITPLANAR
* 0b1100..Y0L2
* 0b1101..DAHUAHEVC
* 0b1110..DAHUAH264
*/
#define VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT)) & VPU_H264_SWREG38_SW_ENC_INPUT_FORMAT_MASK)
/*! @} */
/*! @name SWREG39 - Pre-processor color conversion parameters0 */
/*! @{ */
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_MASK (0xFFFFU)
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_SHIFT (0U)
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_SHIFT)) & VPU_H264_SWREG39_SW_ENC_RGBCOEFFB_MASK)
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_MASK (0xFFFF0000U)
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_SHIFT (16U)
#define VPU_H264_SWREG39_SW_ENC_RGBCOEFFA(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_SHIFT)) & VPU_H264_SWREG39_SW_ENC_RGBCOEFFA_MASK)
/*! @} */
/*! @name SWREG40 - Pre-processor color conversion parameters1 */
/*! @{ */
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_MASK (0xFFFFU)
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_SHIFT (0U)
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_SHIFT)) & VPU_H264_SWREG40_SW_ENC_RGBCOEFFE_MASK)
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_MASK (0xFFFF0000U)
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_SHIFT (16U)
#define VPU_H264_SWREG40_SW_ENC_RGBCOEFFC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_SHIFT)) & VPU_H264_SWREG40_SW_ENC_RGBCOEFFC_MASK)
/*! @} */
/*! @name SWREG41 - Pre-processor color conversion parameters2 */
/*! @{ */
#define VPU_H264_SWREG41_SW_ENC_BMASKMSB_MASK (0x3EU)
#define VPU_H264_SWREG41_SW_ENC_BMASKMSB_SHIFT (1U)
#define VPU_H264_SWREG41_SW_ENC_BMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_BMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_BMASKMSB_MASK)
#define VPU_H264_SWREG41_SW_ENC_GMASKMSB_MASK (0x7C0U)
#define VPU_H264_SWREG41_SW_ENC_GMASKMSB_SHIFT (6U)
#define VPU_H264_SWREG41_SW_ENC_GMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_GMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_GMASKMSB_MASK)
#define VPU_H264_SWREG41_SW_ENC_RMASKMSB_MASK (0xF800U)
#define VPU_H264_SWREG41_SW_ENC_RMASKMSB_SHIFT (11U)
#define VPU_H264_SWREG41_SW_ENC_RMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_RMASKMSB_SHIFT)) & VPU_H264_SWREG41_SW_ENC_RMASKMSB_MASK)
#define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_MASK (0xFFFF0000U)
#define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_SHIFT (16U)
#define VPU_H264_SWREG41_SW_ENC_RGBCOEFFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_SHIFT)) & VPU_H264_SWREG41_SW_ENC_RGBCOEFFF_MASK)
/*! @} */
/*! @name SWREG42 - Pre-processor Base address for down-scaled output */
/*! @{ */
#define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT (0U)
#define VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT)) & VPU_H264_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK)
/*! @} */
/*! @name SWREG43 - Pre-processor down-scaled configuration0 */
/*! @{ */
#define VPU_H264_SWREG43_SW_ENC_SCALE_MODE_MASK (0x3U)
#define VPU_H264_SWREG43_SW_ENC_SCALE_MODE_SHIFT (0U)
/*! SW_ENC_SCALE_MODE
* 0b00..disabled.
* 0b01..scaling only.
* 0b10..scale+encode
*/
#define VPU_H264_SWREG43_SW_ENC_SCALE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALE_MODE_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALE_MODE_MASK)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK (0x4U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT (2U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK (0x7FFF8U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT (3U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK (0xFFF80000U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT (19U)
#define VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT)) & VPU_H264_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK)
/*! @} */
/*! @name SWREG44 - Pre-processor down-scaled configuration1 */
/*! @{ */
#define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK (0x3U)
#define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT (0U)
#define VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT)) & VPU_H264_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK (0x3FFFCU)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT (2U)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT)) & VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK (0xFFFC0000U)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT (18U)
#define VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT)) & VPU_H264_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK)
/*! @} */
/*! @name SWREG45 - Pre-processor down-scaled configuration2 */
/*! @{ */
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK (0x4U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT (2U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK)
#define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK (0x78U)
#define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT (3U)
#define VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK)
#define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK (0x80U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT (7U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK)
#define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK (0x100U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT (8U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK)
#define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK (0x200U)
#define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT (9U)
#define VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT)) & VPU_H264_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK (0xC00U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT (10U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK (0x3000U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT (12U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK)
#define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK (0x7FFC000U)
#define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT (14U)
#define VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT)) & VPU_H264_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK)
#define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_MASK (0x8000000U)
#define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT (27U)
#define VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_CHROMA_SWAP_MASK)
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK (0xF0000000U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT (28U)
#define VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT)) & VPU_H264_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK)
/*! @} */
/*! @name SWREG46 - compressed coefficients base address for SAN module. */
/*! @{ */
#define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT (0U)
#define VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT)) & VPU_H264_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK)
/*! @} */
/*! @name SWREG60 - Base address for recon luma compress table LSB. */
/*! @{ */
#define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG62 - Base address for recon Chroma compress table LSB */
/*! @{ */
#define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG64 - Base address for list 0 ref 0 luma compress table LSB. */
/*! @{ */
#define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG66 - Base address for list 0 ref 0 Chroma compress table LSB. */
/*! @{ */
#define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG72 - Base address for recon luma 4n base LSB. */
/*! @{ */
#define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT (0U)
#define VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT)) & VPU_H264_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK)
/*! @} */
/*! @name SWREG74 - reference picture reconstructed list0 4n 0 */
/*! @{ */
#define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT (0U)
#define VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT)) & VPU_H264_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK)
/*! @} */
/*! @name SWREG78_H2V5 - inter me SATD lambda config 7. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT (6U)
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK)
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT (19U)
#define VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT)) & VPU_H264_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG79_H2V5 - inter me SSE lambda config 0. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG80 - HW synthesis config register, read-only */
/*! @{ */
#define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK (0x1FFFU)
#define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT (0U)
#define VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAXVIDEOWIDTH_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_MASK (0x6000U)
#define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_SHIFT (13U)
/*! SW_ENC_HWBUSWIDTH
* 0b00..32b.
* 0b01..64b.
* 0b10..128b
*/
#define VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBUSWIDTH_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_MASK (0x8000U)
#define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_SHIFT (15U)
/*! SW_ENC_HWJPEGSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWJPEGSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_MASK (0x10000U)
#define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_SHIFT (16U)
/*! SW_ENC_HWTU32SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWTU32SUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_MASK (0x20000U)
#define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_SHIFT (17U)
/*! SW_ENC_HWRFCSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWRFCSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_MASK (0x40000U)
#define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_SHIFT (18U)
/*! SW_ENC_HWPROGRDOSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWPROGRDOSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_MASK (0x80000U)
#define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_SHIFT (19U)
/*! SW_ENC_HWLINEBUFSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWLINEBUFSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_MASK (0x100000U)
#define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_SHIFT (20U)
/*! SW_ENC_HWCAVLCSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWCAVLCSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWBUS_MASK (0xE00000U)
#define VPU_H264_SWREG80_SW_ENC_HWBUS_SHIFT (21U)
/*! SW_ENC_HWBUS
* 0b001..AHB.
* 0b010..OCP.
* 0b011..AXI.
* 0b100..PCI.
* 0b101..AXIAHB.
* 0b110..AXIAPB.
*/
#define VPU_H264_SWREG80_SW_ENC_HWBUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBUS_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBUS_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_MASK (0x1000000U)
#define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_SHIFT (24U)
/*! SW_ENC_HWMAIN10SUPPORT
* 0b0..main8 supported.
* 0b1..main10 supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWMAIN10SUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_MASK (0x2000000U)
#define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_SHIFT (25U)
/*! SW_ENC_HWDENOISESUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWDENOISESUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_MASK (0x4000000U)
#define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_SHIFT (26U)
/*! SW_ENC_HWVP9SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWVP9SUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_MASK (0x8000000U)
#define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_SHIFT (27U)
/*! SW_ENC_HWHEVCSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWHEVCSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_MASK (0x10000000U)
#define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_SHIFT (28U)
/*! SW_ENC_HWRGBSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWRGBSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_MASK (0x20000000U)
#define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_SHIFT (29U)
/*! SW_ENC_HWBFRAMESUPPORT
* 0b0..not support bframe.
* 0b1..support bframe
*/
#define VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWBFRAMESUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_MASK (0x40000000U)
#define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_SHIFT (30U)
/*! SW_ENC_HWSCALINGSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWSCALINGSUPPORT_MASK)
#define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_MASK (0x80000000U)
#define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_SHIFT (31U)
/*! SW_ENC_HWH264SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_SHIFT)) & VPU_H264_SWREG80_SW_ENC_HWH264SUPPORT_MASK)
/*! @} */
/*! @name SWREG81 - hardware configuation 0 */
/*! @{ */
#define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_MASK (0x7FFFFFU)
#define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_SHIFT (0U)
#define VPU_H264_SWREG81_SW_TIMEOUT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_H264_SWREG81_SW_TIMEOUT_CYCLES_MASK)
#define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK (0x800000U)
#define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT (23U)
#define VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_H264_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK)
#define VPU_H264_SWREG81_SW_ENC_MAX_BURST_MASK (0xFF000000U)
#define VPU_H264_SWREG81_SW_ENC_MAX_BURST_SHIFT (24U)
#define VPU_H264_SWREG81_SW_ENC_MAX_BURST(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG81_SW_ENC_MAX_BURST_SHIFT)) & VPU_H264_SWREG81_SW_ENC_MAX_BURST_MASK)
/*! @} */
/*! @name SWREG82 - record hardware performance */
/*! @{ */
#define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT (0U)
#define VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT)) & VPU_H264_SWREG82_SW_ENC_HW_PERFORMANCE_MASK)
/*! @} */
/*! @name SWREG83 - reference picture reconstructed list1 luma0 */
/*! @{ */
#define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT (0U)
#define VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT)) & VPU_H264_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK)
/*! @} */
/*! @name SWREG84 - reference picture reconstructed list1 chroma0 */
/*! @{ */
#define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT (0U)
#define VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT)) & VPU_H264_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK)
/*! @} */
/*! @name SWREG91 - reference pictures list1 config */
/*! @{ */
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK (0x4U)
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT (2U)
/*! SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE
* 0b0..disable
* 0b1..enable.
*/
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK (0x8U)
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT (3U)
/*! SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE
* 0b0..disable
* 0b1..enable.
*/
#define VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK)
#define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK (0x10U)
#define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT (4U)
#define VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT)) & VPU_H264_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK)
#define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK (0xC0U)
#define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT (6U)
#define VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT)) & VPU_H264_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK (0x100U)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT (8U)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK (0x200U)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT (9U)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_MASK (0xFFC00U)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT (10U)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC1_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK (0x100000U)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT (20U)
#define VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK (0x200000U)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT (21U)
#define VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_MASK (0xFFC00000U)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT (22U)
#define VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT)) & VPU_H264_SWREG91_SW_ENC_L1_DELTA_POC0_MASK)
/*! @} */
/*! @name SWREG92 - reference picture reconstructed list1 4n 0 */
/*! @{ */
#define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT (0U)
#define VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT)) & VPU_H264_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK)
/*! @} */
/*! @name SWREG96 - Base address for list 1 ref 0 luma compress table LSB. */
/*! @{ */
#define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG98 - Base address for list 1 ref 0 Chroma compress table LSB. */
/*! @{ */
#define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_H264_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG106 - Min picture size */
/*! @{ */
#define VPU_H264_SWREG106_SW_ENC_MINPICSIZE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG106_SW_ENC_MINPICSIZE_SHIFT (0U)
#define VPU_H264_SWREG106_SW_ENC_MINPICSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG106_SW_ENC_MINPICSIZE_SHIFT)) & VPU_H264_SWREG106_SW_ENC_MINPICSIZE_MASK)
/*! @} */
/*! @name SWREG107 - Max picture size */
/*! @{ */
#define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_SHIFT (0U)
#define VPU_H264_SWREG107_SW_ENC_MAXPICSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_SHIFT)) & VPU_H264_SWREG107_SW_ENC_MAXPICSIZE_MASK)
/*! @} */
/*! @name SWREG109 - Qp delta map */
/*! @{ */
#define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT (0U)
#define VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT)) & VPU_H264_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK)
/*! @} */
/*! @name SWREG111 - adaptive GOP configuration1 */
/*! @{ */
#define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U)
#define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_SHIFT (12U)
#define VPU_H264_SWREG111_SW_ENC_INTRACU8NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_H264_SWREG111_SW_ENC_INTRACU8NUM_MASK)
/*! @} */
/*! @name SWREG112 - adaptive GOP configuration2 */
/*! @{ */
#define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_MASK (0xFFFFF000U)
#define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT (12U)
#define VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT)) & VPU_H264_SWREG112_SW_ENC_SKIPCU8NUM_MASK)
/*! @} */
/*! @name SWREG113 - adaptive GOP configuration3 */
/*! @{ */
#define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT (0U)
#define VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT)) & VPU_H264_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK)
/*! @} */
/*! @name SWREG114 - ctb rate control bit memory address of current frame */
/*! @{ */
#define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_SHIFT (0U)
#define VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_SHIFT)) & VPU_H264_SWREG114_SW_ENC_COLCTBS_STORE_BASE_MASK)
/*! @} */
/*! @name SWREG116 - ctb rate control bit memory address of previous frame */
/*! @{ */
#define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_SHIFT (0U)
#define VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_SHIFT)) & VPU_H264_SWREG116_SW_ENC_COLCTBS_LOAD_BASE_MASK)
/*! @} */
/*! @name SWREG119 - min/max lcu bits number of last picture */
/*! @{ */
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_MASK (0xFFFFU)
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_SHIFT (0U)
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_SHIFT)) & VPU_H264_SWREG119_SW_ENC_CTBBITSMAX_MASK)
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_MASK (0xFFFF0000U)
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_SHIFT (16U)
#define VPU_H264_SWREG119_SW_ENC_CTBBITSMIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_SHIFT)) & VPU_H264_SWREG119_SW_ENC_CTBBITSMIN_MASK)
/*! @} */
/*! @name SWREG120 - total bits number of all lcus of last picture not including slice header bits */
/*! @{ */
#define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT (0U)
#define VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT)) & VPU_H264_SWREG120_SW_ENC_TOTALLCUBITS_MASK)
/*! @} */
/*! @name SWREG122_H2V5 - inter me SSE lambda config 1. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG123_H2V5 - inter me SSE lambda config 2. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG124_H2V5 - inter me SSE lambda config 3. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG125 - intra SATD lambda config 0 */
/*! @{ */
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK (0x3FFF0U)
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT (4U)
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT)) & VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK)
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK (0xFFFC0000U)
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT (18U)
#define VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT)) & VPU_H264_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK)
/*! @} */
/*! @name SWREG126 - intra SATD lambda config 1 */
/*! @{ */
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK (0x3FFF0U)
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT (4U)
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT)) & VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK)
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK (0xFFFC0000U)
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT (18U)
#define VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT)) & VPU_H264_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK)
/*! @} */
/*! @name SWREG127 - intra SATD lambda config 2 */
/*! @{ */
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK (0x3FFF0U)
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT (4U)
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT)) & VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK)
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK (0xFFFC0000U)
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT (18U)
#define VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT)) & VPU_H264_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK)
/*! @} */
/*! @name SWREG128 - intra SATD lambda config 3 */
/*! @{ */
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK (0x3FFF0U)
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT (4U)
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT)) & VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK)
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK (0xFFFC0000U)
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT (18U)
#define VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT)) & VPU_H264_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK)
/*! @} */
/*! @name SWREG129 - intra SATD lambda config 4 */
/*! @{ */
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK (0x3FFF0U)
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT (4U)
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT)) & VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK)
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK (0xFFFC0000U)
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT (18U)
#define VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT)) & VPU_H264_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK)
/*! @} */
/*! @name SWREG130 - intra SATD lambda config 5 */
/*! @{ */
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK (0x3FFF0U)
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT (4U)
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT)) & VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK)
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK (0xFFFC0000U)
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT (18U)
#define VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT)) & VPU_H264_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK)
/*! @} */
/*! @name SWREG131 - intra SATD lambda config 6 */
/*! @{ */
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK (0x3FFF0U)
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT (4U)
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT)) & VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK)
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK (0xFFFC0000U)
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT (18U)
#define VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT)) & VPU_H264_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK)
/*! @} */
/*! @name SWREG132 - intra SATD lambda config 7 */
/*! @{ */
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK (0x3FFF0U)
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT (4U)
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT)) & VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK)
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK (0xFFFC0000U)
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT (18U)
#define VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT)) & VPU_H264_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK)
/*! @} */
/*! @name SWREG133 - SSE devide 256 */
/*! @{ */
#define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_SHIFT (0U)
#define VPU_H264_SWREG133_SW_ENC_SSE_DIV_256(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_SHIFT)) & VPU_H264_SWREG133_SW_ENC_SSE_DIV_256_MASK)
/*! @} */
/*! @name SWREG138_H2V5 - inter me SSE lambda config 4. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG139_H2V5 - inter me SSE lambda config 5. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG140_H2V5 - inter me SSE lambda config 6. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG141_H2V5 - inter me SSE lambda config 7. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG142_H2V5 - inter me SSE lambda config 8. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG143_H2V5 - inter me SSE lambda config 9. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG144_H2V5 - inter me SSE lambda config 10. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG145_H2V5 - inter me SSE lambda config 11. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG146_H2V5 - inter me SSE lambda config 12. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG147_H2V5 - inter me SSE lambda config 13. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG148_H2V5 - inter me SSE lambda config 14. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG149_H2V5 - inter me SSE lambda config 15. For H2V5 or later version. */
/*! @{ */
#define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT (11U)
#define VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT)) & VPU_H264_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG150 - inter me SATD lambda config 8 */
/*! @{ */
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK (0x7FFC0U)
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT (6U)
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT)) & VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK)
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK (0xFFF80000U)
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT (19U)
#define VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT)) & VPU_H264_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK)
/*! @} */
/*! @name SWREG151 - inter me SATD lambda config 9 */
/*! @{ */
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK (0x7FFC0U)
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT (6U)
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT)) & VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK)
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK (0xFFF80000U)
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT (19U)
#define VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT)) & VPU_H264_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK)
/*! @} */
/*! @name SWREG152 - inter me SATD lambda config 10 */
/*! @{ */
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK (0x7FFC0U)
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT (6U)
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT)) & VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK)
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK (0xFFF80000U)
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT (19U)
#define VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT)) & VPU_H264_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK)
/*! @} */
/*! @name SWREG153 - inter me SATD lambda config 11 */
/*! @{ */
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK (0x7FFC0U)
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT (6U)
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT)) & VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK)
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK (0xFFF80000U)
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT (19U)
#define VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT)) & VPU_H264_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK)
/*! @} */
/*! @name SWREG154 - inter me SATD lambda config 12 */
/*! @{ */
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK (0x7FFC0U)
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT (6U)
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT)) & VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK)
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK (0xFFF80000U)
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT (19U)
#define VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT)) & VPU_H264_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK)
/*! @} */
/*! @name SWREG155 - inter me SATD lambda config 13 */
/*! @{ */
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK (0x7FFC0U)
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT (6U)
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT)) & VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK)
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK (0xFFF80000U)
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT (19U)
#define VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT)) & VPU_H264_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK)
/*! @} */
/*! @name SWREG156 - inter me SATD lambda config 14 */
/*! @{ */
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK (0x7FFC0U)
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT (6U)
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT)) & VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK)
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK (0xFFF80000U)
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT (19U)
#define VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT)) & VPU_H264_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK)
/*! @} */
/*! @name SWREG157 - inter me SATD lambda config 15 */
/*! @{ */
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK (0x7FFC0U)
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT (6U)
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT)) & VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK)
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK (0xFFF80000U)
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT (19U)
#define VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT)) & VPU_H264_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK)
/*! @} */
/*! @name SWREG158 - inter me SSE lambda config 16 */
/*! @{ */
#define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK (0xFFFFF800U)
#define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT (11U)
#define VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT)) & VPU_H264_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK)
/*! @} */
/*! @name SWREG159 - inter me SSE lambda config 17 */
/*! @{ */
#define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK (0xFFFFF800U)
#define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT (11U)
#define VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT)) & VPU_H264_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK)
/*! @} */
/*! @name SWREG160 - inter me SSE lambda config 18 */
/*! @{ */
#define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK (0xFFFFF800U)
#define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT (11U)
#define VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT)) & VPU_H264_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK)
/*! @} */
/*! @name SWREG161 - inter me SSE lambda config 19 */
/*! @{ */
#define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK (0xFFFFF800U)
#define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT (11U)
#define VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT)) & VPU_H264_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK)
/*! @} */
/*! @name SWREG162 - inter me SSE lambda config 20 */
/*! @{ */
#define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK (0xFFFFF800U)
#define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT (11U)
#define VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT)) & VPU_H264_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK)
/*! @} */
/*! @name SWREG163 - inter me SSE lambda config 21 */
/*! @{ */
#define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK (0xFFFFF800U)
#define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT (11U)
#define VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT)) & VPU_H264_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK)
/*! @} */
/*! @name SWREG164 - inter me SSE lambda config 22 */
/*! @{ */
#define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK (0xFFFFF800U)
#define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT (11U)
#define VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT)) & VPU_H264_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK)
/*! @} */
/*! @name SWREG165 - inter me SSE lambda config 23 */
/*! @{ */
#define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK (0xFFFFF800U)
#define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT (11U)
#define VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT)) & VPU_H264_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK)
/*! @} */
/*! @name SWREG166 - inter me SSE lambda config 24 */
/*! @{ */
#define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK (0xFFFFF800U)
#define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT (11U)
#define VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT)) & VPU_H264_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK)
/*! @} */
/*! @name SWREG167 - inter me SSE lambda config 25 */
/*! @{ */
#define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK (0xFFFFF800U)
#define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT (11U)
#define VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT)) & VPU_H264_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK)
/*! @} */
/*! @name SWREG168 - inter me SSE lambda config 26 */
/*! @{ */
#define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK (0xFFFFF800U)
#define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT (11U)
#define VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT)) & VPU_H264_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK)
/*! @} */
/*! @name SWREG169 - inter me SSE lambda config 27 */
/*! @{ */
#define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK (0xFFFFF800U)
#define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT (11U)
#define VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT)) & VPU_H264_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK)
/*! @} */
/*! @name SWREG172 - inter me SSE lambda config 30 */
/*! @{ */
#define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK (0x1FU)
#define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT (0U)
#define VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT)) & VPU_H264_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK)
#define VPU_H264_SWREG172_SW_ENC_QP_MIN_MASK (0x7E0U)
#define VPU_H264_SWREG172_SW_ENC_QP_MIN_SHIFT (5U)
#define VPU_H264_SWREG172_SW_ENC_QP_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_QP_MIN_SHIFT)) & VPU_H264_SWREG172_SW_ENC_QP_MIN_MASK)
#define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK (0xFFFFF800U)
#define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT (11U)
#define VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT)) & VPU_H264_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK)
/*! @} */
/*! @name SWREG173 - inter me SSE lambda config 31 */
/*! @{ */
#define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK (0xFU)
#define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT (0U)
#define VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT)) & VPU_H264_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK)
#define VPU_H264_SWREG173_SW_ENC_QP_MAX_MASK (0x7E0U)
#define VPU_H264_SWREG173_SW_ENC_QP_MAX_SHIFT (5U)
#define VPU_H264_SWREG173_SW_ENC_QP_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_QP_MAX_SHIFT)) & VPU_H264_SWREG173_SW_ENC_QP_MAX_MASK)
#define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK (0xFFFFF800U)
#define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT (11U)
#define VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT)) & VPU_H264_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK)
/*! @} */
/*! @name SWREG174 - intra SATD lambda config 8 */
/*! @{ */
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK (0x3FFF0U)
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT (4U)
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT)) & VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK)
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK (0xFFFC0000U)
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT (18U)
#define VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT)) & VPU_H264_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK)
/*! @} */
/*! @name SWREG175 - intra SATD lambda config 9 */
/*! @{ */
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK (0x3FFF0U)
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT (4U)
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT)) & VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK)
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK (0xFFFC0000U)
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT (18U)
#define VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT)) & VPU_H264_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK)
/*! @} */
/*! @name SWREG176 - intra SATD lambda config 10 */
/*! @{ */
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK (0x3FFF0U)
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT (4U)
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT)) & VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK)
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK (0xFFFC0000U)
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT (18U)
#define VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT)) & VPU_H264_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK)
/*! @} */
/*! @name SWREG177 - intra SATD lambda config 11 */
/*! @{ */
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK (0x3FFF0U)
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT (4U)
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT)) & VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK)
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK (0xFFFC0000U)
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT (18U)
#define VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT)) & VPU_H264_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK)
/*! @} */
/*! @name SWREG178 - intra SATD lambda config 12 */
/*! @{ */
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK (0x3FFF0U)
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT (4U)
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT)) & VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK)
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK (0xFFFC0000U)
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT (18U)
#define VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT)) & VPU_H264_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK)
/*! @} */
/*! @name SWREG179 - intra SATD lambda config 13 */
/*! @{ */
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK (0x3FFF0U)
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT (4U)
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT)) & VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK)
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK (0xFFFC0000U)
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT (18U)
#define VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT)) & VPU_H264_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK)
/*! @} */
/*! @name SWREG180 - intra SATD lambda config 14 */
/*! @{ */
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK (0x3FFF0U)
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT (4U)
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT)) & VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK)
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK (0xFFFC0000U)
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT (18U)
#define VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT)) & VPU_H264_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK)
/*! @} */
/*! @name SWREG181 - intra SATD lambda config 15 */
/*! @{ */
#define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK (0xCU)
#define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT (2U)
/*! SW_ENC_RC_BLOCK_SIZE
* 0b00..64x64.
* 0b01..32x32.
* 0b10..16x16
*/
#define VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT)) & VPU_H264_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK (0x3FFF0U)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT (4U)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT)) & VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK (0xFFFC0000U)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT (18U)
#define VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT)) & VPU_H264_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK)
/*! @} */
/*! @name SWREG182 - qp fractional part */
/*! @{ */
#define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK (0xFFFFU)
#define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT (0U)
#define VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT)) & VPU_H264_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK)
#define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_MASK (0xFFFF0000U)
#define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT (16U)
#define VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT)) & VPU_H264_SWREG182_SW_ENC_QP_FRACTIONAL_MASK)
/*! @} */
/*! @name SWREG183 - qp sum */
/*! @{ */
#define VPU_H264_SWREG183_SW_ENC_QP_SUM_MASK (0xFFFFFFC0U)
#define VPU_H264_SWREG183_SW_ENC_QP_SUM_SHIFT (6U)
#define VPU_H264_SWREG183_SW_ENC_QP_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG183_SW_ENC_QP_SUM_SHIFT)) & VPU_H264_SWREG183_SW_ENC_QP_SUM_MASK)
/*! @} */
/*! @name SWREG184 - qp num */
/*! @{ */
#define VPU_H264_SWREG184_SW_ENC_QP_NUM_MASK (0xFFFFF000U)
#define VPU_H264_SWREG184_SW_ENC_QP_NUM_SHIFT (12U)
#define VPU_H264_SWREG184_SW_ENC_QP_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG184_SW_ENC_QP_NUM_SHIFT)) & VPU_H264_SWREG184_SW_ENC_QP_NUM_MASK)
/*! @} */
/*! @name SWREG185 - picture complexity. Timeout cycles MSB. */
/*! @{ */
#define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK (0x1FFU)
#define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT (0U)
#define VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT)) & VPU_H264_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK)
#define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK (0xFFFFFE00U)
#define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT (9U)
#define VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT)) & VPU_H264_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK)
/*! @} */
/*! @name SWREG190 - Long-term reference pictures config */
/*! @{ */
#define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK (0xC0000000U)
#define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT (30U)
#define VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT)) & VPU_H264_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK)
/*! @} */
/*! @name SWREG191 - Temporal scalable config */
/*! @{ */
#define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK (0xFFFFU)
#define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT (0U)
#define VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT)) & VPU_H264_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK)
#define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_MASK (0x10000U)
#define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_SHIFT (16U)
/*! SW_ENC_PREFIXNAL_SVC_EXT
* 0b1..enabled (insert H264Scalability SEI).
* 0b0..disabled
*/
#define VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_SHIFT)) & VPU_H264_SWREG191_SW_ENC_PREFIXNAL_SVC_EXT_MASK)
#define VPU_H264_SWREG191_SW_ENC_PPS_ID_MASK (0x7E0000U)
#define VPU_H264_SWREG191_SW_ENC_PPS_ID_SHIFT (17U)
#define VPU_H264_SWREG191_SW_ENC_PPS_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_PPS_ID_SHIFT)) & VPU_H264_SWREG191_SW_ENC_PPS_ID_MASK)
#define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK (0x3800000U)
#define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT (23U)
#define VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT)) & VPU_H264_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK)
#define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK (0xFC000000U)
#define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT (26U)
#define VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT)) & VPU_H264_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK)
/*! @} */
/*! @name SWREG192 - encoded Picture frame number (for H.264) */
/*! @{ */
#define VPU_H264_SWREG192_SW_ENC_FRAMENUM_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG192_SW_ENC_FRAMENUM_SHIFT (0U)
#define VPU_H264_SWREG192_SW_ENC_FRAMENUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG192_SW_ENC_FRAMENUM_SHIFT)) & VPU_H264_SWREG192_SW_ENC_FRAMENUM_MASK)
/*! @} */
/*! @name SWREG193 - reference pictures list0 config (for H.264) */
/*! @{ */
#define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_MASK (0x1U)
#define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_SHIFT (0U)
#define VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_SHIFT)) & VPU_H264_SWREG193_SW_ENC_ENTROPY_CODING_MODE_MASK)
#define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_MASK (0x2U)
#define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_SHIFT (1U)
#define VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_SHIFT)) & VPU_H264_SWREG193_SW_ENC_TRANSFORM8X8_ENABLE_MASK)
#define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_MASK (0x4U)
#define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_SHIFT (2U)
#define VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_SHIFT)) & VPU_H264_SWREG193_SW_ENC_IDR_PIC_ID_MASK)
#define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_MASK (0x8U)
#define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_SHIFT (3U)
#define VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_SHIFT)) & VPU_H264_SWREG193_SW_ENC_NAL_REF_IDC_MASK)
#define VPU_H264_SWREG193_SW_ENC_YFILL_MSB_MASK (0x30U)
#define VPU_H264_SWREG193_SW_ENC_YFILL_MSB_SHIFT (4U)
#define VPU_H264_SWREG193_SW_ENC_YFILL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_YFILL_MSB_SHIFT)) & VPU_H264_SWREG193_SW_ENC_YFILL_MSB_MASK)
#define VPU_H264_SWREG193_SW_ENC_XFILL_MSB_MASK (0xC0U)
#define VPU_H264_SWREG193_SW_ENC_XFILL_MSB_SHIFT (6U)
#define VPU_H264_SWREG193_SW_ENC_XFILL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_XFILL_MSB_SHIFT)) & VPU_H264_SWREG193_SW_ENC_XFILL_MSB_MASK)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_MASK (0x100U)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_SHIFT (8U)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC1_MASK)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_MASK (0xFFE00U)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_SHIFT (9U)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM1_MASK)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_MASK (0x100000U)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_SHIFT (20U)
#define VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_USED_BY_NEXT_PIC0_MASK)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_MASK (0xFFE00000U)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_SHIFT (21U)
#define VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_SHIFT)) & VPU_H264_SWREG193_SW_ENC_L0_DELTA_FRAMENUM0_MASK)
/*! @} */
/*! @name SWREG194 - reference pictures list1 config (for H.264) */
/*! @{ */
#define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_MASK (0x1CU)
#define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_SHIFT (2U)
#define VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_SHIFT)) & VPU_H264_SWREG194_SW_ENC_CUR_LONGTERMIDX_MASK)
#define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_MASK (0xE0U)
#define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_SHIFT (5U)
#define VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_MAX_LONGTERMIDX_PLUS1_MASK)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_MASK (0x100U)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_SHIFT (8U)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC1_MASK)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_MASK (0xFFE00U)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_SHIFT (9U)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM1_MASK)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_MASK (0x100000U)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_SHIFT (20U)
#define VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_USED_BY_NEXT_PIC0_MASK)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_MASK (0xFFE00000U)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_SHIFT (21U)
#define VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_SHIFT)) & VPU_H264_SWREG194_SW_ENC_L1_DELTA_FRAMENUM0_MASK)
/*! @} */
/*! @name SWREG195 - register extension for ctu_size=16 */
/*! @{ */
#define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK (0xCU)
#define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT (2U)
#define VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK (0x10U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT (4U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK (0x20U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT (5U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK (0x40U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT (6U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK (0x80U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT (7U)
#define VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK (0x100U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT (8U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK (0x200U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT (9U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK (0x400U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT (10U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK (0x800U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT (11U)
#define VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK (0x1000U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT (12U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK (0x2000U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT (13U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK (0x4000U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT (14U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK (0x8000U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT (15U)
#define VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK (0xF0000U)
#define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT (16U)
#define VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_MASK (0xF00000U)
#define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_SHIFT (20U)
#define VPU_H264_SWREG195_SW_ENC_CIR_START_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_CIR_START_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK (0x3000000U)
#define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT (24U)
#define VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK (0xC000000U)
#define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT (26U)
#define VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK)
#define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK (0xF0000000U)
#define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT (28U)
#define VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT)) & VPU_H264_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK)
/*! @} */
/*! @name SWREG196 - Low Latency Controls */
/*! @{ */
#define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_MASK (0x3FFU)
#define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT (0U)
#define VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT)) & VPU_H264_SWREG196_SW_CTB_ROW_WR_PTR_MASK)
#define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_MASK (0xFFC00U)
#define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT (10U)
#define VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT)) & VPU_H264_SWREG196_SW_CTB_ROW_RD_PTR_MASK)
#define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK (0x1FF00000U)
#define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT (20U)
#define VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT)) & VPU_H264_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK)
#define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK (0x20000000U)
#define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT (29U)
#define VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT)) & VPU_H264_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_EN_MASK (0x40000000U)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_EN_SHIFT (30U)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_LOW_LATENCY_EN_SHIFT)) & VPU_H264_SWREG196_SW_LOW_LATENCY_EN_MASK)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK (0x80000000U)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT (31U)
#define VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT)) & VPU_H264_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK)
/*! @} */
/*! @name SWREG197 - Delta POC extension */
/*! @{ */
#define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK (0xFFCU)
#define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT (2U)
#define VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK (0x3FF000U)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT (12U)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK (0xFFC00000U)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT (22U)
#define VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT)) & VPU_H264_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK)
/*! @} */
/*! @name SWREG198 - Long Term Reference Control */
/*! @{ */
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_MASK (0x7U)
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_SHIFT (0U)
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX1_MASK)
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_MASK (0x38U)
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_SHIFT (3U)
#define VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_LONGTERMIDX0_MASK)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_MASK (0x1C0U)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_SHIFT (6U)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX1_MASK)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_MASK (0xE00U)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_SHIFT (9U)
#define VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_LONGTERMIDX0_MASK)
#define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_MASK (0x1000U)
#define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_SHIFT (12U)
#define VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_SHIFT)) & VPU_H264_SWREG198_SW_ENC_MARK_CURRENT_LONGTERM_MASK)
#define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_MASK (0x3FE000U)
#define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_SHIFT (13U)
#define VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L0_DELTA_FRAMENUM0_MSB_MASK)
#define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK (0xFFC00000U)
#define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT (22U)
#define VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT)) & VPU_H264_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK)
/*! @} */
/*! @name SWREG199 - Hash Code Control */
/*! @{ */
#define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK (0x1U)
#define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT (0U)
/*! SW_ENC_OSD_ALPHABLEND_ENABLE
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT)) & VPU_H264_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK)
#define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_MASK (0x6U)
#define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_SHIFT (1U)
#define VPU_H264_SWREG199_SW_ENC_HASH_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_SHIFT)) & VPU_H264_SWREG199_SW_ENC_HASH_OFFSET_MASK)
#define VPU_H264_SWREG199_SW_ENC_HASH_TYPE_MASK (0x18U)
#define VPU_H264_SWREG199_SW_ENC_HASH_TYPE_SHIFT (3U)
/*! SW_ENC_HASH_TYPE
* 0b00..none.
* 0b01..crc32.
* 0b10..checksum32
*/
#define VPU_H264_SWREG199_SW_ENC_HASH_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_HASH_TYPE_SHIFT)) & VPU_H264_SWREG199_SW_ENC_HASH_TYPE_MASK)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_MASK (0x3FE0U)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_SHIFT (5U)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM1_MSB_MASK)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_MASK (0x7FC000U)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_SHIFT (14U)
#define VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L1_DELTA_FRAMENUM0_MSB_MASK)
#define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_MASK (0xFF800000U)
#define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_SHIFT (23U)
#define VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_SHIFT)) & VPU_H264_SWREG199_SW_ENC_L0_DELTA_FRAMENUM1_MSB_MASK)
/*! @} */
/*! @name SWREG200 - Hash Code Value */
/*! @{ */
#define VPU_H264_SWREG200_SW_ENC_HASH_VAL_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG200_SW_ENC_HASH_VAL_SHIFT (0U)
#define VPU_H264_SWREG200_SW_ENC_HASH_VAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG200_SW_ENC_HASH_VAL_SHIFT)) & VPU_H264_SWREG200_SW_ENC_HASH_VAL_MASK)
/*! @} */
/*! @name SWREG201 - Background SKIP Control 0 */
/*! @{ */
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR3_MASK (0xFFU)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR3_SHIFT (0U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR3_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR3_MASK)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR2_MASK (0xFF00U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR2_SHIFT (8U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR2_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR2_MASK)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR1_MASK (0xFF0000U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR1_SHIFT (16U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR1_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR1_MASK)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR0_MASK (0xFF000000U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR0_SHIFT (24U)
#define VPU_H264_SWREG201_SW_ENC_MEAN_THR0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG201_SW_ENC_MEAN_THR0_SHIFT)) & VPU_H264_SWREG201_SW_ENC_MEAN_THR0_MASK)
/*! @} */
/*! @name SWREG203 - Background SKIP Control 2 */
/*! @{ */
#define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_MASK (0xFFU)
#define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_SHIFT (0U)
#define VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_CR_DC_SUM_THR_MASK)
#define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_MASK (0xFF00U)
#define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_SHIFT (8U)
#define VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_CB_DC_SUM_THR_MASK)
#define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_MASK (0xFF000000U)
#define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_SHIFT (24U)
#define VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_SHIFT)) & VPU_H264_SWREG203_SW_ENC_LUM_DC_SUM_THR_MASK)
/*! @} */
/*! @name SWREG208 - Background SKIP Control 7 */
/*! @{ */
#define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK (0x8U)
#define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT (3U)
#define VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT)) & VPU_H264_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK)
#define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_MASK (0x1FF0U)
#define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT (4U)
#define VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT)) & VPU_H264_SWREG208_SW_ENC_IPCM1_LEFT_MASK)
#define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_MASK (0x2000U)
#define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_SHIFT (13U)
#define VPU_H264_SWREG208_SW_ENC_ENABLE_SMART(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_SHIFT)) & VPU_H264_SWREG208_SW_ENC_ENABLE_SMART_MASK)
#define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK (0xFC000U)
#define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT (14U)
#define VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT)) & VPU_H264_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK)
#define VPU_H264_SWREG208_SW_ENC_SMART_QP_MASK (0xFC000000U)
#define VPU_H264_SWREG208_SW_ENC_SMART_QP_SHIFT (26U)
#define VPU_H264_SWREG208_SW_ENC_SMART_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG208_SW_ENC_SMART_QP_SHIFT)) & VPU_H264_SWREG208_SW_ENC_SMART_QP_MASK)
/*! @} */
/*! @name SWREG209 - IPCM Control 0 */
/*! @{ */
#define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK (0x8U)
#define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT (3U)
#define VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK)
#define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK (0x10U)
#define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT (4U)
#define VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT)) & VPU_H264_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK (0x3FE0U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT (5U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_MASK (0x7FC000U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_SHIFT (14U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_TOP_MASK)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_MASK (0xFF800000U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT (23U)
#define VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT)) & VPU_H264_SWREG209_SW_ENC_IPCM1_RIGHT_MASK)
/*! @} */
/*! @name SWREG210 - IPCM Control 1 */
/*! @{ */
#define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_MASK (0xFF8U)
#define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT (3U)
#define VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT)) & VPU_H264_SWREG210_SW_ENC_IPCM2_LEFT_MASK)
/*! @} */
/*! @name SWREG211 - IPCM Control 2 */
/*! @{ */
#define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_MASK (0xFF8U)
#define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT (3U)
#define VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT)) & VPU_H264_SWREG211_SW_ENC_IPCM2_RIGHT_MASK)
/*! @} */
/*! @name SWREG212 - IPCM Control 3 */
/*! @{ */
#define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_MASK (0xFF8U)
#define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_SHIFT (3U)
#define VPU_H264_SWREG212_SW_ENC_IPCM2_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_SHIFT)) & VPU_H264_SWREG212_SW_ENC_IPCM2_TOP_MASK)
/*! @} */
/*! @name SWREG213 - IPCM Control 4 */
/*! @{ */
#define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK (0x3FE0U)
#define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT (5U)
#define VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT)) & VPU_H264_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK)
/*! @} */
/*! @name SWREG214 - HW synthesis config register 2, read-only */
/*! @{ */
#define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_MASK (0x3FFE000U)
#define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_SHIFT (13U)
#define VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWMAXVIDEOWIDTHH264_MASK)
#define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_MASK (0x1C000000U)
#define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT (26U)
/*! SW_ENC_HWROIMAPVERSION
* 0b000..4 bit per pixel.
* 0b001..8 bit per pixel
*/
#define VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWROIMAPVERSION_MASK)
#define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK (0x40000000U)
#define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT (30U)
/*! SW_ENC_HWABSQPSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK)
#define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK (0x80000000U)
#define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT (31U)
/*! SW_ENC_HWLJPEGSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT)) & VPU_H264_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK)
/*! @} */
/*! @name SWREG215 - AXI Information 0 */
/*! @{ */
#define VPU_H264_SWREG215_SW_ENC_TOTALARLEN_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG215_SW_ENC_TOTALARLEN_SHIFT (0U)
#define VPU_H264_SWREG215_SW_ENC_TOTALARLEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG215_SW_ENC_TOTALARLEN_SHIFT)) & VPU_H264_SWREG215_SW_ENC_TOTALARLEN_MASK)
/*! @} */
/*! @name SWREG216 - AXI Information 1 */
/*! @{ */
#define VPU_H264_SWREG216_SW_ENC_TOTALR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG216_SW_ENC_TOTALR_SHIFT (0U)
#define VPU_H264_SWREG216_SW_ENC_TOTALR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG216_SW_ENC_TOTALR_SHIFT)) & VPU_H264_SWREG216_SW_ENC_TOTALR_MASK)
/*! @} */
/*! @name SWREG217 - AXI Information 2 */
/*! @{ */
#define VPU_H264_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG217_SW_ENC_TOTALAR_SHIFT (0U)
#define VPU_H264_SWREG217_SW_ENC_TOTALAR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_H264_SWREG217_SW_ENC_TOTALAR_MASK)
/*! @} */
/*! @name SWREG218 - AXI Information 3 */
/*! @{ */
#define VPU_H264_SWREG218_SW_ENC_TOTALRLAST_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG218_SW_ENC_TOTALRLAST_SHIFT (0U)
#define VPU_H264_SWREG218_SW_ENC_TOTALRLAST(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG218_SW_ENC_TOTALRLAST_SHIFT)) & VPU_H264_SWREG218_SW_ENC_TOTALRLAST_MASK)
/*! @} */
/*! @name SWREG219 - AXI Information 4 */
/*! @{ */
#define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_SHIFT (0U)
#define VPU_H264_SWREG219_SW_ENC_TOTALAWLEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_SHIFT)) & VPU_H264_SWREG219_SW_ENC_TOTALAWLEN_MASK)
/*! @} */
/*! @name SWREG220 - AXI Information 5 */
/*! @{ */
#define VPU_H264_SWREG220_SW_ENC_TOTALW_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG220_SW_ENC_TOTALW_SHIFT (0U)
#define VPU_H264_SWREG220_SW_ENC_TOTALW(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG220_SW_ENC_TOTALW_SHIFT)) & VPU_H264_SWREG220_SW_ENC_TOTALW_MASK)
/*! @} */
/*! @name SWREG221 - AXI Information 6 */
/*! @{ */
#define VPU_H264_SWREG221_SW_ENC_TOTALAW_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG221_SW_ENC_TOTALAW_SHIFT (0U)
#define VPU_H264_SWREG221_SW_ENC_TOTALAW(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG221_SW_ENC_TOTALAW_SHIFT)) & VPU_H264_SWREG221_SW_ENC_TOTALAW_MASK)
/*! @} */
/*! @name SWREG222 - AXI Information 7 */
/*! @{ */
#define VPU_H264_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG222_SW_ENC_TOTALWLAST_SHIFT (0U)
#define VPU_H264_SWREG222_SW_ENC_TOTALWLAST(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_H264_SWREG222_SW_ENC_TOTALWLAST_MASK)
/*! @} */
/*! @name SWREG223 - AXI Information 8 */
/*! @{ */
#define VPU_H264_SWREG223_SW_ENC_TOTALB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG223_SW_ENC_TOTALB_SHIFT (0U)
#define VPU_H264_SWREG223_SW_ENC_TOTALB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG223_SW_ENC_TOTALB_SHIFT)) & VPU_H264_SWREG223_SW_ENC_TOTALB_MASK)
/*! @} */
/*! @name SWREG224 - control register 4 */
/*! @{ */
#define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK (0x3FFU)
#define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT (0U)
#define VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK)
#define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK (0xFFC00U)
#define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT (10U)
#define VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK)
#define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_MASK (0x100000U)
#define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT (20U)
/*! SW_ENC_SKIPFRAME_EN
* 0b0..no.
* 0b1..yes
*/
#define VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_SKIPFRAME_EN_MASK)
#define VPU_H264_SWREG224_SW_ENC_SSIM_EN_MASK (0x200000U)
#define VPU_H264_SWREG224_SW_ENC_SSIM_EN_SHIFT (21U)
/*! SW_ENC_SSIM_EN
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_H264_SWREG224_SW_ENC_SSIM_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_SSIM_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_SSIM_EN_MASK)
#define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK (0x80000000U)
#define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT (31U)
/*! SW_ENC_CHROMA_CONST_EN
* 0b0..no.
* 0b1..yes.
*/
#define VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT)) & VPU_H264_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK)
/*! @} */
/*! @name SWREG225 - Tile Control */
/*! @{ */
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK (0x1C0U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT (6U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK (0xE00U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT (9U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK (0x1000U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT (12U)
/*! SW_ENC_ROIMAP_CUCTRL_ENABLE
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK (0x2000U)
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT (13U)
/*! SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT)) & VPU_H264_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK)
/*! @} */
/*! @name SWREG226 - HW synthesis config register 3, read-only */
/*! @{ */
#define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_MASK (0x2U)
#define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT (1U)
/*! SW_ENC_HWIFRAMEONLY
* 0b0..support I/P/B frame.
* 0b1..only support I frame
*/
#define VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWIFRAMEONLY_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK (0x4U)
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT (2U)
/*! SW_ENC_HWSTREAMSEGMENTSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK (0x8U)
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT (3U)
/*! SW_ENC_HWSTREAMBUFCHAIN
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK (0x10U)
#define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT (4U)
/*! SW_ENC_HWINLOOPDSRATIO
* 0b0..1:1
* 0b1..1:2
*/
#define VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK (0x20U)
#define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT (5U)
/*! SW_ENC_HWMULTIPASSSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK (0x40U)
#define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT (6U)
/*! SW_ENC_HWRDOQSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK (0x180U)
#define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT (7U)
/*! SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE
* 0b00..64.
* 0b01..128.
* 0b10..192.
* 0b11..256
*/
#define VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT)) & VPU_H264_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U)
#define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT (9U)
#define VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_MASK (0x400U)
#define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT (10U)
/*! SW_ENC_HWGMVSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWGMVSUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK (0x800U)
#define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT (11U)
/*! SW_ENC_HWJPEG422SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_MASK (0x7000U)
#define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT (12U)
#define VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWCTBRCVERSION_MASK)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK (0x1F8000U)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT (15U)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT)) & VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK (0x7E00000U)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT (21U)
#define VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT)) & VPU_H264_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_MASK (0x38000000U)
#define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT (27U)
#define VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWCUINFORVERSION_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK (0x40000000U)
#define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT (30U)
/*! SW_ENC_HWP010REFSUPPORT
* 0b1..P010 tile raster format.
* 0b0..normal format
*/
#define VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK)
#define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK (0x80000000U)
#define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT (31U)
/*! SW_ENC_HWSSIMSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT)) & VPU_H264_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK)
/*! @} */
/*! @name SWREG235 - RPS encoding control 0 */
/*! @{ */
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK (0x1U)
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT (0U)
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK)
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK (0x2U)
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT (1U)
#define VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK (0xFFCU)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT (2U)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK (0x3FF000U)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT (12U)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK (0xFFC00000U)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT (22U)
#define VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT)) & VPU_H264_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK)
/*! @} */
/*! @name SWREG236 - RPS encoding control 1 */
/*! @{ */
#define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_MASK (0x1000U)
#define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT (12U)
/*! SW_ENC_P010_REF_ENABLE
* 0b0..not supported.
* 0b1..supported.
*/
#define VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT)) & VPU_H264_SWREG236_SW_ENC_P010_REF_ENABLE_MASK)
#define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK (0x2000U)
#define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT (13U)
#define VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT)) & VPU_H264_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK)
#define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK (0x1C000U)
#define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT (14U)
#define VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK)
#define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK (0xE0000U)
#define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT (17U)
#define VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK (0x100000U)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT (20U)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK (0x200000U)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT (21U)
#define VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK)
#define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK (0xFFC00000U)
#define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT (22U)
#define VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT)) & VPU_H264_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK)
/*! @} */
/*! @name SWREG237 - Stride Control */
/*! @{ */
#define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_MASK (0x800U)
#define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_SHIFT (11U)
#define VPU_H264_SWREG237_SW_ENC_DUMMYREADEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_SHIFT)) & VPU_H264_SWREG237_SW_ENC_DUMMYREADEN_MASK)
#define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_MASK (0xFFFFF000U)
#define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT (12U)
#define VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT)) & VPU_H264_SWREG237_SW_ENC_REF_CH_STRIDE_MASK)
/*! @} */
/*! @name SWREG238 - Dummy Read */
/*! @{ */
#define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT (0U)
#define VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT)) & VPU_H264_SWREG238_SW_ENC_DUMMYREADADDR_MASK)
/*! @} */
/*! @name SWREG239 - Base Address LSB of CTB MADs of current frame. */
/*! @{ */
#define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT (0U)
#define VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT)) & VPU_H264_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK)
/*! @} */
/*! @name SWREG241 - Base Address LSB of CTB MADs of previous frame. */
/*! @{ */
#define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT (0U)
#define VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT)) & VPU_H264_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK)
/*! @} */
/*! @name SWREG243 - CTB RC Control 0 */
/*! @{ */
#define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK (0xFFFFF800U)
#define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT (11U)
#define VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT)) & VPU_H264_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK)
/*! @} */
/*! @name SWREG244 - CTB RC Control 1 */
/*! @{ */
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK (0x4U)
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT (2U)
/*! SW_ENC_ROI3_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT)) & VPU_H264_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK)
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK (0x3F8U)
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT (3U)
#define VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT)) & VPU_H264_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK)
#define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK (0xFFFFFC00U)
#define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT (10U)
#define VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT)) & VPU_H264_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK)
/*! @} */
/*! @name SWREG245 - CTB RC Control 2 */
/*! @{ */
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK (0x3FFFCU)
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT (2U)
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT)) & VPU_H264_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK)
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK (0xFFFC0000U)
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT (18U)
#define VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT)) & VPU_H264_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK)
/*! @} */
/*! @name SWREG246 - CTB RC Control 3 */
/*! @{ */
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_MASK (0x38U)
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT (3U)
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT)) & VPU_H264_SWREG246_SW_ENC_CTB_RC_DELAY_MASK)
#define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK (0x3FC0U)
#define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT (6U)
#define VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT)) & VPU_H264_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK)
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK (0xFFFFC000U)
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT (14U)
#define VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT)) & VPU_H264_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK)
/*! @} */
/*! @name SWREG247 - CTB RC Control 4 */
/*! @{ */
#define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK (0x2U)
#define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT (1U)
/*! SW_ENC_CTB_RC_PREV_MAD_VALID
* 0b0..no
* 0b1..yes.
*/
#define VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT)) & VPU_H264_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK)
#define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK (0xFFFFFFC0U)
#define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT (6U)
#define VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT)) & VPU_H264_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK)
/*! @} */
/*! @name SWREG248 - CTB RC Control 5 */
/*! @{ */
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK (0x1U)
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT (0U)
/*! SW_ENC_ROI4_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT)) & VPU_H264_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK)
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK (0xFEU)
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT (1U)
#define VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT)) & VPU_H264_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK)
#define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK (0xFFFFFF00U)
#define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT (8U)
#define VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT)) & VPU_H264_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK)
/*! @} */
/*! @name SWREG249 - register extension for 8K width */
/*! @{ */
#define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK (0x8U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT (3U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK (0x10U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT (4U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK (0x20U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT (5U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK (0x40U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT (6U)
#define VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK (0x80U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT (7U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK (0x100U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT (8U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK (0x200U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT (9U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK (0x400U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT (10U)
#define VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT)) & VPU_H264_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK)
#define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK (0x800U)
#define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT (11U)
#define VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK (0x1000U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT (12U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK (0x2000U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT (13U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK (0x4000U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT (14U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK (0x8000U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT (15U)
#define VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK (0x10000U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT (16U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK (0x20000U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT (17U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK (0x40000U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT (18U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK (0x80000U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT (19U)
#define VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK (0x100000U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT (20U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK (0x200000U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT (21U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK (0x400000U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT (22U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK (0x800000U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT (23U)
#define VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK (0x3000000U)
#define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT (24U)
#define VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_MASK (0xC000000U)
#define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT (26U)
#define VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_CIR_START_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK (0x10000000U)
#define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT (28U)
#define VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK (0x20000000U)
#define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT (29U)
#define VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK)
#define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK (0xC0000000U)
#define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT (30U)
#define VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT)) & VPU_H264_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK)
/*! @} */
/*! @name SWREG250 - Global MV Control 0 */
/*! @{ */
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK (0x3FFF0U)
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT (4U)
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT)) & VPU_H264_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK)
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK (0xFFFC0000U)
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT (18U)
#define VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT)) & VPU_H264_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK)
/*! @} */
/*! @name SWREG251 - Global MV Control 1 */
/*! @{ */
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK (0x3FFF0U)
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT (4U)
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT)) & VPU_H264_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK)
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK (0xFFFC0000U)
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT (18U)
#define VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT)) & VPU_H264_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK)
/*! @} */
/*! @name SWREG252 - ROI3 Area */
/*! @{ */
#define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_MASK (0xFFCU)
#define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT (2U)
#define VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_RIGHT_MASK)
#define VPU_H264_SWREG252_SW_ENC_ROI3_TOP_MASK (0x3FF000U)
#define VPU_H264_SWREG252_SW_ENC_ROI3_TOP_SHIFT (12U)
#define VPU_H264_SWREG252_SW_ENC_ROI3_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_TOP_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_TOP_MASK)
#define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_MASK (0xFFC00000U)
#define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_SHIFT (22U)
#define VPU_H264_SWREG252_SW_ENC_ROI3_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_SHIFT)) & VPU_H264_SWREG252_SW_ENC_ROI3_LEFT_MASK)
/*! @} */
/*! @name SWREG253 - ROI3&4 Area */
/*! @{ */
#define VPU_H264_SWREG253_SW_ENC_ROI4_TOP_MASK (0xFFCU)
#define VPU_H264_SWREG253_SW_ENC_ROI4_TOP_SHIFT (2U)
#define VPU_H264_SWREG253_SW_ENC_ROI4_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI4_TOP_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI4_TOP_MASK)
#define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_MASK (0x3FF000U)
#define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_SHIFT (12U)
#define VPU_H264_SWREG253_SW_ENC_ROI4_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI4_LEFT_MASK)
#define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_MASK (0xFFC00000U)
#define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT (22U)
#define VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT)) & VPU_H264_SWREG253_SW_ENC_ROI3_BOTTOM_MASK)
/*! @} */
/*! @name SWREG254 - ROI4&5 Area */
/*! @{ */
#define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_MASK (0xFFCU)
#define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_SHIFT (2U)
#define VPU_H264_SWREG254_SW_ENC_ROI5_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI5_LEFT_MASK)
#define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_MASK (0x3FF000U)
#define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT (12U)
#define VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI4_BOTTOM_MASK)
#define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_MASK (0xFFC00000U)
#define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT (22U)
#define VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT)) & VPU_H264_SWREG254_SW_ENC_ROI4_RIGHT_MASK)
/*! @} */
/*! @name SWREG255 - ROI5 Area */
/*! @{ */
#define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_MASK (0xFFCU)
#define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT (2U)
#define VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_BOTTOM_MASK)
#define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_MASK (0x3FF000U)
#define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT (12U)
#define VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_RIGHT_MASK)
#define VPU_H264_SWREG255_SW_ENC_ROI5_TOP_MASK (0xFFC00000U)
#define VPU_H264_SWREG255_SW_ENC_ROI5_TOP_SHIFT (22U)
#define VPU_H264_SWREG255_SW_ENC_ROI5_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG255_SW_ENC_ROI5_TOP_SHIFT)) & VPU_H264_SWREG255_SW_ENC_ROI5_TOP_MASK)
/*! @} */
/*! @name SWREG256 - ROI6 Area */
/*! @{ */
#define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_MASK (0xFFCU)
#define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT (2U)
#define VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_RIGHT_MASK)
#define VPU_H264_SWREG256_SW_ENC_ROI6_TOP_MASK (0x3FF000U)
#define VPU_H264_SWREG256_SW_ENC_ROI6_TOP_SHIFT (12U)
#define VPU_H264_SWREG256_SW_ENC_ROI6_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_TOP_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_TOP_MASK)
#define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_MASK (0xFFC00000U)
#define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_SHIFT (22U)
#define VPU_H264_SWREG256_SW_ENC_ROI6_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_SHIFT)) & VPU_H264_SWREG256_SW_ENC_ROI6_LEFT_MASK)
/*! @} */
/*! @name SWREG257 - ROI6&7 Area */
/*! @{ */
#define VPU_H264_SWREG257_SW_ENC_ROI7_TOP_MASK (0xFFCU)
#define VPU_H264_SWREG257_SW_ENC_ROI7_TOP_SHIFT (2U)
#define VPU_H264_SWREG257_SW_ENC_ROI7_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI7_TOP_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI7_TOP_MASK)
#define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_MASK (0x3FF000U)
#define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_SHIFT (12U)
#define VPU_H264_SWREG257_SW_ENC_ROI7_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI7_LEFT_MASK)
#define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_MASK (0xFFC00000U)
#define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT (22U)
#define VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT)) & VPU_H264_SWREG257_SW_ENC_ROI6_BOTTOM_MASK)
/*! @} */
/*! @name SWREG258 - ROI7&8 Area */
/*! @{ */
#define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_MASK (0xFFCU)
#define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_SHIFT (2U)
#define VPU_H264_SWREG258_SW_ENC_ROI8_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI8_LEFT_MASK)
#define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_MASK (0x3FF000U)
#define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT (12U)
#define VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI7_BOTTOM_MASK)
#define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_MASK (0xFFC00000U)
#define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT (22U)
#define VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT)) & VPU_H264_SWREG258_SW_ENC_ROI7_RIGHT_MASK)
/*! @} */
/*! @name SWREG259 - ROI8 Area */
/*! @{ */
#define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK (0x2U)
#define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT (1U)
/*! SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE
* 0b0..max tu size 32.
* 0b1..max tu size 16.
*/
#define VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT)) & VPU_H264_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK)
#define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_MASK (0xFFCU)
#define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT (2U)
#define VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_BOTTOM_MASK)
#define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_MASK (0x3FF000U)
#define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT (12U)
#define VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_RIGHT_MASK)
#define VPU_H264_SWREG259_SW_ENC_ROI8_TOP_MASK (0xFFC00000U)
#define VPU_H264_SWREG259_SW_ENC_ROI8_TOP_SHIFT (22U)
#define VPU_H264_SWREG259_SW_ENC_ROI8_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG259_SW_ENC_ROI8_TOP_SHIFT)) & VPU_H264_SWREG259_SW_ENC_ROI8_TOP_MASK)
/*! @} */
/*! @name SWREG260 - ROI qp */
/*! @{ */
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK (0x1U)
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT (0U)
/*! SW_ENC_ROI5_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK (0xFEU)
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT (1U)
#define VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK (0x100U)
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT (8U)
/*! SW_ENC_ROI6_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK (0xFE00U)
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT (9U)
#define VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK (0x10000U)
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT (16U)
/*! SW_ENC_ROI7_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK (0xFE0000U)
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT (17U)
#define VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK (0x1000000U)
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT (24U)
/*! SW_ENC_ROI8_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK)
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK (0xFE000000U)
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT (25U)
#define VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT)) & VPU_H264_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK)
/*! @} */
/*! @name SWREG261 - Stride Control */
/*! @{ */
#define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK (0x1U)
#define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT (0U)
#define VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT)) & VPU_H264_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK)
#define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK (0x2U)
#define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT (1U)
#define VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT)) & VPU_H264_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK)
#define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_MASK (0x4U)
#define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT (2U)
#define VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT)) & VPU_H264_SWREG261_SW_ENC_RDOQ_ENABLE_MASK)
#define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_MASK (0x8U)
#define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT (3U)
#define VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT)) & VPU_H264_SWREG261_SW_ENC_MULTI_CORE_EN_MASK)
#define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK (0xFF0U)
#define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT (4U)
#define VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT)) & VPU_H264_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK)
#define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK (0x1000U)
#define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT (12U)
#define VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT)) & VPU_H264_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK)
#define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK (0x3E000U)
#define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT (13U)
#define VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT)) & VPU_H264_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK)
/*! @} */
/*! @name SWREG265 - Multicore sync ctrl */
/*! @{ */
#define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK (0xFFFFU)
#define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT (0U)
#define VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT)) & VPU_H264_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK)
#define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK (0xFFFF0000U)
#define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT (16U)
#define VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT)) & VPU_H264_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK)
/*! @} */
/*! @name SWREG266 - Multicore sync address L0 LSB */
/*! @{ */
#define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT (0U)
#define VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT)) & VPU_H264_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK)
/*! @} */
/*! @name SWREG267 - Multicore sync address L0 MSB */
/*! @{ */
#define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT (0U)
#define VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT)) & VPU_H264_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG268 - Multicore sync address L1 LSB */
/*! @{ */
#define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT (0U)
#define VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT)) & VPU_H264_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK)
/*! @} */
/*! @name SWREG269 - Multicore sync address L1 MSB */
/*! @{ */
#define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT (0U)
#define VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT)) & VPU_H264_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG270 - Multicore sync address recon LSB */
/*! @{ */
#define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT (0U)
#define VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT)) & VPU_H264_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK)
/*! @} */
/*! @name SWREG271 - Multicore sync address recon MSB */
/*! @{ */
#define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT (0U)
#define VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT)) & VPU_H264_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG272 - Programmable AXI urgent sideband signals */
/*! @{ */
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK (0xFFU)
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT (0U)
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK)
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK (0xFF00U)
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT (8U)
#define VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK (0xFF0000U)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT (16U)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK (0xFF000000U)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT (24U)
#define VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_H264_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK)
/*! @} */
/*! @name SWREG273 - roimap cu ctrl index address LSB */
/*! @{ */
#define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT (0U)
#define VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT)) & VPU_H264_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK)
/*! @} */
/*! @name SWREG274 - roimap cu ctrl index address MSB */
/*! @{ */
#define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT (0U)
#define VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT)) & VPU_H264_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG275 - roimap cu ctrl address LSB */
/*! @{ */
#define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT (0U)
#define VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT)) & VPU_H264_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK)
/*! @} */
/*! @name SWREG276 - roimap cu ctrl address MSB */
/*! @{ */
#define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT (0U)
#define VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT)) & VPU_H264_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG277 - poc type/bits setting */
/*! @{ */
#define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK (0xFFFE0U)
#define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT (5U)
#define VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT)) & VPU_H264_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK)
#define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_MASK (0x300000U)
#define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_SHIFT (20U)
#define VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_SHIFT)) & VPU_H264_SWREG277_SW_ENC_PIC_ORDER_CNT_TYPE_MASK)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_MASK (0x7C00000U)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_SHIFT (22U)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_SHIFT)) & VPU_H264_SWREG277_SW_ENC_LOG2_MAX_FRAME_NUM_MASK)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK (0xF8000000U)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT (27U)
#define VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT)) & VPU_H264_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK)
/*! @} */
/*! @name SWREG278 - stream output buffer1 address */
/*! @{ */
#define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT (0U)
#define VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT)) & VPU_H264_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK)
/*! @} */
/*! @name SWREG280 - stream output buffer1 limit size */
/*! @{ */
#define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK (0xFFFFFFFFU)
#define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT (0U)
#define VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT)) & VPU_H264_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK)
/*! @} */
/*! @name SWREG281 - poc type/bits setting */
/*! @{ */
#define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK (0x3F0U)
#define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT (4U)
#define VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT)) & VPU_H264_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK (0xFFC00U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT (10U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK (0x3FF00000U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT (20U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK (0x40000000U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT (30U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK (0x80000000U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT (31U)
#define VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT)) & VPU_H264_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK)
/*! @} */
/*! @name SWREG287 - HW synthesis config register 4, read-only */
/*! @{ */
#define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK (0x20000000U)
#define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT (29U)
/*! SW_ENC_HWSCALER420SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK)
#define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK (0x40000000U)
#define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT (30U)
/*! SW_ENC_HWCSCEXTENSIONSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK)
#define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK (0x80000000U)
#define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT (31U)
/*! SW_ENC_HWVIDEOHEIGHTEXT
* 0b0..Not.
* 0b1..Yes.
*/
#define VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT)) & VPU_H264_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK)
/*! @} */
/*! @name SWREG289 - Pre-processor color conversion parameters1 */
/*! @{ */
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_MASK (0xFFFFU)
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_SHIFT (0U)
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFH(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_SHIFT)) & VPU_H264_SWREG289_SW_ENC_RGBCOEFFH_MASK)
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_MASK (0xFFFF0000U)
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_SHIFT (16U)
#define VPU_H264_SWREG289_SW_ENC_RGBCOEFFG(x) (((uint32_t)(((uint32_t)(x)) << VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_SHIFT)) & VPU_H264_SWREG289_SW_ENC_RGBCOEFFG_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_H264_Register_Masks */
/* VPU_H264 - Peripheral instance base addresses */
/** Peripheral VPU_H264 base address */
#define VPU_H264_BASE (0x38320000u)
/** Peripheral VPU_H264 base pointer */
#define VPU_H264 ((VPU_H264_Type *)VPU_H264_BASE)
/** Array initializer of VPU_H264 peripheral base addresses */
#define VPU_H264_BASE_ADDRS { VPU_H264_BASE }
/** Array initializer of VPU_H264 peripheral base pointers */
#define VPU_H264_BASE_PTRS { VPU_H264 }
/*!
* @}
*/ /* end of group VPU_H264_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VPU_HEVC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_HEVC_Peripheral_Access_Layer VPU_HEVC Peripheral Access Layer
* @{
*/
/** VPU_HEVC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t SWREG1; /**< Interrupt register encoder, offset: 0x4 */
__IO uint32_t SWREG2; /**< Data configuration register0, offset: 0x8 */
__IO uint32_t SWREG3; /**< Data configuration register1, offset: 0xC */
__IO uint32_t SWREG4; /**< control register 0, offset: 0x10 */
__IO uint32_t SWREG5; /**< control register 1, offset: 0x14 */
uint8_t RESERVED_1[4];
__IO uint32_t SWREG7; /**< control register 3, offset: 0x1C */
__IO uint32_t SWREG8; /**< stream output buffer0 address, offset: 0x20 */
__IO uint32_t SWREG9; /**< stream output buffer0 limit size, offset: 0x24 */
__IO uint32_t SWREG10; /**< sizeTblBase, offset: 0x28 */
__IO uint32_t SWREG11; /**< encoded Picture order count, offset: 0x2C */
__IO uint32_t SWREG12; /**< input lum base address, offset: 0x30 */
__IO uint32_t SWREG13; /**< input cb base address, offset: 0x34 */
__IO uint32_t SWREG14; /**< input cr base address, offset: 0x38 */
__IO uint32_t SWREG15; /**< recon image luma base address, offset: 0x3C */
__IO uint32_t SWREG16; /**< recon image chroma base address, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t SWREG18; /**< reference picture reconstructed list0 luma0, offset: 0x48 */
__IO uint32_t SWREG19; /**< reference picture reconstructed list0 chroma0, offset: 0x4C */
uint8_t RESERVED_3[8];
__IO uint32_t SWREG22; /**< Cyclic Intra, offset: 0x58 */
__IO uint32_t SWREG23; /**< intra Area, offset: 0x5C */
__IO uint32_t SWREG24; /**< ROI1 Area, offset: 0x60 */
__IO uint32_t SWREG25; /**< ROI2 Area, offset: 0x64 */
__IO uint32_t SWREG26_H2V2; /**< intra size factors. For H2V2 or later version., offset: 0x68 */
__IO uint32_t SWREG27_H2V2; /**< intra mode factors . For H2V2 or later version., offset: 0x6C */
__IO uint32_t SWREG28_H2V5; /**< inter me SATD lambda config 0. For H2V5 or later version., offset: 0x70 */
__IO uint32_t SWREG29_H2V5; /**< inter me SATD lambda config 1.For H2V5 or later version., offset: 0x74 */
__IO uint32_t SWREG30_H2V5; /**< inter me SATD lambda config 2. For H2V5 or later version., offset: 0x78 */
__IO uint32_t SWREG31_H2V5; /**< inter me SATD lambda config 3. For H2V5 or later version., offset: 0x7C */
__IO uint32_t SWREG32_H2V5; /**< inter me SATD lambda config 4. For H2V5 or later version., offset: 0x80 */
__IO uint32_t SWREG33_H2V5; /**< inter me SATD lambda config 5. For H2V5 or later version., offset: 0x84 */
__IO uint32_t SWREG34_H2V5; /**< inter me SATD lambda config 6. For H2V5 or later version., offset: 0x88 */
__IO uint32_t SWREG35; /**< inter prediction parameters1, offset: 0x8C */
__IO uint32_t SWREG36; /**< inter prediction parameters2, offset: 0x90 */
__IO uint32_t SWREG37; /**< SAO lambda parameter, offset: 0x94 */
__IO uint32_t SWREG38; /**< Pre-processor configuration, offset: 0x98 */
__IO uint32_t SWREG39; /**< Pre-processor color conversion parameters0, offset: 0x9C */
__IO uint32_t SWREG40; /**< Pre-processor color conversion parameters1, offset: 0xA0 */
__IO uint32_t SWREG41; /**< Pre-processor color conversion parameters2, offset: 0xA4 */
__IO uint32_t SWREG42; /**< Pre-processor Base address for down-scaled output, offset: 0xA8 */
__IO uint32_t SWREG43; /**< Pre-processor down-scaled configuration0, offset: 0xAC */
__IO uint32_t SWREG44; /**< Pre-processor down-scaled configuration1, offset: 0xB0 */
__IO uint32_t SWREG45; /**< Pre-processor down-scaled configuration2, offset: 0xB4 */
__IO uint32_t SWREG46; /**< compressed coefficients base address for SAN module., offset: 0xB8 */
uint8_t RESERVED_4[52];
__IO uint32_t SWREG60; /**< Base address for recon luma compress table LSB., offset: 0xF0 */
uint8_t RESERVED_5[4];
__IO uint32_t SWREG62; /**< Base address for recon Chroma compress table LSB, offset: 0xF8 */
uint8_t RESERVED_6[4];
__IO uint32_t SWREG64; /**< Base address for list 0 ref 0 luma compress table LSB., offset: 0x100 */
uint8_t RESERVED_7[4];
__IO uint32_t SWREG66; /**< Base address for list 0 ref 0 Chroma compress table LSB., offset: 0x108 */
uint8_t RESERVED_8[20];
__IO uint32_t SWREG72; /**< Base address for recon luma 4n base LSB., offset: 0x120 */
uint8_t RESERVED_9[4];
__IO uint32_t SWREG74; /**< reference picture reconstructed list0 4n 0, offset: 0x128 */
uint8_t RESERVED_10[12];
__IO uint32_t SWREG78_H2V5; /**< inter me SATD lambda config 7. For H2V5 or later version., offset: 0x138 */
__IO uint32_t SWREG79_H2V5; /**< inter me SSE lambda config 0. For H2V5 or later version., offset: 0x13C */
uint8_t RESERVED_11[4];
__IO uint32_t SWREG81; /**< hardware configuation 0, offset: 0x144 */
__I uint32_t SWREG82; /**< record hardware performance, offset: 0x148 */
__IO uint32_t SWREG83; /**< reference picture reconstructed list1 luma0, offset: 0x14C */
__IO uint32_t SWREG84; /**< reference picture reconstructed list1 chroma0, offset: 0x150 */
uint8_t RESERVED_12[24];
__IO uint32_t SWREG91; /**< reference pictures list1 config, offset: 0x16C */
__IO uint32_t SWREG92; /**< reference picture reconstructed list1 4n 0, offset: 0x170 */
uint8_t RESERVED_13[12];
__IO uint32_t SWREG96; /**< Base address for list 1 ref 0 luma compress table LSB., offset: 0x180 */
uint8_t RESERVED_14[4];
__IO uint32_t SWREG98; /**< Base address for list 1 ref 0 Chroma compress table LSB., offset: 0x188 */
uint8_t RESERVED_15[20];
__IO uint32_t SWREG104; /**< reference picture lists modification, offset: 0x1A0 */
uint8_t RESERVED_16[4];
__IO uint32_t SWREG106; /**< Min picture size, offset: 0x1A8 */
__IO uint32_t SWREG107; /**< Max picture size, offset: 0x1AC */
uint8_t RESERVED_17[4];
__IO uint32_t SWREG109; /**< Qp delta map, offset: 0x1B4 */
uint8_t RESERVED_18[4];
__I uint32_t SWREG111; /**< adaptive GOP configuration1, offset: 0x1BC */
__I uint32_t SWREG112; /**< adaptive GOP configuration2, offset: 0x1C0 */
__IO uint32_t SWREG113; /**< adaptive GOP configuration3, offset: 0x1C4 */
uint8_t RESERVED_19[20];
__IO uint32_t SWREG119; /**< min/max lcu bits number of last picture, offset: 0x1DC */
__IO uint32_t SWREG120; /**< total bits number of all lcus of last picture not including slice header bits, offset: 0x1E0 */
uint8_t RESERVED_20[4];
__IO uint32_t SWREG122_H2V5; /**< inter me SSE lambda config 1. For H2V5 or later version., offset: 0x1E8 */
__IO uint32_t SWREG123_H2V5; /**< inter me SSE lambda config 2. For H2V5 or later version., offset: 0x1EC */
__IO uint32_t SWREG124_H2V5; /**< inter me SSE lambda config 3. For H2V5 or later version., offset: 0x1F0 */
__IO uint32_t SWREG125; /**< intra SATD lambda config 0, offset: 0x1F4 */
__IO uint32_t SWREG126; /**< intra SATD lambda config 1, offset: 0x1F8 */
__IO uint32_t SWREG127; /**< intra SATD lambda config 2, offset: 0x1FC */
__IO uint32_t SWREG128; /**< intra SATD lambda config 3, offset: 0x200 */
__IO uint32_t SWREG129; /**< intra SATD lambda config 4, offset: 0x204 */
__IO uint32_t SWREG130; /**< intra SATD lambda config 5, offset: 0x208 */
__IO uint32_t SWREG131; /**< intra SATD lambda config 6, offset: 0x20C */
__IO uint32_t SWREG132; /**< intra SATD lambda config 7, offset: 0x210 */
__IO uint32_t SWREG133; /**< SSE devide 256, offset: 0x214 */
__IO uint32_t SWREG134; /**< noise reduction, offset: 0x218 */
__IO uint32_t SWREG135; /**< noise reduction 1, offset: 0x21C */
__IO uint32_t SWREG136; /**< noise reduction 2, offset: 0x220 */
__IO uint32_t SWREG137; /**< noise reduction 3, offset: 0x224 */
__IO uint32_t SWREG138_H2V5; /**< inter me SSE lambda config 4. For H2V5 or later version., offset: 0x228 */
__IO uint32_t SWREG139_H2V5; /**< inter me SSE lambda config 5. For H2V5 or later version., offset: 0x22C */
__IO uint32_t SWREG140_H2V5; /**< inter me SSE lambda config 6. For H2V5 or later version., offset: 0x230 */
__IO uint32_t SWREG141_H2V5; /**< inter me SSE lambda config 7. For H2V5 or later version., offset: 0x234 */
__IO uint32_t SWREG142_H2V5; /**< inter me SSE lambda config 8. For H2V5 or later version., offset: 0x238 */
__IO uint32_t SWREG143_H2V5; /**< inter me SSE lambda config 9. For H2V5 or later version., offset: 0x23C */
__IO uint32_t SWREG144_H2V5; /**< inter me SSE lambda config 10. For H2V5 or later version., offset: 0x240 */
__IO uint32_t SWREG145_H2V5; /**< inter me SSE lambda config 11. For H2V5 or later version., offset: 0x244 */
__IO uint32_t SWREG146_H2V5; /**< inter me SSE lambda config 12. For H2V5 or later version., offset: 0x248 */
__IO uint32_t SWREG147_H2V5; /**< inter me SSE lambda config 13. For H2V5 or later version., offset: 0x24C */
__IO uint32_t SWREG148_H2V5; /**< inter me SSE lambda config 14. For H2V5 or later version., offset: 0x250 */
__IO uint32_t SWREG149_H2V5; /**< inter me SSE lambda config 15. For H2V5 or later version., offset: 0x254 */
__IO uint32_t SWREG150; /**< inter me SATD lambda config 8, offset: 0x258 */
__IO uint32_t SWREG151; /**< inter me SATD lambda config 9, offset: 0x25C */
__IO uint32_t SWREG152; /**< inter me SATD lambda config 10, offset: 0x260 */
__IO uint32_t SWREG153; /**< inter me SATD lambda config 11, offset: 0x264 */
__IO uint32_t SWREG154; /**< inter me SATD lambda config 12, offset: 0x268 */
__IO uint32_t SWREG155; /**< inter me SATD lambda config 13, offset: 0x26C */
__IO uint32_t SWREG156; /**< inter me SATD lambda config 14, offset: 0x270 */
__IO uint32_t SWREG157; /**< inter me SATD lambda config 15, offset: 0x274 */
__IO uint32_t SWREG158; /**< inter me SSE lambda config 16, offset: 0x278 */
__IO uint32_t SWREG159; /**< inter me SSE lambda config 17, offset: 0x27C */
__IO uint32_t SWREG160; /**< inter me SSE lambda config 18, offset: 0x280 */
__IO uint32_t SWREG161; /**< inter me SSE lambda config 19, offset: 0x284 */
__IO uint32_t SWREG162; /**< inter me SSE lambda config 20, offset: 0x288 */
__IO uint32_t SWREG163; /**< inter me SSE lambda config 21, offset: 0x28C */
__IO uint32_t SWREG164; /**< inter me SSE lambda config 22, offset: 0x290 */
__IO uint32_t SWREG165; /**< inter me SSE lambda config 23, offset: 0x294 */
__IO uint32_t SWREG166; /**< inter me SSE lambda config 24, offset: 0x298 */
__IO uint32_t SWREG167; /**< inter me SSE lambda config 25, offset: 0x29C */
__IO uint32_t SWREG168; /**< inter me SSE lambda config 26, offset: 0x2A0 */
__IO uint32_t SWREG169; /**< inter me SSE lambda config 27, offset: 0x2A4 */
uint8_t RESERVED_21[8];
__IO uint32_t SWREG172; /**< inter me SSE lambda config 30, offset: 0x2B0 */
__IO uint32_t SWREG173; /**< inter me SSE lambda config 31, offset: 0x2B4 */
__IO uint32_t SWREG174; /**< intra SATD lambda config 8, offset: 0x2B8 */
__IO uint32_t SWREG175; /**< intra SATD lambda config 9, offset: 0x2BC */
__IO uint32_t SWREG176; /**< intra SATD lambda config 10, offset: 0x2C0 */
__IO uint32_t SWREG177; /**< intra SATD lambda config 11, offset: 0x2C4 */
__IO uint32_t SWREG178; /**< intra SATD lambda config 12, offset: 0x2C8 */
__IO uint32_t SWREG179; /**< intra SATD lambda config 13, offset: 0x2CC */
__IO uint32_t SWREG180; /**< intra SATD lambda config 14, offset: 0x2D0 */
__IO uint32_t SWREG181; /**< intra SATD lambda config 15, offset: 0x2D4 */
__IO uint32_t SWREG182; /**< qp fractional part, offset: 0x2D8 */
__I uint32_t SWREG183; /**< qp sum, offset: 0x2DC */
__I uint32_t SWREG184; /**< qp num, offset: 0x2E0 */
__IO uint32_t SWREG185; /**< picture complexity. Timeout cycles MSB., offset: 0x2E4 */
__IO uint32_t SWREG186; /**< Base address for CU information table LSB, offset: 0x2E8 */
uint8_t RESERVED_22[4];
__IO uint32_t SWREG188; /**< Base address for CU information LSB, offset: 0x2F0 */
uint8_t RESERVED_23[4];
__IO uint32_t SWREG190; /**< Long-term reference pictures config, offset: 0x2F8 */
__IO uint32_t SWREG191; /**< Temporal scalable config, offset: 0x2FC */
uint8_t RESERVED_24[12];
__IO uint32_t SWREG195; /**< register extension for ctu_size=16, offset: 0x30C */
__IO uint32_t SWREG196; /**< Low Latency Controls, offset: 0x310 */
__IO uint32_t SWREG197; /**< Delta POC extension, offset: 0x314 */
__IO uint32_t SWREG198; /**< Long Term Reference Control, offset: 0x318 */
__IO uint32_t SWREG199; /**< Hash Code Control, offset: 0x31C */
__IO uint32_t SWREG200; /**< Hash Code Value, offset: 0x320 */
__IO uint32_t SWREG201; /**< Background SKIP Control 0, offset: 0x324 */
__IO uint32_t SWREG202; /**< Background SKIP Control 1, offset: 0x328 */
__IO uint32_t SWREG203; /**< Background SKIP Control 2, offset: 0x32C */
__IO uint32_t SWREG204; /**< Background SKIP Control 3, offset: 0x330 */
__IO uint32_t SWREG205; /**< Background SKIP Control 4, offset: 0x334 */
__IO uint32_t SWREG206; /**< Background SKIP Control 5, offset: 0x338 */
__IO uint32_t SWREG207; /**< Background SKIP Control 6, offset: 0x33C */
__IO uint32_t SWREG208; /**< Background SKIP Control 7, offset: 0x340 */
__IO uint32_t SWREG209; /**< IPCM Control 0, offset: 0x344 */
__IO uint32_t SWREG210; /**< IPCM Control 1, offset: 0x348 */
__IO uint32_t SWREG211; /**< IPCM Control 2, offset: 0x34C */
__IO uint32_t SWREG212; /**< IPCM Control 3, offset: 0x350 */
__IO uint32_t SWREG213; /**< IPCM Control 4, offset: 0x354 */
__I uint32_t SWREG214; /**< HW synthesis config register 2, read-only, offset: 0x358 */
__I uint32_t SWREG215; /**< AXI Information 0, offset: 0x35C */
__I uint32_t SWREG216; /**< AXI Information 1, offset: 0x360 */
__I uint32_t SWREG217; /**< AXI Information 2, offset: 0x364 */
__I uint32_t SWREG218; /**< AXI Information 3, offset: 0x368 */
__I uint32_t SWREG219; /**< AXI Information 4, offset: 0x36C */
__I uint32_t SWREG220; /**< AXI Information 5, offset: 0x370 */
__I uint32_t SWREG221; /**< AXI Information 6, offset: 0x374 */
__I uint32_t SWREG222; /**< AXI Information 7, offset: 0x378 */
__I uint32_t SWREG223; /**< AXI Information 8, offset: 0x37C */
__IO uint32_t SWREG224; /**< control register 4, offset: 0x380 */
__IO uint32_t SWREG225; /**< Tile Control, offset: 0x384 */
__I uint32_t SWREG226; /**< HW synthesis config register 3, read-only, offset: 0x388 */
uint8_t RESERVED_25[32];
__IO uint32_t SWREG235; /**< RPS encoding control 0, offset: 0x3AC */
__IO uint32_t SWREG236; /**< RPS encoding control 1, offset: 0x3B0 */
__IO uint32_t SWREG237; /**< Stride Control, offset: 0x3B4 */
__IO uint32_t SWREG238; /**< Dummy Read, offset: 0x3B8 */
__IO uint32_t SWREG239; /**< Base Address LSB of CTB MADs of current frame., offset: 0x3BC */
uint8_t RESERVED_26[4];
__IO uint32_t SWREG241; /**< Base Address LSB of CTB MADs of previous frame., offset: 0x3C4 */
uint8_t RESERVED_27[4];
__IO uint32_t SWREG243; /**< CTB RC Control 0, offset: 0x3CC */
__IO uint32_t SWREG244; /**< CTB RC Control 1, offset: 0x3D0 */
__IO uint32_t SWREG245; /**< CTB RC Control 2, offset: 0x3D4 */
__IO uint32_t SWREG246; /**< CTB RC Control 3, offset: 0x3D8 */
__IO uint32_t SWREG247; /**< CTB RC Control 4, offset: 0x3DC */
__IO uint32_t SWREG248; /**< CTB RC Control 5, offset: 0x3E0 */
__IO uint32_t SWREG249; /**< register extension for 8K width, offset: 0x3E4 */
__IO uint32_t SWREG250; /**< Global MV Control 0, offset: 0x3E8 */
__IO uint32_t SWREG251; /**< Global MV Control 1, offset: 0x3EC */
__IO uint32_t SWREG252; /**< ROI3 Area, offset: 0x3F0 */
__IO uint32_t SWREG253; /**< ROI3&4 Area, offset: 0x3F4 */
__IO uint32_t SWREG254; /**< ROI4&5 Area, offset: 0x3F8 */
__IO uint32_t SWREG255; /**< ROI5 Area, offset: 0x3FC */
__IO uint32_t SWREG256; /**< ROI6 Area, offset: 0x400 */
__IO uint32_t SWREG257; /**< ROI6&7 Area, offset: 0x404 */
__IO uint32_t SWREG258; /**< ROI7&8 Area, offset: 0x408 */
__IO uint32_t SWREG259; /**< ROI8 Area, offset: 0x40C */
__IO uint32_t SWREG260; /**< ROI qp, offset: 0x410 */
__IO uint32_t SWREG261; /**< Stride Control, offset: 0x414 */
uint8_t RESERVED_28[12];
__IO uint32_t SWREG265; /**< Multicore sync ctrl, offset: 0x424 */
__IO uint32_t SWREG266; /**< Multicore sync address L0 LSB, offset: 0x428 */
__IO uint32_t SWREG267; /**< Multicore sync address L0 MSB, offset: 0x42C */
__IO uint32_t SWREG268; /**< Multicore sync address L1 LSB, offset: 0x430 */
__IO uint32_t SWREG269; /**< Multicore sync address L1 MSB, offset: 0x434 */
__IO uint32_t SWREG270; /**< Multicore sync address recon LSB, offset: 0x438 */
__IO uint32_t SWREG271; /**< Multicore sync address recon MSB, offset: 0x43C */
__IO uint32_t SWREG272; /**< Programmable AXI urgent sideband signals, offset: 0x440 */
__IO uint32_t SWREG273; /**< roimap cu ctrl index address LSB, offset: 0x444 */
__IO uint32_t SWREG274; /**< roimap cu ctrl index address MSB, offset: 0x448 */
__IO uint32_t SWREG275; /**< roimap cu ctrl address LSB, offset: 0x44C */
__IO uint32_t SWREG276; /**< roimap cu ctrl address MSB, offset: 0x450 */
__IO uint32_t SWREG277; /**< poc type/bits setting, offset: 0x454 */
__IO uint32_t SWREG278; /**< stream output buffer1 address, offset: 0x458 */
uint8_t RESERVED_29[4];
__IO uint32_t SWREG280; /**< stream output buffer1 limit size, offset: 0x460 */
__IO uint32_t SWREG281; /**< poc type/bits setting, offset: 0x464 */
uint8_t RESERVED_30[20];
__I uint32_t SWREG287; /**< HW synthesis config register 4, read-only, offset: 0x47C */
uint8_t RESERVED_31[4];
__IO uint32_t SWREG289; /**< Pre-processor color conversion parameters1, offset: 0x484 */
} VPU_HEVC_Type;
/* ----------------------------------------------------------------------------
-- VPU_HEVC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VPU_HEVC_Register_Masks VPU_HEVC Register Masks
* @{
*/
/*! @name SWREG1 - Interrupt register encoder */
/*! @{ */
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_MASK (0x1U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_SHIFT (0U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_MASK (0x2U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_SHIFT (1U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_DIS_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK (0x4U)
#define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT (2U)
#define VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_FRAME_RDY_STATUS_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK (0x8U)
#define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT (3U)
#define VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_BUS_ERROR_STATUS_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_SW_RESET_MASK (0x10U)
#define VPU_HEVC_SWREG1_SW_ENC_SW_RESET_SHIFT (4U)
#define VPU_HEVC_SWREG1_SW_ENC_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_SW_RESET_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_SW_RESET_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_MASK (0x20U)
#define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_SHIFT (5U)
#define VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_BUFFER_FULL_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_MASK (0x40U)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_SHIFT (6U)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK (0x80U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT (7U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_LINE_BUFFER_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK (0x100U)
#define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT (8U)
#define VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_SLICE_RDY_STATUS_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK (0x200U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT (9U)
#define VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_IRQ_FUSE_ERROR_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_MASK (0x800U)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT (11U)
#define VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_TIMEOUT_INT_MASK)
#define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK (0x1000U)
#define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT (12U)
#define VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_SHIFT)) & VPU_HEVC_SWREG1_SW_ENC_STRM_SEGMENT_RDY_INT_MASK)
/*! @} */
/*! @name SWREG2 - Data configuration register0 */
/*! @{ */
#define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK (0xFU)
#define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT (0U)
#define VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_CTB_RC_MEM_OUT_SWAP_MASK)
#define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK (0xF0U)
#define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT (4U)
#define VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_ROI_MAP_QP_DELTA_MAP_SWAP_MASK)
#define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_MASK (0xF00U)
#define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_SHIFT (8U)
#define VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_PIC_SWAP_MASK)
#define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_MASK (0xF000U)
#define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_SHIFT (12U)
#define VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_STRM_SWAP_MASK)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_MASK (0xFF0000U)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_SHIFT (16U)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_AXI_READ_ID_MASK)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_MASK (0xFF000000U)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT (24U)
#define VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_SHIFT)) & VPU_HEVC_SWREG2_SW_ENC_AXI_WRITE_ID_MASK)
/*! @} */
/*! @name SWREG3 - Data configuration register1 */
/*! @{ */
#define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK (0x2U)
#define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT (1U)
#define VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_STRM_SEGMENT_INT_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK (0x4U)
#define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT (2U)
#define VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_LINE_BUFFER_INT_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_MASK (0x8U)
#define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_SHIFT (3U)
#define VPU_HEVC_SWREG3_SW_ENC_SLICE_INT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_SLICE_INT_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK (0xF00000U)
#define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT (20U)
#define VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CU_INFO_MEM_OUT_SWAP_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_MASK (0x1000000U)
#define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT (24U)
/*! SW_ENC_AXI_RD_ID_E
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_AXI_RD_ID_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_MASK (0x2000000U)
#define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT (25U)
/*! SW_ENC_AXI_WR_ID_E
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_AXI_WR_ID_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK (0x4000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT (26U)
/*! SW_ENC_CLOCK_GATE_INTER_H264_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H264_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK (0x8000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT (27U)
/*! SW_ENC_CLOCK_GATE_INTER_H265_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_H265_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK (0x10000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT (28U)
/*! SW_ENC_CLOCK_GATE_INTER_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_INTER_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK (0x20000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT (29U)
/*! SW_ENC_CLOCK_GATE_ENCODER_H264_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H264_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK (0x40000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT (30U)
/*! SW_ENC_CLOCK_GATE_ENCODER_H265_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_H265_E_MASK)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK (0x80000000U)
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT (31U)
/*! SW_ENC_CLOCK_GATE_ENCODER_E
* 0b0..clock always on.
* 0b1..hardware clock gating control
*/
#define VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_SHIFT)) & VPU_HEVC_SWREG3_SW_ENC_CLOCK_GATE_ENCODER_E_MASK)
/*! @} */
/*! @name SWREG4 - control register 0 */
/*! @{ */
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK (0x7U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT (0U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTER_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK (0x38U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT (3U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRANS_HIERARCHY_DEPTH_INTRA_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_MASK (0x40U)
#define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_SHIFT (6U)
#define VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_SAO_ENABLE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_MASK (0x80U)
#define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_SHIFT (7U)
#define VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_ACTIVE_OVERRIDE_FLAG_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK (0x100U)
#define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT (8U)
#define VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_SCALING_LIST_ENABLED_FLAG_MASK)
#define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_MASK (0x800U)
#define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT (11U)
#define VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_SHIFT)) & VPU_HEVC_SWREG4_SW_BW_LINEBUF_DISABLE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_MASK (0x1000U)
#define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_SHIFT (12U)
#define VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_STRONG_INTRA_SMOOTHING_ENABLED_FLAG_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK (0x3E000U)
#define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT (13U)
#define VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_CHROMA_QP_OFFSET_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK (0x40000U)
#define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT (18U)
/*! SW_ENC_OUTPUT_STRM_MODE
* 0b0..byte stream
* 0b1..Nal stream
*/
#define VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_OUTPUT_STRM_MODE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK (0x180000U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT (19U)
/*! SW_ENC_MAX_TRB_SIZE
* 0b00..4x4
* 0b01..8x8
* 0b10..16x16
* 0b11..32x32
*/
#define VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_TRB_SIZE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK (0x600000U)
#define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT (21U)
/*! SW_ENC_MIN_TRB_SIZE
* 0b00..4x4
* 0b01..8x8
* 0b10..16x16
* 0b11..32x32
*/
#define VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MIN_TRB_SIZE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_MASK (0x1800000U)
#define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT (23U)
/*! SW_ENC_MAX_CB_SIZE
* 0b00..8x8
* 0b01..16x16
* 0b10..32x32
* 0b11..64x64
*/
#define VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MAX_CB_SIZE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_MASK (0x6000000U)
#define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT (25U)
/*! SW_ENC_MIN_CB_SIZE
* 0b00..8x8
* 0b01..16x16
* 0b10..32x32
* 0b11..64x64
*/
#define VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MIN_CB_SIZE_MASK)
#define VPU_HEVC_SWREG4_SW_ENC_MODE_MASK (0xE0000000U)
#define VPU_HEVC_SWREG4_SW_ENC_MODE_SHIFT (29U)
/*! SW_ENC_MODE
* 0b001..hevc.
* 0b010..h264.
* 0b100..jpeg
*/
#define VPU_HEVC_SWREG4_SW_ENC_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG4_SW_ENC_MODE_SHIFT)) & VPU_HEVC_SWREG4_SW_ENC_MODE_MASK)
/*! @} */
/*! @name SWREG5 - control register 1 */
/*! @{ */
#define VPU_HEVC_SWREG5_SW_ENC_E_MASK (0x1U)
#define VPU_HEVC_SWREG5_SW_ENC_E_SHIFT (0U)
#define VPU_HEVC_SWREG5_SW_ENC_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_E_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_E_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK (0x6U)
#define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT (1U)
#define VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_FRAME_CODING_TYPE_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_MASK (0x40U)
#define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_SHIFT (6U)
/*! SW_ENC_OUTPUT_CU_INFO_ENABLED
* 0b0..disable
* 0b1..enable
*/
#define VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_OUTPUT_CU_INFO_ENABLED_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK (0x100U)
#define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT (8U)
/*! SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG
* 0b0..no
* 0b1..yes
*/
#define VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_SLICE_DEBLOCKING_FILTER_OVERRIDE_FLAG_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK (0x200U)
#define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT (9U)
/*! SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG
* 0b0..disable
* 0b1..enable
*/
#define VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PPS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_MASK (0x3FF800U)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT (11U)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PIC_HEIGHT_MASK)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_SHIFT (22U)
#define VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_SHIFT)) & VPU_HEVC_SWREG5_SW_ENC_PIC_WIDTH_MASK)
/*! @} */
/*! @name SWREG7 - control register 3 */
/*! @{ */
#define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK (0xFU)
#define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT (0U)
#define VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_ROI2_DELTA_QP_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK (0xF0U)
#define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT (4U)
#define VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_ROI1_DELTA_QP_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_QP_MASK (0x3F00U)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_QP_SHIFT (8U)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_PIC_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_PIC_QP_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK (0xC000U)
#define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT (14U)
#define VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_DIFF_CU_QP_DELTA_DEPTH_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_MASK (0x1FE0000U)
#define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT (17U)
#define VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_NUM_SLICES_READY_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK (0x2000000U)
#define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT (25U)
#define VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_CABAC_INIT_FLAG_MASK)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_MASK (0xFC000000U)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT (26U)
#define VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_SHIFT)) & VPU_HEVC_SWREG7_SW_ENC_PIC_INIT_QP_MASK)
/*! @} */
/*! @name SWREG8 - stream output buffer0 address */
/*! @{ */
#define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_SHIFT)) & VPU_HEVC_SWREG8_SW_ENC_OUTPUT_STRM_BASE_MASK)
/*! @} */
/*! @name SWREG9 - stream output buffer0 limit size */
/*! @{ */
#define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT (0U)
#define VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_SHIFT)) & VPU_HEVC_SWREG9_SW_ENC_OUTPUT_STRM_BUFFER_LIMIT_MASK)
/*! @} */
/*! @name SWREG10 - sizeTblBase */
/*! @{ */
#define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_SHIFT)) & VPU_HEVC_SWREG10_SW_ENC_SIZE_TBL_BASE_MASK)
/*! @} */
/*! @name SWREG11 - encoded Picture order count */
/*! @{ */
#define VPU_HEVC_SWREG11_SW_ENC_POC_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG11_SW_ENC_POC_SHIFT (0U)
#define VPU_HEVC_SWREG11_SW_ENC_POC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG11_SW_ENC_POC_SHIFT)) & VPU_HEVC_SWREG11_SW_ENC_POC_MASK)
/*! @} */
/*! @name SWREG12 - input lum base address */
/*! @{ */
#define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_SHIFT)) & VPU_HEVC_SWREG12_SW_ENC_INPUT_Y_BASE_MASK)
/*! @} */
/*! @name SWREG13 - input cb base address */
/*! @{ */
#define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_SHIFT)) & VPU_HEVC_SWREG13_SW_ENC_INPUT_CB_BASE_MASK)
/*! @} */
/*! @name SWREG14 - input cr base address */
/*! @{ */
#define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_SHIFT)) & VPU_HEVC_SWREG14_SW_ENC_INPUT_CR_BASE_MASK)
/*! @} */
/*! @name SWREG15 - recon image luma base address */
/*! @{ */
#define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_SHIFT)) & VPU_HEVC_SWREG15_SW_ENC_RECON_Y_BASE_MASK)
/*! @} */
/*! @name SWREG16 - recon image chroma base address */
/*! @{ */
#define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_SHIFT)) & VPU_HEVC_SWREG16_SW_ENC_RECON_CHROMA_BASE_MASK)
/*! @} */
/*! @name SWREG18 - reference picture reconstructed list0 luma0 */
/*! @{ */
#define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT (0U)
#define VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_SHIFT)) & VPU_HEVC_SWREG18_SW_ENC_REFPIC_RECON_L0_Y0_MASK)
/*! @} */
/*! @name SWREG19 - reference picture reconstructed list0 chroma0 */
/*! @{ */
#define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT (0U)
#define VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_SHIFT)) & VPU_HEVC_SWREG19_SW_ENC_REFPIC_RECON_L0_CHROMA0_MASK)
/*! @} */
/*! @name SWREG22 - Cyclic Intra */
/*! @{ */
#define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_MASK (0xFU)
#define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT (0U)
#define VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_RCROI_ENABLE_MASK)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT (4U)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_CIR_INTERVAL_MASK)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_START_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_START_SHIFT (18U)
#define VPU_HEVC_SWREG22_SW_ENC_CIR_START(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG22_SW_ENC_CIR_START_SHIFT)) & VPU_HEVC_SWREG22_SW_ENC_CIR_START_MASK)
/*! @} */
/*! @name SWREG23 - intra Area */
/*! @{ */
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK (0xFFU)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT (0U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_BOTTOM_MASK)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK (0xFF00U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT (8U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_TOP_MASK)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK (0xFF0000U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT (16U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_RIGHT_MASK)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK (0xFF000000U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT (24U)
#define VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_SHIFT)) & VPU_HEVC_SWREG23_SW_ENC_INTRA_AREA_LEFT_MASK)
/*! @} */
/*! @name SWREG24 - ROI1 Area */
/*! @{ */
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_MASK (0xFFU)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT (0U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_BOTTOM_MASK)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_MASK (0xFF00U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_SHIFT (8U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_TOP_MASK)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_MASK (0xFF0000U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT (16U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_RIGHT_MASK)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_MASK (0xFF000000U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_SHIFT (24U)
#define VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_SHIFT)) & VPU_HEVC_SWREG24_SW_ENC_ROI1_LEFT_MASK)
/*! @} */
/*! @name SWREG25 - ROI2 Area */
/*! @{ */
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_MASK (0xFFU)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT (0U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_BOTTOM_MASK)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_MASK (0xFF00U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_SHIFT (8U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_TOP_MASK)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_MASK (0xFF0000U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT (16U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_RIGHT_MASK)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_MASK (0xFF000000U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_SHIFT (24U)
#define VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_SHIFT)) & VPU_HEVC_SWREG25_SW_ENC_ROI2_LEFT_MASK)
/*! @} */
/*! @name SWREG26_H2V2 - intra size factors. For H2V2 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK (0xFFCU)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT (2U)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_2_MASK)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK (0x3FF000U)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT (12U)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_1_MASK)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT (22U)
#define VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_SHIFT)) & VPU_HEVC_SWREG26_H2V2_SW_ENC_INTRA_SIZE_FACTOR_0_MASK)
/*! @} */
/*! @name SWREG27_H2V2 - intra mode factors . For H2V2 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK (0x7F0U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT (4U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_2_MASK)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK (0x1F800U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT (11U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_1_MASK)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK (0x3E0000U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT (17U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_MODE_FACTOR_0_MASK)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT (22U)
#define VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_SHIFT)) & VPU_HEVC_SWREG27_H2V2_SW_ENC_INTRA_SIZE_FACTOR_3_MASK)
/*! @} */
/*! @name SWREG28_H2V5 - inter me SATD lambda config 0. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_1_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG28_H2V5_SW_ENC_LAMDA_SATD_ME_0_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG29_H2V5 - inter me SATD lambda config 1.For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_3_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG29_H2V5_SW_ENC_LAMDA_SATD_ME_2_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG30_H2V5 - inter me SATD lambda config 2. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_5_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG30_H2V5_SW_ENC_LAMDA_SATD_ME_4_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG31_H2V5 - inter me SATD lambda config 3. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_7_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG31_H2V5_SW_ENC_LAMDA_SATD_ME_6_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG32_H2V5 - inter me SATD lambda config 4. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_9_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG32_H2V5_SW_ENC_LAMDA_SATD_ME_8_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG33_H2V5 - inter me SATD lambda config 5. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_11_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG33_H2V5_SW_ENC_LAMDA_SATD_ME_10_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG34_H2V5 - inter me SATD lambda config 6. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_13_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG34_H2V5_SW_ENC_LAMDA_SATD_ME_12_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG35 - inter prediction parameters1 */
/*! @{ */
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK (0xFFU)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT (0U)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_16_MASK)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK (0x7F00U)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT (8U)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_BIAS_INTRA_CU_8_MASK)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK (0x38000U)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT (15U)
#define VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_BITS_EST_TU_SPLIT_PENALTY_MASK)
#define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT (18U)
#define VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_SHIFT)) & VPU_HEVC_SWREG35_SW_ENC_LAMDA_MOTION_SSE_MASK)
/*! @} */
/*! @name SWREG36 - inter prediction parameters2 */
/*! @{ */
#define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK (0x3U)
#define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT (0U)
/*! SW_ENC_OUTPUT_BITWIDTH_CHROMA
* 0b00..8 bit.
* 0b01..9 bit.
* 0b10..10 bit.
*/
#define VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_OUTPUT_BITWIDTH_CHROMA_MASK)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK (0x3CU)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT (2U)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_1N_CU_PENALTY_MASK)
#define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK (0x1FC0U)
#define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT (6U)
#define VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_INTER_SKIP_BIAS_MASK)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK (0x7FE000U)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT (13U)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_64_MASK)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK (0xFF800000U)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT (23U)
#define VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_SHIFT)) & VPU_HEVC_SWREG36_SW_ENC_BITS_EST_BIAS_INTRA_CU_32_MASK)
/*! @} */
/*! @name SWREG37 - SAO lambda parameter */
/*! @{ */
#define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_MASK (0xFU)
#define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_SHIFT (0U)
#define VPU_HEVC_SWREG37_SW_ENC_CHROFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_CHROFFSET_MASK)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_SHIFT (4U)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_LUMA_MASK)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_SHIFT (18U)
#define VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_SHIFT)) & VPU_HEVC_SWREG37_SW_ENC_LAMDA_SAO_CHROMA_MASK)
/*! @} */
/*! @name SWREG38 - Pre-processor configuration */
/*! @{ */
#define VPU_HEVC_SWREG38_SW_ENC_MIRROR_MASK (0x1U)
#define VPU_HEVC_SWREG38_SW_ENC_MIRROR_SHIFT (0U)
#define VPU_HEVC_SWREG38_SW_ENC_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_MIRROR_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_MIRROR_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_YFILL_MASK (0xEU)
#define VPU_HEVC_SWREG38_SW_ENC_YFILL_SHIFT (1U)
#define VPU_HEVC_SWREG38_SW_ENC_YFILL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_YFILL_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_YFILL_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_XFILL_MASK (0x30U)
#define VPU_HEVC_SWREG38_SW_ENC_XFILL_SHIFT (4U)
#define VPU_HEVC_SWREG38_SW_ENC_XFILL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_XFILL_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_XFILL_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_MASK (0xFFFC0U)
#define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_SHIFT (6U)
#define VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_ROWLENGTH_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_MASK (0xF00000U)
#define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_SHIFT (20U)
#define VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_LUMOFFSET_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK (0x3000000U)
#define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT (24U)
/*! SW_ENC_OUTPUT_BITWIDTH_LUM
* 0b00..8 bit.
* 0b01..9 bit.
* 0b10..10 bit.
*/
#define VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_OUTPUT_BITWIDTH_LUM_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_MASK (0xC000000U)
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT (26U)
/*! SW_ENC_INPUT_ROTATION
* 0b00..disabled.
* 0b01..90 degrees right.
* 0b10..90 degrees left.
* 0b11..180 degree right.
*/
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_INPUT_ROTATION_MASK)
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_MASK (0xF0000000U)
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT (28U)
/*! SW_ENC_INPUT_FORMAT
* 0b0001..YUV420SP
* 0b0010..YUYV422
* 0b0011..UYVY422
* 0b0100..RGB565
* 0b0101..RGB555
* 0b0110..RGB444
* 0b0111..RGB888
* 0b1000..RGB101010
* 0b1001..I010
* 0b1010..P010
* 0b1011..PACKED10BITPLANAR
* 0b1100..Y0L2
* 0b1101..DAHUAHEVC
* 0b1110..DAHUAH264
*/
#define VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_SHIFT)) & VPU_HEVC_SWREG38_SW_ENC_INPUT_FORMAT_MASK)
/*! @} */
/*! @name SWREG39 - Pre-processor color conversion parameters0 */
/*! @{ */
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_MASK (0xFFFFU)
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_SHIFT (0U)
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_SHIFT)) & VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFB_MASK)
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_SHIFT (16U)
#define VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_SHIFT)) & VPU_HEVC_SWREG39_SW_ENC_RGBCOEFFA_MASK)
/*! @} */
/*! @name SWREG40 - Pre-processor color conversion parameters1 */
/*! @{ */
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_MASK (0xFFFFU)
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_SHIFT (0U)
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_SHIFT)) & VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFE_MASK)
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_SHIFT (16U)
#define VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_SHIFT)) & VPU_HEVC_SWREG40_SW_ENC_RGBCOEFFC_MASK)
/*! @} */
/*! @name SWREG41 - Pre-processor color conversion parameters2 */
/*! @{ */
#define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_MASK (0x3EU)
#define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_SHIFT (1U)
#define VPU_HEVC_SWREG41_SW_ENC_BMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_BMASKMSB_MASK)
#define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_MASK (0x7C0U)
#define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_SHIFT (6U)
#define VPU_HEVC_SWREG41_SW_ENC_GMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_GMASKMSB_MASK)
#define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_MASK (0xF800U)
#define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_SHIFT (11U)
#define VPU_HEVC_SWREG41_SW_ENC_RMASKMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_RMASKMSB_MASK)
#define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_SHIFT (16U)
#define VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_SHIFT)) & VPU_HEVC_SWREG41_SW_ENC_RGBCOEFFF_MASK)
/*! @} */
/*! @name SWREG42 - Pre-processor Base address for down-scaled output */
/*! @{ */
#define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT (0U)
#define VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_SHIFT)) & VPU_HEVC_SWREG42_SW_ENC_BASESCALEDOUTLUM_MASK)
/*! @} */
/*! @name SWREG43 - Pre-processor down-scaled configuration0 */
/*! @{ */
#define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_MASK (0x3U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_SHIFT (0U)
/*! SW_ENC_SCALE_MODE
* 0b00..disabled.
* 0b01..scaling only.
* 0b10..scale+encode
*/
#define VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALE_MODE_MASK)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK (0x4U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT (2U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHMSB_MASK)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK (0x7FFF8U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT (3U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTHRATIO_MASK)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT (19U)
#define VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_SHIFT)) & VPU_HEVC_SWREG43_SW_ENC_SCALEDOUTWIDTH_MASK)
/*! @} */
/*! @name SWREG44 - Pre-processor down-scaled configuration1 */
/*! @{ */
#define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK (0x3U)
#define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_INPUT_FORMAT_MSB_MASK)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK (0x3FFFCU)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT (2U)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHTRATIO_MASK)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT (18U)
#define VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_SHIFT)) & VPU_HEVC_SWREG44_SW_ENC_SCALEDOUTHEIGHT_MASK)
/*! @} */
/*! @name SWREG45 - Pre-processor down-scaled configuration2 */
/*! @{ */
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK (0x4U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT (2U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_FORMAT_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK (0x78U)
#define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT (3U)
#define VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_NALUNITSIZE_SWAP_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK (0x80U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT (7U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDVERTICALCOPY_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK (0x100U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT (8U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDHORIZONTALCOPY_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK (0x200U)
#define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT (9U)
#define VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_VSCALE_WEIGHT_EN_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK (0xC00U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT (10U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPTOPPIXELROW_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK (0x3000U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT (12U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDSKIPLEFTPIXELCOLUMN_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK (0x7FFC000U)
#define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT (14U)
#define VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_ENCODED_CTB_NUMBER_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_MASK (0x8000000U)
#define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT (27U)
#define VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_CHROMA_SWAP_MASK)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK (0xF0000000U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT (28U)
#define VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_SHIFT)) & VPU_HEVC_SWREG45_SW_ENC_SCALEDOUT_SWAP_MASK)
/*! @} */
/*! @name SWREG46 - compressed coefficients base address for SAN module. */
/*! @{ */
#define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_SHIFT)) & VPU_HEVC_SWREG46_SW_ENC_COMPRESSEDCOEFF_BASE_MASK)
/*! @} */
/*! @name SWREG60 - Base address for recon luma compress table LSB. */
/*! @{ */
#define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG60_SW_ENC_RECON_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG62 - Base address for recon Chroma compress table LSB */
/*! @{ */
#define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG62_SW_ENC_RECON_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG64 - Base address for list 0 ref 0 luma compress table LSB. */
/*! @{ */
#define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG64_SW_ENC_L0_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG66 - Base address for list 0 ref 0 Chroma compress table LSB. */
/*! @{ */
#define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG66_SW_ENC_L0_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG72 - Base address for recon luma 4n base LSB. */
/*! @{ */
#define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_SHIFT)) & VPU_HEVC_SWREG72_SW_ENC_RECON_LUMA_4N_BASE_MASK)
/*! @} */
/*! @name SWREG74 - reference picture reconstructed list0 4n 0 */
/*! @{ */
#define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_SHIFT)) & VPU_HEVC_SWREG74_SW_ENC_REFPIC_RECON_L0_4N0_BASE_MASK)
/*! @} */
/*! @name SWREG78_H2V5 - inter me SATD lambda config 7. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT (6U)
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_15_EXPAND5BIT_MASK)
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT (19U)
#define VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_SHIFT)) & VPU_HEVC_SWREG78_H2V5_SW_ENC_LAMDA_SATD_ME_14_EXPAND5BIT_MASK)
/*! @} */
/*! @name SWREG79_H2V5 - inter me SSE lambda config 0. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG79_H2V5_SW_ENC_LAMDA_SSE_ME_0_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG81 - hardware configuation 0 */
/*! @{ */
#define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_MASK (0x7FFFFFU)
#define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_SHIFT (0U)
#define VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_SHIFT)) & VPU_HEVC_SWREG81_SW_TIMEOUT_CYCLES_MASK)
#define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK (0x800000U)
#define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT (23U)
#define VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_SHIFT)) & VPU_HEVC_SWREG81_SW_TIMEOUT_OVERRIDE_E_MASK)
#define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_MASK (0xFF000000U)
#define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_SHIFT (24U)
#define VPU_HEVC_SWREG81_SW_ENC_MAX_BURST(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_SHIFT)) & VPU_HEVC_SWREG81_SW_ENC_MAX_BURST_MASK)
/*! @} */
/*! @name SWREG82 - record hardware performance */
/*! @{ */
#define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT (0U)
#define VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_SHIFT)) & VPU_HEVC_SWREG82_SW_ENC_HW_PERFORMANCE_MASK)
/*! @} */
/*! @name SWREG83 - reference picture reconstructed list1 luma0 */
/*! @{ */
#define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT (0U)
#define VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_SHIFT)) & VPU_HEVC_SWREG83_SW_ENC_REFPIC_RECON_L1_Y0_MASK)
/*! @} */
/*! @name SWREG84 - reference picture reconstructed list1 chroma0 */
/*! @{ */
#define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT (0U)
#define VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_SHIFT)) & VPU_HEVC_SWREG84_SW_ENC_REFPIC_RECON_L1_CHROMA0_MASK)
/*! @} */
/*! @name SWREG91 - reference pictures list1 config */
/*! @{ */
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK (0x4U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT (2U)
/*! SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE
* 0b0..disable
* 0b1..enable.
*/
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_REF0_CHROMA_COMPRESSOR_ENABLE_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK (0x8U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT (3U)
/*! SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE
* 0b0..disable
* 0b1..enable.
*/
#define VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_REF0_LUMA_COMPRESSOR_ENABLE_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK (0x10U)
#define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT (4U)
#define VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_LONG_TERM_REF_PICS_PRESENT_FLAG_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK (0xC0U)
#define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT (6U)
#define VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_ACTIVE_L1_CNT_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK (0x100U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT (8U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC1_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK (0x200U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT (9U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG1_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_MASK (0xFFC00U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT (10U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC1_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK (0x100000U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT (20U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_USED_BY_CURR_PIC0_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK (0x200000U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT (21U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_LONG_TERM_FLAG0_MASK)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT (22U)
#define VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_SHIFT)) & VPU_HEVC_SWREG91_SW_ENC_L1_DELTA_POC0_MASK)
/*! @} */
/*! @name SWREG92 - reference picture reconstructed list1 4n 0 */
/*! @{ */
#define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_SHIFT)) & VPU_HEVC_SWREG92_SW_ENC_REFPIC_RECON_L1_4N0_BASE_MASK)
/*! @} */
/*! @name SWREG96 - Base address for list 1 ref 0 luma compress table LSB. */
/*! @{ */
#define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG96_SW_ENC_L1_REF0_LUMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG98 - Base address for list 1 ref 0 Chroma compress table LSB. */
/*! @{ */
#define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG98_SW_ENC_L1_REF0_CHROMA_COMPRESS_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG104 - reference picture lists modification */
/*! @{ */
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_MASK (0x1U)
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_SHIFT (0U)
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L0_MASK)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_MASK (0x1EU)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_SHIFT (1U)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L0_PIC0_MASK)
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_MASK (0x10000U)
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_SHIFT (16U)
#define VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_REF_PIC_LIST_MODI_FLAG_L1_MASK)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_MASK (0x1E0000U)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_SHIFT (17U)
#define VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LIST_ENTRY_L1_PIC0_MASK)
#define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_MASK (0x60000000U)
#define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_SHIFT (29U)
#define VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_RDO_LEVEL_MASK)
#define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_MASK (0x80000000U)
#define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_SHIFT (31U)
#define VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_SHIFT)) & VPU_HEVC_SWREG104_SW_ENC_LISTS_MODI_PRESENT_FLAG_MASK)
/*! @} */
/*! @name SWREG106 - Min picture size */
/*! @{ */
#define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_SHIFT (0U)
#define VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_SHIFT)) & VPU_HEVC_SWREG106_SW_ENC_MINPICSIZE_MASK)
/*! @} */
/*! @name SWREG107 - Max picture size */
/*! @{ */
#define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_SHIFT (0U)
#define VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_SHIFT)) & VPU_HEVC_SWREG107_SW_ENC_MAXPICSIZE_MASK)
/*! @} */
/*! @name SWREG109 - Qp delta map */
/*! @{ */
#define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT (0U)
#define VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_SHIFT)) & VPU_HEVC_SWREG109_SW_ENC_ROIMAPDELTAQPADDR_MASK)
/*! @} */
/*! @name SWREG111 - adaptive GOP configuration1 */
/*! @{ */
#define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK (0xFFFFF000U)
#define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT (12U)
#define VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_SHIFT)) & VPU_HEVC_SWREG111_SW_ENC_INTRACU8NUM_MASK)
/*! @} */
/*! @name SWREG112 - adaptive GOP configuration2 */
/*! @{ */
#define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_MASK (0xFFFFF000U)
#define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT (12U)
#define VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_SHIFT)) & VPU_HEVC_SWREG112_SW_ENC_SKIPCU8NUM_MASK)
/*! @} */
/*! @name SWREG113 - adaptive GOP configuration3 */
/*! @{ */
#define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT (0U)
#define VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_SHIFT)) & VPU_HEVC_SWREG113_SW_ENC_PBFRAME4NRDCOST_MASK)
/*! @} */
/*! @name SWREG119 - min/max lcu bits number of last picture */
/*! @{ */
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_MASK (0xFFFFU)
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_SHIFT (0U)
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_SHIFT)) & VPU_HEVC_SWREG119_SW_ENC_CTBBITSMAX_MASK)
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_SHIFT (16U)
#define VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_SHIFT)) & VPU_HEVC_SWREG119_SW_ENC_CTBBITSMIN_MASK)
/*! @} */
/*! @name SWREG120 - total bits number of all lcus of last picture not including slice header bits */
/*! @{ */
#define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT (0U)
#define VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_SHIFT)) & VPU_HEVC_SWREG120_SW_ENC_TOTALLCUBITS_MASK)
/*! @} */
/*! @name SWREG122_H2V5 - inter me SSE lambda config 1. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG122_H2V5_SW_ENC_LAMDA_SSE_ME_1_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG123_H2V5 - inter me SSE lambda config 2. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG123_H2V5_SW_ENC_LAMDA_SSE_ME_2_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG124_H2V5 - inter me SSE lambda config 3. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG124_H2V5_SW_ENC_LAMDA_SSE_ME_3_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG125 - intra SATD lambda config 0 */
/*! @{ */
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT (4U)
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_SHIFT)) & VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_1_MASK)
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT (18U)
#define VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_SHIFT)) & VPU_HEVC_SWREG125_SW_ENC_INTRA_SATD_LAMDA_0_MASK)
/*! @} */
/*! @name SWREG126 - intra SATD lambda config 1 */
/*! @{ */
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT (4U)
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_SHIFT)) & VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_3_MASK)
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT (18U)
#define VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_SHIFT)) & VPU_HEVC_SWREG126_SW_ENC_INTRA_SATD_LAMDA_2_MASK)
/*! @} */
/*! @name SWREG127 - intra SATD lambda config 2 */
/*! @{ */
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT (4U)
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_SHIFT)) & VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_5_MASK)
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT (18U)
#define VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_SHIFT)) & VPU_HEVC_SWREG127_SW_ENC_INTRA_SATD_LAMDA_4_MASK)
/*! @} */
/*! @name SWREG128 - intra SATD lambda config 3 */
/*! @{ */
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT (4U)
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_SHIFT)) & VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_7_MASK)
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT (18U)
#define VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_SHIFT)) & VPU_HEVC_SWREG128_SW_ENC_INTRA_SATD_LAMDA_6_MASK)
/*! @} */
/*! @name SWREG129 - intra SATD lambda config 4 */
/*! @{ */
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT (4U)
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_SHIFT)) & VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_9_MASK)
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT (18U)
#define VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_SHIFT)) & VPU_HEVC_SWREG129_SW_ENC_INTRA_SATD_LAMDA_8_MASK)
/*! @} */
/*! @name SWREG130 - intra SATD lambda config 5 */
/*! @{ */
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT (4U)
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_SHIFT)) & VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_11_MASK)
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT (18U)
#define VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_SHIFT)) & VPU_HEVC_SWREG130_SW_ENC_INTRA_SATD_LAMDA_10_MASK)
/*! @} */
/*! @name SWREG131 - intra SATD lambda config 6 */
/*! @{ */
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT (4U)
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_SHIFT)) & VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_13_MASK)
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT (18U)
#define VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_SHIFT)) & VPU_HEVC_SWREG131_SW_ENC_INTRA_SATD_LAMDA_12_MASK)
/*! @} */
/*! @name SWREG132 - intra SATD lambda config 7 */
/*! @{ */
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT (4U)
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_SHIFT)) & VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_15_MASK)
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT (18U)
#define VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_SHIFT)) & VPU_HEVC_SWREG132_SW_ENC_INTRA_SATD_LAMDA_14_MASK)
/*! @} */
/*! @name SWREG133 - SSE devide 256 */
/*! @{ */
#define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_SHIFT (0U)
#define VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_SHIFT)) & VPU_HEVC_SWREG133_SW_ENC_SSE_DIV_256_MASK)
/*! @} */
/*! @name SWREG134 - noise reduction */
/*! @{ */
#define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_MASK (0xFFFFU)
#define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_SHIFT (0U)
#define VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NR_MBNUM_INVERT_REG_MASK)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_MASK (0x3F000000U)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_SHIFT (24U)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NOISE_LOW_MASK)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_MASK (0xC0000000U)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_SHIFT (30U)
#define VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_SHIFT)) & VPU_HEVC_SWREG134_SW_ENC_NOISE_REDUCTION_ENABLE_MASK)
/*! @} */
/*! @name SWREG135 - noise reduction 1 */
/*! @{ */
#define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_MASK (0x3FFFFE0U)
#define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_SHIFT (5U)
#define VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_SHIFT)) & VPU_HEVC_SWREG135_SW_ENC_THRESH_SIGMA_CUR_MASK)
#define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_MASK (0xFC000000U)
#define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_SHIFT (26U)
#define VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_SHIFT)) & VPU_HEVC_SWREG135_SW_ENC_SLICEQP_PREV_MASK)
/*! @} */
/*! @name SWREG136 - noise reduction 2 */
/*! @{ */
#define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_MASK (0xFFFFU)
#define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_SHIFT (0U)
#define VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_SHIFT)) & VPU_HEVC_SWREG136_SW_ENC_FRAME_SIGMA_CALCED_MASK)
#define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_SHIFT (16U)
#define VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_SHIFT)) & VPU_HEVC_SWREG136_SW_ENC_SIGMA_CUR_MASK)
/*! @} */
/*! @name SWREG137 - noise reduction 3 */
/*! @{ */
#define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_SHIFT (11U)
#define VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_SHIFT)) & VPU_HEVC_SWREG137_SW_ENC_THRESH_SIGMA_CALCED_MASK)
/*! @} */
/*! @name SWREG138_H2V5 - inter me SSE lambda config 4. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG138_H2V5_SW_ENC_LAMDA_SSE_ME_4_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG139_H2V5 - inter me SSE lambda config 5. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG139_H2V5_SW_ENC_LAMDA_SSE_ME_5_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG140_H2V5 - inter me SSE lambda config 6. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG140_H2V5_SW_ENC_LAMDA_SSE_ME_6_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG141_H2V5 - inter me SSE lambda config 7. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG141_H2V5_SW_ENC_LAMDA_SSE_ME_7_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG142_H2V5 - inter me SSE lambda config 8. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG142_H2V5_SW_ENC_LAMDA_SSE_ME_8_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG143_H2V5 - inter me SSE lambda config 9. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG143_H2V5_SW_ENC_LAMDA_SSE_ME_9_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG144_H2V5 - inter me SSE lambda config 10. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG144_H2V5_SW_ENC_LAMDA_SSE_ME_10_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG145_H2V5 - inter me SSE lambda config 11. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG145_H2V5_SW_ENC_LAMDA_SSE_ME_11_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG146_H2V5 - inter me SSE lambda config 12. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG146_H2V5_SW_ENC_LAMDA_SSE_ME_12_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG147_H2V5 - inter me SSE lambda config 13. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG147_H2V5_SW_ENC_LAMDA_SSE_ME_13_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG148_H2V5 - inter me SSE lambda config 14. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG148_H2V5_SW_ENC_LAMDA_SSE_ME_14_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG149_H2V5 - inter me SSE lambda config 15. For H2V5 or later version. */
/*! @{ */
#define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT (11U)
#define VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_SHIFT)) & VPU_HEVC_SWREG149_H2V5_SW_ENC_LAMDA_SSE_ME_15_EXPAND6BIT_MASK)
/*! @} */
/*! @name SWREG150 - inter me SATD lambda config 8 */
/*! @{ */
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT (6U)
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_SHIFT)) & VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_17_MASK)
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT (19U)
#define VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_SHIFT)) & VPU_HEVC_SWREG150_SW_ENC_LAMDA_SATD_ME_16_MASK)
/*! @} */
/*! @name SWREG151 - inter me SATD lambda config 9 */
/*! @{ */
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT (6U)
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_SHIFT)) & VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_19_MASK)
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT (19U)
#define VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_SHIFT)) & VPU_HEVC_SWREG151_SW_ENC_LAMDA_SATD_ME_18_MASK)
/*! @} */
/*! @name SWREG152 - inter me SATD lambda config 10 */
/*! @{ */
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT (6U)
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_SHIFT)) & VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_21_MASK)
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT (19U)
#define VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_SHIFT)) & VPU_HEVC_SWREG152_SW_ENC_LAMDA_SATD_ME_20_MASK)
/*! @} */
/*! @name SWREG153 - inter me SATD lambda config 11 */
/*! @{ */
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT (6U)
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_SHIFT)) & VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_23_MASK)
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT (19U)
#define VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_SHIFT)) & VPU_HEVC_SWREG153_SW_ENC_LAMDA_SATD_ME_22_MASK)
/*! @} */
/*! @name SWREG154 - inter me SATD lambda config 12 */
/*! @{ */
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT (6U)
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_SHIFT)) & VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_25_MASK)
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT (19U)
#define VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_SHIFT)) & VPU_HEVC_SWREG154_SW_ENC_LAMDA_SATD_ME_24_MASK)
/*! @} */
/*! @name SWREG155 - inter me SATD lambda config 13 */
/*! @{ */
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT (6U)
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_SHIFT)) & VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_27_MASK)
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT (19U)
#define VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_SHIFT)) & VPU_HEVC_SWREG155_SW_ENC_LAMDA_SATD_ME_26_MASK)
/*! @} */
/*! @name SWREG156 - inter me SATD lambda config 14 */
/*! @{ */
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT (6U)
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_SHIFT)) & VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_29_MASK)
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT (19U)
#define VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_SHIFT)) & VPU_HEVC_SWREG156_SW_ENC_LAMDA_SATD_ME_28_MASK)
/*! @} */
/*! @name SWREG157 - inter me SATD lambda config 15 */
/*! @{ */
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK (0x7FFC0U)
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT (6U)
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_SHIFT)) & VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_31_MASK)
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK (0xFFF80000U)
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT (19U)
#define VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_SHIFT)) & VPU_HEVC_SWREG157_SW_ENC_LAMDA_SATD_ME_30_MASK)
/*! @} */
/*! @name SWREG158 - inter me SSE lambda config 16 */
/*! @{ */
#define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT (11U)
#define VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_SHIFT)) & VPU_HEVC_SWREG158_SW_ENC_LAMDA_SSE_ME_16_MASK)
/*! @} */
/*! @name SWREG159 - inter me SSE lambda config 17 */
/*! @{ */
#define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT (11U)
#define VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_SHIFT)) & VPU_HEVC_SWREG159_SW_ENC_LAMDA_SSE_ME_17_MASK)
/*! @} */
/*! @name SWREG160 - inter me SSE lambda config 18 */
/*! @{ */
#define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT (11U)
#define VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_SHIFT)) & VPU_HEVC_SWREG160_SW_ENC_LAMDA_SSE_ME_18_MASK)
/*! @} */
/*! @name SWREG161 - inter me SSE lambda config 19 */
/*! @{ */
#define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT (11U)
#define VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_SHIFT)) & VPU_HEVC_SWREG161_SW_ENC_LAMDA_SSE_ME_19_MASK)
/*! @} */
/*! @name SWREG162 - inter me SSE lambda config 20 */
/*! @{ */
#define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT (11U)
#define VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_SHIFT)) & VPU_HEVC_SWREG162_SW_ENC_LAMDA_SSE_ME_20_MASK)
/*! @} */
/*! @name SWREG163 - inter me SSE lambda config 21 */
/*! @{ */
#define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT (11U)
#define VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_SHIFT)) & VPU_HEVC_SWREG163_SW_ENC_LAMDA_SSE_ME_21_MASK)
/*! @} */
/*! @name SWREG164 - inter me SSE lambda config 22 */
/*! @{ */
#define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT (11U)
#define VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_SHIFT)) & VPU_HEVC_SWREG164_SW_ENC_LAMDA_SSE_ME_22_MASK)
/*! @} */
/*! @name SWREG165 - inter me SSE lambda config 23 */
/*! @{ */
#define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT (11U)
#define VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_SHIFT)) & VPU_HEVC_SWREG165_SW_ENC_LAMDA_SSE_ME_23_MASK)
/*! @} */
/*! @name SWREG166 - inter me SSE lambda config 24 */
/*! @{ */
#define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT (11U)
#define VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_SHIFT)) & VPU_HEVC_SWREG166_SW_ENC_LAMDA_SSE_ME_24_MASK)
/*! @} */
/*! @name SWREG167 - inter me SSE lambda config 25 */
/*! @{ */
#define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT (11U)
#define VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_SHIFT)) & VPU_HEVC_SWREG167_SW_ENC_LAMDA_SSE_ME_25_MASK)
/*! @} */
/*! @name SWREG168 - inter me SSE lambda config 26 */
/*! @{ */
#define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT (11U)
#define VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_SHIFT)) & VPU_HEVC_SWREG168_SW_ENC_LAMDA_SSE_ME_26_MASK)
/*! @} */
/*! @name SWREG169 - inter me SSE lambda config 27 */
/*! @{ */
#define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT (11U)
#define VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_SHIFT)) & VPU_HEVC_SWREG169_SW_ENC_LAMDA_SSE_ME_27_MASK)
/*! @} */
/*! @name SWREG172 - inter me SSE lambda config 30 */
/*! @{ */
#define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK (0x1FU)
#define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT (0U)
#define VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_COMPLEXITY_OFFSET_MASK)
#define VPU_HEVC_SWREG172_SW_ENC_QP_MIN_MASK (0x7E0U)
#define VPU_HEVC_SWREG172_SW_ENC_QP_MIN_SHIFT (5U)
#define VPU_HEVC_SWREG172_SW_ENC_QP_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_QP_MIN_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_QP_MIN_MASK)
#define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT (11U)
#define VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_SHIFT)) & VPU_HEVC_SWREG172_SW_ENC_LAMDA_SSE_ME_30_MASK)
/*! @} */
/*! @name SWREG173 - inter me SSE lambda config 31 */
/*! @{ */
#define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK (0xFU)
#define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT (0U)
#define VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_RC_QPDELTA_RANGE_MASK)
#define VPU_HEVC_SWREG173_SW_ENC_QP_MAX_MASK (0x7E0U)
#define VPU_HEVC_SWREG173_SW_ENC_QP_MAX_SHIFT (5U)
#define VPU_HEVC_SWREG173_SW_ENC_QP_MAX(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_QP_MAX_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_QP_MAX_MASK)
#define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT (11U)
#define VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_SHIFT)) & VPU_HEVC_SWREG173_SW_ENC_LAMDA_SSE_ME_31_MASK)
/*! @} */
/*! @name SWREG174 - intra SATD lambda config 8 */
/*! @{ */
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT (4U)
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_SHIFT)) & VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_17_MASK)
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT (18U)
#define VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_SHIFT)) & VPU_HEVC_SWREG174_SW_ENC_INTRA_SATD_LAMDA_16_MASK)
/*! @} */
/*! @name SWREG175 - intra SATD lambda config 9 */
/*! @{ */
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT (4U)
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_SHIFT)) & VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_19_MASK)
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT (18U)
#define VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_SHIFT)) & VPU_HEVC_SWREG175_SW_ENC_INTRA_SATD_LAMDA_18_MASK)
/*! @} */
/*! @name SWREG176 - intra SATD lambda config 10 */
/*! @{ */
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT (4U)
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_SHIFT)) & VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_21_MASK)
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT (18U)
#define VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_SHIFT)) & VPU_HEVC_SWREG176_SW_ENC_INTRA_SATD_LAMDA_20_MASK)
/*! @} */
/*! @name SWREG177 - intra SATD lambda config 11 */
/*! @{ */
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT (4U)
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_SHIFT)) & VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_23_MASK)
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT (18U)
#define VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_SHIFT)) & VPU_HEVC_SWREG177_SW_ENC_INTRA_SATD_LAMDA_22_MASK)
/*! @} */
/*! @name SWREG178 - intra SATD lambda config 12 */
/*! @{ */
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT (4U)
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_SHIFT)) & VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_25_MASK)
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT (18U)
#define VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_SHIFT)) & VPU_HEVC_SWREG178_SW_ENC_INTRA_SATD_LAMDA_24_MASK)
/*! @} */
/*! @name SWREG179 - intra SATD lambda config 13 */
/*! @{ */
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT (4U)
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_SHIFT)) & VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_27_MASK)
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT (18U)
#define VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_SHIFT)) & VPU_HEVC_SWREG179_SW_ENC_INTRA_SATD_LAMDA_26_MASK)
/*! @} */
/*! @name SWREG180 - intra SATD lambda config 14 */
/*! @{ */
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT (4U)
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_SHIFT)) & VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_29_MASK)
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT (18U)
#define VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_SHIFT)) & VPU_HEVC_SWREG180_SW_ENC_INTRA_SATD_LAMDA_28_MASK)
/*! @} */
/*! @name SWREG181 - intra SATD lambda config 15 */
/*! @{ */
#define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK (0xCU)
#define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT (2U)
/*! SW_ENC_RC_BLOCK_SIZE
* 0b00..64x64.
* 0b01..32x32.
* 0b10..16x16
*/
#define VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_RC_BLOCK_SIZE_MASK)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT (4U)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_31_MASK)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT (18U)
#define VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_SHIFT)) & VPU_HEVC_SWREG181_SW_ENC_INTRA_SATD_LAMDA_30_MASK)
/*! @} */
/*! @name SWREG182 - qp fractional part */
/*! @{ */
#define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK (0xFFFFU)
#define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT (0U)
#define VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_SHIFT)) & VPU_HEVC_SWREG182_SW_ENC_QP_DELTA_GAIN_MASK)
#define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT (16U)
#define VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_SHIFT)) & VPU_HEVC_SWREG182_SW_ENC_QP_FRACTIONAL_MASK)
/*! @} */
/*! @name SWREG183 - qp sum */
/*! @{ */
#define VPU_HEVC_SWREG183_SW_ENC_QP_SUM_MASK (0xFFFFFFC0U)
#define VPU_HEVC_SWREG183_SW_ENC_QP_SUM_SHIFT (6U)
#define VPU_HEVC_SWREG183_SW_ENC_QP_SUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG183_SW_ENC_QP_SUM_SHIFT)) & VPU_HEVC_SWREG183_SW_ENC_QP_SUM_MASK)
/*! @} */
/*! @name SWREG184 - qp num */
/*! @{ */
#define VPU_HEVC_SWREG184_SW_ENC_QP_NUM_MASK (0xFFFFF000U)
#define VPU_HEVC_SWREG184_SW_ENC_QP_NUM_SHIFT (12U)
#define VPU_HEVC_SWREG184_SW_ENC_QP_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG184_SW_ENC_QP_NUM_SHIFT)) & VPU_HEVC_SWREG184_SW_ENC_QP_NUM_MASK)
/*! @} */
/*! @name SWREG185 - picture complexity. Timeout cycles MSB. */
/*! @{ */
#define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK (0x1FFU)
#define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_SHIFT)) & VPU_HEVC_SWREG185_SW_TIMEOUT_CYCLES_MSB_MASK)
#define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK (0xFFFFFE00U)
#define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT (9U)
#define VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_SHIFT)) & VPU_HEVC_SWREG185_SW_ENC_PIC_COMPLEXITY_MASK)
/*! @} */
/*! @name SWREG186 - Base address for CU information table LSB */
/*! @{ */
#define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_SHIFT)) & VPU_HEVC_SWREG186_SW_ENC_CU_INFORMATION_TABLE_BASE_MASK)
/*! @} */
/*! @name SWREG188 - Base address for CU information LSB */
/*! @{ */
#define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_SHIFT)) & VPU_HEVC_SWREG188_SW_ENC_CU_INFORMATION_BASE_MASK)
/*! @} */
/*! @name SWREG190 - Long-term reference pictures config */
/*! @{ */
#define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK (0xC0000000U)
#define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT (30U)
#define VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_SHIFT)) & VPU_HEVC_SWREG190_SW_ENC_NUM_LONG_TERM_PICS_MASK)
/*! @} */
/*! @name SWREG191 - Temporal scalable config */
/*! @{ */
#define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK (0xFFFFU)
#define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT (0U)
#define VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_SLICE_HEADER_SIZE_MASK)
#define VPU_HEVC_SWREG191_SW_ENC_PPS_ID_MASK (0x7E0000U)
#define VPU_HEVC_SWREG191_SW_ENC_PPS_ID_SHIFT (17U)
#define VPU_HEVC_SWREG191_SW_ENC_PPS_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_PPS_ID_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_PPS_ID_MASK)
#define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK (0x3800000U)
#define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT (23U)
#define VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_NUH_TEMPORAL_ID_MASK)
#define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK (0xFC000000U)
#define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT (26U)
#define VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_SHIFT)) & VPU_HEVC_SWREG191_SW_ENC_NAL_UNIT_TYPE_MASK)
/*! @} */
/*! @name SWREG195 - register extension for ctu_size=16 */
/*! @{ */
#define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK (0xCU)
#define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT (2U)
#define VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_PIC_WIDTH_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK (0x10U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT (4U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_BOTTOM_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK (0x20U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT (5U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_TOP_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK (0x40U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT (6U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_RIGHT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK (0x80U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT (7U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI2_LEFT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK (0x100U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT (8U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_BOTTOM_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK (0x200U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT (9U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_TOP_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK (0x400U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT (10U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_RIGHT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK (0x800U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT (11U)
#define VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ROI1_LEFT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK (0x1000U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT (12U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_BOTTOM_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK (0x2000U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT (13U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_TOP_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK (0x4000U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT (14U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_RIGHT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK (0x8000U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT (15U)
#define VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_INTRA_AREA_LEFT_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK (0xF0000U)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT (16U)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_CIR_INTERVAL_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_MASK (0xF00000U)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_SHIFT (20U)
#define VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_CIR_START_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK (0x3000000U)
#define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT (24U)
#define VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_SLICE_SIZE_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK (0xC000000U)
#define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT (26U)
#define VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_NUM_SLICES_READY_MSB_MASK)
#define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK (0xF0000000U)
#define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT (28U)
#define VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_SHIFT)) & VPU_HEVC_SWREG195_SW_ENC_ENCODED_CTB_NUMBER_MSB_MASK)
/*! @} */
/*! @name SWREG196 - Low Latency Controls */
/*! @{ */
#define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_MASK (0x3FFU)
#define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT (0U)
#define VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_SHIFT)) & VPU_HEVC_SWREG196_SW_CTB_ROW_WR_PTR_MASK)
#define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_MASK (0xFFC00U)
#define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT (10U)
#define VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_SHIFT)) & VPU_HEVC_SWREG196_SW_CTB_ROW_RD_PTR_MASK)
#define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK (0x1FF00000U)
#define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT (20U)
#define VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_SHIFT)) & VPU_HEVC_SWREG196_SW_NUM_CTB_ROWS_PER_SYNC_MASK)
#define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK (0x20000000U)
#define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT (29U)
#define VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_INPUT_BUF_LOOPBACK_EN_MASK)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_MASK (0x40000000U)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_SHIFT (30U)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_LOW_LATENCY_EN_MASK)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK (0x80000000U)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT (31U)
#define VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_SHIFT)) & VPU_HEVC_SWREG196_SW_LOW_LATENCY_HW_SYNC_EN_MASK)
/*! @} */
/*! @name SWREG197 - Delta POC extension */
/*! @{ */
#define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK (0xFFCU)
#define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT (2U)
#define VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L1_DELTA_POC0_MSB_MASK)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK (0x3FF000U)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT (12U)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC1_MSB_MASK)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT (22U)
#define VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_SHIFT)) & VPU_HEVC_SWREG197_SW_ENC_L0_DELTA_POC0_MSB_MASK)
/*! @} */
/*! @name SWREG198 - Long Term Reference Control */
/*! @{ */
#define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT (22U)
#define VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_SHIFT)) & VPU_HEVC_SWREG198_SW_ENC_L1_DELTA_POC1_MSB_MASK)
/*! @} */
/*! @name SWREG199 - Hash Code Control */
/*! @{ */
#define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK (0x1U)
#define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT (0U)
/*! SW_ENC_OSD_ALPHABLEND_ENABLE
* 0b0..disable.
* 0b1..enable.
*/
#define VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_OSD_ALPHABLEND_ENABLE_MASK)
#define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_MASK (0x6U)
#define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_SHIFT (1U)
#define VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_HASH_OFFSET_MASK)
#define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_MASK (0x18U)
#define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_SHIFT (3U)
/*! SW_ENC_HASH_TYPE
* 0b00..none.
* 0b01..crc32.
* 0b10..checksum32
*/
#define VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_SHIFT)) & VPU_HEVC_SWREG199_SW_ENC_HASH_TYPE_MASK)
/*! @} */
/*! @name SWREG200 - Hash Code Value */
/*! @{ */
#define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_SHIFT (0U)
#define VPU_HEVC_SWREG200_SW_ENC_HASH_VAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_SHIFT)) & VPU_HEVC_SWREG200_SW_ENC_HASH_VAL_MASK)
/*! @} */
/*! @name SWREG201 - Background SKIP Control 0 */
/*! @{ */
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_MASK (0xFFU)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_SHIFT (0U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR3_MASK)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_MASK (0xFF00U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_SHIFT (8U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR2_MASK)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_MASK (0xFF0000U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_SHIFT (16U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR1_MASK)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_MASK (0xFF000000U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_SHIFT (24U)
#define VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_SHIFT)) & VPU_HEVC_SWREG201_SW_ENC_MEAN_THR0_MASK)
/*! @} */
/*! @name SWREG202 - Background SKIP Control 1 */
/*! @{ */
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_MASK (0xFFFFU)
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_SHIFT (0U)
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_SHIFT)) & VPU_HEVC_SWREG202_SW_ENC_THR_DC_CHROMA_8X8_MASK)
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_SHIFT (16U)
#define VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_SHIFT)) & VPU_HEVC_SWREG202_SW_ENC_THR_DC_LUM_8X8_MASK)
/*! @} */
/*! @name SWREG203 - Background SKIP Control 2 */
/*! @{ */
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_MASK (0xFFFFU)
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_SHIFT (0U)
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_SHIFT)) & VPU_HEVC_SWREG203_SW_ENC_THR_DC_CHROMA_16X16_MASK)
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_SHIFT (16U)
#define VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_SHIFT)) & VPU_HEVC_SWREG203_SW_ENC_THR_DC_LUM_16X16_MASK)
/*! @} */
/*! @name SWREG204 - Background SKIP Control 3 */
/*! @{ */
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_MASK (0xFFFFU)
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_SHIFT (0U)
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_SHIFT)) & VPU_HEVC_SWREG204_SW_ENC_THR_DC_CHROMA_32X32_MASK)
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_SHIFT (16U)
#define VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_SHIFT)) & VPU_HEVC_SWREG204_SW_ENC_THR_DC_LUM_32X32_MASK)
/*! @} */
/*! @name SWREG205 - Background SKIP Control 4 */
/*! @{ */
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_MASK (0xFFFFU)
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_SHIFT (0U)
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_SHIFT)) & VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_CHROMA_8X8_MASK)
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_SHIFT (16U)
#define VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_SHIFT)) & VPU_HEVC_SWREG205_SW_ENC_THR_AC_NUM_LUM_8X8_MASK)
/*! @} */
/*! @name SWREG206 - Background SKIP Control 5 */
/*! @{ */
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_MASK (0xFFFFU)
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_SHIFT (0U)
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_SHIFT)) & VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_CHROMA_16X16_MASK)
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_SHIFT (16U)
#define VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_SHIFT)) & VPU_HEVC_SWREG206_SW_ENC_THR_AC_NUM_LUM_16X16_MASK)
/*! @} */
/*! @name SWREG207 - Background SKIP Control 6 */
/*! @{ */
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_MASK (0xFFFFU)
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_SHIFT (0U)
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_SHIFT)) & VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_CHROMA_32X32_MASK)
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_SHIFT (16U)
#define VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_SHIFT)) & VPU_HEVC_SWREG207_SW_ENC_THR_AC_NUM_LUM_32X32_MASK)
/*! @} */
/*! @name SWREG208 - Background SKIP Control 7 */
/*! @{ */
#define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK (0x8U)
#define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT (3U)
#define VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_SKIP_MAP_ENABLE_MASK)
#define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_MASK (0x1FF0U)
#define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT (4U)
#define VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_IPCM1_LEFT_MASK)
#define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_MASK (0x2000U)
#define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_SHIFT (13U)
#define VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_ENABLE_SMART_MASK)
#define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK (0xFC000U)
#define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT (14U)
#define VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_FOREGROUND_PIXEL_THX_MASK)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPC_MASK (0x3F00000U)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPC_SHIFT (20U)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPC_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPC_MASK)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK (0xFC000000U)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT (26U)
#define VPU_HEVC_SWREG208_SW_ENC_MDQPY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG208_SW_ENC_MDQPY_SHIFT)) & VPU_HEVC_SWREG208_SW_ENC_MDQPY_MASK)
/*! @} */
/*! @name SWREG209 - IPCM Control 0 */
/*! @{ */
#define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK (0x8U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT (3U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM_MAP_ENABLE_MASK)
#define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK (0x10U)
#define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT (4U)
#define VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_PCM_FILTER_DISABLE_MASK)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK (0x3FE0U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT (5U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_BOTTOM_MASK)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_MASK (0x7FC000U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_SHIFT (14U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_TOP_MASK)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_MASK (0xFF800000U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT (23U)
#define VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_SHIFT)) & VPU_HEVC_SWREG209_SW_ENC_IPCM1_RIGHT_MASK)
/*! @} */
/*! @name SWREG210 - IPCM Control 1 */
/*! @{ */
#define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_MASK (0xFF8U)
#define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT (3U)
#define VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_SHIFT)) & VPU_HEVC_SWREG210_SW_ENC_IPCM2_LEFT_MASK)
/*! @} */
/*! @name SWREG211 - IPCM Control 2 */
/*! @{ */
#define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_MASK (0xFF8U)
#define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT (3U)
#define VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_SHIFT)) & VPU_HEVC_SWREG211_SW_ENC_IPCM2_RIGHT_MASK)
/*! @} */
/*! @name SWREG212 - IPCM Control 3 */
/*! @{ */
#define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_MASK (0xFF8U)
#define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_SHIFT (3U)
#define VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_SHIFT)) & VPU_HEVC_SWREG212_SW_ENC_IPCM2_TOP_MASK)
/*! @} */
/*! @name SWREG213 - IPCM Control 4 */
/*! @{ */
#define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK (0x3FE0U)
#define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT (5U)
#define VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_SHIFT)) & VPU_HEVC_SWREG213_SW_ENC_IPCM2_BOTTOM_MASK)
/*! @} */
/*! @name SWREG214 - HW synthesis config register 2, read-only */
/*! @{ */
#define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_MASK (0x1C000000U)
#define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT (26U)
/*! SW_ENC_HWROIMAPVERSION
* 0b000..4 bit per pixel.
* 0b001..8 bit per pixel
*/
#define VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWROIMAPVERSION_MASK)
#define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_MASK (0x20000000U)
#define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_SHIFT (29U)
/*! SW_ENC_HWINTRATU32SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWINTRATU32SUPPORT_MASK)
#define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK (0x40000000U)
#define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT (30U)
/*! SW_ENC_HWABSQPSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWABSQPSUPPORT_MASK)
#define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK (0x80000000U)
#define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT (31U)
/*! SW_ENC_HWLJPEGSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_SHIFT)) & VPU_HEVC_SWREG214_SW_ENC_HWLJPEGSUPPORT_MASK)
/*! @} */
/*! @name SWREG215 - AXI Information 0 */
/*! @{ */
#define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_SHIFT (0U)
#define VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_SHIFT)) & VPU_HEVC_SWREG215_SW_ENC_TOTALARLEN_MASK)
/*! @} */
/*! @name SWREG216 - AXI Information 1 */
/*! @{ */
#define VPU_HEVC_SWREG216_SW_ENC_TOTALR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG216_SW_ENC_TOTALR_SHIFT (0U)
#define VPU_HEVC_SWREG216_SW_ENC_TOTALR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG216_SW_ENC_TOTALR_SHIFT)) & VPU_HEVC_SWREG216_SW_ENC_TOTALR_MASK)
/*! @} */
/*! @name SWREG217 - AXI Information 2 */
/*! @{ */
#define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT (0U)
#define VPU_HEVC_SWREG217_SW_ENC_TOTALAR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG217_SW_ENC_TOTALAR_SHIFT)) & VPU_HEVC_SWREG217_SW_ENC_TOTALAR_MASK)
/*! @} */
/*! @name SWREG218 - AXI Information 3 */
/*! @{ */
#define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_SHIFT (0U)
#define VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_SHIFT)) & VPU_HEVC_SWREG218_SW_ENC_TOTALRLAST_MASK)
/*! @} */
/*! @name SWREG219 - AXI Information 4 */
/*! @{ */
#define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_SHIFT (0U)
#define VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_SHIFT)) & VPU_HEVC_SWREG219_SW_ENC_TOTALAWLEN_MASK)
/*! @} */
/*! @name SWREG220 - AXI Information 5 */
/*! @{ */
#define VPU_HEVC_SWREG220_SW_ENC_TOTALW_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG220_SW_ENC_TOTALW_SHIFT (0U)
#define VPU_HEVC_SWREG220_SW_ENC_TOTALW(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG220_SW_ENC_TOTALW_SHIFT)) & VPU_HEVC_SWREG220_SW_ENC_TOTALW_MASK)
/*! @} */
/*! @name SWREG221 - AXI Information 6 */
/*! @{ */
#define VPU_HEVC_SWREG221_SW_ENC_TOTALAW_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG221_SW_ENC_TOTALAW_SHIFT (0U)
#define VPU_HEVC_SWREG221_SW_ENC_TOTALAW(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG221_SW_ENC_TOTALAW_SHIFT)) & VPU_HEVC_SWREG221_SW_ENC_TOTALAW_MASK)
/*! @} */
/*! @name SWREG222 - AXI Information 7 */
/*! @{ */
#define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT (0U)
#define VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_SHIFT)) & VPU_HEVC_SWREG222_SW_ENC_TOTALWLAST_MASK)
/*! @} */
/*! @name SWREG223 - AXI Information 8 */
/*! @{ */
#define VPU_HEVC_SWREG223_SW_ENC_TOTALB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG223_SW_ENC_TOTALB_SHIFT (0U)
#define VPU_HEVC_SWREG223_SW_ENC_TOTALB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG223_SW_ENC_TOTALB_SHIFT)) & VPU_HEVC_SWREG223_SW_ENC_TOTALB_MASK)
/*! @} */
/*! @name SWREG224 - control register 4 */
/*! @{ */
#define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK (0x3FFU)
#define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT (0U)
#define VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CB_CONST_PIXEL_MASK)
#define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK (0xFFC00U)
#define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT (10U)
#define VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CR_CONST_PIXEL_MASK)
#define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_MASK (0x100000U)
#define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT (20U)
/*! SW_ENC_SKIPFRAME_EN
* 0b0..no.
* 0b1..yes
*/
#define VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_SKIPFRAME_EN_MASK)
#define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_MASK (0x200000U)
#define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_SHIFT (21U)
/*! SW_ENC_SSIM_EN
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_HEVC_SWREG224_SW_ENC_SSIM_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_SSIM_EN_MASK)
#define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK (0x80000000U)
#define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT (31U)
/*! SW_ENC_CHROMA_CONST_EN
* 0b0..no.
* 0b1..yes.
*/
#define VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_SHIFT)) & VPU_HEVC_SWREG224_SW_ENC_CHROMA_CONST_EN_MASK)
/*! @} */
/*! @name SWREG225 - Tile Control */
/*! @{ */
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK (0x1C0U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT (6U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_QPDELTA_VER_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK (0xE00U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT (9U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_VER_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK (0x1000U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT (12U)
/*! SW_ENC_ROIMAP_CUCTRL_ENABLE
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_ENABLE_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK (0x2000U)
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT (13U)
/*! SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE
* 0b0..Disable.
* 0b1..Enable
*/
#define VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_ROIMAP_CUCTRL_INDEX_ENABLE_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_MASK (0x4000U)
#define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_SHIFT (14U)
/*! SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG
* 0b0..disabled.
* 0b1..enabled.
*/
#define VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_MASK (0x8000U)
#define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_SHIFT (15U)
/*! SW_ENC_TILES_ENABLED_FLAG
* 0b0..disabled.
* 0b1..enabled.
*/
#define VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_TILES_ENABLED_FLAG_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_MASK (0xFF0000U)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_SHIFT (16U)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_ROWS_MASK)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_MASK (0xFF000000U)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_SHIFT (24U)
#define VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_SHIFT)) & VPU_HEVC_SWREG225_SW_ENC_NUM_TILE_COLUMNS_MASK)
/*! @} */
/*! @name SWREG226 - HW synthesis config register 3, read-only */
/*! @{ */
#define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_MASK (0x1U)
#define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_SHIFT (0U)
/*! SW_ENC_HWDYNAMICMAXTUSIZE
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWDYNAMICMAXTUSIZE_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_MASK (0x2U)
#define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT (1U)
/*! SW_ENC_HWIFRAMEONLY
* 0b0..support I/P/B frame.
* 0b1..only support I frame
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWIFRAMEONLY_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK (0x4U)
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT (2U)
/*! SW_ENC_HWSTREAMSEGMENTSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSTREAMSEGMENTSUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK (0x8U)
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT (3U)
/*! SW_ENC_HWSTREAMBUFCHAIN
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSTREAMBUFCHAIN_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK (0x10U)
#define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT (4U)
/*! SW_ENC_HWINLOOPDSRATIO
* 0b0..1:1
* 0b1..1:2
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWINLOOPDSRATIO_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK (0x20U)
#define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT (5U)
/*! SW_ENC_HWMULTIPASSSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWMULTIPASSSUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK (0x40U)
#define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT (6U)
/*! SW_ENC_HWRDOQSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWRDOQSUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK (0x180U)
#define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT (7U)
/*! SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE
* 0b00..64.
* 0b01..128.
* 0b10..192.
* 0b11..256
*/
#define VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_BFRAME_ME4N_HOR_SEARCHRANGE_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK (0x200U)
#define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT (9U)
#define VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWROI8SUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_MASK (0x400U)
#define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT (10U)
/*! SW_ENC_HWGMVSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWGMVSUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK (0x800U)
#define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT (11U)
/*! SW_ENC_HWJPEG422SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWJPEG422SUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_MASK (0x7000U)
#define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT (12U)
#define VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWCTBRCVERSION_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK (0x1F8000U)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT (15U)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_H264_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK (0x7E00000U)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT (21U)
#define VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_ME_VERT_SEARCHRANGE_HEVC_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_MASK (0x38000000U)
#define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT (27U)
#define VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWCUINFORVERSION_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK (0x40000000U)
#define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT (30U)
/*! SW_ENC_HWP010REFSUPPORT
* 0b1..P010 tile raster format.
* 0b0..normal format
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWP010REFSUPPORT_MASK)
#define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK (0x80000000U)
#define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT (31U)
/*! SW_ENC_HWSSIMSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_SHIFT)) & VPU_HEVC_SWREG226_SW_ENC_HWSSIMSUPPORT_MASK)
/*! @} */
/*! @name SWREG235 - RPS encoding control 0 */
/*! @{ */
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK (0x1U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT (0U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_1_MASK)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK (0x2U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT (1U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_USED_BY_CUR_0_MASK)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK (0xFFCU)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT (2U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_2_MASK)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK (0x3FF000U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT (12U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_1_MASK)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT (22U)
#define VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_SHIFT)) & VPU_HEVC_SWREG235_SW_ENC_RPS_DELTA_POC_0_MASK)
/*! @} */
/*! @name SWREG236 - RPS encoding control 1 */
/*! @{ */
#define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_MASK (0x1000U)
#define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT (12U)
/*! SW_ENC_P010_REF_ENABLE
* 0b0..not supported.
* 0b1..supported.
*/
#define VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_P010_REF_ENABLE_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK (0x2000U)
#define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT (13U)
#define VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_SHORT_TERM_REF_PIC_SET_SPS_FLAG_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK (0x1C000U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT (14U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_POS_PIC_NUM_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK (0xE0000U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT (17U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_NEG_PIC_NUM_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK (0x100000U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT (20U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_3_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK (0x200000U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT (21U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_USED_BY_CUR_2_MASK)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT (22U)
#define VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_SHIFT)) & VPU_HEVC_SWREG236_SW_ENC_RPS_DELTA_POC_3_MASK)
/*! @} */
/*! @name SWREG237 - Stride Control */
/*! @{ */
#define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_MASK (0x800U)
#define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_SHIFT (11U)
#define VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_SHIFT)) & VPU_HEVC_SWREG237_SW_ENC_DUMMYREADEN_MASK)
#define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_MASK (0xFFFFF000U)
#define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT (12U)
#define VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_SHIFT)) & VPU_HEVC_SWREG237_SW_ENC_REF_CH_STRIDE_MASK)
/*! @} */
/*! @name SWREG238 - Dummy Read */
/*! @{ */
#define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT (0U)
#define VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_SHIFT)) & VPU_HEVC_SWREG238_SW_ENC_DUMMYREADADDR_MASK)
/*! @} */
/*! @name SWREG239 - Base Address LSB of CTB MADs of current frame. */
/*! @{ */
#define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_SHIFT)) & VPU_HEVC_SWREG239_SW_ENC_CURRENT_CTB_MAD_BASE_MASK)
/*! @} */
/*! @name SWREG241 - Base Address LSB of CTB MADs of previous frame. */
/*! @{ */
#define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_SHIFT)) & VPU_HEVC_SWREG241_SW_ENC_PREVIOUS_CTB_MAD_BASE_MASK)
/*! @} */
/*! @name SWREG243 - CTB RC Control 0 */
/*! @{ */
#define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK (0xFFFFF800U)
#define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT (11U)
#define VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_SHIFT)) & VPU_HEVC_SWREG243_SW_ENC_CTB_RC_MODEL_PARAM0_MASK)
/*! @} */
/*! @name SWREG244 - CTB RC Control 1 */
/*! @{ */
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK (0x4U)
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT (2U)
/*! SW_ENC_ROI3_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_TYPE_MASK)
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK (0x3F8U)
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT (3U)
#define VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_ROI3_QP_VALUE_MASK)
#define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK (0xFFFFFC00U)
#define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT (10U)
#define VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_SHIFT)) & VPU_HEVC_SWREG244_SW_ENC_CTB_RC_MODEL_PARAM1_MASK)
/*! @} */
/*! @name SWREG245 - CTB RC Control 2 */
/*! @{ */
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK (0x3FFFCU)
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT (2U)
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_SHIFT)) & VPU_HEVC_SWREG245_SW_ENC_CTB_RC_ROW_FACTOR_MASK)
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT (18U)
#define VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_SHIFT)) & VPU_HEVC_SWREG245_SW_ENC_CTB_RC_MODEL_PARAM_MIN_MASK)
/*! @} */
/*! @name SWREG246 - CTB RC Control 3 */
/*! @{ */
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_MASK (0x38U)
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT (3U)
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_CTB_RC_DELAY_MASK)
#define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK (0x3FC0U)
#define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT (6U)
#define VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_AXI_WRITE_OUTSTANDING_NUM_MASK)
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK (0xFFFFC000U)
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT (14U)
#define VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_SHIFT)) & VPU_HEVC_SWREG246_SW_ENC_CTB_RC_QP_STEP_MASK)
/*! @} */
/*! @name SWREG247 - CTB RC Control 4 */
/*! @{ */
#define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK (0x2U)
#define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT (1U)
/*! SW_ENC_CTB_RC_PREV_MAD_VALID
* 0b0..no
* 0b1..yes.
*/
#define VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_SHIFT)) & VPU_HEVC_SWREG247_SW_ENC_CTB_RC_PREV_MAD_VALID_MASK)
#define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK (0xFFFFFFC0U)
#define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT (6U)
#define VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_SHIFT)) & VPU_HEVC_SWREG247_SW_ENC_PREV_PIC_LUM_MAD_MASK)
/*! @} */
/*! @name SWREG248 - CTB RC Control 5 */
/*! @{ */
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK (0x1U)
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT (0U)
/*! SW_ENC_ROI4_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_TYPE_MASK)
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK (0xFEU)
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT (1U)
#define VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_ROI4_QP_VALUE_MASK)
#define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK (0xFFFFFF00U)
#define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT (8U)
#define VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_SHIFT)) & VPU_HEVC_SWREG248_SW_ENC_CTB_QP_SUM_FOR_RC_MASK)
/*! @} */
/*! @name SWREG249 - register extension for 8K width */
/*! @{ */
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK (0x8U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT (3U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_BOTTOM_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK (0x10U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT (4U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_TOP_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK (0x20U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT (5U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_RIGHT_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK (0x40U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT (6U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM2_LEFT_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK (0x80U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT (7U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_BOTTOM_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK (0x100U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT (8U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_TOP_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK (0x200U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT (9U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_RIGHT_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK (0x400U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT (10U)
#define VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_IPCM1_LEFT_MSB_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK (0x800U)
#define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT (11U)
#define VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_PIC_WIDTH_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK (0x1000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT (12U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_BOTTOM_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK (0x2000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT (13U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_TOP_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK (0x4000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT (14U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_RIGHT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK (0x8000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT (15U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI2_LEFT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK (0x10000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT (16U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_BOTTOM_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK (0x20000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT (17U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_TOP_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK (0x40000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT (18U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_RIGHT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK (0x80000U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT (19U)
#define VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ROI1_LEFT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK (0x100000U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT (20U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_BOTTOM_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK (0x200000U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT (21U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_TOP_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK (0x400000U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT (22U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_RIGHT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK (0x800000U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT (23U)
#define VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_INTRA_AREA_LEFT_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK (0x3000000U)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT (24U)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_CIR_INTERVAL_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_MASK (0xC000000U)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT (26U)
#define VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_CIR_START_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK (0x10000000U)
#define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT (28U)
#define VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_SLICE_SIZE_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK (0x20000000U)
#define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT (29U)
#define VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_NUM_SLICES_READY_MSB2_MASK)
#define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK (0xC0000000U)
#define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT (30U)
#define VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_SHIFT)) & VPU_HEVC_SWREG249_SW_ENC_ENCODED_CTB_NUMBER_MSB2_MASK)
/*! @} */
/*! @name SWREG250 - Global MV Control 0 */
/*! @{ */
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT (4U)
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_SHIFT)) & VPU_HEVC_SWREG250_SW_ENC_GLOBAL_VERTICAL_MV_L0_MASK)
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT (18U)
#define VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_SHIFT)) & VPU_HEVC_SWREG250_SW_ENC_GLOBAL_HORIZONTAL_MV_L0_MASK)
/*! @} */
/*! @name SWREG251 - Global MV Control 1 */
/*! @{ */
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK (0x3FFF0U)
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT (4U)
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_SHIFT)) & VPU_HEVC_SWREG251_SW_ENC_GLOBAL_VERTICAL_MV_L1_MASK)
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK (0xFFFC0000U)
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT (18U)
#define VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_SHIFT)) & VPU_HEVC_SWREG251_SW_ENC_GLOBAL_HORIZONTAL_MV_L1_MASK)
/*! @} */
/*! @name SWREG252 - ROI3 Area */
/*! @{ */
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_MASK (0xFFCU)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT (2U)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_RIGHT_MASK)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_MASK (0x3FF000U)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_SHIFT (12U)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_TOP_MASK)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_SHIFT (22U)
#define VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_SHIFT)) & VPU_HEVC_SWREG252_SW_ENC_ROI3_LEFT_MASK)
/*! @} */
/*! @name SWREG253 - ROI3&4 Area */
/*! @{ */
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_MASK (0xFFCU)
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_SHIFT (2U)
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI4_TOP_MASK)
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_MASK (0x3FF000U)
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_SHIFT (12U)
#define VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI4_LEFT_MASK)
#define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT (22U)
#define VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_SHIFT)) & VPU_HEVC_SWREG253_SW_ENC_ROI3_BOTTOM_MASK)
/*! @} */
/*! @name SWREG254 - ROI4&5 Area */
/*! @{ */
#define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_MASK (0xFFCU)
#define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_SHIFT (2U)
#define VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI5_LEFT_MASK)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_MASK (0x3FF000U)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT (12U)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI4_BOTTOM_MASK)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT (22U)
#define VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_SHIFT)) & VPU_HEVC_SWREG254_SW_ENC_ROI4_RIGHT_MASK)
/*! @} */
/*! @name SWREG255 - ROI5 Area */
/*! @{ */
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_MASK (0xFFCU)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT (2U)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_BOTTOM_MASK)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_MASK (0x3FF000U)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT (12U)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_RIGHT_MASK)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_SHIFT (22U)
#define VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_SHIFT)) & VPU_HEVC_SWREG255_SW_ENC_ROI5_TOP_MASK)
/*! @} */
/*! @name SWREG256 - ROI6 Area */
/*! @{ */
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_MASK (0xFFCU)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT (2U)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_RIGHT_MASK)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_MASK (0x3FF000U)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_SHIFT (12U)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_TOP_MASK)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_SHIFT (22U)
#define VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_SHIFT)) & VPU_HEVC_SWREG256_SW_ENC_ROI6_LEFT_MASK)
/*! @} */
/*! @name SWREG257 - ROI6&7 Area */
/*! @{ */
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_MASK (0xFFCU)
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_SHIFT (2U)
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI7_TOP_MASK)
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_MASK (0x3FF000U)
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_SHIFT (12U)
#define VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI7_LEFT_MASK)
#define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT (22U)
#define VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_SHIFT)) & VPU_HEVC_SWREG257_SW_ENC_ROI6_BOTTOM_MASK)
/*! @} */
/*! @name SWREG258 - ROI7&8 Area */
/*! @{ */
#define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_MASK (0xFFCU)
#define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_SHIFT (2U)
#define VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI8_LEFT_MASK)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_MASK (0x3FF000U)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT (12U)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI7_BOTTOM_MASK)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT (22U)
#define VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_SHIFT)) & VPU_HEVC_SWREG258_SW_ENC_ROI7_RIGHT_MASK)
/*! @} */
/*! @name SWREG259 - ROI8 Area */
/*! @{ */
#define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK (0x2U)
#define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT (1U)
/*! SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE
* 0b0..max tu size 32.
* 0b1..max tu size 16.
*/
#define VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_CURRENT_MAX_TU_SIZE_DECREASE_MASK)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_MASK (0xFFCU)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT (2U)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_BOTTOM_MASK)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_MASK (0x3FF000U)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT (12U)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_RIGHT_MASK)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_MASK (0xFFC00000U)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_SHIFT (22U)
#define VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_SHIFT)) & VPU_HEVC_SWREG259_SW_ENC_ROI8_TOP_MASK)
/*! @} */
/*! @name SWREG260 - ROI qp */
/*! @{ */
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK (0x1U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT (0U)
/*! SW_ENC_ROI5_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_TYPE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK (0xFEU)
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT (1U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI5_QP_VALUE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK (0x100U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT (8U)
/*! SW_ENC_ROI6_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_TYPE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK (0xFE00U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT (9U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI6_QP_VALUE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK (0x10000U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT (16U)
/*! SW_ENC_ROI7_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_TYPE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK (0xFE0000U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT (17U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI7_QP_VALUE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK (0x1000000U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT (24U)
/*! SW_ENC_ROI8_QP_TYPE
* 0b0..delta
* 0b1..Absolute value
*/
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_TYPE_MASK)
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK (0xFE000000U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT (25U)
#define VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_SHIFT)) & VPU_HEVC_SWREG260_SW_ENC_ROI8_QP_VALUE_MASK)
/*! @} */
/*! @name SWREG261 - Stride Control */
/*! @{ */
#define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK (0x1U)
#define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT (0U)
#define VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_MOTION_SCORE_ENABLE_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK (0x2U)
#define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT (1U)
#define VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_PASS1_SKIP_CABAC_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_MASK (0x4U)
#define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT (2U)
#define VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_RDOQ_ENABLE_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_MASK (0x8U)
#define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT (3U)
#define VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_MULTI_CORE_EN_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK (0xFF0U)
#define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT (4U)
#define VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_AXI_READ_OUTSTANDING_NUM_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK (0x1000U)
#define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT (12U)
#define VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_PRP_IN_LOOP_DS_RATIO_MASK)
#define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK (0x3E000U)
#define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT (13U)
#define VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_SHIFT)) & VPU_HEVC_SWREG261_SW_ENC_RGBLUMAOFFSET_MASK)
/*! @} */
/*! @name SWREG265 - Multicore sync ctrl */
/*! @{ */
#define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK (0xFFFFU)
#define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT (0U)
#define VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_SHIFT)) & VPU_HEVC_SWREG265_SW_ENC_DDR_POLLING_INTERVAL_MASK)
#define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT (16U)
#define VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG265_SW_ENC_REF_READY_THRESHOLD_MASK)
/*! @} */
/*! @name SWREG266 - Multicore sync address L0 LSB */
/*! @{ */
#define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT (0U)
#define VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_SHIFT)) & VPU_HEVC_SWREG266_SW_ENC_MULTICORE_SYNC_L0_ADDR_MASK)
/*! @} */
/*! @name SWREG267 - Multicore sync address L0 MSB */
/*! @{ */
#define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG267_SW_ENC_MULTICORE_SYNC_L0_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG268 - Multicore sync address L1 LSB */
/*! @{ */
#define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT (0U)
#define VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_SHIFT)) & VPU_HEVC_SWREG268_SW_ENC_MULTICORE_SYNC_L1_ADDR_MASK)
/*! @} */
/*! @name SWREG269 - Multicore sync address L1 MSB */
/*! @{ */
#define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG269_SW_ENC_MULTICORE_SYNC_L1_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG270 - Multicore sync address recon LSB */
/*! @{ */
#define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT (0U)
#define VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_SHIFT)) & VPU_HEVC_SWREG270_SW_ENC_MULTICORE_SYNC_REC_ADDR_MASK)
/*! @} */
/*! @name SWREG271 - Multicore sync address recon MSB */
/*! @{ */
#define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG271_SW_ENC_MULTICORE_SYNC_REC_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG272 - Programmable AXI urgent sideband signals */
/*! @{ */
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK (0xFFU)
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT (0U)
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_DISABLE_THRESHOLD_MASK)
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK (0xFF00U)
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT (8U)
#define VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_WR_URGENT_ENABLE_THRESHOLD_MASK)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK (0xFF0000U)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT (16U)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_DISABLE_THRESHOLD_MASK)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK (0xFF000000U)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT (24U)
#define VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_SHIFT)) & VPU_HEVC_SWREG272_SW_ENC_RD_URGENT_ENABLE_THRESHOLD_MASK)
/*! @} */
/*! @name SWREG273 - roimap cu ctrl index address LSB */
/*! @{ */
#define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT (0U)
#define VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_SHIFT)) & VPU_HEVC_SWREG273_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MASK)
/*! @} */
/*! @name SWREG274 - roimap cu ctrl index address MSB */
/*! @{ */
#define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG274_SW_ENC_ROIMAP_CUCTRL_INDEX_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG275 - roimap cu ctrl address LSB */
/*! @{ */
#define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT (0U)
#define VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_SHIFT)) & VPU_HEVC_SWREG275_SW_ENC_ROIMAP_CUCTRL_ADDR_MASK)
/*! @} */
/*! @name SWREG276 - roimap cu ctrl address MSB */
/*! @{ */
#define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT (0U)
#define VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_SHIFT)) & VPU_HEVC_SWREG276_SW_ENC_ROIMAP_CUCTRL_ADDR_MSB_MASK)
/*! @} */
/*! @name SWREG277 - poc type/bits setting */
/*! @{ */
#define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK (0xFFFE0U)
#define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT (5U)
#define VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_SHIFT)) & VPU_HEVC_SWREG277_SW_ENC_SYN_AMOUNT_PER_LOOPBACK_MASK)
#define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK (0xF8000000U)
#define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT (27U)
#define VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_SHIFT)) & VPU_HEVC_SWREG277_SW_ENC_LOG2_MAX_PIC_ORDER_CNT_LSB_MASK)
/*! @} */
/*! @name SWREG278 - stream output buffer1 address */
/*! @{ */
#define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT (0U)
#define VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_SHIFT)) & VPU_HEVC_SWREG278_SW_ENC_OUTPUT_STRM_BUF1_BASE_MASK)
/*! @} */
/*! @name SWREG280 - stream output buffer1 limit size */
/*! @{ */
#define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK (0xFFFFFFFFU)
#define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT (0U)
#define VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_SHIFT)) & VPU_HEVC_SWREG280_SW_ENC_OUTPUT_STRM_BUFFER1_LIMIT_MASK)
/*! @} */
/*! @name SWREG281 - poc type/bits setting */
/*! @{ */
#define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK (0x3F0U)
#define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT (4U)
#define VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_SHIFT)) & VPU_HEVC_SWREG281_SW_NUM_CTB_ROWS_PER_SYNC_MSB_MASK)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK (0xFFC00U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT (10U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_WR_PTR_MASK)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK (0x3FF00000U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT (20U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_RD_PTR_MASK)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK (0x40000000U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT (30U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_EN_MASK)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK (0x80000000U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT (31U)
#define VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_SHIFT)) & VPU_HEVC_SWREG281_SW_ENC_STRM_SEGMENT_SW_SYNC_EN_MASK)
/*! @} */
/*! @name SWREG287 - HW synthesis config register 4, read-only */
/*! @{ */
#define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK (0x20000000U)
#define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT (29U)
/*! SW_ENC_HWSCALER420SUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWSCALER420SUPPORT_MASK)
#define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK (0x40000000U)
#define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT (30U)
/*! SW_ENC_HWCSCEXTENSIONSUPPORT
* 0b0..not supported.
* 0b1..supported
*/
#define VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWCSCEXTENSIONSUPPORT_MASK)
#define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK (0x80000000U)
#define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT (31U)
/*! SW_ENC_HWVIDEOHEIGHTEXT
* 0b0..Not.
* 0b1..Yes.
*/
#define VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_SHIFT)) & VPU_HEVC_SWREG287_SW_ENC_HWVIDEOHEIGHTEXT_MASK)
/*! @} */
/*! @name SWREG289 - Pre-processor color conversion parameters1 */
/*! @{ */
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_MASK (0xFFFFU)
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_SHIFT (0U)
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_SHIFT)) & VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFH_MASK)
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_MASK (0xFFFF0000U)
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_SHIFT (16U)
#define VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG(x) (((uint32_t)(((uint32_t)(x)) << VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_SHIFT)) & VPU_HEVC_SWREG289_SW_ENC_RGBCOEFFG_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VPU_HEVC_Register_Masks */
/* VPU_HEVC - Peripheral instance base addresses */
/** Peripheral VPU_HEVC base address */
#define VPU_HEVC_BASE (0x38320000u)
/** Peripheral VPU_HEVC base pointer */
#define VPU_HEVC ((VPU_HEVC_Type *)VPU_HEVC_BASE)
/** Array initializer of VPU_HEVC peripheral base addresses */
#define VPU_HEVC_BASE_ADDRS { VPU_HEVC_BASE }
/** Array initializer of VPU_HEVC peripheral base pointers */
#define VPU_HEVC_BASE_PTRS { VPU_HEVC }
/*!
* @}
*/ /* end of group VPU_HEVC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
__IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/*! @name WCR - Watchdog Control Register */
/*! @{ */
#define WDOG_WCR_WDZST_MASK (0x1U)
#define WDOG_WCR_WDZST_SHIFT (0U)
/*! WDZST
* 0b0..Continue timer operation (Default).
* 0b1..Suspend the watchdog timer.
*/
#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
#define WDOG_WCR_WDBG_MASK (0x2U)
#define WDOG_WCR_WDBG_SHIFT (1U)
/*! WDBG
* 0b0..Continue WDOG timer operation (Default).
* 0b1..Suspend the watchdog timer.
*/
#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
#define WDOG_WCR_WDE_MASK (0x4U)
#define WDOG_WCR_WDE_SHIFT (2U)
/*! WDE
* 0b0..Disable the Watchdog (Default).
* 0b1..Enable the Watchdog.
*/
#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
#define WDOG_WCR_WDT_MASK (0x8U)
#define WDOG_WCR_WDT_SHIFT (3U)
/*! WDT
* 0b0..No effect on WDOG_B (Default).
* 0b1..Assert WDOG_B upon a Watchdog Time-out event.
*/
#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
#define WDOG_WCR_SRS_MASK (0x10U)
#define WDOG_WCR_SRS_SHIFT (4U)
/*! SRS
* 0b0..Assert system reset signal.
* 0b1..No effect on the system (Default).
*/
#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
#define WDOG_WCR_WDA_MASK (0x20U)
#define WDOG_WCR_WDA_SHIFT (5U)
/*! WDA
* 0b0..Assert WDOG_B output.
* 0b1..No effect on system (Default).
*/
#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
#define WDOG_WCR_SRE_MASK (0x40U)
#define WDOG_WCR_SRE_SHIFT (6U)
/*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal (SRS).
* 0b0..Reserved
* 0b1..This bit must be set to 1.
*/
#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
#define WDOG_WCR_WDW_MASK (0x80U)
#define WDOG_WCR_WDW_SHIFT (7U)
/*! WDW
* 0b0..Continue WDOG timer operation (Default).
* 0b1..Suspend WDOG timer operation.
*/
#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
#define WDOG_WCR_WT_MASK (0xFF00U)
#define WDOG_WCR_WT_SHIFT (8U)
/*! WT
* 0b00000000..- 0.5 Seconds (Default).
* 0b00000001..- 1.0 Seconds.
* 0b00000010..- 1.5 Seconds.
* 0b00000011..- 2.0 Seconds.
* 0b11111111..- 128 Seconds.
*/
#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
/*! @} */
/*! @name WSR - Watchdog Service Register */
/*! @{ */
#define WDOG_WSR_WSR_MASK (0xFFFFU)
#define WDOG_WSR_WSR_SHIFT (0U)
/*! WSR
* 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
* 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
*/
#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
/*! @} */
/*! @name WRSR - Watchdog Reset Status Register */
/*! @{ */
#define WDOG_WRSR_SFTW_MASK (0x1U)
#define WDOG_WRSR_SFTW_SHIFT (0U)
/*! SFTW
* 0b0..Reset is not the result of a software reset.
* 0b1..Reset is the result of a software reset.
*/
#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
#define WDOG_WRSR_TOUT_MASK (0x2U)
#define WDOG_WRSR_TOUT_SHIFT (1U)
/*! TOUT
* 0b0..Reset is not the result of a WDOG timeout.
* 0b1..Reset is the result of a WDOG timeout.
*/
#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
#define WDOG_WRSR_POR_MASK (0x10U)
#define WDOG_WRSR_POR_SHIFT (4U)
/*! POR
* 0b0..Reset is not the result of a power on reset.
* 0b1..Reset is the result of a power on reset.
*/
#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
/*! @} */
/*! @name WICR - Watchdog Interrupt Control Register */
/*! @{ */
#define WDOG_WICR_WICT_MASK (0xFFU)
#define WDOG_WICR_WICT_SHIFT (0U)
/*! WICT
* 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
* 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
* 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
* 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
*/
#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
#define WDOG_WICR_WTIS_MASK (0x4000U)
#define WDOG_WICR_WTIS_SHIFT (14U)
/*! WTIS
* 0b0..No interrupt has occurred (Default).
* 0b1..Interrupt has occurred
*/
#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
#define WDOG_WICR_WIE_MASK (0x8000U)
#define WDOG_WICR_WIE_SHIFT (15U)
/*! WIE
* 0b0..Disable Interrupt (Default).
* 0b1..Enable Interrupt.
*/
#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
/*! @} */
/*! @name WMCR - Watchdog Miscellaneous Control Register */
/*! @{ */
#define WDOG_WMCR_PDE_MASK (0x1U)
#define WDOG_WMCR_PDE_SHIFT (0U)
/*! PDE
* 0b0..Power Down Counter of WDOG is disabled.
* 0b1..Power Down Counter of WDOG is enabled (Default).
*/
#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG1 base address */
#define WDOG1_BASE (0x30280000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
/** Peripheral WDOG2 base address */
#define WDOG2_BASE (0x30290000u)
/** Peripheral WDOG2 base pointer */
#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
/** Peripheral WDOG3 base address */
#define WDOG3_BASE (0x302A0000u)
/** Peripheral WDOG3 base pointer */
#define WDOG3 ((WDOG_Type *)WDOG3_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 }
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn }
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XTALOSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer
* @{
*/
/** XTALOSC - Register Layout Typedef */
typedef struct {
__IO uint32_t SYS_OSCNML_CTL0; /**< OSC Normal Clock Generation Control Register0, offset: 0x0 */
__IO uint32_t SYS_OSCNML_CTL1; /**< OSC Normal Clock Generation Control Register1, offset: 0x4 */
} XTALOSC_Type;
/* ----------------------------------------------------------------------------
-- XTALOSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks
* @{
*/
/*! @name SYS_OSCNML_CTL0 - OSC Normal Clock Generation Control Register0 */
/*! @{ */
#define XTALOSC_SYS_OSCNML_CTL0_SF0_MASK (0x1U)
#define XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT (0U)
#define XTALOSC_SYS_OSCNML_CTL0_SF0(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF0_MASK)
#define XTALOSC_SYS_OSCNML_CTL0_SF1_MASK (0x2U)
#define XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT (1U)
#define XTALOSC_SYS_OSCNML_CTL0_SF1(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF1_MASK)
#define XTALOSC_SYS_OSCNML_CTL0_SP_MASK (0x4U)
#define XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT (2U)
#define XTALOSC_SYS_OSCNML_CTL0_SP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SP_MASK)
#define XTALOSC_SYS_OSCNML_CTL0_RTO_MASK (0x10U)
#define XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT (4U)
#define XTALOSC_SYS_OSCNML_CTL0_RTO(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_RTO_MASK)
#define XTALOSC_SYS_OSCNML_CTL0_EN_MASK (0x80000000U)
#define XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT (31U)
#define XTALOSC_SYS_OSCNML_CTL0_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_EN_MASK)
/*! @} */
/*! @name SYS_OSCNML_CTL1 - OSC Normal Clock Generation Control Register1 */
/*! @{ */
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK (0x2U)
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT (1U)
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK)
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK (0x4U)
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT (2U)
#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK)
#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK (0xFF0U)
#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT (4U)
#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XTALOSC_Register_Masks */
/* XTALOSC - Peripheral instance base addresses */
/** Peripheral XTALOSC base address */
#define XTALOSC_BASE (0x30270000u)
/** Peripheral XTALOSC base pointer */
#define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE)
/** Array initializer of XTALOSC peripheral base addresses */
#define XTALOSC_BASE_ADDRS { XTALOSC_BASE }
/** Array initializer of XTALOSC peripheral base pointers */
#define XTALOSC_BASE_PTRS { XTALOSC }
/*!
* @}
*/ /* end of group XTALOSC_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#else
#pragma pop
#endif
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
---------------------------------------------------------------------------- */
/*!
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
* @{
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang system_header
#endif
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma system_include
#endif
/**
* @brief Mask and left-shift a bit field value for use in a register bit range.
* @param field Name of the register bit field.
* @param value Value of the bit field.
* @return Masked and shifted value.
*/
#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
* @brief Mask and right-shift a register value to extract a bit field value.
* @param field Name of the register bit field.
* @param value Value of the register.
* @return Masked and shifted bit field value.
*/
#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
/*!
* @}
*/ /* end of group Bit_Field_Generic_Macros */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
/* No SDK compatibility issues. */
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _MIMX8ML3_CM7_H_ */